Printed wiring board

Abstract

A printed wiring board is provided with: an insulating layer having a first main surface and a second main surface; a first copper layer disposed on the first main surface; a second copper layer disposed on the second main surface; and a third copper layer in which a through-hole that reaches the second copper layer is formed in the insulating layer and the first copper layer, the third copper layer being disposed on the second copper layer inside the through-hole, on the inner wall surface of the through-hole, and on the first copper layer positioned around the through-hole, a single copper layer being disposed on the inner wall surface of the through-hole, the single copper layer being the third copper layer.

Description

Technical Field

[0001] The present disclosure relates to a printed wiring board. This application claims priority based on Japanese Application No. 2022-168266 filed on October 20, 2022, and all the contents described in the Japanese Application are incorporated herein by reference. Background Art

[0002] Japanese Patent Application Laid-Open No. 2017-037990 (Patent Document 1) discloses a printed wiring board, which includes an inner resin layer, an inner circuit, an organic adhesive layer, an organic insulating resin layer, an outer copper layer, and an outer circuit.

[0003] The inner layer resin layer has a first main surface. The inner layer circuit is arranged on the first main surface. The organic bonding layer is arranged on the first main surface in a manner of covering the inner layer circuit. The organic insulating resin layer has a second main surface and a third main surface. The third main surface is a surface opposite to the second main surface. The organic insulating resin layer is arranged on the organic bonding layer in a manner of facing the second main surface to the organic bonding layer. Through holes are formed in the organic bonding layer and the organic insulating resin layer to expose the inner layer circuit.

[0004] The outer copper layer is a copper layer formed by electroless plating. The outer copper layer is arranged on the inner circuit exposed from the through hole, the inner wall surface of the through hole, and the third main surface located around the through hole. The outer circuit is a copper layer formed by electrolytic plating. The outer circuit is arranged on the outer copper layer. In this way, in the printed wiring board described in Patent Document 1, the outer circuit is electrically connected to the inner circuit.

[0005] Prior art literature

[0006] Patent Literature

[0007] Patent Document 1: Japanese Patent Application Publication No. 2017-037990 Summary of the invention

[0008] The printed wiring board disclosed in the present invention comprises: an insulating layer having a first main surface and a second main surface; a first copper layer arranged on the first main surface; a second copper layer arranged on the second main surface; and a third copper layer, wherein a through hole reaching the second copper layer is formed in the insulating layer and the first copper layer, the third copper layer is arranged on the second copper layer inside the through hole, on the inner wall surface of the through hole, and on the first copper layer located around the through hole, and a single copper layer is arranged on the inner wall surface of the through hole, and the single copper layer is the third copper layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a cross-sectional view of printed wiring board 100 .

[0010] Figure 2 It is a manufacturing process diagram of the printed wiring board 100 .

[0011] Figure 3 It is a cross-sectional view for explaining the production step S1.

[0012] Figure 4 It is a cross-sectional view for explaining the first etching step S2.

[0013] Figure 5 It is a cross-sectional view for explaining the hole-forming step S3.

[0014] Figure 6 It is a cross-sectional view explaining the resist pattern forming step S5.

[0015] Figure 7 It is a cross-sectional view explaining the electrolytic plating step S6.

[0016] Figure 8 It is a cross-sectional view for explaining the resist pattern removal step S7.

[0017] Fig. 9 2 is a cross-sectional view of the printed wiring board 100A.

[0018] Fig.10 is a cross-sectional view of the printed wiring board 200 .

[0019] Fig.11 It is a manufacturing process diagram of the printed wiring board 200.

[0020] Fig.12 It is a cross-sectional view for explaining the preparation step S11.

[0021] Fig.13 It is a cross-sectional view for explaining the first hole-forming step S12.

[0022] Fig.14 It is a cross-sectional view explaining the first resist pattern forming step S13.

[0023] Fig.15 It is a cross-sectional view explaining the first electrolytic plating step S14.

[0024] Fig.16 It is a cross-sectional view for explaining the first resist pattern removing step S15.

[0025] Fig.17 It is a cross-sectional view for explaining the first etching step S16.

[0026] Fig.18 It is a cross-sectional view explaining the insulating layer pasting step S17.

[0027] Fig.19 It is a cross-sectional view for explaining the second hole-forming step S18.

[0028] Fig. 20It is a cross-sectional view explaining the second resist pattern forming step S19.

[0029] Fig.21 It is a cross-sectional view explaining the second electrolytic plating step S20.

[0030] Fig. 22 It is a cross-sectional view explaining the second resist pattern removing step S21. DETAILED DESCRIPTION

[0031] [Technical Problems to be Solved by the Present Disclosure]

[0032] In the printed wiring board described in Patent Document 1, palladium is used as a catalyst when forming an outer copper layer by electroless plating. For this reason, palladium may remain at the interface between the inner layer circuit and the outer copper layer. The palladium remaining between the inner layer circuit and the outer copper layer may cause the outer layer circuit to be peeled off from the inner layer circuit together with the outer copper layer due to, for example, thermal shock, resulting in disconnection.

[0033] In the printed wiring board described in Patent Document 1, before the outer copper layer is formed by electroless plating, etching is sometimes performed to remove foreign matter and oxide film (hereinafter referred to as foreign matter, etc.) located on the surface of the inner layer circuit. In order to avoid excessive corrosion of the inner layer circuit, the etching has to be weak, resulting in foreign matter, etc. remaining on the surface of the inner layer circuit. If foreign matter, etc. remain on the surface of the inner layer circuit, the adhesion between the inner layer circuit and the outer copper layer is reduced, which sometimes causes the outer layer circuit to be peeled off from the inner layer circuit together with the outer copper layer, resulting in disconnection.

[0034] The present disclosure is made in view of the above-mentioned problems of the prior art. More specifically, the present disclosure provides a printed wiring board capable of suppressing disconnection in a blind hole. A blind hole is a hole that electrically or physically connects the outermost circuit of a printed wiring board to one or more inner layer circuits by copper plating or the like. The blind hole does not penetrate to the outermost circuit on the opposite side of the hole.

[0035] [Effects of the present disclosure]

[0036] According to the printed wiring board of the present disclosure, it is possible to suppress disconnection in the blind via.

[0037] [Description of Embodiments of the Present Disclosure]

[0038] First, embodiments of the present disclosure will be listed and described.

[0039] (1) A printed wiring board according to an embodiment includes: an insulating layer having a first main surface and a second main surface; a first copper layer arranged on the first main surface; a second copper layer arranged on the second main surface; and a third copper layer, wherein a through hole reaching the second copper layer is formed in the insulating layer and the first copper layer, the third copper layer is arranged on the second copper layer inside the through hole, on the inner wall surface of the through hole, and on the first copper layer located around the through hole, and a single copper layer is arranged on the inner wall surface of the through hole, and the single copper layer is the third copper layer.

[0040] According to the printed wiring board of (1) above, it is possible to suppress disconnection in the blind via.

[0041] (2) In the printed wiring board of (1) above, the thickness of the third copper layer on the first copper layer may be 0.4 times or more the thickness of the insulating layer and 0.6 times or less the minimum width of the through hole on the first main surface.

[0042] According to the printed wiring board of (2) above, the third copper layer formed on the first copper layer located around the through hole and the third copper layer formed on the second copper layer exposed from the through hole can be easily connected.

[0043] (3) In the printed wiring board of (1) above, the thickness of the third copper layer on the first copper layer may be 0.8 times or more the thickness of the insulating layer and 0.45 times or less the minimum width of the through hole on the first main surface.

[0044] According to the printed wiring board of (3) above, the third copper layer formed on the first copper layer located around the through hole and the third copper layer formed on the second copper layer exposed from the through hole can be connected more easily.

[0045] (4) In the printed wiring boards of (1) to (3) above, the concentration of palladium in a region of the third copper layer from the interface between the insulating layer and the third copper layer to a depth of 10 nm and in a region of the third copper layer from the interface between the second copper layer and the third copper layer to a depth of 10 nm may be 0.5 mass % or less.

[0046] (5) In the printed wiring board of (1) to (4) above, the third copper layer may be an electrolytic copper plated layer.

[0047] (6) The printed wiring board involved in the embodiment comprises: a first insulating layer having a first main surface; a first copper layer arranged on the first main surface; an adhesive layer arranged on the first main surface in a manner covering the first copper layer; a second insulating layer having a second main surface and a third main surface and arranged on the adhesive layer in a manner such that the second main surface faces the adhesive layer; a second copper layer arranged on the third main surface; and a third copper layer, wherein a through hole reaching the first copper layer is formed in the second insulating layer, the second copper layer and the adhesive layer, the third copper layer is arranged on the first copper layer inside the through hole, on the inner wall surface of the through hole and on the second copper layer located around the through hole, and a single copper layer is arranged on the inner wall surface of the through hole, and the single copper layer is the third copper layer.

[0048] According to the printed wiring board of (6) above, it is possible to suppress disconnection in the blind via.

[0049] (7) In the printed wiring board of (6) above, the thickness of the third copper layer on the second copper layer may be greater than 0.4 times the sum of the thickness of the second insulating layer and the thickness of the adhesive layer between the first copper layer and the second insulating layer, and less than 0.6 times the minimum value of the width of the through hole at the third main surface.

[0050] According to the printed wiring board of (7) above, the third copper layer formed on the second copper layer located around the through hole and the third copper layer formed on the first copper layer exposed from the through hole can be easily connected.

[0051] (8) In the printed wiring board of (6) above, the thickness of the third copper layer on the second copper layer may be greater than 0.8 times the sum of the thickness of the second insulating layer and the thickness of the adhesive layer between the first copper layer and the second insulating layer, and less than 0.45 times the minimum value of the width of the through hole at the third main surface.

[0052] According to the printed wiring board of (8) above, the third copper layer formed on the second copper layer located around the through hole and the third copper layer formed on the first copper layer exposed from the through hole can be easily connected.

[0053] (9) In the printed wiring boards of (6) to (8) above, the concentration of palladium in the region of the third copper layer from the interface between the second insulating layer and the third copper layer to a depth of 10 nm and in the region of the third copper layer from the interface between the first copper layer and the third copper layer to a depth of 10 nm may be 0.5 mass % or less.

[0054] (10) In the printed wiring board of (6) to (9) above, the third copper layer may be an electrolytic copper plated layer.

[0055] [Details of the embodiments of the present disclosure]

[0056] The details of the embodiments of the present disclosure will be described with reference to the accompanying drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and repeated description will not be repeated.

[0057] (First Embodiment)

[0058] A printed wiring board according to the first embodiment will be described. The printed wiring board according to the first embodiment is referred to as a printed wiring board 100 .

[0059] <Configuration of Printed Wiring Board 100>

[0060] Hereinafter, the configuration of printed wiring board 100 will be described.

[0061] Figure 1 is a cross-sectional view of the printed wiring board 100. Figure 1 As shown, the printed wiring board 100 includes an insulating layer 10 , a first copper layer 11 , a second copper layer 12 , and a third copper layer 20 .

[0062] The constituent material of the insulating layer 10 has electrical insulation and flexibility. The constituent material of the insulating layer 10 is, for example, polyimide. However, the constituent material of the insulating layer 10 is not limited thereto. The insulating layer 10 has a first principal surface 10a and a second principal surface 10b. The first principal surface 10a and the second principal surface 10b are surfaces perpendicular to the thickness direction of the insulating layer 10, and constitute the front and back surfaces of the insulating layer 10. The second principal surface 10b is a surface opposite to the first principal surface 10a. The thickness of the insulating layer 10 is set to thickness T1. Thickness T1 is, for example, greater than 12.5 μm and less than 100 μm. Thickness T1 is an average value obtained by measuring any ten points of the cross-sectional photograph.

[0063] The constituent material of the first copper layer 11 is copper or a copper alloy. The first copper layer 11 is disposed on the first main surface 10a. The constituent material of the second copper layer 12 is copper or a copper alloy. The second copper layer 12 is disposed on the second main surface 10b.

[0064] A through hole 13 is formed in the insulating layer 10 and the first copper layer 11. The through hole 13 penetrates the insulating layer 10 and the first copper layer 11 in the thickness direction. The shape of the through hole 13 is, for example, circular when viewed from above. However, the planar shape of the through hole 13 is not limited thereto. The opening diameter of the through hole 13, for example, becomes smaller as it approaches the second main surface 10b. The width of the through hole 13 at the first main surface 10a is set to width W1. The second copper layer 12 is exposed from the through hole 13. The width W1 is, for example, greater than 25 μm and less than 250 μm.

[0065] The constituent material of the third copper layer 20 is copper or a copper alloy. The third copper layer 20 may also be a copper layer formed by electrolytic plating (electrolytic copper plating layer). A single copper layer is arranged on the inner wall surface of the through hole 13. The single copper layer referred to here is the third copper layer 20. "A single copper layer is arranged on the inner wall surface of the through hole 13" means that there are no more than two copper layers stacked continuously on the inner wall surface of the through hole 13. In other words, on the inner wall surface of the through hole 13, a resin layer or an adhesive layer is formed on the surface of the third copper layer 20 on the opposite side of the inner wall surface, for example. Alternatively, a metal layer other than copper is stacked on the surface of the third copper layer 20 on the opposite side of the inner wall surface.

[0066] The third copper layer 20 is arranged on the second copper layer 12 exposed inside the through hole 13, on the inner wall surface of the through hole 13, and on the first copper layer 11 located around the through hole 13. Here, "the third copper layer 20 is arranged on the first copper layer 11 located around the through hole 13" means that the third copper layer 20 is arranged on the side of the first copper layer 11 constituting the through hole 13, and is arranged on at least a part of the upper surface of the first copper layer 11 (the surface opposite to the surface in contact with the first main surface 10a). By arranging the third copper layer 20 on at least a part of the upper surface of the first copper layer 11, it is possible to suppress the third copper layer 20 from peeling off from the insulating layer 10 (through hole 13) by the anchor effect. The third copper layer 20 is also arranged on the first copper layer 11 located outside the periphery of the through hole 13. The third copper layer 20 constitutes the wiring of the printed wiring board 100. The wiring of the printed wiring board 100 is electrically connected to the second copper layer 12 exposed inside the through hole 13.

[0067] The thickness of the third copper layer 20 located on the first copper layer 11 is set to thickness T2. The thickness T2 can also be greater than 0.4 times the thickness T1 and less than 0.6 times the width W1. The thickness T2 is the average value obtained by measuring any ten points of the cross-sectional photograph. The thickness T2 can also be greater than 0.8 times the thickness T1 and less than 0.45 times the width W1. The thickness T2 is, for example, greater than 10 μm and less than 45 μm. The width W1 mentioned here is the minimum value of the width of the through hole 13 at the first main surface 10a. "The minimum value of the width of the through hole 13 at the first main surface 10a" refers to the diameter of the inscribed circle of the shape of the through hole 13 at the first main surface 10a when viewed from above.

[0068] There is no palladium at the interface between the insulating layer 10 and the third copper layer 20 constituting the inner wall surface of the through hole 13, and at the interface between the second copper layer 12 and the third copper layer 20, or palladium that is unintentionally mixed into the plating tank is inevitably attached. That is, the palladium concentration in the region of the third copper layer 20 from the interface between the insulating layer 10 (the inner wall surface of the through hole 13) and the third copper layer 20 to a depth of 10 nm is 0.5 mass % or less. In addition, the palladium concentration in the region of the third copper layer 20 from the interface between the second copper layer 12 and the third copper layer 20 exposed inside the through hole 13 to a depth of 10 nm is 0.5 mass % or less. It should be noted that there is no palladium at the interface between the first copper layer 11 and the third copper layer 20, and the palladium concentration in the region of the third copper layer 20 from the interface between the first copper layer 11 and the third copper layer 20 to a depth of 10 nm is 0.5 mass % or less. For example, the palladium concentration in the region of the third copper layer 20 is measured by energy dispersive X-ray spectroscopy for a cross section obtained by cutting a hole using a focused ion beam.

[0069] <Method of Manufacturing Printed Wiring Board 100>

[0070] Hereinafter, a method for manufacturing printed wiring board 100 will be described.

[0071] Figure 2 1 is a manufacturing process diagram of the printed wiring board 100. Figure 2 As shown, the method for manufacturing the printed wiring board 100 includes a preparation step S1, a first etching step S2, a hole forming step S3, a desmear step S4, a resist pattern forming step S5, an electrolytic plating step S6, a resist pattern removing step S7, and a second etching step S8.

[0072] Figure 3 is a cross-sectional view illustrating the preparation step S1. Figure 3 As shown, in the preparation step S1, the insulating layer 10 is prepared. The insulating layer 10 prepared in the preparation step S1 has a first copper layer 11 arranged on the entire surface of the first main surface 10a, and has a second copper layer 12 arranged on the entire surface of the second main surface 10b. The through hole 13 is not formed in the insulating layer 10 prepared in the preparation step S1.

[0073] The first etching step S2 is performed after the preparation step S1. Figure 4 is a cross-sectional view illustrating the first etching step S2. Figure 4 As shown, in the first etching step S2, etching is performed to form a portion of the through hole 13 located in the first copper layer 11. The hole opening step S3 is performed after the first etching step S2. Figure 5 2 is a cross-sectional view illustrating the hole-forming step S3. Figure 5 As shown, the portion of the through hole 13 located in the insulating layer 10 is formed by irradiating a laser, for example.

[0074] The desmear process S4 is performed after the hole forming process S3. In the desmear process S4, foreign matter and the like on the surface of the second copper layer 12 exposed inside the through hole 13 are removed by etching.

[0075] The resist pattern forming step S5 is performed after the desmear step S4. The etching in the desmear step S4 is performed weakly so as not to excessively erode the second copper layer 12 exposed inside the through hole 13. Therefore, foreign matter and the like may remain on the surface of the second copper layer 12 exposed inside the through hole 13 at a stage after the desmear step S4 and before the resist pattern forming step S5.

[0076] Figure 6 2 is a cross-sectional view illustrating the resist pattern forming step S5. Figure 6 As shown, in the resist pattern forming step S5, a resist pattern 30 is formed. For example, a dry film resist is attached to the first copper layer 11, and the attached dry film resist is exposed and developed to form the resist pattern 30. The development of the dry film resist is performed using an alkaline solution, so that a part of foreign matter and the like remaining on the surface of the second copper layer 12 exposed inside the through hole 13 is removed at this time.

[0077] The electrolytic plating step S6 is performed after the resist pattern forming step S5. Figure 7 2 is a cross-sectional view illustrating the electrolytic plating step S6. Figure 7 As shown, in the electrolytic plating step S6 , the third copper layer 20 is formed on the first copper layer 11 exposed from the opening of the resist pattern 30 and on the second copper layer 12 exposed inside the through hole 13 by performing electrolytic plating.

[0078] When the third copper layer 20 on the first copper layer 11 located around the through hole 13 grows, it extends along the inner wall surface of the through hole 13. When the third copper layer 20 on the second copper layer 12 exposed inside the through hole 13 grows, it also extends along the inner wall surface of the through hole 13. For this reason, the third copper layer 20 extending from the first copper layer 11 located around the through hole 13 along the inner wall surface of the through hole 13 and the third copper layer 20 extending from the second copper layer 12 exposed inside the through hole 13 along the inner wall surface of the through hole 13 are integrated, and the third copper layer 20 is also formed on the inner wall surface of the through hole 13.

[0079] It should be noted that after the resist pattern forming step S5 and before the electrolytic plating step S6 , a degreasing process is performed to further remove foreign matter and the like remaining on the surface of the second copper layer 12 exposed inside the through hole 13 .

[0080] The resist pattern removal step S7 is performed after the electrolytic plating step S6 . Figure 82 is a cross-sectional view illustrating the resist pattern removal step S7. Figure 8 As shown, in the resist pattern removal step S7, the resist pattern 30 is removed. The second etching step S8 is performed after the resist pattern removal step S7. In the second etching step S8, the first copper layer 11 located under the resist pattern 30 is removed. Thus, Figure 1 A printed wiring board 100 of the structure shown.

[0081] <Effects of Printed Wiring Board 100>

[0082] Hereinafter, the effects of the printed wiring board 100 will be described in comparison with a comparative example. The printed wiring board according to the comparative example is referred to as a printed wiring board 100A.

[0083] Fig. 9 1 is a cross-sectional view of the printed wiring board 100A. Fig. 9 As shown in FIG. 1 , the printed wiring board 100A further includes an electroless copper plating layer 40. The electroless copper plating layer 40 is a copper layer formed by electroless plating. The electroless copper plating layer 40 is arranged on the first copper layer 11, the inner wall surface of the through hole 13, and the second copper layer 12 exposed inside the through hole 13. Except for these points, the structure of the printed wiring board 100A is the same as that of the printed wiring board 100.

[0084] The method for manufacturing the printed wiring board 100A further includes an electroless plating step S9. The electroless plating step S9 is performed after the desmear step S4 and before the resist pattern forming step S5. In the electroless plating step S9, the electroless copper plating layer 40 is formed by performing electroless plating after providing a palladium catalyst on the first copper layer 11, the inner wall surface of the through hole 13, and the second copper layer 12 exposed inside the through hole 13.

[0085] In the method for manufacturing the printed wiring board 100A, in the resist pattern forming step S5, the resist pattern 30 is formed on the electroless copper plating layer 40 located on the first copper layer 11. In the method for manufacturing the printed wiring board 100A, in the electrolytic plating step S6, the third copper layer 20 is formed on the electroless copper plating layer 40. In the method for manufacturing the printed wiring board 100A, in the second etching step S8, the electroless copper plating layer 40 and the first copper layer 11 located under the resist pattern 30 are removed. Except for these points, the method for manufacturing the printed wiring board 100A is common to the method for manufacturing the printed wiring board 100.

[0086] Since the method for manufacturing printed wiring board 100A includes electroless plating step S9 , palladium remains at the interface between insulating layer 10 (inner wall surface of through hole 13 ) and electroless copper plating layer 40 and at the interface between second copper layer 12 exposed inside through hole 13 and electroless copper plating layer 40 .

[0087] In addition, since foreign matter etc. may remain on the surface of the second copper layer 12 exposed inside the through hole 13 at a stage after the desmear process S4 is performed, foreign matter etc. may remain between the second copper layer 12 exposed inside the through hole 13 and the electroless copper plating layer 40. In the method for manufacturing the printed wiring board 100A, since the second copper layer 12 exposed inside the through hole 13 is covered with the electroless copper plating layer 40 when the resist pattern forming process S5 and the electrolytic plating process S6 are performed, the foreign matter etc. mentioned above is not removed by the development in the resist pattern forming process S5 and the degreasing treatment before the electrolytic plating process S6.

[0088] Palladium remaining at the interface between the insulating layer 10 (inner wall surface of the through hole 13) and the electroless copper plating layer 40 and at the interface between the second copper layer 12 exposed inside the through hole 13 and the electroless copper plating layer 40, foreign matter located between the second copper layer 12 exposed inside the through hole 13 and the electroless copper plating layer 40, etc., may sometimes cause the third copper layer 20 to peel off together with the electroless copper plating layer 40 and become a cause of disconnection.

[0089] In the method for manufacturing the printed wiring board 100, since the electroless plating step S9 is not performed, palladium does not remain at the interface between the insulating layer 10 (the inner wall surface of the through hole 13) and the third copper layer 20 and at the interface between the second copper layer 12 exposed inside the through hole 13 and the third copper layer 20. In addition, in the method for manufacturing the printed wiring board 100, foreign matter and the like located on the surface of the second copper layer 12 exposed inside the through hole 13 are also removed by the development in the resist pattern forming step S5 and the degreasing treatment before the electrolytic plating step S6. In this way, according to the printed wiring board 100, it is possible to suppress the third copper layer 20 from being peeled off due to palladium, foreign matter, etc., and thus preventing the wire from being disconnected in the blind hole.

[0090] When the thickness T2 is less than 0.4 times the thickness T1, the growth of the third copper layer 20 is insufficient, and the third copper layer 20 extending from the first copper layer 11 around the through hole 13 along the inner wall surface of the through hole 13 is difficult to connect with the third copper layer 20 extending from the second copper layer 12 exposed inside the through hole 13 along the inner wall surface of the through hole 13. In addition, when the thickness T2 exceeds 0.6 times the width W1, the third copper layer on the first copper layer 11 around the through hole 13 may block the upper end of the through hole 13, and the growth of the third copper layer 20 on the second copper layer 12 exposed inside the through hole 13 may become insufficient.

[0091] To this end, by making the thickness T2 not less than 0.4 times the thickness T1 and not more than 0.6 times the width W1, the third copper layer 20 extending from the first copper layer 11 located around the through hole 13 along the inner wall surface of the through hole 13 and the third copper layer 20 extending from the second copper layer 12 exposed inside the through hole 13 along the inner wall surface of the through hole 13 are easily connected, and the third copper layer 20 can be appropriately formed on the inner wall surface of the through hole 13.

[0092] <Example>

[0093] In order to evaluate the influence of thickness T2, samples 1 to 8 were prepared. In samples 1 to 8, the ratio of thickness T2 to thickness T1 and the ratio of thickness T2 to width W1 changed. Details of samples 1 to 8 are shown in Table 1. In samples 1, 2, and 4 to 6, thickness T2 is greater than 0.4 times the thickness T1 and less than 0.6 times the width W1. On the other hand, in sample 3, thickness T2 is less than 0.4 times the thickness T1 and greater than 0.6 times the width W1. In sample 7, thickness T2 is less than 0.4 times the thickness T1, and in sample 8, thickness T2 exceeds 0.6 times the width W1.

[0094] [Table 1]

[0095] Table 1

[0096] sample 1 2 3 4 5 6 7 8 Thickness T1(μm) 12.5 25 125 100 25 35 100 25 Thickness T2(μm) 10 45 45 45 45 20 20 45 Width W1(μm) 25 100 70 250 80 50 50 50 Thickness T2 / Thickness T1 0.8 1.8 0.36 0.45 1.8 0.57 0.2 1.8 Thickness T2 / Width W1 0.4 0.45 0.64 0.18 0.56 0.4 0.4 0.9 Defective rate (%) 0 0 100 12 17 33 100 100

[0097] For samples 1 to 8, whether there is a break in the blind hole was observed. The defective rate in Table 1 is the ratio of blind holes that were not properly formed in each sample. As shown in Table 1, the defective rates in samples 1, 2, and 4 to 6 are lower than those in samples 3, 7, and 8.

[0098] As is clear from this comparison, by making the thickness T2 not less than 0.4 times the thickness T1 and not more than 0.6 times the width W1, the third copper layer 20 extending from the first copper layer 11 located around the through hole 13 along the inner wall surface of the through hole 13 and the third copper layer 20 extending from the second copper layer 12 exposed inside the through hole 13 along the inner wall surface of the through hole 13 are connected, and the third copper layer 20 is easily formed appropriately on the inner wall surface of the through hole 13.

[0099] In sample 1, thickness T2 is 0.8 times or more of thickness T1, while in sample 6, thickness T2 is 0.4 times or more and less than 0.8 times of thickness T1. The defective rate in sample 1 is lower than that in sample 6. In sample 2, thickness T2 is 0.45 times or less of width W1, while in sample 5, thickness T2 exceeds 0.45 times and is 0.6 times or less of width W1. The defective rate in sample 2 is lower than that in sample 5.

[0100] From these comparisons, it can be seen that when the condition that the thickness T2 is 0.8 times or more of the thickness T1 or the condition that the thickness T2 is 0.45 times or less of the width W2 is further satisfied, the third copper layer 20 extending from the first copper layer 11 located around the through hole 13 along the inner wall surface of the through hole 13 and the third copper layer 20 extending from the second copper layer 12 exposed inside the through hole 13 along the inner wall surface of the through hole 13 are further easily connected, and the third copper layer 20 can be further appropriately formed on the inner wall surface of the through hole 13.

[0101] (Second Embodiment)

[0102] A printed wiring board according to a second embodiment will be described. The printed wiring board according to the second embodiment is referred to as a printed wiring board 200 .

[0103] <Configuration of Printed Wiring Board 200>

[0104] Hereinafter, the configuration of the printed wiring board 200 will be described.

[0105] Fig.10 2 is a cross-sectional view of the printed wiring board 200. Fig.10 As shown, the printed wiring board 200 includes a first insulating layer 50 , a first copper layer 51 , an adhesive layer 60 , a second insulating layer 70 , a second copper layer 71 , and a third copper layer 80 .

[0106] The constituent material of the first insulating layer 50 has electrical insulation and flexibility. The constituent material of the first insulating layer 50 is, for example, polyimide. However, the constituent material of the first insulating layer 50 is not limited thereto. The first insulating layer 50 has a first main surface 50a. The first main surface 50a is a surface perpendicular to the thickness direction of the first insulating layer 50, and constitutes either the front surface or the back surface of the first insulating layer 50.

[0107] The constituent material of the first copper layer 51 is copper or a copper alloy. The first copper layer 51 is disposed on the first main surface 50a. The fourth copper layer 52 may be interposed between the first copper layer 51 and the first main surface 50a. In this case, the first copper layer 51 is an electrolytic copper plating layer.

[0108] The adhesive layer 60 is disposed on the first main surface 50a so as to cover the first copper layer 51 (and the fourth copper layer 52). The constituent material of the adhesive layer 60 is an adhesive. The constituent material of the adhesive layer 60 is, for example, an epoxy-based adhesive.

[0109] The constituent material of the second insulating layer 70 has electrical insulation and flexibility. The constituent material of the second insulating layer 70 is, for example, polyimide. However, the constituent material of the second insulating layer 70 is not limited thereto. The second insulating layer 70 has a second main surface 70a and a third main surface 70b. The second main surface 70a and the third main surface 70b are surfaces perpendicular to the thickness direction of the second insulating layer 70, and constitute the front and back surfaces of the second insulating layer 70. The third main surface 70b is a surface opposite to the second main surface 70a. The second insulating layer 70 is arranged on the adhesive layer 60 in a manner that the second main surface 70a faces the adhesive layer 60.

[0110] The constituent material of the second copper layer 71 is copper or a copper alloy. The second copper layer 71 is disposed on the third main surface 70b.

[0111] A through hole 72 is formed in the adhesive layer 60, the second insulating layer 70 and the second copper layer 71. The through hole 72 penetrates the adhesive layer 60, the second insulating layer 70 and the second copper layer 71 along the thickness direction. The first copper layer 51 is exposed from the through hole 72. The width of the through hole 72 at the third main surface 70b is set to width W2. The width W2 mentioned here is the minimum value of the width of the through hole 72 at the third main surface 70b. The minimum value of the width of the through hole 72 at the third main surface 70b refers to the diameter of the inscribed circle of the shape of the through hole 72 at the third main surface 70b when viewed from above. The width W2 is, for example, greater than 25μm and less than 250μm. The sum of the thickness of the second insulating layer 70 and the thickness of the adhesive layer 60 located between the first copper layer 51 and the second insulating layer 70 is set to thickness T3. The thickness T3 is, for example, greater than 12.5μm and less than 250μm. The thickness T3 is an average value obtained by measuring arbitrary ten points of the cross-sectional photograph. The shape of the through hole 72 in a plan view is, for example, a circle. However, the planar shape of the through hole 72 is not limited to this.

[0112] The third copper layer 80 is disposed on the first copper layer 51 exposed inside the through hole 72, on the inner wall surface of the through hole 72, and on the second copper layer 71 located around the through hole 72. The third copper layer 80 is also disposed on the second copper layer 71 located outside the periphery of the through hole 72. The constituent material of the third copper layer 80 is copper or a copper alloy. The third copper layer 80 may also be an electrolytic copper plating layer.

[0113] The concentration of palladium in the region of the third copper layer 80 from the interface between the first copper layer 51 and the third copper layer 80 exposed inside the through hole 72 to a depth of 10 nm is 0.5 mass % or less. The concentration of palladium in the region of the third copper layer 80 from the interface between the second insulating layer 70 (the inner wall surface of the through hole 72) and the third copper layer 80 to a depth of 10 nm is 0.5 mass % or less. The concentration of palladium in the region of the third copper layer 80 from the interface between the second copper layer 71 and the third copper layer 80 to a depth of 10 nm is 0.5 mass % or less. For example, the concentration of palladium in the region of the third copper layer 80 is measured by energy dispersive X-ray spectrometry for a cross section obtained by cutting a hole portion with a focused ion beam.

[0114] The thickness of the third copper layer 80 located on the second copper layer 71 is set to thickness T4. Thickness T4 is the average value obtained by measuring any ten points of the cross-sectional photograph. Thickness T4 can also be 0.4 times or more of thickness T3 and 0.6 times or less of width W2. Thickness T4 can also be 0.8 times or more of thickness T3 and 0.45 times or less of width W2. Thickness T4 is, for example, 10 μm or more and 45 μm or less.

[0115] The printed wiring board 200 may further include a fifth copper layer 53, a sixth copper layer 54, an adhesive layer 61, a third insulating layer 73, a seventh copper layer 74, and an eighth copper layer 81. A through hole 55 may be formed in the first insulating layer 50, the fourth copper layer 52, and the fifth copper layer 53. The through hole 55 penetrates the first insulating layer 50, the fourth copper layer 52, and the fifth copper layer 53 in the thickness direction.

[0116] The fourth main surface 50b is a surface perpendicular to the thickness direction of the first insulating layer 50 and is a surface opposite to the first main surface 50a. The fifth copper layer 53 is arranged on the fourth main surface 50b, and the constituent material of the fifth copper layer 53 is copper or a copper alloy. The sixth copper layer 54 is arranged on the fifth copper layer 53. The constituent material of the sixth copper layer 54 is copper or a copper alloy. The sixth copper layer 54 is an electrolytic copper plating layer. The first copper layer 51 and the sixth copper layer 54 are connected to each other on the inner wall surface of the through hole 55.

[0117] The adhesive layer 61 is disposed on the fourth main surface 50b so as to cover the fifth copper layer 53 and the sixth copper layer 54. The constituent material of the adhesive layer 61 is an adhesive. The constituent material of the adhesive layer 61 is, for example, an epoxy-based adhesive.

[0118] The constituent material of the third insulating layer 73 has electrical insulation and flexibility. The constituent material of the third insulating layer 73 is, for example, polyimide. However, the constituent material of the third insulating layer 73 is not limited thereto. The third insulating layer 73 has a fifth main surface 73a and a sixth main surface 73b. The fifth main surface 73a and the sixth main surface 73b are surfaces perpendicular to the thickness direction of the third insulating layer 73, forming the front and back surfaces of the third insulating layer 73. The sixth main surface 73b is a surface opposite to the fifth main surface 73a. The third insulating layer 73 is arranged on the adhesive layer 61 in such a manner that the fifth main surface 73a faces the adhesive layer 61.

[0119] The seventh copper layer 74 is made of copper or a copper alloy and is disposed on the sixth main surface 73 b.

[0120] A through hole 75 is formed in the adhesive layer 61, the third insulating layer 73 and the seventh copper layer 74. The through hole 75 penetrates the adhesive layer 61, the third insulating layer 73 and the seventh copper layer 74 in the thickness direction. The sixth copper layer 54 is exposed from the through hole 75. The width of the through hole 75 at the sixth main surface 73b is set to width W3. The width W3 mentioned here is the minimum value of the width of the through hole 75 at the sixth main surface 73b. "The minimum value of the width of the through hole 75 at the sixth main surface 73b" refers to the diameter of the inscribed circle of the shape of the through hole 75 at the sixth main surface 73b when viewed from above. The width W3 is, for example, greater than 25μm and less than 250μm. The sum of the thickness of the third insulating layer 73 and the thickness of the adhesive layer 61 located between the sixth copper layer 54 and the third insulating layer 73 is set to thickness T5. The shape of the through hole 75 when viewed from above is, for example, circular. However, the planar shape of the through hole 75 is not limited to this. The thickness T5 is, for example, not less than 12.5 μm and not more than 250 μm. The thickness T5 is an average value obtained by measuring arbitrary ten points of the cross-sectional photograph.

[0121] The eighth copper layer 81 is disposed on the sixth copper layer 54 exposed inside the through hole 75, on the inner wall surface of the through hole 75, and on the seventh copper layer 74 located around the through hole 75. The eighth copper layer 81 is also disposed on the seventh copper layer 74 located outside the periphery of the through hole 75. The constituent material of the eighth copper layer 81 is copper or a copper alloy. The eighth copper layer 81 may also be an electrolytic copper plating layer.

[0122] The thickness of the eighth copper layer 81 located on the seventh copper layer 74 is set to thickness T6. The thickness T6 may be 0.4 times or more of the thickness T5 and 0.6 times or less of the width W3. The thickness T6 may be 0.8 times or more of the thickness T5 and 0.45 times or less of the width W3. The thickness T6 is, for example, 10 μm or more and 45 μm or less.

[0123] The concentration of palladium in the region of the eighth copper layer 81 from the interface between the sixth copper layer 54 and the eighth copper layer 81 exposed inside the through hole 75 to a depth of 10 nm is 0.5 mass % or less. The concentration of palladium in the region of the eighth copper layer 81 from the interface between the third insulating layer 73 (the inner wall surface of the through hole 75) and the eighth copper layer 81 to a depth of 10 nm is 0.5 mass % or less. It should be noted that the concentration of palladium in the region of the eighth copper layer 81 from the interface between the seventh copper layer 74 and the eighth copper layer 81 to a depth of 10 nm is 0.5 mass % or less. For example, the concentration of palladium in the region of the eighth copper layer 81 is measured by energy dispersive X-ray spectroscopy for a cross section obtained by cutting a hole portion with a focused ion beam.

[0124] It should be noted that Fig.10 The printed wiring board 200 shown has circuits formed on both sides of the first insulating layer 50, and includes two through holes (through hole 72 and through hole 75) connected to each other, but the printed wiring board of the present disclosure is not limited to this. It can also be a combination of multiple single-sided substrates, and the circuit can also include more than two layers, more than three layers, or more than six layers.

[0125] <Method of Manufacturing Printed Wiring Board 200>

[0126] Hereinafter, a method for manufacturing printed wiring board 200 will be described.

[0127] Fig.11 2 is a manufacturing process diagram of the printed wiring board 200. Fig.11 As shown, the method for manufacturing the printed wiring board 200 includes a preparation step S11 , a first hole forming step S12 , a first resist pattern forming step S13 , a first electrolytic plating step S14 , a first resist pattern removing step S15 , and a first etching step S16 .

[0128] The method for manufacturing the printed wiring board 200 further includes an insulating layer pasting step S17 , a second hole opening step S18 , a second resist pattern forming step S19 , a second electrolytic plating step S20 , a second resist pattern removing step S21 , and a second etching step S22 .

[0129] Fig.12 is a cross-sectional view illustrating the preparation step S11. Fig.12 As shown, in the preparation step S11, the first insulating layer 50 is prepared. The first insulating layer 50 prepared in the preparation step S11 has a fourth copper layer 52 arranged on the first main surface 50a, and a fifth copper layer 53 arranged on the fourth main surface 50b. At this stage, the through hole 55 is not formed in the first insulating layer 50, the fourth copper layer 52, and the fifth copper layer 53.

[0130] The first hole-forming step S12 is performed after the preparation step S11. Fig.13 2 is a cross-sectional view illustrating the first hole-opening step S12. Fig.13 As shown, in the first hole forming step S12, a through hole 55 is formed. The through hole 55 is formed by, for example, irradiating a laser.

[0131] The first resist pattern forming step S13 is performed after the first hole opening step S12. Fig.14 2 is a cross-sectional view illustrating the first resist pattern forming step S13. Fig.14 As shown, in the first resist pattern forming step S13, the resist pattern 31 is formed on the fourth copper layer 52, and the resist pattern 32 is formed on the fifth copper layer 53. The resist pattern 31 and the resist pattern 32 are formed by, for example, pasting a dry film resist, exposing and developing the pasted dry film resist.

[0132] The first electrolytic plating step S14 is performed after the first resist pattern forming step S13 . Fig.15 2 is a cross-sectional view illustrating the first electrolytic plating step S14. Fig.15 As shown, in the first electrolytic plating step S14, the first copper layer 51 is formed on the fourth copper layer 52 exposed from the opening of the resist pattern 31 by electrolytic plating, and the sixth copper layer 54 is formed on the fifth copper layer 53 exposed from the opening of the resist pattern 32. In addition, by the growth of the first copper layer 51 and the sixth copper layer 54, the first copper layer 51 and the sixth copper layer 54 are connected to each other at the through hole 55 and integrated.

[0133] The first resist pattern removal step S15 is performed after the first electrolytic plating step S14. Fig.16 1 is a cross-sectional view illustrating the first resist pattern removal step S15. Fig.16 As shown, in the first resist pattern removal step S15 , the resist pattern 31 and the resist pattern 32 are removed.

[0134] The first etching step S16 is performed after the first resist pattern removal step S15 . Fig.17 is a cross-sectional view illustrating the first etching step S16. Fig.17 As shown, in the first etching step S16 , the fourth copper layer 52 located under the resist pattern 31 and the fifth copper layer 53 located under the resist pattern 32 are removed by etching.

[0135] The insulating layer pasting step S17 is performed after the first etching step S16. Fig.18 2 is a cross-sectional view illustrating the insulating layer pasting step S17. Fig.18As shown, in the insulating layer pasting step S17, the second insulating layer 70 and the third insulating layer 73 are pasted. In the insulating layer pasting step S17, first, the uncured adhesive layer 60 is applied on the first main surface 50a in a manner covering the first copper layer 51 and the fourth copper layer 52, and the uncured adhesive layer 61 is applied on the fourth main surface 50b in a manner covering the fifth copper layer 53 and the sixth copper layer 54. Second, the second insulating layer 70 and the third insulating layer 73 are prepared. At this stage, the second copper layer 71 is arranged on the third main surface 70b, and the seventh copper layer 74 is arranged on the sixth main surface 73b.

[0136] Third, the second insulating layer 70 is disposed on the adhesive layer 60 so that the second main surface 70a faces the adhesive layer 60, and the third insulating layer 73 is disposed on the adhesive layer 61 so that the fifth main surface 73a faces the adhesive layer 61. Fourth, the second insulating layer 70 and the third insulating layer 73 are attached by heating and curing the adhesive layer 60 and the adhesive layer 61.

[0137] The second hole forming step S18 is performed after the insulating layer pasting step S17. Fig.19 2 is a cross-sectional view illustrating the second hole-opening step S18. Fig.19 As shown, in the second hole forming step S18, the through hole 72 and the through hole 75 are formed by, for example, irradiating with laser light.

[0138] The second resist pattern forming step S19 is performed after the second hole opening step S18. Fig. 20 2 is a cross-sectional view illustrating the second resist pattern forming step S19. Fig. 20 As shown, in the second resist pattern forming step S19, the resist pattern 33 is formed on the second copper layer 71, and the resist pattern 34 is formed on the seventh copper layer 74. The resist pattern 33 and the resist pattern 34 are formed by attaching a dry film resist, exposing and developing the attached dry film resist, for example.

[0139] The second electrolytic plating step S20 is performed after the second resist pattern forming step S19. Fig.21 2 is a cross-sectional view illustrating the second electrolytic plating step S20. Fig. 20 As shown, in the second electrolytic plating step S20, the third copper layer 80 is formed by electrolytic plating on the second copper layer 71 exposed from the opening of the resist pattern 33, the inner wall surface of the through hole 72, and the first copper layer 51 exposed inside the through hole 72. In addition, in the second electrolytic plating step S20, the eighth copper layer 81 is formed on the seventh copper layer 74 exposed from the opening of the resist pattern 34, the inner wall surface of the through hole 75, and the sixth copper layer 54 exposed inside the through hole 75.

[0140] The second resist pattern removal step S21 is performed after the second electrolytic plating step S20 . Fig. 22 2 is a cross-sectional view illustrating the second resist pattern removal step S21. Fig. 22 As shown, in the second resist pattern removal step S21, the resist pattern 33 and the resist pattern 34 are removed. The second etching step S22 is performed after the second resist pattern removal step S21. In the second etching step S22, the second copper layer 71 located under the resist pattern 33 and the seventh copper layer 74 located under the resist pattern 34 are removed by etching. By the above method, a Fig.10 A printed wiring board 200 of the structure shown.

[0141] <Effects of Printed Wiring Board 200>

[0142] Hereinafter, the effects of the printed wiring board 200 will be described.

[0143] In the method for manufacturing the printed wiring board 200, since the electroless plating step is not performed, palladium does not remain at the interface between the second insulating layer 70 (the inner wall surface of the through hole 72) and the third copper layer 80 and at the interface between the first copper layer 51 exposed inside the through hole 72 and the third copper layer 80. In addition, in the method for manufacturing the printed wiring board 200, foreign matter and the like located on the surface of the first copper layer 51 exposed inside the through hole 72 are removed by the development in the second resist pattern forming step S19 and the degreasing treatment before the second electrolytic plating step S20 is performed.

[0144] Thus, the printed wiring board 200 can prevent the third copper layer 80 from being broken in the blind via due to peeling of palladium, foreign matter, etc. For the same reason, the printed wiring board 200 can prevent the eighth copper layer 81 from being broken in the blind via due to peeling of palladium, foreign matter, etc.

[0145] The embodiments disclosed this time should be considered as illustrative in all aspects and not restrictive. The scope of the present invention is indicated by the claims rather than the embodiments described above, and is intended to include all modifications within the meaning and scope equivalent to the claims.

[0146] Description of Reference Numerals

[0147] 10 insulating layer; 10a first main surface; 10b second main surface; 11 first copper layer; 12 second copper layer; 13 through hole; 20 third copper layer; 30, 31, 32, 33, 34 resist pattern; 40 electroless copper plating layer; 50 first insulating layer; 50a first main surface; 50b fourth main surface; 51 first copper layer; 52 fourth copper layer; 53 fifth copper layer; 54 sixth copper layer; 55 through hole; 60, 61 adhesive layer; 70 second insulating layer; 70a second main surface; 70b third main surface; 71 second copper layer; 72 through hole; 73 third insulating layer; 73a fifth main surface; 73b sixth main surface; 74 seventh copper layer; 75 through hole; 80 third copper layer; 81 eighth copper layer; 100, 100A, 200 printed wiring board; S1 system Preparation process; S2 first etching process; S3 drilling process; S4 desmear process; S5 resist pattern forming process; S6 electrolytic plating process; S7 resist pattern removal process; S8 second etching process; S9 non-electrolytic plating process; S11 preparation process; S12 first drilling process; S13 first resist pattern forming process; S14 first electrolytic plating process; S15 first resist pattern removal process; S16 first etching process; S17 insulating layer pasting process; S18 second drilling process; S19 second resist pattern forming process; S20 second electrolytic plating process; S21 second resist pattern removal process; S22 second etching process; T1, T2, T3, T4, T5, T6 thickness; W1, W2, W3 width.

Claims

1. A printed wiring board comprising: An insulating layer having a first main surface and a second main surface; A first copper layer, disposed on the first main surface; A second copper layer is disposed on the second main surface; and The third copper layer, A through hole reaching the second copper layer is formed in the insulating layer and the first copper layer, The third copper layer is arranged on the second copper layer inside the through hole, on the inner wall surface of the through hole, and on the first copper layer located around the through hole. A single copper layer is disposed on the inner wall surface of the through hole, and the single copper layer is the third copper layer.

2. The printed wiring board according to claim 1, wherein The thickness of the third copper layer on the first copper layer is not less than 0.4 times the thickness of the insulating layer and not more than 0.6 times the minimum value of the width of the through hole in the first main surface.

3. The printed wiring board according to claim 1, wherein The thickness of the third copper layer on the first copper layer is not less than 0.8 times the thickness of the insulating layer and not more than 0.45 times the minimum value of the width of the through hole in the first main surface.

4. The printed wiring board according to any one of claims 1 to 3, wherein The concentration of palladium in a region of the third copper layer from an interface between the insulating layer and the third copper layer to a depth of 10 nm and in a region of the third copper layer from an interface between the second copper layer and the third copper layer to a depth of 10 nm is 0.5 mass % or less.

5. The printed wiring board according to any one of claims 1 to 4, wherein The third copper layer is an electrolytic copper plating layer.

6. A printed wiring board comprising: A first insulating layer having a first main surface; A first copper layer, disposed on the first main surface; an adhesive layer, arranged on the first main surface in a manner of covering the first copper layer; A second insulating layer having a second main surface and a third main surface, and arranged on the adhesive layer in a manner that the second main surface faces the adhesive layer; A second copper layer is disposed on the third main surface; as well as The third copper layer, A through hole reaching the first copper layer is formed in the second insulating layer, the second copper layer, and the adhesive layer. The third copper layer is disposed on the first copper layer inside the through hole, on the inner wall surface of the through hole, and on the second copper layer located around the through hole. A single copper layer is disposed on the inner wall surface of the through hole, and the single copper layer is the third copper layer.

7. The printed wiring board according to claim 6, wherein The thickness of the third copper layer on the second copper layer is greater than or equal to 0.4 times the sum of the thickness of the second insulating layer and the thickness of the adhesive layer between the first copper layer and the second insulating layer, and less than or equal to 0.6 times the minimum width of the through hole at the third main surface.

8. The printed wiring board according to claim 6, wherein The thickness of the third copper layer on the second copper layer is greater than or equal to 0.8 times the sum of the thickness of the second insulating layer and the thickness of the adhesive layer between the first copper layer and the second insulating layer, and less than or equal to 0.45 times the minimum width of the through hole at the third main surface.

9. The printed wiring board according to any one of claims 6 to 8, wherein The concentration of palladium in a region of the third copper layer from an interface between the second insulating layer and the third copper layer to a depth of 10 nm and in a region of the third copper layer from an interface between the first copper layer and the third copper layer to a depth of 10 nm is 0.5 mass % or less.

10. The printed wiring board according to any one of claims 6 to 9, wherein The third copper layer is an electrolytic copper plating layer.

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