Opus correction method, semiconductor apparatus, and semiconductor product

Abstract

The application provides an OPC correction method, a semiconductor device and a semiconductor product, relates to the technical field of semiconductor manufacturing, and solves the problem of low via rounding degree and easy short circuit after development and etching in the related art. According to the application, the target pattern of the corresponding via is adjusted by correcting the via layout design, the imaging contrast is improved, the imaging quality is improved, the spacing between the vias after development and etching is increased, the probability of the occurrence of sharp corners is reduced, and the risk of short circuit of the metal line is reduced. Moreover, the spacing between the vias is increased, the process window can be further expanded, and the competitiveness of the platform is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to an OPC correction method, semiconductor equipment, and semiconductor products. Background Technology

[0002] In the semiconductor field, the 55nm HV (High Voltage) platform refers to a high-voltage technology platform using a 55nm process. In the 55nm HV platform, the critical dimension (CD) and pitch (the distance between the centers of two adjacent cells) of the VIA (vertical conductive channel used to connect different metal layers in a chip) are designed to be 90nm and 180nm respectively, approaching the process limits of dry lithography machines.

[0003] In practical applications, the inventors discovered that due to the low imaging contrast of the platform, the roundness of the VIAs (vias) after development is relatively low. Sharp corners tend to appear between adjacent vias, pointing towards another via. After etching, these sharp corners further enlarge, leading to short circuits between adjacent vias. If the vias are located at the wafer edge, this results in a narrowing of the process window, further increasing the difficulty of process control during manufacturing. Summary of the Invention

[0004] This application provides an OPC correction method that solves the problem of low roundness of vias in related technologies, which easily leads to short circuits after development and etching. This solution can improve imaging contrast to enhance imaging quality, increase the spacing between vias after development and etching, reduce the probability of sharp corners, and lower the risk of short circuits in metal lines.

[0005] In a first aspect, this application provides an OPC correction method, which includes:

[0006] Determine the first target pattern of several corresponding through holes;

[0007] Based on the preset modification direction, the shape of the first target graphic is modified to obtain the second target graphic, and the area of ​​the second target graphic is equal to the area of ​​the first target graphic;

[0008] According to the preset OPC algorithm, each second target graphic is compensated and corrected to obtain the corrected graphic;

[0009] Based on the through holes after development and etching of the mask prepared by the modified pattern, determine whether the through holes corresponding to the modified pattern meet the preset spacing.

[0010] If the through-holes corresponding to the corrected pattern meet the preset spacing, the second target pattern is determined as the pattern of the corresponding through-hole.

[0011] Secondly, this application also provides a semiconductor device comprising:

[0012] One or more processors;

[0013] A storage device for storing one or more programs, which, when executed by one or more processors, cause the one or more processors to implement the OPC correction method provided in the first aspect above.

[0014] Thirdly, this application also provides a semiconductor product generated based on a mask fabricated from a pattern determined by the OPC correction method provided in the first aspect above.

[0015] This application's solution improves imaging contrast and quality by modifying the via layout design, thereby adjusting the target pattern of the corresponding vias. Furthermore, it increases the spacing between vias after development and etching, reducing the probability of sharp corners and lowering the risk of short circuits in the metal lines. Moreover, the increased spacing between vias further expands the process window, contributing to enhanced platform competitiveness. Attached Figure Description

[0016] Figure 1 This is a schematic diagram illustrating the steps of an OPC correction method provided in an embodiment of this application.

[0017] Figure 2 In related technologies, the target graphic is processed by OPC to obtain the corresponding mask graphic.

[0018] Figure 3 This is a schematic diagram illustrating the steps of modifying a target graphic according to an embodiment of this application.

[0019] Figure 4 This is a schematic diagram comparing a second target graphic and a first target graphic provided in an embodiment of this application.

[0020] Figure 5 This is a schematic diagram of the light intensity distribution curve corresponding to the target graphic generated according to relevant technologies.

[0021] Figure 6 This is a schematic diagram of the light intensity distribution curve corresponding to the target graphic generated according to the OPC correction method of this application.

[0022] Figure 7 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this application. Detailed Implementation

[0023] The embodiments of this application will be further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely illustrative of the embodiments of this application and are not intended to limit the scope of this application. Furthermore, it should be noted that, for ease of description, the accompanying drawings only show the parts related to the embodiments of this application, not all structures. Those skilled in the art, after reading this specification, should be able to conceive that any combination of technical features can constitute an optional implementation method, provided that the technical features do not contradict each other.

[0024] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects, not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class, not limited in number; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship. In the description of this application, "multiple" means two or more, and "several" means one or more.

[0025] In the semiconductor field, the CD and Pitch of vias in the 55nm HV platform approach the process limits of dry lithography machines, and the platform has low imaging contrast, resulting in low roundness of vias after development. Sharp corners tend to appear between adjacent vias, pointing towards another via. Moreover, these sharp corners are further enlarged after etching, making it easy for short circuits to occur between adjacent vias. In other words, after development and etching, the sharp corners between vias in the mask fabricated according to the layout design implemented by the relevant technology become more prominent, making short circuits extremely likely and leading to device damage.

[0026] In related technologies, immersion scanners are commonly used to achieve better roundness and DoF (Depth of Focus). However, this solution is limited to platforms developed by specific manufacturers, and its adoption increases process costs. Another approach is to modify the design rule to increase the pitch of the via, but this reduces the platform's competitiveness, especially for COT (Customer-Owned Tooling) projects. Using this solution can lead to incompatibility with customer processes, requiring customers to modify their designs, thus reducing the platform's competitiveness.

[0027] To address this, this application provides an OPC (Optical Proximity Correction) correction method. Figure 1 This diagram illustrates the steps of an OPC correction method provided in an embodiment of this application. The solution involves redesigning the layout of vias to correct the corresponding via patterns, thereby increasing the spacing between two etched vias and reducing the occurrence of sharp corners, thus lowering the risk of short circuits. The specific steps are as follows:

[0028] Step S110: Determine the first target pattern of several corresponding through holes.

[0029] The completed layout design contains the first target pattern corresponding to the via and the pattern corresponding to the trench to be etched. It can be inferred that the via is a vertical conductive channel used to connect different metal layers in the chip. Therefore, it is necessary to first determine several first target patterns corresponding to the via.

[0030] Step S120: Based on the preset modification direction, modify the shape of the first target graphic to obtain the second target graphic, the area of ​​the second target graphic is equal to the area of ​​the first target graphic.

[0031] The preset modification direction is pre-set for the location of the via. For example, this preset modification direction can be associated with the wiring direction of the metal interconnect layer where the via is located. Then, the shape of the first target pattern is modified along the preset modification direction, that is, the layout of the first target pattern is redesigned to modify its shape, thereby obtaining the second target pattern. The second target pattern is the pattern obtained after modifying the first target pattern, and both correspond to the same via. Furthermore, the area of ​​the second target pattern is equal to the area of ​​the first target pattern; that is, the area of ​​the pattern corresponding to the via remains unchanged before and after the modification. It can be understood that during the modification of the first target pattern, the first target pattern is modified based on the preset modification direction and the principle of unchanged area.

[0032] Step S130: According to the preset OPC algorithm, each second target graphic is compensated and corrected to obtain the corrected graphic.

[0033] Optical Proximity Correction (OPC) is a technique used to compensate for image errors caused by diffraction. It is primarily applied in the semiconductor device manufacturing process to ensure that the manufactured circuit matches the original design. As an algorithm pre-configured within semiconductor equipment to implement OPC technology, the OPC algorithm corrects image errors by moving the edges of the pattern on the mask or adding additional polygons, ensuring that the final etched pattern is identical to the original layout design. This is illustrated in the figure. Figure 2In related technologies, OPC is used to process a target graphic to obtain a corresponding mask graphic. The figure shows that the target graphics (T1 and T2 in the figure) are processed by OPC to obtain corresponding mask graphics (M1 and M2 in the figure), where the area of ​​the mask graphics is larger than that of the target graphics. The solution in this application also processes the second target graphic using OPC, specifically employing the OPC algorithm provided in related technologies, to compensate and correct the second target graphic, thereby obtaining the corrected graphic.

[0034] Step S140: Based on the through holes after development and etching of the mask prepared by the modified pattern, determine whether the through holes corresponding to the modified pattern meet the preset spacing.

[0035] Based on the modified pattern, a photomask is prepared. This photomask serves to verify whether the modified pattern meets the requirements. Based on this photomask, the vias after development and etching are determined. It can be understood that for the vias obtained after development and etching, a photolithography process is performed based on the photomask to form the vias, thereby obtaining an image including the via pattern to determine the spacing of the vias corresponding to the modified pattern. Alternatively, photolithography simulation software provided in related technologies can be used to simulate and generate the vias after development and etching based on the photomask, thereby determining the spacing of the vias corresponding to the modified pattern.

[0036] To address this, this solution also sets a corresponding preset spacing, which is used to determine whether the current modification meets the requirements, i.e., whether the spacing of the vias corresponding to the corrected pattern is greater than the preset spacing. It is conceivable that in some embodiments, two values ​​are set for the preset spacing, corresponding to an upper and lower limit, respectively, to avoid situations where the spacing is too large, resulting in excessive compression of the available space on the device surface, or where the spacing is too small, leading to short circuits. Therefore, the corresponding spacing should be greater than the lower limit and less than the upper limit to be considered to meet the preset spacing condition.

[0037] Step S150: If the through hole corresponding to the modified pattern meets the preset spacing, determine the second target pattern as the pattern of the corresponding through hole.

[0038] In the presence of multiple first target patterns, after verification in the above steps, if it is determined that the via corresponding to the modified pattern meets the preset spacing, it can be determined that modifying the first target icon corresponding to the via is feasible. Then, the second target pattern obtained by modifying the first target pattern is used as the pattern corresponding to the via, i.e., the second target pattern replaces the original first target pattern. Furthermore, by combining the compliant second target pattern with OPC processing, a corresponding modified pattern can be obtained to finally prepare the corresponding mask. Based on this, the final mask can prevent short circuits in the etched vias during semiconductor device fabrication.

[0039] As can be seen from the above solution, this approach improves imaging contrast and thus image quality by modifying the via layout design, thereby adjusting the target pattern of the corresponding vias. Furthermore, it increases the spacing between vias after development and etching, reducing the probability of sharp corners and lowering the risk of short circuits in the metal lines. Moreover, the increased spacing between vias further expands the process window, contributing to enhanced platform competitiveness.

[0040] Figure 3 This is a schematic diagram illustrating the steps of modifying a target pattern according to an embodiment of this application. In one embodiment, for the revision of the first target pattern, this solution can determine the direction of modification based on the metal interconnect layer and modify the first target pattern according to the principle of unchanged area. The specific steps are as follows:

[0041] Step S210: Compress the first target pattern according to the preset compression ratio along the first target direction perpendicular to the wiring direction of the metal interconnect layer on the first target pattern.

[0042] Step S220: Based on the area of ​​the first target pattern and the amount of compression in the first target direction, determine the amount of extension in the second target direction, where the second target direction is the wiring direction of the metal interconnect layer.

[0043] Step S230: Extend the first target graphic along the second target direction according to the extension amount.

[0044] It is understood that the corresponding compression amount can be determined according to a preset compression ratio. For example, if the preset compression ratio is 5%, then 5% of the original size is used as the compression amount. Then, according to this compression amount, the first target pattern is compressed along a first target direction, which is the direction on the first target pattern perpendicular to the wiring direction of the metal interconnect layer. It should be noted that in some embodiments, the preset compression ratio is greater than 0% and less than or equal to 10%, meaning the upper limit of the compression amount is 10% of the original size.

[0045] However, in the layout design of vias, they are usually set in a square shape. Therefore, when modifying the first target pattern, after compressing the first target pattern based on the first target direction, in order to make the second target pattern consistent with the first target pattern in terms of area, the first target pattern is extended in another direction, such as extending the first target pattern along the second target direction, thereby obtaining the second target pattern. The second target direction is the wiring direction of the metal interconnect layer, which is perpendicular to the first target direction.

[0046] It can be conceivable that the amount of extension in the second target direction can be determined based on the area of ​​the first target graphic (i.e., the area before modification) and the amount of compression. That is, the area reduced due to compression in the first target direction can be increased by extending in the second target direction to gain an equivalent area; or, based on the compressed size in the first target direction and the initial area of ​​the first target graphic, the extended size can be determined, and then the amount of extension in the second target direction can be determined by comparing it with the initial size. Therefore, extending the first target graphic along the second target direction according to this amount of extension will keep the area unchanged.

[0047] For example, Figure 4 This is a comparative diagram of a second target graphic and a first target graphic provided in an embodiment of this application. As shown in the figure, the solid line corresponds to the second target graphic, and the dashed line corresponds to the first target graphic. In modifying the first target graphic, compression is first performed along the first target direction, such as along the X-axis direction as shown in the figure, and according to a preset compression ratio. In the figure, the two ends of the side corresponding to the X-axis direction are compressed inwards. Optionally, in one embodiment, only one end of this side can be compressed, such as compressing the end of the target graphic close to the other through hole. Additionally, it extends along the second target direction (the Y-axis direction in the figure) to obtain the second target graphic.

[0048] Therefore, based on the preset compression ratio and the area of ​​the graphic, the corresponding compression and extension amounts can be determined, thereby better modifying the target graphic to obtain a new graphic of the corresponding size, which helps to improve the imaging contrast, so as to increase the spacing between the through holes and reduce the probability of sharp corners.

[0049] In some embodiments, the second target pattern is classified into different types depending on the region where the via is located. For example, the second target pattern located in a dense region can be determined as a dense pattern, and the second target pattern located in a sparse region can be determined as an isolated pattern. The dense region is a region in which there are more than a preset number of patterns, while the sparse region is a region in which there are fewer than a preset number of patterns.

[0050] Furthermore, when the second target pattern is a pattern located in a dense region, the metal line spacing between adjacent vias is obtained. If the metal line spacing is greater than the minimum distance, it is determined that the vias corresponding to the corrected pattern meet the preset spacing; while if the metal line spacing is less than or equal to the minimum distance, it is determined that the vias corresponding to the corrected pattern do not meet the preset spacing.

[0051] However, in order to further avoid short circuits in the vias corresponding to the modified pattern, if the vias corresponding to the modified pattern do not meet the preset spacing, the first target pattern needs to be modified again. That is, the modification scheme according to the preset compression ratio cannot prevent short circuits in the vias obtained by generating a mask and completing development and etching according to the modified pattern. In this regard, the corresponding compression amount and extension amount can be re-determined to modify the shape of the first target pattern.

[0052] For example, in cases where the modified vias still do not meet the preset spacing, in some embodiments, it is necessary to determine the metal wire spacing and the corresponding minimum distance between adjacent vias. This allows for the determination of the corresponding compression and extension amounts based on the metal wire spacing and the minimum distance, thereby modifying the shape of the first target pattern based on the preset modification direction to obtain a new second target pattern. It is conceivable that after obtaining the new second target pattern, steps S140 and S150 described above should also be executed to determine whether the new second target pattern can be used as a replacement for the first target pattern.

[0053] Optionally, in one embodiment, similarly, during the process of modifying the first target pattern, it is still necessary to maintain the same area for both the first and second target patterns. Then, based on the difference between the metal line spacing and the minimum distance, the single-sided compression amount and single-sided extension amount of the first target pattern in the first target direction and the second target direction are re-determined. It is conceivable that the single-sided compression amount and single-sided extension amount correspond to the compression and extension amounts of different sides, respectively. Therefore, when compressing, the two opposite sides of the first target pattern in the first target direction are compressed according to the single-sided compression amount; and when extending, the two opposite sides of the first target pattern in the second target direction are extended according to the single-sided extension amount.

[0054] In other words, when modifying the first target graphic, this solution compresses the two sides corresponding to the first target direction inward to shorten the size of the first target graphic in the first target direction, and extends the two sides corresponding to the second target direction outward to lengthen the size of the first target graphic in the second target direction, thereby obtaining a new second target graphic.

[0055] Therefore, after verification, the unsatisfactory graphics are modified again. This solution can obtain graphics dimensions that meet the requirements more effectively, thereby reducing the probability of sharp corners and the possibility of short circuits between through holes, which helps to ensure product safety.

[0056] For example, in one embodiment, during the subsequent modification process, based on the obtained metal wire spacing d1 and minimum distance d0, one-quarter of the difference between the two is used as the unilateral compression amount, that is, the total compression amount is half of this difference, and the total compression amount is twice the unilateral compression amount. Based on this, the determined unilateral compression amount is:

[0057]

[0058] To ensure that the modified second target shape has the same area as the original first target shape, the corresponding extension amount can be determined by the area and the aforementioned unilateral compression amount. For example, if the initial first target shape is a square with a side length of d2, then the total extension amount ∆C2 and the unilateral extension amount ∆C3 are:

[0059]

[0060]

[0061] Figure 5 The figure shows a schematic diagram of the light intensity distribution curve corresponding to the target pattern generated according to relevant technologies. The horizontal axis represents distance, and the vertical axis represents light intensity. The first target pattern 101 is generated according to relevant technologies and processed by OPC to obtain the first mask pattern 102, and the spacing between the two vias is 58nm. Moreover, the presence of a relatively high light intensity between the two vias will have two adverse effects on the photolithography process: first, the contrast is low, which easily produces sharp corners; second, it leads to a reduction in the PR (Photo Resist) thickness at this location, which reduces the blocking ability during etching and causes the sharp corners to be aggravated after etching.

[0062] Figure 6The figure shows a schematic diagram of the light intensity distribution curve corresponding to the target pattern generated according to the OPC correction method of this application. As shown, the first target pattern is corrected according to the scheme of this application to obtain the second target pattern 201, and then processed by OPC to obtain the second mask pattern 202, with the spacing between the two vias being 87.5 nm. After correction, the light intensity of the position between the vias is reduced relative to the design of related technologies, thereby improving the contrast. This is reflected by NILS (Normalization Image Log Slope), which characterizes the contrast. The increase in contrast improves the imaging quality and reduces the probability of sharp corners. At the same time, the increase in the spacing between the vias (from the original 58 nm to 87.5 nm) can effectively reduce the risk of short circuits in the metal lines, thereby improving the process window.

[0063] It should be noted that in some embodiments, when the determined total compression amount is greater than 10% of the target size of the through hole, the value of the total compression amount is set to 10% of the target size of the through hole to redetermine the unilateral compression amount.

[0064] This application also provides a semiconductor device for executing the OPC correction method provided in the above embodiments, and has corresponding functional modules and beneficial effects for executing the method. As shown in the figure... Figure 7 This is a schematic diagram of a semiconductor device provided in an embodiment of this application. The semiconductor device includes a processor 301, a memory 302, an input device 303, and an output device 304. The number of processors 301 can be one or more; the figure shows one processor 301 as an example. The processor 301, memory 302, input device 303, and output device 304 can be connected via a bus or other means; the figure shows a bus connection as an example. The memory 302, as a computer-readable storage medium, can be used to store software programs, computer-executable programs, and modules, such as the program instructions / modules corresponding to the OPC correction method in this embodiment. The processor 301 executes various corresponding functional applications and data processing by running the software programs, instructions, and modules stored in the memory 302, thereby implementing the aforementioned OPC correction method.

[0065] The memory 302 may primarily include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data recorded or created during use. Furthermore, the memory 302 may include high-speed random access memory and non-volatile memory, such as at least one disk storage device, flash memory device, or other non-volatile solid-state storage device. In some embodiments, the memory 302 may further include memory remotely located relative to the processor 301, which can be connected to the device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0066] The input device 303 can be used to input corresponding digital or character information to the processor 301, and to generate key signal inputs related to the user settings and function control of the device; the output device 304 can be used to send or display key signal outputs related to the user settings and function control of the device.

[0067] This application also provides a semiconductor product, which is generated based on a mask fabricated using the pattern determined by the OPC correction method provided in the above embodiments. The mask may include semiconductor devices such as chips and switching transistors. It is understood that the target patterns of the corresponding vias on the fabricated mask have been modified so that the spacing between adjacent vias is increased after development and etching, reducing the probability of sharp corners appearing between adjacent vias on the semiconductor device. It also reduces the risk of short circuits in the metal lines and ensures the safety of the device.

[0068] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0069] Note that the above are merely preferred embodiments and the technical principles employed in this application. Those skilled in the art will understand that this application is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of this application. Therefore, although this application has been described in detail through the above embodiments, this application is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of this application, the scope of which is determined by the scope of the appended claims.

Claims

1. An OPC correction method, characterized in that, include: Determine the first target pattern of several corresponding through holes; Based on a preset modification direction, the shape of the first target graphic is modified to obtain a second target graphic, the area of ​​the second target graphic being equal to the area of ​​the first target graphic; According to the preset OPC algorithm, each of the second target graphics is compensated and corrected to obtain the corrected graphics; Based on the through holes after development and etching of the mask prepared by the modified pattern, determine whether the through holes corresponding to the modified pattern meet the preset spacing. If the through-holes corresponding to the modified pattern meet the preset spacing, the second target pattern is determined as the pattern corresponding to the through-holes; The step of modifying the shape of the first target graphic based on a preset modification direction to obtain the second target graphic includes: According to a preset compression ratio, the first target pattern is compressed along a first target direction that is perpendicular to the wiring direction of the metal interconnect layer on the first target pattern; Based on the area of ​​the first target pattern and the amount of compression in the first target direction, the amount of extension in the second target direction is determined, where the second target direction is the wiring direction of the metal interconnect layer. The first target graphic is extended along the second target direction according to the extension amount.

2. The OPC correction method according to claim 1, characterized in that, The preset compression ratio is greater than 0% and less than or equal to 10%.

3. The OPC correction method according to claim 1, characterized in that, Based on the vias etched after development of the mask prepared by the modified pattern, determining whether the vias corresponding to the modified pattern meet the preset spacing includes: When the second target pattern is a pattern located in a dense region, the metal line spacing between adjacent vias is obtained; When the metal wire spacing is greater than the minimum distance, it is determined that the through hole corresponding to the corrected pattern meets the preset spacing; If the spacing between the metal wires is less than or equal to the minimum distance, it is determined that the through-hole corresponding to the corrected pattern does not meet the preset spacing.

4. The OPC correction method according to any one of claims 1-3, characterized in that, The method further includes: If the through holes corresponding to the corrected pattern do not meet the preset spacing, obtain the metal line spacing between adjacent through holes and the corresponding minimum distance. Based on the metal wire spacing and the minimum distance, the shape of the first target graphic is modified again in the preset modification direction to obtain a new second target graphic.

5. The OPC correction method according to claim 4, characterized in that, The step of modifying the shape of the first target graphic in the preset modification direction according to the metal wire spacing and the minimum distance to obtain a new second target graphic includes: Based on the difference between the metal wire spacing and the minimum distance, the unilateral compression amount of the first target pattern in the first target direction and the unilateral extension amount in the second target direction are re-determined. Based on the single-sided compression amount and the single-sided extension amount, the two opposite sides of the first target graphic in the first target direction are compressed respectively, and the two opposite sides of the first target graphic in the second target direction are extended respectively, so as to obtain a new second target graphic.

6. The OPC correction method according to claim 5, characterized in that, The step of redetermining the unilateral compression and unilateral extension of the first target pattern in the first target direction based on the difference between the metal wire spacing and the minimum distance includes: One-quarter of the difference is taken as the unilateral compression amount; Based on the area of ​​the first target graphic and the unilateral compression amount, the total extension amount of the first target graphic corresponding to the second target direction is determined, so as to determine the unilateral extension amount.

7. The OPC correction method according to claim 5 or 6, characterized in that, The method further includes: If the total compression is greater than 10% of the target size of the through hole, the value of the total compression is set to 10% of the target size of the through hole to redetermine the single-sided compression, wherein the total compression is twice the single-sided compression.

8. A semiconductor device, characterized in that, include: One or more processors; A storage device for storing one or more programs, which, when executed by one or more said processors, cause the one or more said processors to implement the OPC correction method as described in any one of claims 1-7.

9. A semiconductor product, characterized in that, The semiconductor product is generated based on a mask fabricated from a pattern determined by the OPC correction method according to any one of claims 1-7.

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