Method and device for verifying renaming, electronic equipment and storage medium

Abstract

The invention provides a renaming verification method which comprises the steps that a verification environment of a renaming component is constructed, the verification environment comprises a simulated register file, and the simulated register file is used for storing instruction information interacting with the renaming component; the instruction information at least comprises release information and / or data information; distributing a first instruction identifier for the first instruction; generating input information based on the first instruction and the first instruction identifier; the renaming component determines a first physical register allocated for the first instruction based on the input information; and verifying the renaming component based on the instruction information in the simulated register file.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a method, device, electronic device and storage medium for verifying renaming. Background Art

[0002] Register renaming is the process of mapping the same logical register to different physical registers. In order to verify the correctness of register renaming, it is usually necessary to build a reference model of the renamed component; when the register renaming algorithm of the reference model (Refercence Model, RFM) is completely consistent with the register renaming algorithm of the design under test (DUT), the correctness of register renaming or renamed components can be accurately verified.

[0003] With the evolution and development of processor cores, the design of renaming components has become more complex, and the design differences between different processor cores have become more and more significant, making it difficult to keep the register renaming algorithm of RFM consistent with the register renaming algorithm of DUT, and unable to guarantee the accuracy of verifying the renaming components. Summary of the invention

[0004] The embodiments of the present application provide a method, device, electronic device and storage medium for verifying renaming, which can improve the accuracy of verifying renaming components.

[0005] The technical solution of the embodiment of the present application is implemented as follows:

[0006] In a first aspect, an embodiment of the present application provides a method for verifying renaming, the method comprising: constructing a verification environment for a renaming component, the verification environment comprising a simulated register file, the simulated register file being used to store instruction information for interacting with the renaming component; the instruction information comprising at least release information and / or data information; assigning a first instruction identifier to a first instruction; generating input information based on the first instruction and the first instruction identifier; the renaming component determining, based on the input information, a first physical register assigned to the first instruction; and verifying the renaming component based on the instruction information in the simulated register file.

[0007] In some embodiments, the verifying the renaming component based on the instruction information in the simulated register file includes:

[0008] The first instruction is a write instruction, and searching for a release flag bit corresponding to the first register in the release information stored in the simulated register file;

[0009] If the release flag bit indicates that the first register is in an idle state, verifying that the renaming process of the first instruction by the renaming component is correct;

[0010] If the release flag bit indicates that the first register is in a non-idle state, it is verified that the renaming process of the first instruction performed by the renaming component is incorrect.

[0011] In some embodiments, if the result of verifying the renaming component is that the renaming process of the renaming component for the first instruction is correct, the method further includes:

[0012] The first instruction identifier and related information of the first instruction are written into a register file.

[0013] In some embodiments, the verifying the renaming component based on the instruction information in the simulated register file includes:

[0014] The first instruction is a read instruction, and the corresponding first data information is searched in the simulated register file;

[0015] Based on the first physical register, searching for corresponding second data information in data information stored in a preset reference model register file;

[0016] The renaming component is verified based on the first data information and the second data information.

[0017] In some embodiments, the first data information and the second data information each include at least one of the following:

[0018] The register number, the second instruction identifier corresponding to the first instruction, the input data and the release mark bit are read.

[0019] In some embodiments, the verifying the renamed component based on the first data information and the second data information includes:

[0020] Comparing the first data information with the second data information;

[0021] If the first data information is completely consistent with the second data information, verifying that the renaming process of the renaming component for the first instruction is correct;

[0022] If the first data information is not completely consistent with the second data information, it is verified that the renaming process of the first instruction by the renaming component is incorrect.

[0023] In a second aspect, an embodiment of the present application provides a device for verifying renaming, the device for verifying renaming comprising:

[0024] A construction unit, configured to construct a verification environment for the renaming component, wherein the verification environment includes a simulated register file, and the simulated register file is used to store instruction information for interacting with the renaming component; the instruction information includes at least release information and / or data information;

[0025] An allocating unit, configured to allocate a first instruction identifier to the first instruction;

[0026] A generating unit, configured to generate input information based on the first instruction and the first instruction identifier;

[0027] The renaming component is used to determine a first physical register allocated to the first instruction based on the input information;

[0028] A verification unit is used to verify the renaming component based on the instruction information in the simulated register file.

[0029] In some embodiments, the first instruction is a write instruction, and the verification unit is specifically used to search for a release mark bit corresponding to the first register in the release information stored in the simulated register file; if the release mark bit indicates that the first register is in an idle state, then verify that the renaming process of the renaming component for the first instruction is correct; if the release mark bit indicates that the first register is in a non-idle state, then verify that the renaming process of the renaming component for the first instruction is incorrect.

[0030] In some embodiments, if the result of verifying the renaming component is that the renaming process of the renaming component for the first instruction is correct, the device for verifying renaming also includes: a processing unit, which is used to write the first instruction identifier and related information of the first instruction into a register file.

[0031] In some embodiments, the first instruction is a read instruction, and the verification unit is specifically used to search for corresponding first data information in the simulated register file; based on the first physical register, search for corresponding second data information in the data information stored in the preset reference model register file; based on the first data information and the second data information, verify the renaming component.

[0032] In some embodiments, the first data information and the second data information each include at least one of the following: a read register number, a second instruction identifier corresponding to the first instruction, input data, and a release mark bit.

[0033] In some embodiments, the verification unit is specifically used to compare the first data information with the second data information; if the first data information is completely consistent with the second data information, then verify that the renaming process of the renaming component for the first instruction is correct; if the first data information is not completely consistent with the second data information, then verify that the renaming process of the renaming component for the first instruction is incorrect.

[0034] In a third aspect, an embodiment of the present application provides an electronic device, the electronic device comprising:

[0035] at least one processor; and

[0036] a memory communicatively connected to the at least one processor; wherein,

[0037] The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the above-mentioned verification renaming method.

[0038] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium storing computer instructions, wherein the computer instructions are used to enable the computer to execute the above-mentioned verification renaming method.

[0039] In a fifth aspect, an embodiment of the present application provides a computer program product, including a computer program / instruction, which implements the above-mentioned verification renaming method when executed by a processor.

[0040] The method for verifying renaming provided by an embodiment of the present application includes: constructing a verification environment for a renaming component, the verification environment includes a simulated register file, the simulated register file is used to store instruction information for interacting with the renaming component; the instruction information includes at least release information and / or data information; assigning a first instruction identifier to a first instruction; generating input information based on the first instruction and the first instruction identifier; the renaming component determines the first physical register assigned to the first instruction based on the input information; and verifies the renaming component based on the instruction information in the simulated register file. The method for verifying renaming provided by the present application adjusts the content of the simulated register file, and can verify the renaming component according to the content of the simulated register file. When verifying the renaming component, there is no requirement for the consistency between the register renaming algorithm of the RFM and the register renaming algorithm of the DUT, which can improve the accuracy of verifying the renaming component. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 It is a processing flow diagram of the method for verifying renaming provided in an embodiment of the present application;

[0042] Figure 2 is a schematic diagram of a physical register table entry provided in an embodiment of the present application;

[0043] Figure 3 It is a schematic diagram of an overall implementation of the verification renaming method provided in an embodiment of the present application;

[0044] Figure 4 It is a schematic diagram of the composition structure of the device for verifying renaming provided in an embodiment of the present application;

[0045] Figure 5 It is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0046] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings. The described embodiments should not be regarded as limiting the present application. All other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of this application.

[0047] In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it can be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0048] In the following description, the terms "first\second" involved are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that "first\second" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0049] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0050] It should be understood that in the various embodiments of the present application, the size of the serial number of each implementation process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0051] Before further describing the embodiments of the present application in detail, the nouns and terms involved in the embodiments of the present application are explained. The nouns and terms involved in the embodiments of the present application are subject to the following interpretations.

[0052] 1) Renaming, also known as register renaming, is to map logical registers to physical registers and allow logically identical registers to be mapped to different physical registers at different time points.

[0053] 2) Verification environment refers to the environment used to test and verify the correctness and stability of the software system. The verification environment includes a combination of software, hardware, and network environment to ensure the normal operation of the software on different platforms and under different conditions. The role of the verification environment is to simulate actual usage scenarios, discover and fix errors and defects in the software, and ensure that the software achieves the expected performance and stability before formal deployment.

[0054] 3) Register file, also known as register file, is an array of multiple registers in the central processing unit (CPU), usually implemented by fast static random read-write memory (SRAM).

[0055] The verification renaming method provided in the embodiment of the present application can at least solve the above problems.

[0056] A processing flow diagram of a method for verifying renaming provided in an embodiment of the present application is as follows: Figure 1 As shown, at least the following steps are included:

[0057] Step S101 : constructing a verification environment for the renaming component, wherein the verification environment includes a simulated register file, and the simulated register file is used to store instruction information for interacting with the renaming component; the instruction information at least includes release information and / or data information.

[0058] In some embodiments, the release information may include a release flag bit corresponding to each register, and the value corresponding to the release flag bit is used to indicate whether the register is in an idle state. As an example, if the value corresponding to the release flag bit is 0, it indicates that the register corresponding to the release flag bit is not in an idle state; if the value corresponding to the release flag bit is 1, it indicates that the register corresponding to the release flag bit is in an idle state.

[0059] In some embodiments, the data information may be RFM data read from a simulated register file according to a read instruction.

[0060] In the embodiment of the present application, it is necessary to add release information and data information items to the physical register table items in the verification environment. A schematic diagram of a physical register table item, such as Figure 2As shown, the physical register table entries include the physical register table entries of the reference model and the physical register table entries of the model to be verified. Among them, the physical register table entries of the reference model include: the register number (rfm_ptag) of the reference model, the reference model instruction identifier (rfm_uid), the reference model data information (rfm_data) and the reference model release information (rfm_re_v); among them, rfm_ptag is used to identify the physical register, and different physical registers correspond to different rfm_ptags. Rfm_uid is used to identify the instructions input to the reference model, and different instructions correspond to different rfm_uids. Rfm_data is used to identify the data information output after the instruction passes through the reference model. Rfm_re_v is used to identify the idle state of the physical register. The physical register table entry of the model to be verified includes: the register number of the model to be verified (dut_ptag), the instruction identifier of the model to be verified (dut_uid), the data information of the model to be verified (dut_data) and the release information of the model to be verified (dut_re_v); wherein, dut_ptag is used to identify the physical register, and different physical registers correspond to different dut_ptags. dut_uid is used to identify the instruction input to the model to be verified, and different instructions correspond to different dut_uids. dut_data is used to identify the data information output by the instruction after passing through the model to be verified. dut_re_v is used to identify the idle state of the physical register.

[0061] Step S102: assign a first instruction identifier to the first instruction.

[0062] In some embodiments, the first instruction may be an instruction for writing data or an instruction for reading data; each instruction corresponds to a unique identifier (User Identification, UID), and the UID corresponding to the first instruction is the first instruction identifier. The first instruction is input into the renaming component and the reference model respectively, and the information output by the renaming component for the first instruction carries the first instruction identifier, and the information output by the reference model for the first instruction also carries the first instruction identifier. The instruction association between the information output by the renaming component and the reference model can be determined through the first instruction identifier.

[0063] In an embodiment of the present application, the UID corresponding to each instruction can be generated by accumulating one by one in the order of instructions during the register renaming process.

[0064] Step S103: Generate input information based on the first instruction and the first instruction identifier.

[0065] In some embodiments, a write data generation logic may be constructed, and input information may be generated by using the write data generation logic; specifically, the write data generation logic generates input information based on the first instruction and the first instruction identifier. The input information is input to the renaming component and the reference model respectively; in this way, it is ensured that the values ​​of different UIDs input to the renaming component are different, and the data (such as the first instruction) for the same UID in the renaming component and the reference model are the same.

[0066] Step S104: The renaming component determines a first physical register allocated to the first instruction based on the input information.

[0067] In some embodiments, if the first instruction corresponding to the input information is a write instruction, the first physical register allocated to the first instruction is a write register; if the first instruction corresponding to the input information is a read instruction, the first physical register allocated to the first instruction is a read register.

[0068] Step S105 , verifying the renaming component based on the instruction information in the simulated register file.

[0069] In some embodiments, if the first instruction is a write instruction, the instruction information may include release information, and the release flag corresponding to the first register is searched in the release information stored in the simulated register file. The value corresponding to the release flag is used to indicate whether the register is in an idle state. As an example, if the value corresponding to the release flag is 0, it indicates that the register corresponding to the release flag is not in an idle state; if the value corresponding to the release flag is 1, it indicates that the register corresponding to the release flag is in an idle state.

[0070] If the release flag indicates that the first register is in an idle state, the first register can be allocated for use, and it is verified that the renaming process of the renaming component for the first instruction is correct. If the release flag indicates that the first register is in a non-idle state, the first register cannot be allocated for use, and it is verified that the renaming process of the renaming component for the first instruction is incorrect.

[0071] If the renaming process of the renaming component for the first instruction is verified to be correct, the renaming verification method provided by the embodiment of the present application may further include: writing the first instruction identifier and related information of the first instruction into a register file. In this case, the related information of the first instruction may include: execution unit information of the first instruction.

[0072] In the case where the first instruction is a write instruction, the first register is the destination register for the data to be written.

[0073] In other embodiments, if the first instruction is a read instruction, the instruction information may include data information, and the corresponding first data information is searched in the simulated register file; based on the first physical register, the corresponding second data information is searched in the data information stored in the preset reference model register file; based on the first data information and the second data information, the renaming component is verified.

[0074] The first data information and the second data information each include at least one of the following: a read register number, a second instruction identifier corresponding to the first instruction, input data, and a release mark bit.

[0075] In a specific implementation, based on the first data information and the second data information, the specific implementation process of verifying the renaming component may include: comparing the first data information with the second data information; if the first data information is completely consistent with the second data information, verifying that the renaming process of the renaming component for the first instruction is correct; if the first data information is not completely consistent with the second data information, verifying that the renaming process of the renaming component for the first instruction is incorrect.

[0076] The first data information is completely consistent with the second data information, which means that all contents included in the first data information are consistent with all contents included in the second data information. As an example, if the first data information and the second data information both include a read register number, a second instruction identifier, and input data, and the read register number included in the first data information is the same as the read register number included in the second data information, the second instruction identifier included in the first data information is the same as the second instruction identifier included in the second data information, and the input data included in the first data information is the same as the input data included in the second data information, then the first data information is completely consistent with the second data information.

[0077] Among them, the first data information is not completely consistent with the second data information means that at least one item of all the contents included in the first data information is different from that in the second data information. As an example, if the first data information and the second data information both include a read register number, a second instruction identifier and input data, and the read register number included in the first data information is different from the read register number included in the second data information, the second instruction identifier included in the first data information is the same as the second instruction identifier included in the second data information, and the input data included in the first data information is the same as the input data included in the second data information, then the first data information is not completely consistent with the second data information. The above only takes the read register number included in the first data information as an example of being different from the read register number included in the second data information. In actual applications, if the second instruction identifier included in the first data information is different from the second instruction identifier included in the second data information, then the first data information is not completely consistent with the second data information. Or, if the input data included in the first data information is different from the input data included in the second data information, then the first data information is not completely consistent with the second data information.

[0078] In the case where the first instruction is a read instruction, the first register is a destination register of the data to be read.

[0079] It should be noted that the above takes the first instruction as a read instruction and the first instruction as a write instruction as examples to respectively illustrate the specific implementation process of step S105. In specific implementation, step S105 may also first verify the correctness of the renaming process triggered by the write instruction in the write-after-read instruction, and then verify the correctness of the renaming process triggered by the read instruction in the write-after-read instruction. In this scenario, the source register corresponding to the read instruction is the destination register corresponding to the write instruction.

[0080] Since register renaming is usually associated with instruction dispatch and other contents in chip design, and the algorithms of instruction dispatch and register renaming are becoming more and more complicated, it is difficult to achieve complete consistency between the reference model and the algorithm of the renaming component. The method for verifying renaming provided in the embodiment of the present application can simplify the process of verifying renaming, remove the influence of the instruction dispatch algorithm and the register renaming algorithm, realize the verification of the read and write operations of the renaming component, and realize the unit-level renaming verification for the renaming component.

[0081] based on Figure 1 The process flow of the verification rename method shown and Figure 2 The physical register table entry shown is a schematic diagram of an overall implementation of the verification renaming method provided in an embodiment of the present application, such as Figure 3 As shown,

[0082] The four input information mop0, mop1, mop2 and mop3 are input to RFM and DUT. For each input information in mop0, mop1, mop2 and mop3, the physical register table items output by RFM and DUT output the corresponding register number, instruction identifier, data information and release information. For each input information, compare the physical register table item information output by RFM with the register table item information output by DUT to verify whether the renaming process of the renaming component for the input information is correct.

[0083] The verification renaming method provided in the embodiment of the present application can be applied to a variety of system architectures or scenarios. The following is an example of the system architecture or scenario in which the verification renaming method provided in the embodiment of the present application is applied.

[0084] 1. Applied to high-performance processor cores

[0085] In high-performance processor cores that need to implement superscalar or multiple issue architectures, the renaming unit is essential for handling instruction-level parallelism. By verifying whether the renaming process of the renaming unit for instructions is correct, the correct mapping of registers can be ensured, thereby improving the performance of the overall processor.

[0086] 2. Simultaneous Multithreading (SMT)

[0087] In a processor architecture that supports multithreading, different threads may share physical registers. By verifying whether the renaming process of the renaming component for instructions is correct, the correct allocation and use of registers between different threads can be ensured, preventing resource conflicts and data consistency issues.

[0088] 3. Distributed processing architecture

[0089] In a distributed processor or multi-core system, each core may adopt a different renaming strategy. By verifying whether the renaming process of the renaming component for instructions is correct, the consistency and correctness of the register renaming process across cores can be ensured; especially in the case of shared resources, the consistency and correctness of the register renaming process across cores can be ensured.

[0090] 4. Low power embedded system

[0091] In embedded processor designs that are sensitive to power and area, the design of the renaming unit is often optimized to reduce resource consumption. By verifying whether the renaming process of the renaming unit for instructions is correct, it can be ensured that these optimizations are performed without affecting the correctness of the register mapping and the stability of the system.

[0092] 5. Dynamic Instruction Scheduler

[0093] In processor architectures that rely on dynamic instruction scheduling, the renaming unit needs to manage physical registers quickly and efficiently to optimize the order in which instructions are executed. By verifying that the renaming process of the renaming unit for instructions is correct, it can be ensured that the scheduler can still correctly map and schedule instructions in a dynamic environment.

[0094] 6. Virtualized environment

[0095] In a processor that supports hardware virtualization, the hypervisor may need to rename registers of different virtual machines to manage physical resources. By verifying whether the renaming process of the renaming component for instructions is correct, the resource isolation and register mapping correctness between different virtual machines can be ensured.

[0096] The present application also provides a device for verifying renaming, and the schematic diagram of the structure of the device for verifying renaming is as follows: Figure 4 As shown, including:

[0097] A construction unit 301 is used to construct a verification environment of the renaming component, wherein the verification environment includes a simulated register file, and the simulated register file is used to store instruction information for interacting with the renaming component; the instruction information at least includes release information and / or data information;

[0098] The allocating unit 302 is configured to allocate a first instruction identifier to the first instruction;

[0099] A generating unit 303, configured to generate input information based on the first instruction and the first instruction identifier;

[0100] The renaming component 304 is used to determine a first physical register allocated to the first instruction based on the input information;

[0101] The verification unit 305 is used to verify the renaming component based on the instruction information in the simulated register file.

[0102] In some embodiments, the first instruction is a write instruction, and the verification unit 305 is specifically used to search for a release mark bit corresponding to the first register in the release information stored in the simulated register file; if the release mark bit indicates that the first register is in an idle state, then verify that the renaming process of the renaming component for the first instruction is correct; if the release mark bit indicates that the first register is in a non-idle state, then verify that the renaming process of the renaming component for the first instruction is incorrect.

[0103] In some embodiments, if the result of verifying the renaming component is that the renaming process of the renaming component for the first instruction is correct, the apparatus for verifying renaming further includes: a processing unit ( Figure 4 (not shown) is used to write the first instruction identifier and related information of the first instruction into a register file.

[0104] In some embodiments, the first instruction is a read instruction, and the verification unit 305 is specifically used to search for corresponding first data information in the simulated register file; based on the first physical register, search for corresponding second data information in the data information stored in the preset reference model register file; based on the first data information and the second data information, verify the renaming component.

[0105] In some embodiments, the first data information and the second data information each include at least one of the following: a read register number, a second instruction identifier corresponding to the first instruction, input data, and a release mark bit.

[0106] In some embodiments, the verification unit 305 is specifically used to compare the first data information with the second data information; if the first data information is completely consistent with the second data information, then verify that the renaming process of the renaming component for the first instruction is correct; if the first data information is not completely consistent with the second data information, then verify that the renaming process of the renaming component for the first instruction is incorrect.

[0107] The present application also provides an electronic device, a schematic diagram of the structure of the electronic device, such as Figure 5 As shown, the electronic device includes: a processor 410, a memory 450 and a bus 440; the modules in the electronic device are coupled together through the bus 440. It can be understood that the bus 440 is used to realize the connection and communication between these modules. In addition to the data bus, the bus 440 also includes a power bus, a control bus and a status signal bus. However, for the sake of clarity, Figure 5 Various buses are labeled as bus 440.

[0108] The processor 410 has signal processing capabilities, such as a general-purpose processor, a digital signal processor (DSP), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware models, etc., where the general-purpose processor can be a microprocessor or any conventional processor, etc.

[0109] The memory 450 stores executable instructions for implementing the verification renaming method provided in the embodiment of the present application. The verification renaming method can be performed by Figure 4The construction unit 301, the allocation unit 302, the generation unit 303, the renaming component 304 and the verification unit 305 in the apparatus for verifying renaming are implemented; the memory 450 can be removable, non-removable or a combination thereof. Exemplary hardware devices include solid-state memory, hard disk drives, optical disk drives, etc. The memory 450 optionally includes one or more storage devices that are physically far away from the processor 410.

[0110] In some embodiments, memory 450 is capable of storing data to support various operations, examples of which include programs, modules, and data structures, or a subset or superset thereof.

[0111] In some embodiments, the chip may further include:

[0112] Operating system 451, including system programs for processing various basic system services and performing hardware-related tasks, such as a framework layer, a core library layer, a driver layer, etc., for implementing various basic services and processing hardware-based tasks;

[0113] The network communication module 452 is used to reach other computing devices via one or more (wired or wireless) network interfaces 420 or user interfaces 430. Exemplary network interfaces 420 include: Bluetooth, Wireless Authentication (WiFi), and Universal Serial Bus (USB).

[0114] The embodiment of the present application provides a computer-readable storage medium storing executable instructions, wherein the executable instructions are stored. When the executable instructions are executed by a processor, the processor will be triggered to execute the verification renaming method provided by the embodiment of the present application, for example, Figures 1 to 3 The method of verifying the rename is shown.

[0115] In some embodiments, the computer-readable storage medium may be a ferroelectric random access memory (FRAM), a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, a magnetic surface memory, an optical disk, or a CD-ROM; it may also be various devices including one or any combination of the above memories.

[0116] In some embodiments, executable instructions may be in the form of a program, software, software module, script or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and may be deployed in any form, including as a stand-alone program or as a module, model, subroutine or other unit suitable for use in a computing environment.

[0117] By way of example, executable instructions may be deployed to be executed on one computing device, or on multiple computing devices located at one site, or on multiple computing devices distributed across multiple sites and interconnected by a communication network.

[0118] An embodiment of the present application provides a computer program product, which includes a computer program / instructions. When the computer program / instructions are executed by a processor, the method for verifying and renaming described in the present application is implemented.

[0119] The above are only embodiments of the present application and are not intended to limit the protection scope of the present application. Any modifications, equivalent substitutions and improvements made within the spirit and scope of the present application are included in the protection scope of the present application.

Claims

1. A method for verifying renaming, characterized in that: The method comprises: Constructing a verification environment for the renaming component, wherein the verification environment includes a simulated register file, wherein the simulated register file is used to store instruction information for interacting with the renaming component; the instruction information includes at least release information and / or data information; assigning a first instruction identifier to the first instruction; generating input information based on the first instruction and the first instruction identifier; The renaming component determines, based on the input information, a first physical register allocated to the first instruction; The renaming component is verified based on the instruction information in the simulated register file.

2. The method according to claim 1, characterized in that The verifying the renaming component based on the instruction information in the simulated register file includes: The first instruction is a write instruction, and searching for a release flag bit corresponding to the first register in the release information stored in the simulated register file; If the release flag bit indicates that the first register is in an idle state, verifying that the renaming process of the first instruction by the renaming component is correct; If the release flag bit indicates that the first register is in a non-idle state, it is verified that the renaming process of the first instruction performed by the renaming component is incorrect.

3. The method according to claim 1, characterized in that If the result of verifying the renaming component is that the renaming process of the renaming component for the first instruction is correct, the method further includes: The first instruction identifier and related information of the first instruction are written into a register file.

4. The method according to claim 1, characterized in that: The verifying the renaming component based on the instruction information in the simulated register file includes: The first instruction is a read instruction, and the corresponding first data information is searched in the simulated register file; Based on the first physical register, searching for corresponding second data information in data information stored in a preset reference model register file; The renamed component is verified based on the first data information and the second data information.

5. The method according to claim 4, characterized in that The first data information and the second data information each include at least one of the following: The register number, the second instruction identifier corresponding to the first instruction, the input data and the release mark bit are read.

6. The method according to claim 5, characterized in that The verifying the renamed component based on the first data information and the second data information includes: Comparing the first data information with the second data information; If the first data information is completely consistent with the second data information, verifying that the renaming process of the renaming component for the first instruction is correct; If the first data information is not completely consistent with the second data information, it is verified that the renaming process of the first instruction by the renaming component is incorrect.

7. A device for verifying renaming, characterized in that: The means for verifying the renaming comprises: A construction unit, configured to construct a verification environment for the renaming component, wherein the verification environment includes a simulated register file, and the simulated register file is configured to store instruction information for interacting with the renaming component; the instruction information includes at least release information and / or data information; An allocating unit, configured to allocate a first instruction identifier to the first instruction; A generating unit, configured to generate input information based on the first instruction and the first instruction identifier; The renaming component is used to determine a first physical register allocated to the first instruction based on the input information; A verification unit is used to verify the renaming component based on the instruction information in the simulated register file.

8. An electronic device, characterized in that: The electronic device comprises: at least one processor; and a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the verification renaming method according to any one of claims 1 to 6.

9. A computer-readable storage medium storing computer instructions, wherein: The computer instructions are used to cause the computer to execute the verification renaming method according to any one of claims 1 to 6.

10. A computer program product, comprising a computer program / instruction, wherein when the computer program / instruction is executed by a processor, the method for verifying and renaming according to any one of claims 1 to 6 is implemented.

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