Multi-core synchronization method, device and system for system-on-chip verification
By allocating independent sub-state storage space and main state storage space for each core, the problem of inefficient multi-core synchronization is solved, and faster and more efficient multi-core synchronization is achieved.
Patent Information
- Application Number
- CN202510103021.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-22
- Publication Date
- 2025-05-16
AI Technical Summary
In the prior art, the waiting time of each core is extended during multi-core synchronization, and the synchronization process is complex, resulting in a decrease in the efficiency of multi-core synchronization.
By allocating the main state storage space and independent substate storage space to each kernel with multi-core synchronization requirements, each kernel can independently update its substate, simplifying the kernel state update logic, and achieving inter-core synchronization by notifying all kernels at once.
Improves the speed and efficiency of multi-core synchronization, shortens the duration of multi-core synchronization, and simplifies the kernel state update logic.
Smart Images
Figure CN120011108A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of integrated circuit verification, for example, to a multi-core synchronization method, device and system for system-level chip verification. Background Art
[0002] Currently, when SOC (System on Chip) verification involves the bus, there are requirements such as multi-core synchronous concurrent access to slave, multi-core stress testing, and bus concurrent testing.
[0003] In order to meet the multi-core synchronization requirements faced by SOC verification, the relevant technology discloses a method for data synchronization between multi-core MCU (Microcontroller Unit) cores, including: initializing shared memory space, setting the marked data of the shared memory, and setting the first core to an updated data state; the second core does not perform a data read operation on the shared memory, the first core writes data to the shared memory, and the first core is set to a completed data update state; the second core continues to perform a data read operation on the shared memory, sets a clock detection program to time the second core's data read time, records the timing and stores it in the shared memory; the second core does not perform a data read operation on the shared memory, the first core writes data to the shared memory, and the first core is set to a completed data update state.
[0004] In the process of implementing the embodiments of the present disclosure, it is found that there are at least the following problems in the related art:
[0005] The first core and the second core wait for each other in turn through the shared memory space for core synchronization. When the number of cores that need to be synchronized increases, the waiting time of each core is extended, the synchronization process between cores becomes more cumbersome and complicated, and the efficiency of multi-core synchronization is reduced.
[0006] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present application, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention
[0007] In order to provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. The summary is not an extensive review, nor is it intended to identify key / critical components or delineate the scope of protection of these embodiments, but rather serves as a prelude to the detailed description that follows.
[0008] The disclosed embodiments provide a multi-core synchronization method, device, and system for system-on-chip verification to simplify core status update logic and improve multi-core synchronization speed and multi-core synchronization efficiency.
[0009] In some embodiments, the multi-core synchronization method is applied to an SV verification platform, and the multi-core synchronization method includes: allocating a main state storage space and independent sub-state storage spaces to each core with multi-core synchronization requirements; wherein the core represents the core of the same CPU or the core of different CPUs, the sub-state storage space stores sub-states reflecting the corresponding core state, and the main state storage space stores main states reflecting the states of all cores; reading each sub-state storage space to obtain the sub-state of each core; and when the sub-states of all cores are updated to a new state, updating the main state of the main state storage space to a new state.
[0010] In some embodiments, the kernel state is determined in the following manner: the running programs of the kernel with multi-core synchronization requirements are divided from the time dimension, and the program state in each time period is determined as the kernel state; wherein the program state includes part or all of the configuration state and the start state, stop state, and end state.
[0011] In some embodiments, each sub-state storage space is read to obtain the sub-state of each core, including: periodically reading the sub-state of the sub-state storage space corresponding to each core through a backdoor access method; and / or, the main state of the main state storage space is updated to a new state, including: updating the state of the main state storage space to a new state through a backdoor access method.
[0012] In some embodiments, main state storage space is allocated to each core with multi-core synchronization requirements in the following manner: in the case of multi-core shared memory, one or more common main state storage spaces are allocated to all cores with multi-core synchronization requirements; or, in the case of multi-core non-shared memory, multiple independent main state storage spaces are allocated to each core with multi-core synchronization requirements.
[0013] In some embodiments, it also includes: after reading each sub-state storage space to obtain the sub-state of each core, if the sub-state of one or more cores with multi-core requirements is updated to a new state, determining whether the sub-states of all cores are updated to the new state.
[0014] In some embodiments, the multi-core synchronization method is applied to the kernel, and the multi-core synchronization method includes: when the target kernel has a multi-core synchronization requirement, writing an updated sub-state reflecting the target kernel state to the sub-state storage space corresponding to the target kernel, so that the SV verification platform obtains the sub-state through the sub-state storage space; wherein, the sub-state storage space is allocated by the SV verification platform when the target kernel has a multi-core synchronization requirement; detecting the main state storage space corresponding to the target kernel to determine the main state; wherein, the main state storage space is used to reflect the main state of all kernel states with multi-core synchronization requirements, and is allocated by the SV verification platform when the target kernel has a multi-core synchronization requirement.
[0015] In some embodiments, writing an updated sub-state reflecting the state of the target kernel to the sub-state storage space corresponding to the target kernel includes: calling an update sub-state function to write the sub-state reflecting the state of the target kernel to the sub-state storage space corresponding to the target kernel in a front-door access manner; and / or detecting the main state storage space corresponding to the target kernel to determine the main state, including: calling a wait main state function to periodically read the main state, and determining whether the target kernel has completed multi-core synchronization based on the main state.
[0016] In some embodiments, it also includes: when the target kernel has multi-core synchronization requirements, determining the synchronization position of the target kernel according to the test case; when the running program of the target kernel executes to the synchronization position, triggering the call operation of updating the sub-state function and / or waiting for the main state function.
[0017] In some embodiments, the multi-core synchronization device includes a processor and a memory storing program instructions, and the processor is configured to execute the multi-core synchronization method for system-on-chip verification as described above when running the program instructions.
[0018] In some embodiments, the multi-core synchronization system includes: an SV verification platform; a kernel connected to the SV verification platform, the kernel representing the core of the same CPU or the core of different CPUs; and a multi-core synchronization device for system-level chip verification as described above, installed on the SV verification platform and / or the kernel.
[0019] The multi-core synchronization method, device, and system for system-level chip verification provided by the embodiments of the present disclosure can achieve the following technical effects:
[0020] In the disclosed embodiment, the SV verification platform allocates a main state storage space and a sub-state space to each core with multi-core synchronization requirements, so as to obtain the sub-state of each core by reading the sub-state space. When the sub-states of all cores are updated to a new state, the SV verification platform updates the main state of the main state storage space to the new state to complete multi-core synchronization. By allocating mutually independent sub-state spaces and main state storage spaces to each core, the disclosed embodiment enables each core to update its sub-state independently, and different cores do not need to wait for each other when updating their respective sub-states, thereby simplifying the core state update logic. At the same time, the SV verification platform updates the main state of the main state storage space when the sub-states of all cores are updated to a new state, and realizes inter-core synchronization by notifying all cores at one time, shortening the multi-core synchronization time, and improving the multi-core synchronization speed and efficiency.
[0021] The above general description and the following description are exemplary and explanatory only and are not intended to limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] One or more embodiments are exemplarily described by corresponding drawings, which do not limit the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements, and the drawings do not constitute a scale limitation, and wherein:
[0023] Figure 1 is an environmental schematic diagram of a multi-core synchronization system for system-level chip verification provided by an embodiment of the present disclosure;
[0024] Figure 2 It is a schematic diagram of the SV verification platform provided by the embodiment of the present disclosure allocating storage space to the kernel;
[0025] Figure 3 is a schematic diagram of a multi-core synchronization method for system-level chip verification provided by an embodiment of the present disclosure;
[0026] Figure 4 is a schematic diagram of another multi-core synchronization method for system-level chip verification provided by an embodiment of the present disclosure;
[0027] Figure 5 is a schematic diagram of another multi-core synchronization method for system-level chip verification provided by an embodiment of the present disclosure;
[0028] Figure 6 is a schematic diagram of another multi-core synchronization method for system-level chip verification provided by an embodiment of the present disclosure;
[0029] Figure 7 is a schematic diagram of another multi-core synchronization method for system-level chip verification provided by an embodiment of the present disclosure;
[0030] Figure 8 is a schematic diagram of another multi-core synchronization method for system-level chip verification provided by an embodiment of the present disclosure;
[0031] Fig. 9 is an application schematic diagram provided by an embodiment of the present disclosure;
[0032] Fig.10 It is a schematic diagram of a multi-core synchronization device for system-on-chip verification provided by an embodiment of the present disclosure. DETAILED DESCRIPTION
[0033] In order to be able to understand the features and technical contents of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present disclosure. In the following technical description, for the convenience of explanation, a full understanding of the disclosed embodiments is provided through multiple details. However, one or more embodiments can still be implemented without these details. In other cases, to simplify the drawings, well-known structures and devices can be simplified for display.
[0034] The terms "first", "second", etc. in the specification and claims of the embodiments of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchanged where appropriate, so that the embodiments of the embodiments of the present disclosure described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.
[0035] Unless otherwise stated, the term "plurality" means two or more.
[0036] In the embodiment of the present disclosure, the character " / " indicates that the preceding and following objects are in an "or" relationship. For example, A / B indicates: A or B.
[0037] The term "and / or" is a description of the association relationship between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or, A and B.
[0038] The term "correspondence" may refer to an association relationship or a binding relationship. The correspondence between A and B means that there is an association relationship or a binding relationship between A and B.
[0039] Figure 1 1 is a schematic diagram of the environment of a multi-core synchronization system for system-level chip verification provided by an embodiment of the present disclosure. Figure 1As shown, the multi-core synchronization system for system-level chip verification includes an SV verification platform 10 and a core 20. The core 20 is connected to the SV verification platform 10. The SV verification platform includes an SV management program. The SV management program is used to execute the following multi-core synchronization method for system-level chip verification.
[0040] Combination Figure 2 As shown, the core 20 with multi-core synchronization requirements includes a first core Core0, a second core Core1, ..., and an (n+1)th core Coren, where n is an integer greater than or equal to 0. The SV verification platform 10 allocates a main state storage space and mutually independent sub-state storage spaces to each core 20. As an example, the core 20 with multi-core synchronization requirements includes a first core Core0, a second core Core1, and a third core Core2. The SV verification platform 10 allocates a first sub-state storage space to the first core Core0, a second RAM sub-state storage space to the second core Core1, and a third RAM sub-state storage space to the third core Core2, and the SV verification platform 10 also allocates a main state storage space to all cores to reflect the main state of all core states. Among them, the sub-state storage space is used to reflect the sub-state of the corresponding core state.
[0041] Based on the multi-core synchronization system for system-level chip verification, combined with Figure 2 and Figure 3 As shown, the embodiment of the present disclosure provides a multi-core synchronization method for system-level chip verification, including:
[0042] S01, the SV verification platform allocates a main state storage space and a mutually independent sub-state storage space to each core with multi-core synchronization requirements. The core refers to the core of the same CPU (Central Processing Unit) or the core of different CPUs, the sub-state storage space stores the sub-states reflecting the corresponding core state, and the main state storage space stores the main state reflecting the states of all cores.
[0043] S02, the SV verification platform reads each sub-state storage space to obtain the sub-state of each core.
[0044] In this step, the SV verification platform reads each sub-state storage space, including: the SV verification platform periodically reads each sub-state storage space in a loop. In this way, if the number of cores with multi-core synchronization requirements increases, only the number of loops in the SV management program needs to be increased, and it will not affect the running programs of each core, which is conducive to realizing the template of multi-core synchronization.
[0045] S03, when the sub-states of all the cores are updated to the new state, the SV verification platform updates the main state of the main state storage space to the new state.
[0046] The multi-core synchronization method for system-level chip verification provided by the embodiment of the present disclosure is adopted. In the embodiment of the present disclosure, the SV verification platform allocates a main state storage space and a sub-state space to each core with multi-core synchronization requirements, so as to obtain the sub-state of each core by reading the sub-state space. When the sub-states of all cores are updated to a new state, the SV verification platform updates the main state of the main state storage space to the new state to complete multi-core synchronization. By allocating mutually independent sub-state spaces and main state storage spaces to each core, the embodiment of the present disclosure enables each core to update its sub-state independently, and different cores do not need to wait for each other when updating their respective sub-states, thereby simplifying the core state update logic. At the same time, the SV verification platform updates the main state of the main state storage space when the sub-states of all cores are updated to a new state, and realizes inter-core synchronization by notifying all cores at one time, shortening the multi-core synchronization time, and improving the multi-core synchronization speed and multi-core synchronization efficiency.
[0047] It should be noted that, when the cores are cores of the same CPU, the embodiments of the present disclosure can be used to achieve multi-core synchronization of the same CPU. When the cores are cores of different CPUs, the embodiments of the present disclosure can be used to achieve multi-core synchronization between different CPUs.
[0048] Optionally, the SV verification platform determines the kernel state as follows:
[0049] The SV verification platform divides the running programs of the kernels with multi-core synchronization requirements from the time dimension, and determines the program status in each time period as the kernel status. The program status includes part or all of the configuration status and the start status, stop status, and end status.
[0050] In this way, the embodiment of the present disclosure divides the running programs of the kernel with multi-core synchronization requirements from the time dimension, and the program state in each time period can be defined as the kernel state, so that the kernel state is represented by the corresponding program state.
[0051] In addition, the program status in each time period is represented by the status macro. The sub-state storage space directly uses macros to update their respective states, without the need to maintain and remember multiple numbers, making it easy to clearly know the sub-state of the kernel. It should be noted that the main state is also represented by the status macro. In this way, it is easy to clearly know the status update of all kernels.
[0052] It should be noted that after the SV verification platform allocates the main state storage space and the mutually independent sub-state storage space to each core with multi-core synchronization requirements, it also includes: the SV verification platform assigns initial values to the sub-state storage space corresponding to each core and / or assigns initial values to the main state storage space. Among them, the initial state value of the sub-state storage space is not the value of the state macro, and the initial state value of the main state storage space is not the value of the state macro. In this way, it avoids misjudgment of the sub-state update status of the core.
[0053] Optionally, the SV verification platform reads each sub-state storage space to obtain the sub-state of each core, including: periodically reading the sub-state of the sub-state storage space corresponding to each core through a backdoor access method; or,
[0054] The SV verification platform updates the main state of the main state storage space to a new state, including: updating the state of the main state storage space to a new state through a backdoor access method.
[0055] In this way, since the backdoor access method does not occupy the chip running time, the SV verification platform periodically reads the sub-state of the sub-state storage space corresponding to each core through the backdoor access method or updates the state of the main state storage space to a new state through the backdoor access method, which can reduce the occupancy of the chip by multi-core synchronization and shorten the multi-core synchronization time, thereby improving the multi-core synchronization efficiency.
[0056] Optionally, the SV verification platform reads each sub-state storage space to obtain the sub-state of each core, including: periodically reading the sub-state of the sub-state storage space corresponding to each core through a backdoor access method; and,
[0057] The SV verification platform updates the main state of the main state storage space to a new state, including: updating the state of the main state storage space to a new state through a backdoor access method.
[0058] In this way, while the SV verification platform periodically reads the sub-state of the sub-state storage space corresponding to each core through backdoor access, it also updates the state of the main state storage space to a new state through backdoor access. This can not only shorten the multi-core synchronization time and improve the multi-core synchronization efficiency, but also realize the unified management of the main state under multi-core synchronization, thereby improving the accuracy of multi-core synchronization.
[0059] Optionally, the SV verification platform allocates the main state storage space to each core with multi-core synchronization requirements in the following manner:
[0060] In the case of multi-core shared memory, the SV verification platform allocates one or more common master state storage spaces to all cores with multi-core synchronization requirements. Or,
[0061] In the case of multi-core non-shared memory, the SV verification platform allocates multiple independent main state storage spaces to each core with multi-core synchronization requirements.
[0062] The above memory may be a RAM (Random Access Memory).
[0063] In this way, the SV verification platform can allocate one or more shared main state storage spaces or multiple independent main state storage spaces to the core according to the memory characteristics, realizing flexible allocation of the main state storage space. In addition, when the multiple allocated main state storage spaces are independent of each other, it makes it easier to realize modularization of multi-core synchronization and improve scalability.
[0064] Optionally, the multi-core synchronization method for system-level chip verification further includes:
[0065] The SV verification platform allocates main state storage space and independent sub-state storage space to each core with multi-core synchronization requirements. If a new core with multi-core synchronization requirements is added, the SV verification platform updates the main state storage space and allocates a new sub-state storage space to the new core that is independent of the allocated sub-state storage space.
[0066] Among them, the SV verification platform updates the main state storage space, including: in the case of multi-core shared memory, the SV verification platform updates the main state storage space shared by the new core and other cores; or, in the case of multi-core non-shared memory, the SV verification platform allocates a main state storage space independent of other cores to the new core.
[0067] Combination Figure 4 As shown, the embodiment of the present disclosure also provides a multi-core synchronization method for system-level chip verification, including:
[0068] S11, the SV verification platform allocates a main state storage space and a mutually independent sub-state storage space to each core with multi-core synchronization requirements. The core refers to the core of the same CPU or the core of different CPUs, the sub-state storage space stores the sub-states reflecting the corresponding core state, and the main state storage space stores the main state reflecting the state of all cores.
[0069] S12, the SV verification platform reads each sub-state storage space to obtain the sub-state of each core.
[0070] S13, when the sub-states of one or more cores with multi-core requirements are updated to a new state, the SV verification platform determines whether the sub-states of all cores are updated to the new state.
[0071] S14, when the sub-states of all the cores are updated to the new state, the SV verification platform updates the main state of the main state storage space to the new state.
[0072] The multi-core synchronization method for system-level chip verification provided by the embodiment of the present disclosure is adopted. In the embodiment of the present disclosure, the SV verification platform allocates a main state storage space and a sub-state space to each core with multi-core synchronization requirements, so as to obtain the sub-state of each core by reading the sub-state space. When the sub-state of one or more cores storing the multi-core synchronization requirements is updated to a new state, the SV verification platform determines whether the sub-states of all cores are updated to the new state. If the sub-states of all cores are updated to the new state, the SV verification platform updates the main state of the main state storage space to the new state, and completes the multi-core synchronization. The embodiment of the present disclosure allocates mutually independent sub-state spaces and main state storage spaces to each core, so that each core can update its sub-state independently, and different cores do not need to wait for each other when updating their respective sub-states, thereby simplifying the core state update logic. At the same time, the SV verification platform monitors the sub-state update status of all cores with multi-core synchronization requirements in real time, and updates the main state of the main state storage space when the sub-states of all cores are updated to the new state, and realizes inter-core synchronization by notifying all cores at one time, shortening the multi-core synchronization time, and improving the multi-core synchronization speed and multi-core synchronization efficiency.
[0073] Combination Figure 5 As shown, the embodiment of the present disclosure also provides a multi-core synchronization method for system-level chip verification, including:
[0074] S21, when the target kernel has a multi-core synchronization requirement, the kernel writes an updated sub-state reflecting the target kernel state to the sub-state storage space corresponding to the target kernel, so that the SV verification platform obtains the sub-state through the sub-state storage space. The sub-state storage space is allocated by the SV verification platform when the target kernel has a multi-core synchronization requirement.
[0075] S22, the kernel detects the main state storage space corresponding to the target kernel and determines the main state. The main state storage space is used to reflect the main state of all kernel states with multi-core synchronization requirements and is allocated by the SV verification platform when the target kernel has multi-core synchronization requirements.
[0076] The multi-core synchronization method for system-on-chip verification provided by the embodiment of the present disclosure is adopted. In the embodiment of the present disclosure, when the target kernel has a multi-core synchronization requirement, the kernel writes an updated sub-state reflecting the state of the target kernel to the sub-state storage space corresponding to the target kernel so that the SV verification platform obtains the sub-state through the sub-state storage space. Thereafter, the kernel detects the main state storage space corresponding to the target kernel and determines the main state. The kernel can independently write its sub-state through the sub-state storage space allocated by the SV verification platform, and different kernels do not need to wait for each other when updating their sub-states, which can simplify the kernel's state update logic and shorten the multi-core synchronization time. At the same time, the kernel can obtain the main state by detecting the main state storage space corresponding to the target kernel, thereby knowing the multi-core synchronization status between the target kernel and other kernels based on the update status of the main state, and ensuring the real-time performance of multi-core synchronization.
[0077] It should be noted that in the above embodiment, the kernel writes the updated sub-state reflecting the target kernel state to the sub-state storage space corresponding to the target kernel and the kernel detects the main state storage space corresponding to the target kernel, and determines the execution order of the main state in no particular order.
[0078] Optionally, the kernel writes the updated sub-state reflecting the target kernel state to the sub-state storage space corresponding to the target kernel, including: the kernel calls the update sub-state function to write the sub-state reflecting the target kernel state to the sub-state storage space corresponding to the target kernel in a front-door access manner; and,
[0079] The kernel detects the main state storage space corresponding to the target kernel and determines the main state, including: the kernel calls the wait main state function to periodically read the main state, and determines whether the target kernel completes multi-core synchronization based on the main state.
[0080] The update sub-state function is constructed and generated by the SV management program, and is used to write the sub-state reflecting the kernel state to the sub-state storage space corresponding to the kernel in a front-door manner. The wait main state function is constructed and generated by the SV management program, and is used to periodically read the main state and determine whether the kernel has completed multi-core synchronization based on the main state.
[0081] In this way, the kernel can independently update its sub-state under the management of the SV verification platform, and timely learn the multi-core synchronization status of the kernel and other kernels, simplify the state maintenance logic and code, and ensure the efficiency and real-time performance of multi-core synchronization. In addition, the kernel can achieve multi-core synchronization by calling the corresponding general function, which greatly improves scalability.
[0082] Optionally, the kernel writes the updated sub-state reflecting the target kernel state to the sub-state storage space corresponding to the target kernel, including: the kernel calls the update sub-state function to write the sub-state reflecting the target kernel state to the sub-state storage space corresponding to the target kernel in a front-door access manner. The update sub-state function is constructed and generated by the SV management program, and is used to write the sub-state reflecting the kernel state to the sub-state storage space corresponding to the kernel in a front-door manner.
[0083] In this way, the core can independently update its sub-state under the management of the SV verification platform, simplifying the state maintenance logic and code and improving the efficiency of multi-core synchronization.
[0084] Optionally, the kernel detects the main state storage space corresponding to the target kernel and determines the main state, including: the kernel calls the wait main state function to periodically read the main state, and determines whether the target kernel has completed multi-core synchronization based on the main state. The wait main state function is constructed and generated by the SV management program, which is used to periodically read the main state and determine whether the kernel has completed multi-core synchronization based on the main state.
[0085] In this way, the core can obtain the multi-core synchronization status with other cores in a timely manner under the management of the SV verification platform, thereby improving the efficiency and real-time performance of multi-core synchronization.
[0086] Combination Figure 6 As shown, the embodiment of the present disclosure also provides a multi-core synchronization method for system-level chip verification, including:
[0087] S31, when the target kernel has a multi-core synchronization requirement, the kernel determines the synchronization position of the target kernel according to the test case.
[0088] S32, when the running program of the target kernel is executed to the synchronization position, the kernel triggers the calling operation of updating the sub-state function and waiting for the main state function.
[0089] S33, the kernel calls the update sub-state function to write the sub-state reflecting the state of the target kernel to the sub-state storage space corresponding to the target kernel in a front-door access mode, so that the SV verification platform obtains the sub-state through the sub-state storage space. The sub-state storage space is allocated by the SV verification platform when the target kernel has a multi-core synchronization requirement.
[0090] S34, the kernel calls the wait main state function to periodically read the main state, and determines whether the target kernel has completed multi-core synchronization based on the main state. The main state storage space is used to reflect the main state of all kernel states with multi-core synchronization requirements, and is allocated by the SV verification platform when the target kernel has multi-core synchronization requirements.
[0091] The multi-core synchronization method for system-level chip verification provided by the embodiment of the present disclosure is adopted. In the embodiment of the present disclosure, the kernel determines the synchronization position of the target kernel according to the test case when the target kernel has a multi-core synchronization requirement. When the running program of the target kernel is executed to the synchronization position, the kernel calls the update sub-state function to write the sub-state reflecting the state of the target kernel to the sub-state storage space corresponding to the target kernel in a front-door access manner. Thereafter, the kernel calls the wait main state function to periodically read the main state, and determines whether the target kernel has completed multi-core synchronization based on the main state. After the running program of the target kernel is executed to the synchronization position, the kernel independently writes its sub-state by calling the update sub-state function, which can simplify the kernel's state update logic. At the same time, after the running program of the target kernel is executed to the synchronization position, the kernel calls the wait main state function to periodically read the main state and determines whether the target kernel has completed multi-core synchronization based on the main state, thereby ensuring the real-time and reliability of multi-core synchronization and further improving the efficiency of multi-core synchronization.
[0092] Combination Figure 7 As shown, the embodiment of the present disclosure also provides a multi-core synchronization method for system-level chip verification, including:
[0093] S41, when the target kernel has a multi-core synchronization requirement, the kernel determines the synchronization position of the target kernel according to the test case.
[0094] S42, when the running program of the target kernel is executed to the synchronization position, the kernel triggers the calling operation of updating the sub-state function.
[0095] S43, the kernel calls the update sub-state function to write the sub-state reflecting the state of the target kernel to the sub-state storage space corresponding to the target kernel in a front-door access mode, so that the SV verification platform obtains the sub-state through the sub-state storage space. The sub-state storage space is allocated by the SV verification platform when the target kernel has a multi-core synchronization requirement.
[0096] S44, when the target kernel has a multi-core synchronization requirement, the kernel detects the main state storage space corresponding to the target kernel and determines the main state. The main state storage space is used to reflect the main state of all kernel states with multi-core synchronization requirements and is allocated by the SV verification platform when the target kernel has a multi-core synchronization requirement.
[0097] The multi-core synchronization method for system-on-chip verification provided by the embodiment of the present disclosure is adopted. In the embodiment of the present disclosure, when the running program of the target kernel is executed to the synchronization position, the kernel triggers the calling operation of the update sub-state function. By calling the update sub-state function to independently write its sub-state, the kernel's state update logic can be simplified and the multi-core synchronization time can be shortened. The kernel also obtains the main state by detecting the main state storage space corresponding to the target kernel, so as to know the multi-core synchronization status between the target kernel and other kernels according to the update status of the main state, thereby ensuring the real-time performance of multi-core synchronization.
[0098] Combination Figure 8 As shown, the embodiment of the present disclosure also provides a multi-core synchronization method for system-level chip verification, including:
[0099] S51, when the target kernel has a multi-core synchronization requirement, the kernel writes an updated sub-state reflecting the target kernel state to the sub-state storage space corresponding to the target kernel, so that the SV verification platform obtains the sub-state through the sub-state storage space. The sub-state storage space is allocated by the SV verification platform when the target kernel has a multi-core synchronization requirement.
[0100] S52, when the target kernel has a multi-core synchronization requirement, the kernel determines the synchronization position of the target kernel according to the test case.
[0101] S53, when the running program of the target kernel is executed to the synchronization position, the kernel triggers the calling operation of waiting for the main state function.
[0102] S54, the kernel calls the wait main state function to periodically read the main state, and determines whether the target kernel has completed multi-core synchronization based on the main state. The main state storage space is used to reflect the main state of all kernel states with multi-core synchronization requirements, and is allocated by the SV verification platform when the target kernel has multi-core synchronization requirements.
[0103] Using the multi-core synchronization method for system-on-chip verification provided by the embodiment of the present disclosure, when the target kernel has a multi-core synchronization requirement, the kernel independently writes its sub-state through the sub-state storage space allocated by the SV verification platform, and different kernels do not need to wait for each other when updating their sub-states, which can simplify the kernel's state update logic and shorten the multi-core synchronization time. When the target kernel has a multi-core synchronization requirement, the kernel also determines the synchronization position of the target kernel according to the test case, and triggers the call operation of the waiting main state function when the running program of the target kernel executes to the synchronization position. By calling the waiting main state function to periodically read the main state, and judging whether the target kernel has completed multi-core synchronization based on the main state, the real-time and reliability of multi-core synchronization can be guaranteed, and the efficiency of multi-core synchronization can be further improved.
[0104] In practical applications, Fig. 9 Schematic diagram showing the core sub-state update and main state update of the multi-core synchronization method for system-level chip verification provided by the embodiment of the present disclosure. The core is a core of a multi-core CPU. Figure 2 and Fig. 9 As shown, the multi-core synchronization method for system-level chip verification specifically performs the following steps:
[0105] S101 , the SV management program allocates a mutually independent main state storage space and a mutually independent sub-state storage space to each core having a multi-core synchronization requirement.
[0106] S102, each kernel calls a sub-state update function to write a sub-state reflecting the kernel state into the sub-state storage space corresponding to the kernel in a front-door access manner.
[0107] S103, the SV management program reads each sub-state storage space to obtain the sub-state of each core.
[0108] S104, after reading the sub-state of each core, the SV management program determines whether the sub-states of all cores are updated to the new state; if so, the main state of the main state storage space corresponding to each core is updated to the new state, if not, return to execute step S103.
[0109] S105, each core calls a wait main state function to read the main state of the main state storage space corresponding to the core to confirm whether the main state is updated to a new state, and completes multi-core synchronization when it is determined that the main state is updated to a new state.
[0110] Combination Fig.10 As shown, the embodiment of the present disclosure provides a multi-core synchronization device 70 for system-level chip verification, including a processor (processor) 700 and a memory (memory) 701. Optionally, the device 70 may also include a communication interface (Communication Interface) 702 and a bus 703. Among them, the processor 700, the communication interface 702, and the memory 701 can communicate with each other through the bus 703. The communication interface 702 can be used for information transmission. The processor 700 can call the logic instructions in the memory 701 to execute the multi-core synchronization method for system-level chip verification of the above embodiment.
[0111] In addition, the logic instructions in the memory 701 described above may be implemented in the form of software functional units and when sold or used as independent products, may be stored in a computer-readable storage medium.
[0112] The memory 701 is a computer-readable storage medium that can be used to store software programs and computer executable programs, such as program instructions / modules corresponding to the method in the embodiment of the present disclosure. The processor 700 executes functional applications and data processing by running the program instructions / modules stored in the memory 701, that is, the multi-core synchronization method for system-level chip verification in the above embodiment is implemented.
[0113] The memory 701 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and an application required for at least one function; the data storage area may store data created according to the use of the terminal device, etc. In addition, the memory 701 may include a high-speed random access memory and may also include a non-volatile memory.
[0114] Combination Figure 1 As shown, the embodiment of the present disclosure also provides a multi-core synchronization system for system-level chip verification, including an SV verification platform 10, a core 20, and a multi-core synchronization device 70 for system-level chip verification as described above. The core 20 is connected to the SV verification platform 10. The core 20 represents the core of the same CPU or the core of different CPUs. The multi-core synchronization device 70 for system-level chip verification is installed on the SV verification platform 10 and / or the core 20.
[0115] An embodiment of the present disclosure provides a computer-readable storage medium storing computer-executable instructions, wherein the computer-executable instructions are configured to execute the multi-core synchronization method for system-on-chip verification.
[0116] The technical solution of the embodiment of the present disclosure may be embodied in the form of a software product, which is stored in a storage medium and includes one or more instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in the embodiment of the present disclosure. The aforementioned storage medium may be a non-transitory storage medium, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory, a magnetic disk, or an optical disk, etc., which may store program codes.
[0117] The above description and the accompanying drawings fully illustrate the embodiments of the present disclosure so that those skilled in the art can practice them. Other embodiments may include structural, logical, electrical, process and other changes. The embodiments represent only possible changes. Unless explicitly required, separate components and functions are optional, and the order of operation may vary. The parts and features of some embodiments may be included in or replace the parts and features of other embodiments. Moreover, the words used in this application are only used to describe the embodiments and are not used to limit the claims. As used in the description of the embodiments and the claims, unless the context clearly indicates, the singular forms of "a", "an" and "the" are intended to include plural forms as well. Similarly, the term "and / or" as used in this application refers to any and all possible combinations of listings containing one or more associated ones. In addition, when used in the present application, the term "comprise" and its variants "comprises" and / or comprising refer to the presence of stated features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof. In the absence of further restrictions, the elements defined by the sentence "comprising a ..." do not exclude the presence of other identical elements in the process, method or device comprising the elements. In this article, each embodiment may focus on the differences from other embodiments, and the same and similar parts between the various embodiments may refer to each other. For the methods, products, etc. disclosed in the embodiments, if they correspond to the method part disclosed in the embodiments, then the relevant parts can refer to the description of the method part.
[0118] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software may depend on the specific application and design constraints of the technical solution. The technicians may use different methods for each specific application to implement the described functions, but such implementations should not be considered to exceed the scope of the embodiments of the present disclosure. The technicians may clearly understand that, for the convenience and simplicity of description, the specific working processes of the systems, devices and units described above may refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here.
[0119] In the embodiments disclosed herein, the disclosed methods and products (including but not limited to devices, equipment, etc.) can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units can be only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between each other shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms. The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to implement this embodiment. In addition, each functional unit in the embodiment of the present disclosure may be integrated in a processing unit, or each unit may exist physically alone, or two or more units may be integrated in one unit.
[0120] The flowchart and block diagram in the accompanying drawings show the possible architecture, function and operation of the system, method and computer program product according to the embodiment of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of the code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. In some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, which can depend on the functions involved. In the description corresponding to the flowchart and the block diagram in the accompanying drawings, the operations or steps corresponding to different boxes can also occur in a different order from the order disclosed in the description, and sometimes there is no specific order between different operations or steps. For example, two consecutive operations or steps can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, which can depend on the functions involved. Each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a dedicated hardware-based system that performs the specified functions or actions, or may be implemented by a combination of dedicated hardware and computer instructions.
Claims
1. A multi-core synchronization method for system-level chip verification, characterized in that: Applied to the SV verification platform, the multi-core synchronization method includes: Allocate a main state storage space and a mutually independent sub-state storage space to each core with multi-core synchronization requirements; wherein the core represents the core of the same CPU or the core of different CPUs, the sub-state storage space stores the sub-state reflecting the corresponding core state, and the main state storage space stores the main state reflecting the state of all cores; Read each sub-state storage space to obtain the sub-state of each core; When the sub-states of all the cores are updated to the new state, the main state of the main state storage space is updated to the new state.
2. The multi-core synchronization method according to claim 1, characterized in that: The kernel status is determined as follows: Divide the running programs of the kernel with multi-core synchronization requirements from the time dimension, and determine the program state in each time period as the kernel state; The program status includes part or all of the configuration status, the start status, the stop status, and the end status.
3. The multi-core synchronization method according to claim 1, characterized in that: Reading each sub-state storage space to obtain the sub-state of each core includes: periodically reading the sub-state of the sub-state storage space corresponding to each core through a backdoor access method; and / or, Updating the main state of the main state storage space to a new state includes: updating the state of the main state storage space to a new state through a backdoor access method.
4. The multi-core synchronization method according to claim 1, characterized in that: The main state storage space is allocated to each core with multi-core synchronization requirements as follows: In the case of multi-core shared memory, allocating one or more common main state storage spaces to all cores with multi-core synchronization requirements; or, In the case of multi-core non-shared memory, multiple independent main state storage spaces are allocated to each core with multi-core synchronization requirements.
5. The multi-core synchronization method according to any one of claims 1 to 4, characterized in that: Also includes: After reading each sub-state storage space to obtain the sub-state of each core, if the sub-state of one or more cores with multi-core requirements is updated to a new state, it is determined whether the sub-states of all cores are updated to the new state.
6. A multi-core synchronization method for system-level chip verification, characterized in that: Applied to the kernel, multi-core synchronization methods include: When the target kernel has a multi-core synchronization requirement, write an updated sub-state reflecting the target kernel state to the sub-state storage space corresponding to the target kernel, so that the SV verification platform obtains the sub-state through the sub-state storage space; wherein the sub-state storage space is allocated by the SV verification platform when the target kernel has a multi-core synchronization requirement; Detect the main state storage space corresponding to the target kernel and determine the main state; wherein the main state storage space is used to reflect the main state of all kernel states with multi-core synchronization requirements, and is allocated by the SV verification platform when the target kernel has multi-core synchronization requirements.
7. The multi-core synchronization method according to claim 6, characterized in that: Writing the updated sub-state reflecting the target kernel state to the sub-state storage space corresponding to the target kernel includes: calling the update sub-state function to write the sub-state reflecting the target kernel state to the sub-state storage space corresponding to the target kernel in a front-door access manner; and / or, Detecting the main state storage space corresponding to the target kernel and determining the main state includes: calling a waiting main state function to periodically read the main state, and determining whether the target kernel completes multi-core synchronization based on the main state.
8. The multi-core synchronization method according to claim 7, characterized in that: Also includes: In the case where the target kernel has a multi-core synchronization requirement, the synchronization position of the target kernel is determined according to the test case; When the running program of the target kernel is executed to the synchronization position, the sub-state function is updated and / or the calling operation of waiting for the main state function is triggered.
9. A multi-core synchronization device for system-level chip verification, comprising a processor and a memory storing program instructions, characterized in that: The processor is configured to execute the multi-core synchronization method for system-on-chip verification according to any one of claims 1 to 8 when running the program instructions.
10. A multi-core synchronization system for system-level chip verification, characterized in that: include: SV verification platform; Kernel, connected to the SV verification platform, kernel means the core of the same CPU or the core of different CPUs; The multi-core synchronization device for system-level chip verification as described in claim 9 is installed in the SV verification platform and / or the kernel.