Bus monitoring module and method, system on chip and electronic equipment

Abstract

The invention provides a bus monitoring module and method, a system on chip and electronic equipment, and is applied to the technical field of computers, the bus monitoring module comprises a preprocessing unit, a general data processing unit and a special data processing unit, the preprocessing unit converts a bus signal of a bus into bus data, and the general data processing unit is used for processing the bus data; the general data processing unit extracts target general data in the bus data according to a preset general data screening condition, the preprocessing unit also provides an enable signal when the bus data meets a preset special data screening condition, and the special data processing unit responds to the enable signal; and obtaining the target special data according to the preset special data screening condition, so that through the bus monitoring module provided by the application, the bus signal can be converted into the bus data, and the target general data and the target special data are screened based on the bus data and the preset condition, thereby realizing monitoring of the bus data; and a reference basis is provided for knowing the hardware behavior and the running state of the electronic equipment.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a bus monitoring module, method, system on chip and electronic device. Background Art

[0002] As the integration of SoC (System on Chip) chips continues to increase, more and more functional units are integrated inside the chip to implement different preset functions, such as processors, peripheral controllers, storage controllers, and system controllers. Most of the functional units are connected through bus communication, and then the bus is used to achieve data interaction required for chip operation.

[0003] Based on the actual application of the above-mentioned bus in the system-on-chip, it can be known that the data information carried by the bus is directly related to the operating status of the chip. Therefore, how to monitor the bus data transmitted by the bus of the system-on-chip during the communication process in order to better understand the hardware behavior of the system-on-chip and accurately analyze and process the operating status of the system-on-chip has become a technical problem that technical personnel in this field need to solve urgently. Summary of the invention

[0004] In view of this, the present application is dedicated to providing a bus monitoring module, method, system on chip and electronic device to monitor bus data transmitted during bus communication, providing a reference basis for understanding the hardware behavior and operating status of the electronic device.

[0005] In a first aspect, the present application provides a bus monitoring module, which is applied to a system on a chip configured with a bus, and the bus monitoring module includes: a preprocessing unit, a general data processing unit and a dedicated data processing unit, wherein:

[0006] The preprocessing unit converts the bus signal transmitted on the bus into bus data, and provides an enable signal when the bus data meets a preset special data screening condition;

[0007] The general data processing unit extracts target general data from the bus data according to a preset general data screening condition;

[0008] The dedicated data processing unit acquires target dedicated data according to a preset dedicated data screening condition in response to the enable signal.

[0009] In an optional implementation, the dedicated data processing unit extracts the target dedicated data in the bus data according to the preset dedicated data screening condition in response to the enable signal, or accesses the target functional unit indicated by the preset dedicated data screening condition to obtain the target dedicated data;

[0010] The target functional unit is any one of a plurality of functional units configured in the system on chip.

[0011] In an optional implementation, the bus monitoring module provided in the first aspect of the present application further includes: a register group, the register group includes a snapshot register group, wherein:

[0012] The snapshot register group is used to store the preset special data screening condition;

[0013] The pre-processing unit and the dedicated data processing unit access the snapshot register group to obtain the preset dedicated data screening condition.

[0014] In an optional implementation, the preprocessing unit includes a gating unit and a parsing unit, wherein:

[0015] The gating unit connects one target bus in the multi-channel bus of the system on chip based on preset enable gating information;

[0016] The parsing unit acquires the bus signal transmitted on the target bus, converts the bus signal into bus data, and provides an enable signal when the bus data meets a preset special data screening condition.

[0017] In an optional implementation, the bus monitoring module provided in the first aspect of the present application further includes: a register group, the register group includes an enable strobe register, wherein:

[0018] The enable strobe register is used to store the preset enable strobe information;

[0019] The gating unit accesses the enable gating register to obtain the preset enable gating information.

[0020] In an optional implementation, the register group further includes: a filter condition register, wherein:

[0021] The filtering condition register is used to store preset filtering conditions;

[0022] After converting the bus signal into bus data, the parsing unit extracts the bus data according to the preset filtering condition.

[0023] In an optional implementation, the preprocessing unit further includes: a synchronization unit, wherein:

[0024] The synchronization unit is connected between the gating unit and the parsing unit;

[0025] The synchronization unit performs clock synchronization processing on the bus signal of the target bus to provide the parsing unit with a bus signal synchronized with the clock frequency of the bus monitoring module.

[0026] In an optional implementation, the general data processing unit includes: a transaction tracking unit, wherein:

[0027] The transaction tracking unit extracts target common data from the bus data according to the preset common data screening condition.

[0028] In an optional implementation, the general data processing unit further includes: an export unit and a cache splicing unit, wherein:

[0029] The export unit transmits the target general data output by the transaction tracking unit to the cache splicing unit;

[0030] The cache tiling unit converts at least one of the target common data into bus data that can be transmitted through the bus.

[0031] In an optional implementation, the bus monitoring module provided in the first aspect of the present application further includes: a transmission unit, wherein:

[0032] The transmission unit stores the target general data and the target specific data in a preset memory.

[0033] In an optional implementation, the transmission unit is configured with a dedicated data channel and a universal data channel;

[0034] The transmission unit queries the general data channel according to a first polling cycle to obtain the target general data, and queries the dedicated data channel according to a second polling cycle to obtain the target dedicated data.

[0035] In an optional implementation, the bus monitoring module provided in the first aspect of the present application further includes a register group, the register group includes a first address register and a second address register, wherein:

[0036] The first address register is used to store a storage address range of the target general data in the preset memory;

[0037] The second address register is used to store a storage address range of the target dedicated data in the preset memory;

[0038] The transmission unit stores the target general data according to the address range stored in the first address register, and stores the target specific data according to the address range stored in the second address register.

[0039] In an optional embodiment, the transmission unit counts the current amount of data stored in the preset memory, and when the current amount of data reaches a preset data amount threshold, notifies the processor of the on-chip system to update the address range stored in the first address register and the second address register.

[0040] In an optional implementation, the register group further includes a capacity register, and the capacity register is used to store the preset data volume threshold;

[0041] The transmission unit accesses the capacity register to obtain the preset data volume threshold.

[0042] In an optional implementation, the bus monitoring module provided in the first aspect of the present application further includes a data recurrence unit, wherein:

[0043] The data recurrence unit extracts recurrence data from the target general data and / or the target specific data according to a preset data recurrence condition, and sends the recurrence data to the bus.

[0044] In an optional implementation, the bus monitoring module provided in the first aspect of the present application further includes a register group, the register group includes a data recurrence register group, the data recurrence register group includes a recurrence condition register, wherein:

[0045] The recurrence condition register is used to store the preset data recurrence condition;

[0046] The data recurrence unit accesses the recurrence condition register to obtain the preset data recurrence condition.

[0047] In an optional implementation, the data recurrence register group further includes a recurrence enable register, wherein:

[0048] The recurrence enable register is used to store a first value representing data recurrence enable, or a second value representing data recurrence disable;

[0049] The data recurrence unit extracts recurrence data from the target general data and / or the target specific data in response to the first value according to a preset data recurrence condition, and sends the recurrence data to the bus.

[0050] In a second aspect, the present application provides a bus monitoring method, which is applied to a system on chip configured with a bus and a bus snooping module, and the method includes the following steps performed by the bus snooping module:

[0051] Acquire a bus signal transmitted on the bus, and convert the bus signal into bus data;

[0052] Extracting target general data from the bus data according to a preset general data screening condition;

[0053] And, when the bus data meets a preset special data screening condition, the target special data is acquired according to the preset special data screening condition.

[0054] In an optional implementation, the bus monitoring method provided in the second aspect of the present application further includes: storing the target general data and the target specific data in a preset memory.

[0055] In an optional implementation, the bus monitoring method provided in the second aspect of the present application further includes: extracting recurrence data from the target general data and / or the target special data according to a preset data recurrence condition, and sending the recurrence data to the bus.

[0056] In a third aspect, the present application provides a system on chip, comprising: a processor, a bus, at least one functional unit, and a bus monitoring module as described in any one of the first aspects of the present application, wherein:

[0057] The functional unit is used to implement the preset function of the system on chip;

[0058] The processor, each of the functional units and the bus monitoring module are mounted on the bus respectively.

[0059] In a fourth aspect, the present application provides an electronic device, comprising the system on chip as described in the third aspect of the present application.

[0060] Based on the above content, the bus monitoring module provided by the present application is applied to a system on a chip configured with a bus. The bus monitoring module includes: a preprocessing unit, a general data processing unit and a special data processing unit. The preprocessing unit converts the bus signal of the bus into bus data. The general data processing unit extracts the target general data in the bus data according to the preset general data filtering conditions. The preprocessing unit also provides an enable signal when the bus data meets the preset special data filtering conditions. The special data processing unit responds to the enable signal and obtains the target special data according to the preset special data filtering conditions. It can be seen that through the bus monitoring module provided by the present application, the bus signal can be converted into bus data, and the target general data and target special data can be filtered based on the bus data and preset conditions to realize bus data monitoring, providing a reference basis for understanding the hardware behavior and operating status of electronic equipment. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0062] Figure 1 It is a structural schematic diagram of a system on chip in the prior art.

[0063] Figure 2 It is a schematic diagram of the structure of a system on a chip provided by this application.

[0064] Figure 3 This is a structural block diagram of a bus monitoring module provided by this application.

[0065] Figure 4 This is a structural block diagram of another bus monitoring module provided by the present application.

[0066] Figure 5 This is a structural block diagram of another bus monitoring module provided by the present application.

[0067] Figure 6 This is a structural block diagram of another bus monitoring module provided by the present application.

[0068] Figure 7 This is a flow chart of a bus monitoring method provided by the present application.

[0069] Figure 8 This is a flow chart of another bus monitoring method provided by the present application. DETAILED DESCRIPTION

[0070] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0071] A system on a chip is an integrated circuit that integrates a complete computer system on a chip. A system on a chip usually includes a bus and multiple functional units for implementing preset functions, such as a processor, input and output interface, storage controller, peripheral controller, and multimedia controller. Most of the functional units are connected through bus communication, and the bus is used to achieve data interaction required for chip operation.

[0072] Figure 1The figure shows a typical structural diagram of a system on chip in the prior art. The system includes a processor 101, a storage controller 102, a peripheral controller 103 and a multimedia controller 104. Of course, other functional units may also be included, which will not be described in detail here. For details, please refer to the relevant technology. Furthermore, the functional units are connected through a bus 105, and the functional units can communicate with each other through the bus 105.

[0073] In recent years, in order to meet the needs of different application scenarios, the development of computer technology and practical application needs have jointly promoted the continuous improvement of the integration of on-chip systems. The amount of information transmitted through the bus between the functional units in the chip has increased rapidly, and the data information carried by the bus is directly related to the operating status of the chip. Therefore, how to monitor the bus data transmitted by the bus of the on-chip system during the communication process, so as to better understand the hardware behavior of the on-chip system through the bus data and accurately analyze and process the operating status of the on-chip system has become a technical problem that technical personnel in this field need to solve urgently.

[0074] To solve the above problems, the present application provides a bus monitoring module, which is applied to a system on chip. The system on chip includes a processor, a bus, at least one functional unit for implementing a preset function of the system on chip, and the bus monitoring module provided by the present application. Figure 1 The example shown is the same, the processor, each functional unit, etc. are mounted on the bus, see Figure 2 As shown, the bus monitoring module 106 provided in the present application is also mounted on the bus 105. The bus monitoring module provided in the present application converts the bus signal transmitted on the bus into bus data, extracts the target general data in the bus data according to the preset general data screening conditions, and also obtains the target special data according to the preset special data screening conditions when the bus data meets the preset special data screening conditions. It can be seen that through the bus monitoring module provided in the present application, the bus signal can be converted into bus data, and the target general data and target special data can be screened based on the bus data and preset conditions to realize bus data monitoring, thereby providing a reference basis for understanding the hardware behavior and operating status of electronic equipment.

[0075] Based on the above, see Figure 3 The bus monitoring module provided in the present application includes: a pre-processing unit 10, a general data processing unit 20 and a dedicated data processing unit 30.

[0076] Combination Figure 3As shown, the input end of the preprocessing unit 10 is connected to the bus 105 to obtain the bus signal transmitted by the bus 105, the first output end of the preprocessing unit 10 is connected to the general data processing unit 20, and the second output end is connected to the special data processing unit 30. After obtaining the bus signal transmitted on the bus, the preprocessing unit 10 converts the bus signal into bus data. Further, the preprocessing unit will also provide an enable signal when the obtained bus data meets the preset special data screening condition.

[0077] The general data processing unit 20 receives the bus data provided by the preprocessing unit 10, and extracts the target general data in the bus data according to the preset general data screening conditions; the special data processing unit 30 responds to the enable signal provided by the preprocessing unit 10, and obtains the target special data according to the preset special data screening conditions.

[0078] It should be noted that, in the present application, target general data mainly refers to bus data that is transmitted in the bus and meets preset general data screening conditions when the system on chip is running. The target general data can come from any functional unit inside the system on chip.

[0079] Based on the above definition of target common data, it can be seen that the preset common data filtering conditions are mainly used to filter part of the data from all bus data transmitted on the bus. In practical applications, they can be configured based on the common characteristics of each functional unit in the process of transmitting data through the bus.

[0080] In an optional embodiment, the preset general data screening condition can be set based on the transaction characteristics, and the transaction characteristics used to set the preset general data screening condition can include at least one of the address of the bus request, the identification mark of the bus request, the data content in the bus information, and the response content of the bus request. In practical applications, the preset general data screening condition can be set based on a single specified value of at least one of the aforementioned transaction characteristics, or a corresponding tracking range can be set based on at least one of the aforementioned transaction characteristics. For example, the selected transaction characteristic is the address of the write transaction, and the address of the write transaction is 0x8000_0030. Based on this, the preset general data screening condition can be set to the single address, that is, the target data of the address 0x8000_0030 is obtained, or the address range can be set based on 0x8000_0030, such as 0x8000_0000~0x8000_1000, that is, all data with addresses within the address range will be used as target general bus data.

[0081] In practical applications, transaction features are selected according to actual monitoring needs, and then preset general data screening conditions are configured in combination with transaction features to ensure that the target general data extracted according to the preset general data screening conditions meet the actual needs of bus monitoring. At the same time, the target general data can also be screened and filtered through the preset general data screening conditions, which helps to reduce the data volume of the target general data, thereby reducing the logical overhead of bus monitoring and improving monitoring efficiency. It is understandable that the preset general data screening conditions can also be configured according to other actual monitoring needs, which are no longer listed here one by one. Without exceeding the scope of the core idea of ​​this application, they also fall within the scope of protection of this application. As for the specific configuration method of the preset general data screening conditions, it will be launched in the subsequent content in combination with the specific embodiments, and will not be described in detail here.

[0082] Compared with target general data, target specific data is more targeted and can be the data of a specified functional unit when the on-chip system is running. For example, when it is necessary to analyze the operating status of a peripheral controller, the target specific data is mainly data related to the operating process of the peripheral controller.

[0083] Based on the above definition of target-specific data, it can be understood that target-specific data is more targeted and directed, and is usually used to monitor a certain functional unit or a certain type of bus data. In other aspects, there is not much difference from the target general data. Therefore, the setting of the preset special data filtering conditions can refer to the setting of the preset general filtering conditions, that is, it can also be configured based on transaction characteristics. Of course, when filtering data for a certain functional unit, the preset special data filtering conditions should also limit the corresponding functional unit. For example, a unique corresponding unit identifier is added to each functional unit in the on-chip system. Based on this, the target unit identifier corresponding to the target functional unit can be specified in the preset special data filtering conditions, so that in the subsequent data screening process, the target unit identifier and the configured transaction characteristics can be combined to complete the acquisition of the target special data.

[0084] Combination Figure 3 As shown, as an optional implementation, the bus monitoring module provided by the present application is also provided with a register group 40, and the register group 40 includes a snapshot register group 410. Further, the snapshot register group 410 specifically includes a snapshot object register and a snapshot condition register, wherein the snapshot object register is used to store information indicating a functional unit, such as the target unit identifier mentioned in the aforementioned content, and correspondingly, the snapshot condition register is mainly used to store other features required for configuring preset special data filtering conditions, such as transaction features. Of course, it can also be other information that can indicate special data filtering conditions, which will not be described in detail here.

[0085] Preset special data screening conditions can be stored through the snapshot register group 410. For example, the snapshot condition can be configured in the snapshot condition register as: a read request for address 0x80000000, and the snapshot object can be configured in the snapshot object register as: core1. Based on this, when the preprocessing unit detects that there is a read request for address 0x80000000 on the bus and the request object is core1, the enable signal can be triggered.

[0086] In practical applications, the snapshot register set 410 may be configured by a processor of the system on chip, that is, before performing bus monitoring, the processor accesses the snapshot register set through the bus and configures preset dedicated data screening conditions in the snapshot register set.

[0087] The preprocessing unit 10 accesses the snapshot register group to obtain the preset special data screening condition, and when the bus data meets the preset special data screening condition, provides an enable signal to the special data processing unit 30. The special data processing unit 30 also accesses the snapshot register group to obtain the preset special data screening condition, and in response to the aforementioned enable signal, obtains the target special data according to the preset special data screening condition.

[0088] It can be seen from the foregoing that the target-specific data may come from a specific target functional unit. Since the target functional unit also transmits data through the bus, the obtained bus data may also include the target-specific data. Based on this, in an optional implementation, the dedicated data processing unit 30 can extract the target-specific data from the bus data according to preset dedicated data screening conditions.

[0089] In another optional embodiment, the dedicated data processing unit 30 can communicate directly with the target functional unit (for example, through a dedicated communication link). In response to an enable signal, the dedicated data processing unit 30 can directly access the target functional unit indicated by a preset dedicated data filtering condition to obtain target dedicated data. Of course, in actual applications, the target functional unit can be any one of the multiple functional units set in the on-chip system.

[0090] To summarize, the bus monitoring module provided by the present application converts the bus signal of the bus into bus data through a preprocessing unit, and the general data processing unit extracts the target general data in the bus data according to the preset general data screening conditions. The preprocessing unit also provides an enable signal when the bus data meets the preset special data screening conditions. The special data processing unit responds to the enable signal and obtains the target special data according to the preset special data screening conditions. Through the bus monitoring module provided by the present application, the bus signal can be converted into bus data, and the target general data and target special data can be screened based on the bus data and preset conditions to realize bus data monitoring, thereby providing a reference basis for understanding the hardware behavior and operating status of electronic equipment.

[0091] Furthermore, the present application also provides another bus monitoring module. Figure 3 Based on the embodiment shown, the bus monitoring module provided in this embodiment provides an optional implementation of a preprocessing unit. Figure 4 As shown, in the bus monitoring module provided by the present application, the pre-processing unit 10 includes a gating unit 110 and a parsing unit 120. Furthermore, the register group 40 also includes an enable gating register 420 and a filtering condition register 430.

[0092] It is understandable that there are a large number of functional units in the system on chip. In order to meet the communication requirements between the functional units, multiple buses are usually set inside the system on chip. Based on this, as an optional implementation, the gating unit 40 includes multiple signal input terminals and one signal output terminal. At the same time, at most only one signal input terminal is connected to the signal output terminal. In practical applications, each signal input terminal of the gating unit 110 is connected to a bus, and the buses connected to each signal input terminal are different from each other, so as to realize the reception of bus signals of each bus. Further, the gating unit 110 connects a target bus in the multiple buses of the system on chip based on the preset enable gating information, that is, the signal input terminal corresponding to the control target bus is connected to the signal output terminal, so as to obtain the target bus signal. Of course, when the preset enable gating information is not configured, any signal input terminal is not connected to the signal output terminal.

[0093] In one possible implementation, the gating unit 110 may be implemented based on a multiplexer (MUX), and each bus within the on-chip system is respectively connected to each input terminal of the MUX. Of course, the input terminals of the MUX connected to each bus are different from each other, and the output terminal of the MUX serves as the signal output terminal of the gating unit 110. The MUX may establish connectivity between the input terminal and the output terminal connected to the target bus according to the enable gating information, thereby establishing a communication connection with the target bus.

[0094] Combination Figure 4 As shown, as an optional implementation, the bus monitoring module provided in this embodiment stores the aforementioned preset enable gating information through the enable gating register 420, and the gating unit 110 accesses the enable gating register 420 to obtain the preset enable gating information stored therein. In the present application, the enable gating information has two functions, one of which is to enable, that is, to control the gating unit to start running, and the other is to select, that is, to control the gating unit to select one bus as the target bus in the multi-channel bus. In this embodiment, the above two functions are realized by an enable gating register 420. In another possible implementation, two independent registers can be set, one of which is used to enable the gating unit, that is, when the register is written with a first value indicating that the gating unit can run, the gating unit starts to run, and the other register is used to store the information of the target bus. Of course, when the connection relationship between each bus and the signal input end of the gating unit is determined, it can also be used to store the information of the target signal input end, and the gating unit determines which bus is specifically connected according to the information stored in the register. It should be noted that, similar to the configuration of other types of registers in the aforementioned register group, the enable strobe register 420 provided in this embodiment and the filter condition register 430 described in the subsequent content can both be configured by the processor in the system on chip.

[0095] Furthermore, the parsing unit 120 includes an input end, a first output end and a second output end, wherein the input end of the parsing unit 120 is connected to the output end of the selection unit 110, the first output end of the parsing unit 120 is connected to the general data processing unit 20 as the first output end of the preprocessing unit 10, and the second output end of the parsing unit 120 is connected to the dedicated data processing unit 30 as the second output end of the preprocessing unit 10.

[0096] The parsing unit 120 receives the bus signal provided by the gating unit 110 and parses the bus signal. In combination with the basic principle of the internal bus of the system on chip transmitting bus information, it can be known that the bus signal obtained by the parsing unit 120 is a digital signal arranged according to the relevant definition of the bus communication protocol. The parsing unit 120 needs to parse the obtained bus signal according to the bus communication protocol to obtain the corresponding bus data. As for the specific implementation process of parsing the bus signal based on the bus protocol to obtain the bus data, it can be combined with the specific content of the bus protocol and the relevant technical implementation, which will not be described in detail here.

[0097] Combination Figure 4As shown, as an optional implementation, the register group 40 also includes a filter condition register 430, which stores preset filter conditions. The parsing unit 120 obtains the preset filter conditions recorded in the filter condition register 430 by accessing the filter condition register 430. After converting the bus signal into bus data, the corresponding bus data can be further extracted according to the preset filter conditions. The bus data obtained after extraction according to the preset filter conditions can be defined as target bus data. The parsing unit 120 further sends the bus data filtered according to the preset filter conditions (i.e., the aforementioned target bus data) to the general data processing unit 20, and provides the aforementioned enable signal to the special data processing unit 30 when the filtered bus data meets the preset special data filtering conditions.

[0098] In a possible implementation, the preset filtering condition can be set based on at least one of the amount of data on the bus, the address corresponding to the bus signal, and the identification mark corresponding to the bus signal (such as the number of the bus request). In practical applications, the preset filtering condition can be a single specified value of at least one of the amount of data on the bus, the address corresponding to the bus signal, and the identification mark corresponding to the bus signal, or it can be a filtering range set based on at least one of the aforementioned information. For example, the address corresponding to the bus request is set, and during the bus monitoring process, only the bus data of the address is extracted.

[0099] Based on the setting of preset filtering conditions, it can be seen that through the preset filtering conditions, only the information required for bus monitoring can be obtained, and other information not required for bus monitoring will be filtered out. Therefore, the preset filtering conditions can effectively reduce the amount of bus data obtained.

[0100] In an optional implementation, in the bus monitoring module provided in this embodiment, the preprocessing unit further includes a synchronization unit ( Figure 4 The synchronization unit is connected between the selection unit 110 and the analysis unit 120, and the synchronization unit performs clock synchronization processing on the bus signal of the target bus to provide the analysis unit 120 with a bus signal synchronized with the clock frequency of the bus monitoring module.

[0101] Specifically, the cross-clock domain synchronization processing of any bus signal by the synchronization unit can be divided into two cases: one is that the clock domain where the bus is located is consistent with the clock domain where the bus monitoring module is located, that is, the clock frequency of the bus is the same as the clock frequency of the bus monitoring module. In this case, the synchronization unit can be constructed with two-level registers to form a two-level synchronization unit, and each bus signal in the bus is input to the data input end of the two-level synchronization unit, and finally the synchronized bus signal is output from the output end of the synchronization unit. Another case is that the clock of the clock domain where the bus is located is slower than the clock of the clock domain where the bus monitoring module is located, that is, the clock frequency of the bus is less than the clock frequency of the bus monitoring module. In this case, the synchronization unit can be synchronized based on an asynchronous first-in first-out buffer (First In First Out, FIFO) of Gray code. As for the specific implementation of the two-level synchronization unit and the asynchronous first-in first-out buffer based on Gray code mentioned in the above content, reference can be made to the relevant technology, which will not be described in detail here.

[0102] In practical applications, the clock frequency of the bus monitoring module should be greater than or equal to the clock frequency of each bus in the on-chip system to ensure that changes in the bus signal can be sampled and that the bus signal is not lost.

[0103] In summary, compared with the above-mentioned embodiment, the bus monitoring module provided in this embodiment determines a target bus to be monitored in a multi-channel bus through a gating unit and obtains the bus signal of the target bus. Since only one target bus in a multi-channel bus is monitored, the amount of bus data can be effectively reduced, thereby reducing the logical overhead of bus monitoring and the power consumption of the bus monitoring module. Moreover, in practical applications, the target bus can be selected by presetting the enabling gating information, and a certain bus can be monitored in a targeted manner, thereby focusing on important buses in the system on chip.

[0104] Furthermore, the present application provides another bus monitoring module. Compared with the bus monitoring module provided in any of the above embodiments, the bus monitoring module provided in this embodiment provides an optional implementation of a general data processing unit, see Figure 5 As shown, the general data processing unit 20 provided in this embodiment includes a transaction tracking unit 210, and further includes an export unit 220 and a cache splicing unit 230. Furthermore, a tracking condition register 440 is added to the register group 40.

[0105] Combination Figure 5 As shown, the input end of the transaction tracking unit 210 is connected to the parsing unit 120 in the preprocessing unit 10 as the input end of the general data processing unit 20, and receives the bus data provided by the parsing unit 120. The output end of the transaction tracking unit 210 is connected to the export unit 220, and the export unit 220 is connected to the cache splicing unit 230.

[0106] The tracking condition register 440 is used to store the preset general data screening conditions mentioned above. The transaction tracking unit 210 obtains the preset general data screening conditions by accessing the tracking condition register 440, and extracts the target general data in the bus data according to the preset general data screening conditions. As for the specific setting method of the preset general data screening conditions, please refer to Figure 3 The relevant contents in the illustrated embodiment will not be repeated here. Further, in an optional implementation, the preset general data screening conditions stored in the tracking condition register 440 can be configured by the processor of the system on chip.

[0107] In some application scenarios, after obtaining the target general data, the target general data needs to be further exported so that technicians can analyze the operation of the bus and the system on chip. For this purpose, the general data processing unit 20 provided in the present application is also configured with an export unit 220 and a cache splicing unit 230.

[0108] The transaction tracking unit 210 outputs the target general data to the export unit 220, and the export unit 220 transmits the target general data to the cache splicing unit 230. The cache splicing unit 230 converts at least one target general data into bus data that can be transmitted through the bus. It can be understood that the bus data mentioned in the above content and the target general data obtained after screening are not consistent with the format of the bus transmission signal. In other words, the bus data and the target general data do not meet the relevant requirements of the bus protocol on the data format. Therefore, before data is transmitted through the bus, the cache splicing unit 230 needs to convert the format of the data to be transmitted to meet the data transmission requirements of the bus.

[0109] Furthermore, the cache splicing unit 230 can also play the role of data cache. In actual applications, the target general data screened by the transaction tracking unit 210 may be of different sizes. It is obvious that a large amount of logical overhead is required to perform a data export operation each time a target general data is extracted. In order to improve the data export efficiency, the cache splicing unit 230 can cache the target general data provided by the transaction tracking unit 210. When the obtained target general data meets the minimum requirement of the bus transmission data, the format of at least one obtained target general data is converted to obtain data that meets the bus transmission requirements.

[0110] Correspondingly, the dedicated data processing unit 30 may refer to the function of the cache splicing unit 230 to perform format conversion on the obtained target dedicated data to meet the data transmission requirements of the bus, which will not be repeated here.

[0111] In order to export the target general data and the target specific data, the bus monitoring module provided in this embodiment further includes a transmission unit 50, combined with Figure 5 As shown, the dedicated data channel of the transmission unit 50 is connected to the dedicated data processing unit 30, the general data channel is connected to the output end of the cache splicing unit 230 in the general data processing unit 20, and the output end of the transmission unit 50 is connected to the bus 105. The transmission unit 50 is used to store the target general data and the target dedicated data to the preset memory 60.

[0112] It should be noted that in Figure 5 In the illustrated embodiment, the preset memory 60 is an external memory mounted on the bus, and the transmission unit 50 stores the target general data and the target specific data in the external memory via the bus 105. In another optional embodiment, the preset memory 60 may also be an internal memory disposed inside the bus monitoring module, in which case the transmission unit 50 may store the target general data and the target specific data directly in the internal memory without passing through the bus 105.

[0113] In another optional embodiment, the preset memory includes an external memory and an internal memory, and the capacity of the external memory is greater than the capacity of the internal memory. Based on this, the transmission unit 50 can store target general data with a larger data volume to the external memory, and correspondingly, store target special data with a relatively smaller data volume to the internal memory.

[0114] Of course, as an optional implementation, the external memory and the internal memory can also be used in a time-sharing manner. A selection register for enabling the memory is added to the register group. When the first value representing the enablement of the external memory is written into the selection register, the transmission unit stores both the target-specific data and the target-general data in the external memory. Correspondingly, when the second value representing the enablement of the internal memory is written into the selection register, the transmission unit writes both the target-specific data and the target-general data into the internal memory.

[0115] Furthermore, in order to realize fast transmission of bus data, the transmission unit 50 can be implemented based on a low-depth FIFO queue, thereby realizing concurrent transmission of multiple groups of data and effectively improving data transmission efficiency.

[0116] In an optional embodiment, in order to effectively balance the transmission process of the target-specific data and the target-general data and avoid data omission, the transmission unit 50 queries the aforementioned general data channel according to the first polling cycle to obtain the target general data received through the general data channel. Correspondingly, the transmission unit 50 also queries the aforementioned special data channel according to the second polling cycle to obtain the target-specific data received through the special data channel. It can be understood that in actual applications, the first polling cycle and the second polling cycle can be the same or different, and the specific needs need to be determined in combination with factors such as the data collection efficiency and data volume of the target-specific data and the target general data. The present application does not limit the specific values ​​of the first polling cycle and the second polling cycle.

[0117] As mentioned above, the sources of the target-specific data and the target-general data and their specific functions in the bus monitoring process are different, so it is necessary to store the target-specific data and the target-general data in different storage spaces. Based on this, in the bus monitoring module provided in this embodiment, the register group 40 also includes a first address register 450 and a second address register 460.

[0118] Specifically, the first address register 450 is used to store the storage address range of the target general data in the preset memory 60, and correspondingly, the second address register 460 is used to store the storage address range of the target special data in the preset memory 60. Based on this, when exporting data, the transmission unit 50 stores the target general data according to the address range stored in the first address register 450, and stores the target special data according to the address range stored in the second address register 460, thereby realizing independent storage of the target general data and the target special data.

[0119] In actual applications, the address range recorded by the first address register 450 and the second address register 460 can be configured by the processor of the system on chip. In other words, the processor can set the storage space for target general data and target special data according to the occupancy of the internal storage space of the preset memory 60, so as to meet the data storage requirements in different situations.

[0120] In an optional implementation, the transmission unit 50 provided in this embodiment can also count the current amount of data stored in the preset memory 60 during the process of transmitting the target dedicated data and the target general data, and when the current amount of data reaches the preset data amount threshold, notify the processor of the system on chip to update the address range stored in the first address register and the second address register, that is, to create a new storage space to meet the storage requirements of the bus data. As an optional implementation, the transmission unit 50 can simultaneously update the address range stored in the first address register and the second address register by generating an interrupt signal, so that the processor can perform the address update operation in time to ensure that the bus data will not be lost or missed due to insufficient storage space.

[0121] Combination Figure 5 As shown, the register group 40 also includes a capacity register 470, through which the aforementioned preset data volume threshold is stored, and the transmission unit 50 accesses the capacity register 470 to obtain the preset data volume threshold, and then completes the data storage task based on the preset data volume threshold. Like other registers in the register group 40, the capacity register 470 can also be configured by the processor in the system on chip. Based on the above content, the processor responds to the interrupt signal output by the transmission unit 50, and while updating the address range stored in the first address register and the second address register, it can also synchronously update the preset data volume threshold stored in the capacity register 470. Of course, the same preset data volume threshold can also be used, that is, only the address range stored in the first address register and the second address register is updated.

[0122] In summary, based on the above embodiments, the bus monitoring module provided in this embodiment can also realize the export and storage of target general data and target special data, providing convenience for technicians to analyze the overall operating status of the bus and the system on chip based on the exported data. Furthermore, the storage address of the data can be updated according to the amount of the exported data, and the effective storage of the exported data can be ensured by creating a new storage space to avoid the omission of the exported data, so as to provide comprehensive and accurate data support for analyzing the operating status of the bus and the system on chip.

[0123] In actual applications, the realization of certain functions of the system on chip only depends on the execution results of the software, and does not care about the specific execution process of the software. For example, it depends on the calculation results of the calculation program, but does not care about the specific calculation process. For these functions, if the relevant software is executed once each time the function is realized to obtain the required execution results, this will obviously cause the execution efficiency of the corresponding functions to be low. For another example, the data interaction relationship between the functional modules of the system on chip is stored. For the data receiver, it does not care about the execution process of the data sender. As long as the correct data can be provided, the normal operation of the data receiver can be ensured. For these application scenarios, improving the execution results and data supply efficiency is the key to improving the execution efficiency of related functions or functional units in the system on chip.

[0124] In order to solve the above technical problems, based on any of the above embodiments, the present application also provides another bus monitoring module, combined with Figure 6 As shown ( Figure 5 The bus monitoring module provided in the embodiment shown is based on the bus monitoring module provided in the embodiment, the bus monitoring module provided in this embodiment also includes a data recurrence unit 70, and accordingly, a recurrence register group 480 is newly added in the register group 40, and the register group specifically includes a recurrence enable register and a recurrence condition register.

[0125] Combination Figure 6 As shown, the input end and the output end of the data repetition unit 70 are respectively connected to the bus 105. In practical applications, the repetition enable register is used to represent a first value of data repetition enable, or a second value of data repetition prohibition. The data repetition unit 70 accesses the repetition enable register. If the second value is stored in the repetition enable register, the data repetition function is not executed. On the contrary, if the first value is stored in the repetition enable register, the data repetition unit 70 executes the data repetition function in response to the first value.

[0126] Furthermore, the recurrence condition register in the recurrence register group is used to store the preset data recurrence condition. As mentioned above, the target-specific data and the target general data derived by the transmission unit 50 are stored in the preset memory. Therefore, in an optional embodiment, the preset data recurrence condition can be set based on the storage address of the target-specific data and / or the target general data in the preset memory, that is, the preset data recurrence condition is the corresponding address range. Of course, the preset data recurrence condition can also be other feature settings that can clearly indicate the recurrence data in the target-specific data and / or the target general data. They are not listed here one by one. Without exceeding the core idea of ​​the present application, they also belong to the scope of protection of the present application.

[0127] The data recurrence unit 70 accesses the recurrence condition register, obtains the preset data recurrence condition, extracts the recurrence data from the target general data and / or the target specific data according to the preset data recurrence condition, and then sends the recurrence data to the bus. It can be seen that the recurrence data described in this embodiment can come from at least one of the target general data and the target specific data. In practical applications, the source of the recurrence data can be selected in combination with the actual data recurrence requirements.

[0128] It can be understood that, since the recurrence data comes from the target general data and / or the target specific data, the data recurrence process must occur after the transmission unit 50 stores the target general data and the target specific data in the preset memory. Therefore, in practical applications, it is necessary to reasonably configure the recurrence enable register in combination with the storage status of the target specific data and the target general data to ensure that the data recurrence unit 70 can successfully extract the recurrence data from the preset memory.

[0129] It should be noted that in Figure 6 In the illustrated embodiment, the preset memory 60 adopts an external memory mounted on the bus 105 and independently arranged with the bus monitoring module. Therefore, the data recurrence unit 70 extracts the recurrence data according to the preset data recurrence condition and sends the recurrence data through the bus 105, that is, firstly extracts the recurrence data according to the preset data recurrence condition through the external memory within the scope of the bus 105, further, converts the obtained recurrence data into a bus signal matching the bus, and finally sends the recurrence data to the bus in the form of a bus signal. Correspondingly, if the preset memory 60 adopts an internal memory arranged inside the bus monitoring module, the extraction process of the recurrence data does not need to pass through the bus 105. After obtaining the recurrence data, the obtained recurrence data is converted into a bus signal matching the bus, and the recurrence data is also sent to the bus in the form of a bus signal.

[0130] In a possible implementation, a recurrence cycle register may also be included in the register group, and the recurrence cycle of the recurrence data may be configured through the recurrence cycle register. When the recurrence cycle is defaulted, the data recurrence unit recurs the recurrence data only once; correspondingly, when a determined recurrence cycle is stored, the data recurrence unit repeatedly sends the recurrence data to the bus according to the recurrence cycle.

[0131] To sum up, the bus monitoring module provided in this embodiment, based on the aforementioned embodiment, also has a data recurrence function. By recurring data to the bus data, data for implementing specified functions can be provided to relevant parties without omitting the execution process of relevant software or functional units, thereby saving the time required for relevant software or functional units to generate recurrence data and improving the efficiency of providing recurrence data.

[0132] Furthermore, the bus monitoring module can also enhance its ability to perceive hardware behavior and clearly understand the execution process of related hardware. At the same time, it can also improve its ability to intervene in the operation process of the on-chip system, that is, by extracting recurrent data from the bus data, it can directly provide the required data to the related software or functional units. The data generation process does not require the participation of the original data provider. In other words, the bus monitoring module can achieve the same function without understanding the specific implementation process of the data provider.

[0133] The present application also provides a bus monitoring method, which is applied to Figure 2 The system on chip shown is specifically applied to a bus monitoring module in the system on chip. Figure 7 As shown, the bus monitoring method provided by the present application may include the following steps.

[0134] S100: Acquire a bus signal of a bus, and convert the bus signal into bus data.

[0135] The bus monitoring module is connected to the bus in the system on chip, obtains the bus signal of the bus, and converts the bus signal into corresponding bus data. As for the specific implementation of converting the bus signal into bus data, it can refer to the bus protocol and related technical implementation specifically supported by the bus, which will not be described in detail here.

[0136] In an optional embodiment, if the bus in the on-chip system includes multiple buses, one of the multiple buses can be selected as the target bus according to preset enable selection information, and the bus signal transmitted on the target bus can be obtained, and the bus signal transmitted on the target bus can be converted into corresponding bus data. Furthermore, when the obtained bus data meets the preset special data screening conditions, execution S120 can be triggered.

[0137] In one possible implementation, the bus monitoring module is configured with a register group, which includes an enable strobe register. The processor of the system on chip configures the enable strobe register to store preset enable strobe information. The bus monitoring module can obtain the aforementioned preset enable strobe information by accessing the enable strobe register.

[0138] S110, extracting target common data from the bus data according to preset common data screening conditions.

[0139] It should be noted that in this application, the target general data mainly refers to the bus data that is transmitted in the bus and meets the preset general data screening conditions when the system on chip is running. The target general data can come from any functional unit inside the system on chip. The preset general data screening conditions are mainly used to filter some data from all bus data transmitted by the bus. In practical applications, they can be configured based on the common characteristics of each functional unit in the process of transmitting data through the bus.

[0140] In an optional embodiment, the preset general data filtering conditions can be set based on transaction characteristics, and the transaction characteristics used to set the preset general data filtering conditions can include at least one of the address of the bus request, the identification mark of the bus request, the data content in the bus information, and the response content of the bus request.

[0141] As for the specific implementation of S110, reference may be made to the relevant contents of extracting target general data by the general data processing unit in the bus monitoring module provided in any of the aforementioned embodiments, which will not be repeated here.

[0142] S120. When the bus data meets the preset special data screening condition, obtain the target special data according to the preset special data screening condition.

[0143] Compared with target general data, target specific data is more targeted and can be the data of a specified functional unit when the on-chip system is running. For example, when it is necessary to analyze the operating status of a peripheral controller, the target specific data is mainly data related to the operating process of the peripheral controller.

[0144] Target-specific data is more targeted and directional, and is usually used to monitor a certain functional unit or a certain type of bus data. In other aspects, it is not much different from the target general data. Therefore, the setting of preset special data filtering conditions can refer to the setting of preset general filtering conditions, that is, it can also be configured based on transaction characteristics. Of course, when filtering data for a certain functional unit, the preset special data filtering conditions should also limit the corresponding functional unit, for example, add a unique corresponding unit identifier to each functional unit in the on-chip system.

[0145] In an optional embodiment, the register group of the bus monitoring module also includes a snapshot register group, which specifically includes a snapshot object register and a snapshot condition register, wherein the snapshot object register is used to store information indicating the functional unit, and the snapshot condition register is mainly used to store other features required to configure preset special data screening conditions.

[0146] The processor of the system on chip can store preset special data filtering conditions through the snapshot register group. The preset special data filtering conditions can be obtained by accessing the snapshot register group, and when the bus data meets the preset special data filtering conditions, the target special data can be obtained according to the preset special data filtering conditions.

[0147] As for the specific implementation of S120, reference may be made to the relevant contents of extracting the target dedicated data by the dedicated data processing unit in the bus monitoring module provided in any of the aforementioned embodiments, which will not be repeated here.

[0148] To summarize, through the bus monitoring method provided by the present application, after the bus signal of the bus is converted into bus data, the target general data in the bus data is extracted according to the preset general data screening conditions, and when the bus data meets the preset special data screening conditions, the target special data is obtained according to the preset special data screening conditions. In this way, the bus signal can be converted into bus data, and the target general data and target special data can be screened based on the bus data and the preset conditions to realize bus data monitoring, thereby providing a reference basis for understanding the hardware behavior and operating status of electronic equipment.

[0149] Furthermore, the present application also provides another bus monitoring method, see Figure 8 ,exist Figure 7 Based on the illustrated embodiment, the bus monitoring method provided by this embodiment further includes the following steps.

[0150] S130, storing the target general data and the target specific data into a preset memory.

[0151] In an optional implementation, a first polling cycle and a second polling cycle are set respectively, based on which, the target general data is queried and obtained according to the first polling cycle, and the target special data is queried and obtained according to the second polling cycle, and after the target general data and the target special data are obtained, the obtained data are stored in a preset memory. Furthermore, if the amount of target general data is small, at least one target general data can be converted into bus data that can be transmitted through the bus and then stored in the preset memory.

[0152] In an optional implementation, the register group of the bus monitoring module is further provided with a first address register and a second address register, wherein the first address register is used to store the storage address range of the target general data in the preset memory, and the second address register is used to store the storage address range of the target special data in the preset memory. Based on this, the target general data can be stored according to the address range stored in the first address register, and the target special data can be stored according to the address range stored in the second address register.

[0153] Furthermore, the register group of the bus monitoring module is also configured with a capacity register, which can also be maintained by the processor of the system on chip, and a preset data volume threshold is configured. By accessing the capacity register, the preset data volume threshold can be obtained. Based on this, the current data volume stored in the preset memory is counted, and when the current data volume reaches the preset data volume threshold, the processor of the system on chip is notified to update the address range stored in the first address register and the second address register, so as to continue to store data in the new address space.

[0154] As for the specific implementation of S130, please refer to the above Figure 5 The relevant contents in the illustrated embodiment will not be repeated here.

[0155] S140 , extracting recurrence data from target general data and / or target specific data according to a preset data recurrence condition, and sending the recurrence data to a bus.

[0156] In an optional implementation, the register group of the bus monitoring module also includes a data recurrence register group, which specifically includes a recurrence condition register and a recurrence enable register, wherein the recurrence condition register is used to store a preset data recurrence condition, and the recurrence enable register is used to store a first value representing data recurrence enable, or a second value representing data recurrence prohibition. When accessing the recurrence enable register, if the first value is stored therein, recurrence data can be extracted from the target general data and / or target special data according to the preset data recurrence condition stored in the recurrence condition register, and the recurrence data can be sent to the bus.

[0157] As for the specific implementation of S140, please refer to the above Figure 6 The relevant contents in the illustrated embodiment will not be repeated here.

[0158] In summary, the bus monitoring method provided in this embodiment can realize the export and storage of target general data and target special data, providing convenience for technicians to analyze the overall operating status of the bus and the system on chip based on the exported data. Furthermore, by regurgitating data to the bus data, data for implementing specified functions can be provided to relevant parties without omitting the execution process of related software or functional units, thereby saving the time required for related software or functional units to generate recurrence data and improving the efficiency of providing recurrence data.

[0159] The present application also provides an electronic device, comprising a system on chip as provided in any of the aforementioned embodiments.

[0160] In some embodiments, this embodiment further provides a computer-readable storage medium, such as a floppy disk, an optical disk, a hard disk, a flash memory, a USB flash disk, an SD (Secure Digital Memory Card) card, an MMC (Multimedia Card) card, etc., in which one or more instructions for implementing the above steps are stored, and when the one or more instructions are executed by one or more processors, the processors execute the bus monitoring method described above. For the relevant specific implementation, please refer to the above description, which will not be repeated here.

[0161] In addition to the above-mentioned methods and devices, an embodiment of the present application may also be a computer program product, which includes computer program instructions, which, when executed by a processor, enable the processor to execute the steps of the bus monitoring method according to various embodiments of the present application described in the above content of this specification.

[0162] The computer program product may be written in any combination of one or more programming languages ​​to write program codes for performing the operations of the embodiments of the present application, including object-oriented programming languages ​​such as Java, C++, etc., and conventional procedural programming languages ​​such as "C" language or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a separate software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0163] Those skilled in the art will appreciate that the contents disclosed in this disclosure may be subject to various modifications and improvements. For example, the various devices or components described above may be implemented by hardware, or by software, firmware, or a combination of some or all of the three.

[0164] In addition, although the present disclosure makes various references to certain units in the system according to embodiments of the present disclosure, any number of different units can be used and run on the client and / or server. The units are only illustrative, and different aspects of the system and method can use different units.

[0165] Flowcharts are used in this disclosure to illustrate the steps of the method according to the embodiments of the present disclosure. It should be understood that the preceding or following steps are not necessarily performed precisely in order. On the contrary, various steps may be processed in reverse order or simultaneously. At the same time, other operations may also be added to these processes.

[0166] Those skilled in the art will appreciate that all or part of the steps in the above method can be completed by instructing related hardware through a computer program, and the program can be stored in a computer-readable storage medium, such as a read-only memory. Optionally, all or part of the steps in the above embodiment can also be implemented using one or more integrated circuits. Accordingly, each module / unit in the above embodiment can be implemented in the form of hardware or in the form of a software functional unit. The present disclosure is not limited to any particular form of combination of hardware and software.

[0167] Unless otherwise defined, all terms used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It should also be understood that terms such as those defined in common dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an idealized or highly formal sense, unless explicitly defined as such herein.

[0168] The above is an explanation of the present disclosure and should not be considered as a limitation thereof. Although several exemplary embodiments of the present disclosure are described, it will be readily understood by those skilled in the art that many modifications may be made to the exemplary embodiments without departing from the novel teachings and advantages of the present disclosure. Therefore, all such modifications are intended to be included within the scope of the present disclosure as defined in the claims. It should be understood that the above is an explanation of the present disclosure and should not be considered to be limited to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims. The present disclosure is defined by the claims and their equivalents.

Claims

1. A bus monitoring module, characterized in that: Applied to a system on chip configured with a bus, the bus monitoring module includes: a pre-processing unit, a general data processing unit and a special data processing unit, wherein: The preprocessing unit converts the bus signal transmitted on the bus into bus data, and provides an enable signal when the bus data meets a preset special data screening condition; The general data processing unit extracts target general data from the bus data according to a preset general data screening condition; The dedicated data processing unit acquires target dedicated data according to a preset dedicated data screening condition in response to the enable signal.

2. The bus monitoring module according to claim 1, characterized in that: The dedicated data processing unit extracts the target dedicated data from the bus data according to the preset dedicated data screening condition in response to the enable signal, or accesses the target functional unit indicated by the preset dedicated data screening condition to obtain the target dedicated data; The target functional unit is any one of a plurality of functional units configured in the system on chip.

3. The bus monitoring module according to claim 1, characterized in that: Also includes: A register group, the register group comprising a snapshot register group, wherein: The snapshot register group is used to store the preset special data screening condition; The pre-processing unit and the dedicated data processing unit access the snapshot register group to obtain the preset dedicated data screening condition.

4. The bus monitoring module according to claim 1, characterized in that: The preprocessing unit includes a gating unit and a parsing unit, wherein: The gating unit connects one target bus in the multi-channel bus of the system on chip based on preset enable gating information; The parsing unit acquires the bus signal transmitted on the target bus, converts the bus signal into bus data, and provides an enable signal when the bus data meets a preset special data screening condition.

5. The bus monitoring module according to claim 4, characterized in that: Also includes: A register group, the register group comprising an enable strobe register, wherein: The enable strobe register is used to store the preset enable strobe information; The gating unit accesses the enable gating register to obtain the preset enable gating information.

6. The bus monitoring module according to claim 5, characterized in that: The register group also includes: a filter condition register, wherein: The filtering condition register is used to store preset filtering conditions; After converting the bus signal into bus data, the parsing unit extracts the bus data according to the preset filtering condition.

7. The bus monitoring module according to claim 4, characterized in that: The preprocessing unit further includes: a synchronization unit, wherein: The synchronization unit is connected between the gating unit and the parsing unit; The synchronization unit performs clock synchronization processing on the bus signal of the target bus to provide the parsing unit with a bus signal synchronized with the clock frequency of the bus monitoring module.

8. The bus monitoring module according to claim 1, characterized in that: The general data processing unit includes: a transaction tracking unit, wherein: The transaction tracking unit extracts target common data from the bus data according to the preset common data screening condition.

9. The bus monitoring module according to claim 8, characterized in that: The general data processing unit further includes: an export unit and a cache splicing unit, wherein: The export unit transmits the target general data output by the transaction tracking unit to the cache splicing unit; The cache tiling unit converts at least one of the target common data into bus data that can be transmitted through the bus.

10. The bus monitoring module according to claim 1, characterized in that: Also includes: A transmission unit, wherein The transmission unit stores the target general data and the target specific data in a preset memory.

11. The bus monitoring module according to claim 10, characterized in that: The transmission unit is configured with a dedicated data channel and a general data channel; The transmission unit queries the general data channel according to a first polling cycle to obtain the target general data, and queries the dedicated data channel according to a second polling cycle to obtain the target dedicated data.

12. The bus monitoring module according to claim 10, characterized in that: Also included is a register group, the register group includes a first address register and a second address register, wherein, The first address register is used to store a storage address range of the target general data in the preset memory; The second address register is used to store a storage address range of the target dedicated data in the preset memory; The transmission unit stores the target general data according to the address range stored in the first address register, and stores the target specific data according to the address range stored in the second address register.

13. The bus monitoring module according to claim 12, characterized in that: The transmission unit counts the current data volume stored in the preset memory, and when the current data volume reaches a preset data volume threshold, notifies the processor of the system on chip to update the address range stored in the first address register and the second address register.

14. The bus monitoring module according to claim 13, characterized in that: The register group further includes a capacity register, and the capacity register is used to store the preset data volume threshold; The transmission unit accesses the capacity register to obtain the preset data volume threshold.

15. The bus monitoring module according to any one of claims 1 to 14, characterized in that: Also included is a data recurrence unit, wherein: The data recurrence unit extracts recurrence data from the target general data and / or the target specific data according to a preset data recurrence condition, and sends the recurrence data to the bus.

16. The bus monitoring module according to claim 15, characterized in that: It also includes a register group, the register group includes a data recurrence register group, the data recurrence register group includes a recurrence condition register, wherein, The recurrence condition register is used to store the preset data recurrence condition; The data recurrence unit accesses the recurrence condition register to obtain the preset data recurrence condition.

17. The bus monitoring module according to claim 16, characterized in that: The data recurrence register group also includes a recurrence enable register, wherein: The recurrence enable register is used to store a first value representing data recurrence enable, or a second value representing data recurrence disable; The data recurrence unit extracts recurrence data from the target general data and / or the target specific data in response to the first value according to a preset data recurrence condition, and sends the recurrence data to the bus.

18. A bus monitoring method, characterized in that: Applied to a system on chip configured with a bus and a bus snooping module, the method comprises the following steps performed by the bus snooping module: Acquire a bus signal transmitted on the bus, and convert the bus signal into bus data; Extracting target general data from the bus data according to a preset general data screening condition; And, when the bus data meets a preset special data screening condition, the target special data is acquired according to the preset special data screening condition.

19. The bus monitoring method according to claim 18, characterized in that: Also includes: The target general data and the target specific data are stored in a preset memory.

20. The bus monitoring method according to claim 18 or 19, characterized in that: Also includes: Recurrence data is extracted from the target general data and / or the target specific data according to a preset data recurrence condition, and the recurrence data is sent to the bus.

21. A system on chip, characterized in that: include: A processor, a bus, at least one functional unit, and a bus snooping module according to any one of claims 1 to 17, wherein: The functional unit is used to implement the preset function of the system on chip; The processor, each of the functional units and the bus monitoring module are mounted on the bus respectively.

22. An electronic device, characterized in that: Comprising the system on chip as claimed in claim 21.

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