Memory system
By designing a memory system that calculates high-speed connection switches and signal correctors in the server, the problems of low memory module utilization and long-distance loss of signal transmission are solved, and efficient transmission and low-cost memory system are realized.
Patent Information
- Application Number
- CN202311517913.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-11-14
- Publication Date
- 2025-05-16
AI Technical Summary
In existing servers, the low usage rate of memory modules leads to reduced transmission efficiency and high space and cost. At the same time, long-distance signal transmission is likely to cause loss and stability problems.
A memory system is designed, including a computing high-speed connection switch, a plurality of memory modules and a signal corrector. The memory module and a signal corrector are connected by a computing high-speed connection switch. The computing device includes an operating element and a second signal corrector, and the second signal corrector is connected to the first signal corrector.
Improve transmission efficiency, reduce the space and cost of the overall equipment, maintain signal quality through signal correctors, enable signal transmission to be transmitted longer distances, and generate clean and stable signals.
Smart Images
Figure CN120011301A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to a memory system. Background Art
[0002] In existing servers, it is common to use various switches to configure the server architecture. However, since these architectures are usually large, the space and cost of the overall equipment are very high, and the transmission efficiency is reduced. In addition, these architectures are all fixed, which causes application limitations. In addition, since a variety of signals need to be transmitted in the server, and some signals need to be transmitted over a long distance, it is easy to cause signal loss and may affect the stability of the signal. Take the dual-in-line memory module (DIMM) in the server as an example. In order to maintain the reading speed and instruction cycle required by the processor, the distance between the dual-in-line memory module and the central processing unit cannot be too far, so direct memory access (DMA) is developed. For the dual-in-line memory module in the current server, a central processing unit is roughly equipped with 12 dual-in-line memory modules, but when the server is actually operating, the utilization rate of the dual-in-line memory module is probably less than 80%. Summary of the invention
[0003] In view of the above, the present application provides a memory system that solves the above problems.
[0004] According to an embodiment of the present application, a memory system includes: a memory device and a computing device. The memory device includes a computing high-speed link switch, a plurality of memory modules, and a first signal corrector, and the computing high-speed link switch is connected to the plurality of memory modules and the first signal corrector. The computing device includes an operating element and a second signal corrector. The second signal corrector is connected to the first signal corrector.
[0005] A memory system including a signal corrector according to one or more embodiments of the present application can maintain signal quality and has a lower cost.
[0006] The above description of the disclosed contents and the following description of the implementation modes are used to demonstrate and explain the spirit and principle of the present application, and to provide a further explanation of the scope of the patent application of the present application. BRIEF DESCRIPTION OF THE DRAWINGS
[0007] Figure 1 Shown is a block diagram of a memory device according to an embodiment of the present application.
[0008] Figure 2 Shown is a block diagram of a computing high-speed connection switch and multiple ports illustrated in an embodiment of the present application.
[0009] Figure 3Shown is a schematic diagram of a memory module depicted in an embodiment of the present application.
[0010] Figure 4 FIG. 4 is a block diagram of a memory device according to another embodiment of the present invention.
[0011] Figure 5 Shown is a schematic diagram of a connection module illustrated in an embodiment of the present application.
[0012] Figure 6 Shown is a block diagram of a memory system according to an embodiment of the present application.
[0013] Figure 7 Shown is a block diagram of a memory system according to another embodiment of the present application.
[0014] Figure 8 Shown is a block diagram of a memory system according to another embodiment of the present application.
[0015] Component number description
[0016] 1,2,3A,3B,3C,5,7Memory devices
[0017] 10,20,30a,30b,30c,70 housing
[0018] 11,21,31a,31b,31c,51,71 Calculate high-speed link switches
[0019] Ports 12, 22, 32a, 32b, 32c
[0020] 13,23,33a,33b,33c,52 memory modules
[0021] 24,34a,34b,34c Connection module
[0022] 14,15,130,240 base plate
[0023] 16 CPU
[0024] 131a First subport
[0025] 131b Second subport
[0026] 132 Memory
[0027] 133 Chip
[0028] 241 First Connector
[0029] 242 Second connector
[0030] 53 First Signal Corrector
[0031] 61 Second signal corrector
[0032] 62 Operating elements
[0033] 100,200,300 Memory System
[0034] 4,8,A1 computing device
[0035] 72a First port
[0036] 72b Secondary port
[0037] 73 Electronic devices
[0038] 74 processors DETAILED DESCRIPTION
[0039] The detailed features and advantages of the present application are described in detail in the following embodiments, and the content is sufficient to enable any person skilled in the relevant art to understand the technical content of the present application and implement it accordingly, and according to the content disclosed in this specification, the scope of the patent application and the drawings, any person skilled in the relevant art can easily understand the relevant purposes and advantages of the present application. The following examples further illustrate the viewpoints of the present application in detail, but do not limit the scope of the present application in any way.
[0040] Please refer to Figure 1 , Figure 1 The block diagram of the memory device shown is an embodiment of the present application. Figure 1 As shown, the memory device 1 includes a housing 10 , a computing high-speed connection switch 11 , a plurality of ports 12 and a memory module 13 .
[0041] The computing high-speed connection switch 11, the port 12 and the memory module 13 are all disposed in the housing 10. Further, the computing high-speed connection switch 11, the port 12 and the memory module 13 can be disposed on the same substrate, and the substrate is disposed in the housing 10. The computing high-speed connection switch 11 can be an open high-speed interconnect communication protocol (Compute Express Link, CXL) switch. The port 12 can be a slot of a peripheral component interconnect express (PCIe), and can be a pluggable port.
[0042] The memory module 13 may be a dual in-line memory module (DIMM). The memory module 13 is connected to the computing high-speed link switch 11 through one of the plurality of ports 12. In other words, the number of ports 12 may be equal to or greater than the number of memory modules 13. By arranging the computing high-speed link switch 11 and the memory module 13 together in the housing 10, the transmission efficiency may be improved, and the space and cost occupied by the overall device may be reduced.
[0043] It should also be noted that Figure 1 Two ports 12 and one memory module 13 are shown as an example, but the memory device 1 can also include, for example, 16 ports 12 and 8 memory modules 13 . The present application does not limit the number of ports 12 and memory modules 13 .
[0044] Please refer to Figure 1 and Figure 2 , Figure 2 The block diagram of a computing high-speed link switch and multiple ports shown in one embodiment of the present application is shown. Figure 2 As shown, the memory device 1 further includes a substrate 14, and the computing high-speed connection switch 11 and the port 12 are disposed on the substrate 14. In addition, the memory device 1 further includes another substrate 15 disposed on the substrate 14, and a central processing unit 16 disposed on the substrate 15. Please refer to Figure 1 and Figure 3 , Figure 3 Shown is a schematic diagram of a memory module according to an embodiment of the present application. Figure 3 The memory modules shown are capable of Figure 1 Memory module 13. Figure 3 As shown, the memory module 13 includes a substrate 130, a first sub-port 131a, a plurality of second sub-ports 131b, a plurality of memories 132 and a chip 133. The first sub-port 131a and the second sub-port 131b are located on the substrate 130. The first sub-port 131a can be connected to the computing high-speed connection switch 11. The first sub-port 131a can be a port for fast peripheral component interconnection. The memory 132 can be a dual in-line memory module (Dual In-line Memory Module, referred to as DIMM).
[0045] The chip 133 can be a control chip on the dual-line memory module. The chip 133 is connected to the second sub-port 131b and is used to convert the signal format. Further, the chip 133 can convert the signal from the computing high-speed link switch 11 from a format based on the Express Peripheral Component Interconnect to a format accessible to the memory 132, or convert the signal from the memory 132 to a format based on the Express Peripheral Component Interconnect.
[0046] Please refer to Figure 4 , Figure 4 Shown is a block diagram of a memory device according to another embodiment of the present application. Figure 4 As shown, the memory device 2 includes a housing 20 , a computing high-speed connection switch 21 , a plurality of ports 22 , a memory module 23 and a connection module 24 .
[0047] The computing high-speed connection switch 21, the port 22, the memory module 23 and the connection module 24 are all disposed in the housing 20. Further, the computing high-speed connection switch 21, the port 22, the memory module 23 and the connection module 24 can be disposed on the same substrate, and the substrate is disposed in the housing 20. The housing 20, the computing high-speed connection switch 21, the port 22 and the memory module 23 of the memory device 2 can be implemented in the same manner as described above. Figure 1 The housing 10, computing high-speed connection switch 11, port 12 and memory module 13 of the memory device 1 are the same as those of the memory device 1, and are not described in detail herein.
[0048] The memory module 23 is connected to the computing high-speed connection switch 21 through one of the plurality of ports 22, and the connection module 24 is connected to the computing high-speed connection switch 21 through another of the plurality of ports 22. Specifically, as described above, the port 22 may be a pluggable port. Therefore, each port 23 in the memory device 2 may be used to plug in the memory module 23 or the connection module 24. In addition, if Figure 4 As shown, the connection module 24 can be used to connect the computing device A1, and the memory module 23 is connected to the computing device A1 through the computing high-speed connection switch 21 and the connection module 24. For example, the computing device A1 can be a server, and the connection module 24 can be implemented by a connection card (port card) provided with a server port.
[0049] Figure 4 The number of memory modules 23 and connection modules 24 is only an example, and the ratio between the memory modules 23 and the connection modules 24 is adjustable. Figure 4 The architecture can realize a composable memory device. Therefore, the memory device can be further connected to other devices by adjusting the number and / or position of the memory modules and connection modules inserted in the memory device, thereby expanding the memory architecture.
[0050] Please refer to Figure 4 and Figure 5 , Figure 5 Shown is a schematic diagram of a connection module according to an embodiment of the present application. Figure 5 The connection module shown can be Figure 4 The connection module 24. Figure 5As shown, the connection module 24 includes a substrate 240, a first connector 241 and a second connector 242. The first connector 241 and the second connector 242 are arranged on the substrate 240. The first connector 241 can be, for example, a CDFP connector. The second connector 242 can be a Peripheral Component Interconnect Express connector. The second connector 242 is used for the connection module 24 to be connected to the port 22.
[0051] The first connector 241 can be used to connect to the server. The first connector 241 can be used to receive a platform reset signal generated by the server, and further send the platform reset signal to the port 22 of the memory device 2 through the second connector 242. The server and the memory system 100 are electrically connected through the CDFP connector.
[0052] Please refer to Figure 6 , Figure 6 The block diagram of the memory system shown is an embodiment of the present application. Figure 6 As shown, the memory system 100 includes a plurality of memory devices 3A, 3B, and 3C.
[0053] The memory device 3A includes a housing 30a, a computing high-speed connection switch 31a, a port 32a, a memory module 33a, and a connection module 34a; the memory device 3B includes a housing 30b, a computing high-speed connection switch 31b, a port 32b, a memory module 33b, and a connection module 34b; and the memory device 3C includes a housing 30c, a computing high-speed connection switch 31c, a port 32c, a memory module 33c, and a connection module 34c. The implementation method of each of the memory devices 3A, 3B, and 3C can be the same as that described above. Figures 1 to 5 The memory devices of one or more of the described embodiments are the same, so the details of the memory devices 3A, 3B and 3C are not repeated here.
[0054] The memory module of each of the memory devices 3A, 3B and 3C is connected to the computing high-speed link switch through one of the multiple ports, the connection module of each of the memory devices 3A, 3B and 3C is connected to the computing high-speed link switch through another one of the multiple ports; and the connection module of one of the memory devices 3A, 3B and 3C is connected to the connection module of another one of the memory devices 3A, 3B and 3C.
[0055] Taking the memory device 3A as an example, the memory module 33a of the memory device 3A is connected to the computing high-speed connection switch 31a through one of the ports 32a, and the connection module 34 of the memory device 3A is connected to the computing high-speed connection switch 31a through another port 32a. In addition, one connection module 34a of the memory device 3A is connected to the connection module 34b of the memory device 3B. In addition, another connection module 34a of the memory device 3A can be connected to the connection module 34c of the memory device 3C.
[0056] Each of the memory devices 3A, 3B and 3C can include one or more memory modules and at least one connection module. In other words, the memory module of each of the memory devices 3A, 3B and 3C can be replaced by a connection module, and the connection module of each of the memory devices 3A, 3B and 3C can also be replaced by a memory module. Figure 6 The connections shown are examples only and Figure 6 The number of memory devices and the number of connection modules and memory modules per memory device shown are examples only.
[0057] In addition, if Figure 6 As shown, the memory system 100 further includes a computing device 4, wherein the computing device 4 can be a server. The computing device 4 is a selectively configured component. The computing device 4 is connected to a connection module of at least one of the memory devices 3A, 3B, and 3C. For example, Figure 6 As shown, the computing device 4 can be connected to the connection module 34b of the memory device 3B. Figure 6 Each of the memory devices 3A, 3B and 3C can include two connection modules, one of which is used to connect to another memory device, and the other is used to connect to other devices (eg, computing device A1).
[0058] According to the memory system of one or more embodiments of the present application, the memory pool can be expanded according to demand, and the usage is more flexible.
[0059] Please refer to Figure 7 , Figure 7 Shown is a block diagram of a memory system according to another embodiment of the present application. Figure 7 As shown, the memory system 200 includes a memory device 5 and a computing device 6 .
[0060] The memory device 5 includes a computing high-speed connection switch 51, a plurality of memory modules 52 and a first signal corrector 53. The computing high-speed connection switch 51 and the memory module 52 can be implemented in the same manner as described above. Figures 1 to 6 The computing high-speed link switch and memory module described in one or more embodiments are the same, and the memory module 52 can be as described above. Figures 1 to 6The ports of one or more embodiments described are connected to the high-speed link switch 51. Further, the memory device 5 can be connected to the high-speed link switch 51 through the above reference Figure 4 and Figure 5 The ports and the connection modules of one or more embodiments described are connected to the computing device 6. Furthermore, the first signal corrector 53 can be disposed between the computing high-speed connection switch and the port, or can be disposed in the connection module.
[0061] The computing device 6 includes a second signal corrector 61 and an operating element 62. The second signal corrector 61 is connected to the first signal corrector 53 and the operating element 62. The computing device 6 can be a server. The operating element 62 is, for example, a central processing unit, a graphics processor, etc.
[0062] The first signal corrector 53 and the second signal corrector 61 can be used to correct at least one of the error and loss of the initial signal generated by the memory module 52. The operating element 62 of the computing device 6 can receive the signal generated by one of the first signal corrector 53 and the second signal corrector 61.
[0063] In one embodiment, the first signal corrector 53 and the second signal corrector 61 can each be a redriver. The first signal corrector 53 is used to correct the loss of the initial signal output by the high-speed connection switch 51 to output a first correction signal to the second signal corrector 61, and the second signal corrector 61 is used to correct the loss of the first correction signal to output a second correction signal to the operating element 62. In other words, the first signal corrector 53 can amplify the initial signal to generate a first correction signal, and the second signal corrector 61 can amplify the first correction signal to generate a second correction signal.
[0064] In another embodiment, the first signal corrector 53 is a retimer, and the second signal corrector 61 is a redriver. The first signal corrector 53 is used to correct the error of the initial signal to output the first correction signal to the second signal corrector 61, and the second signal corrector 61 is used to correct the loss of the first correction signal to output the second correction signal to the operating element 62. In other words, the first signal corrector 53 can repair the jittered initial signal to generate the first correction signal, and the second signal corrector 61 can amplify the first correction signal to generate the second correction signal.
[0065] In another embodiment, the first signal corrector 53 is a re-driver, and the second signal corrector 61 is a re-timer. The first signal corrector 53 is used to correct the loss of the initial signal to output the first correction signal to the second signal corrector 61, and the second signal corrector 61 is used to correct the error of the first correction signal to output the second correction signal to the operating element 62. In other words, the first signal corrector 53 can amplify the initial signal to generate the first correction signal, and the second signal corrector 61 can repair the jittered first correction signal to generate the second correction signal.
[0066] Through the memory system of one or more of the above embodiments, by implementing the signal corrector with a redriver, the signal can be transmitted over a longer distance. Furthermore, by implementing the signal corrector with a retimer, a clean and stable signal can be generated.
[0067] Please refer to Figure 8 , Figure 8 Shown is a block diagram of a memory system according to another embodiment of the present application. Figure 8 As shown, the memory system 300 includes a memory device 7 and a computing device 8 .
[0068] The memory device 7 includes a computing high-speed connection switch 71, a plurality of first ports 72a and a second port 72b. The computing high-speed connection switch 71 may be an open high-speed interconnection communication protocol switch. The first port 72a and the second port 72b may be slots for fast peripheral component interconnection and may be pluggable ports. The processor 74 may be a central processing unit, such as a CPU. Figure 2 The central processor 16 is shown. The computing device 8 can be a server.
[0069] The first ports 72a are each connected to an electronic device 73. For example, the first ports 72a can be as described above. Figures 1 to 6 The electronic device 73 can be a port as described above with reference to one or more embodiments. Figures 1 to 7 A memory module or a connection module of one or more embodiments is described.
[0070] The processor 74 is connected to the second port 72b and the computing high-speed connection switch 71, and the second port 72b is also connected to the computing device 8. The second port 72b can be connected to the computing device 8 in a wired or wireless manner. The processor 74 is used to obtain the current configuration of the first port 72a from the computing device 8 through the second port 72b to update the original configuration stored in the processor 74. The current configuration indicates the electronic device 73 connected to each of the first ports 72a. The current configuration can be implemented by a quick peripheral component interconnect enumeration.
[0071] Furthermore, the memory device 7 further includes a housing 70 , and the high-speed connection switch 71 , the first port 72 a , the second port 72 b , the electronic device 73 and the processor 74 are disposed in the housing 70 .
[0072] The computing device 8 can transmit a reset signal to the processor 74 through the second port 72b, and the processor 74 is also used to control the computing high-speed link switch 71 to respectively connect the multiple first ports 72a and the computing device 8 according to the reset signal to generate the current configuration of the multiple first ports 72a. The computing device 8 can scan the multiple first ports 72a respectively through the computing high-speed link switch 71 to generate the current configuration. The reset signal can be a platform environment reset signal. Specifically, as described above, the electronic device 73 can be a memory module and a connection module, and the memory module and the connection module can be provided with respective control chips, and the computing device 8 can obtain the current configuration of the multiple first ports 72a by reading the control chip.
[0073] Specifically, after the computing device 8 transmits a reset signal to the processor 74, the processor 74 can first connect one of the first ports 72a to the computing device 8, and the computing device 8 reads the configuration data of the first port 72a. Then, the processor 74 can connect another first port 72a to the computing device 8, so that the computing device 8 can read the configuration data of the other first port 72a. Accordingly, the computing device 8 can use the read configuration data as the current configuration. The configuration data can indicate one or more of the serial number of the first port 72a, the name of the first port 72a, the brand of the first port 72a, the serial number of the electronic device 73 connected to the first port 72a, the name of the electronic device 73, and the brand of the electronic device 73.
[0074] In addition, the computing device 8 can also set the current configuration according to the user's instruction. For example, the user's instruction can indicate one or more of the serial number, name and brand of each first port 72a, and the user's instruction can also indicate one or more of the serial number, name and brand of the electronic device 73 connected to each first port 72a. The computing device 8 can use the configuration data indicated by the user's instruction as the current configuration.
[0075] After obtaining the current configuration, the computing device 8 can output the current configuration to the processor 74 to update the original configuration stored in the processor 74. The computing device 8 can include a basic input / output system (BIOS), which can be used to generate the aforementioned reset signal.
[0076] According to the memory system of one or more of the above embodiments, the computing device and the processor can determine the latest configuration of the memory device, thereby preventing the computing device and the processor from having operational problems due to unupdated configurations.
[0077] In this embodiment, the server of the present application can be used for artificial intelligence (AI) computing, edge computing, and can also be used as a 5G server, cloud server or Internet of Vehicles server.
[0078] In summary, according to the memory device of one or more embodiments of the present application, by setting the computing high-speed connection switch, multiple ports and multiple memory modules in the housing, the transmission efficiency can be improved, and the space and cost occupied by the overall device can be reduced. According to the memory device of one or more embodiments of the present application, the number and / or position of the memory modules and connection modules inserted in the memory device can be adjusted, so that the memory device can be further connected to other devices, thereby expanding the memory architecture. According to the memory system including multiple memory devices of one or more embodiments of the present application, the memory pool can be expanded according to demand, and it is more flexible in use. According to the memory system including a signal corrector of one or more embodiments of the present application, the computing device can obtain a better quality signal. In addition, by implementing the signal corrector with a re-driver, the signal can be transmitted over a longer distance; and by implementing the signal corrector with a re-timer, a clean and stable signal can also be generated. According to the memory system including a memory device and a computing device of one or more embodiments of the present application, the computing device and the processor can determine the latest configuration of the memory device, and can avoid the computing device and the processor from having operational problems due to the unupdated configuration.
[0079] Although the present application is disclosed in the above embodiments, it is not intended to limit the present application. Any changes and modifications that do not depart from the spirit and scope of the present application are within the scope of patent protection of the present application. Please refer to the scope of the attached claims for the scope of protection defined by the present application.
Claims
1. A memory system, characterized in that: include: A memory device includes a computing high-speed connection switch, a plurality of memory modules and a first signal corrector, wherein the computing high-speed connection switch is connected to the plurality of memory modules and the first signal corrector; and A computing device includes an operating element and a second signal corrector, wherein the second signal corrector is connected to the first signal corrector.
2. The memory system according to claim 1, wherein: The first signal corrector and the second signal corrector are used to correct at least one of an error and a loss of an initial signal generated by one of the plurality of memory modules.
3. The memory system according to claim 1, wherein: The first signal corrector and the second signal corrector are each a redriver.
4. The memory system according to claim 1, wherein: The first signal corrector is used to correct the loss of an initial signal generated by one of the multiple memory modules to output a first correction signal to the second signal corrector, and the second signal corrector is used to correct the loss of the first correction signal to output a second correction signal to the operating element.
5. The memory system according to claim 1, wherein: One of the first signal corrector and the second signal corrector is a retimer, and the other of the first signal corrector and the second signal corrector is a redriver.
6. The memory system according to claim 1, wherein: The first signal corrector is used to correct an error of an initial signal generated by one of the plurality of memory devices to output a first correction signal to the second signal corrector, and the second signal corrector is used to correct a loss of the first correction signal to output a second correction signal to the operating element.
7. The memory system according to claim 1, wherein: The first signal corrector is used to correct the loss of an initial signal generated by one of the plurality of memory devices to output a first correction signal to the first signal corrector, and the second signal corrector is used to correct the error of the first correction signal to output a second correction signal to the operating element.