Chip logic verification method and device, equipment, storage medium and program product

Abstract

The embodiment of the invention provides a method, equipment and device for chip logic verification, a medium and a program product, and relates to the field of chip design tools. The method includes: constructing an NAND graph (and-inverter graph, AIG) that characterizes a sub-logic circuit, the sub-logic circuit including at least a portion of a first circuit and at least a portion of a second circuit; a component graph is determined based on the NAND graph, the component graph including nodes corresponding to circuit function modules in the sub-logic circuits, and the circuit function modules including AND gates and inverters in the NAND graph. The method further includes determining a logical equivalence between the first circuit and the second circuit based on the component map. In this manner, by verifying logical equivalence using the component graph, a logical equivalence verification problem may be solved using circuit configuration information, and a scale of solving a model may be reduced, thereby improving efficiency of verifying logical equivalence.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to the field of chip design tools. More specifically, embodiments of the present disclosure relate to methods, devices, equipment, computer-readable storage media, and computer program products for chip logic verification. Background Art

[0002] Electronic design automation (EDA) software is widely used in the functional design, synthesis, verification, simulation and other processes of chips. Using EDA software, the logic verification of chip design can be performed efficiently. One of the EDA tool chains is the logic equivalence checking (LEC) tool, which is also called the combinatorial equivalence checking (CEC) tool. Specifically, the LEC tool can verify whether two circuits are completely logically equivalent. For example, the logical equivalence between two register-transfer level (RTL) code designs can be verified, or the logical equivalence between the RTL code design and the corresponding gate-level netlist can be verified. In the chip design process, the LEC tool is called frequently at multiple stages of the design. Therefore, a solution for chip logic verification is needed to improve the efficiency of verifying logical equivalence. Summary of the invention

[0003] Some related chip logic verification schemes have problems such as low verification efficiency and high resource consumption. The embodiments of the present disclosure provide a scheme for chip logic verification to at least partially solve the above problems.

[0004] In a first aspect of the present disclosure, a method for chip logic verification is provided. The method includes: constructing an and-inverter graph (AIG) representing a sub-logic circuit, the sub-logic circuit including at least a portion of a first circuit and at least a portion of a second circuit. The first circuit and the second circuit are two circuits to be compared for logical equivalence. The method also includes: determining a component graph based on the and-inverter graph, the component graph including nodes corresponding to circuit function modules in the sub-logic circuit, and the circuit function modules include an and gate and an inverter in the and-inverter graph. In other words, at least one node in the component graph does not correspond to a basic logic gate, but corresponds to a circuit function module, so that the component graph has richer information and a smaller scale than the and-inverter graph. The method also includes: determining the logical equivalence between the first circuit and the second circuit based on the component graph. By using the component graph to verify the logical equivalence, the circuit structure information can be used to solve the logical equivalence verification problem, and the scale of the solution model can be reduced, thereby improving the efficiency of verifying the logical equivalence and reducing resource consumption.

[0005] In some embodiments of the first aspect, the method further comprises: simplifying the component graph by merging multiple nodes in the component graph into a new node. In this way, the scale of the solution model can be further reduced, thereby improving the verification efficiency.

[0006] In some embodiments of the first aspect, the sub-logic circuit further includes an XOR gate, which connects at least a portion of the first circuit and at least a portion of the second circuit. Based on the component graph, determining the logical equivalence between the first circuit and the second circuit includes: setting the output value of the output node of the component graph to a predetermined value, the output node corresponds to the XOR gate, and the predetermined value indicates that the first circuit and the second circuit do not meet the logical equivalence requirement; performing reasoning on the component graph using an automatic test pattern generation (ATPG) algorithm and the predetermined value to determine whether there is a test vector that makes the reasoning successful, the test vector corresponding to multiple output values ​​of multiple nodes in the component graph except the output node; and determining that the first circuit and the second circuit meet the logical equivalence requirement based on determining that there is no test vector that makes the reasoning successful. In this way, ATPG technology can be applied in LEC scenarios to improve verification efficiency.

[0007] In some embodiments of the first aspect, performing reasoning on the component graph includes: constructing an implication graph based on the component graph, the implication graph indicating multiple results obtained by multiple decisions during the reasoning process; determining a conflict constraint for the component graph based on conflicts between the multiple results, the conflict constraint including a logical restriction relationship between output values ​​of at least two nodes in the component graph; and updating at least one of the multiple decisions based on the conflict constraint. In this way, the implication graph and the conflict constraint can be used to accelerate reasoning, thereby improving reasoning efficiency.

[0008] In some embodiments of the first aspect, the component graph is a first component graph determined based on a first portion of the NAND graph, the first portion of the NAND graph corresponding to a first portion of the sub-logic circuit. Determining the logical equivalence between the first circuit and the second circuit includes: determining that the first circuit and the second circuit partially meet the logical equivalence requirement based on a result of the reasoning performed on the first component graph; determining a second component graph based on a second portion of the NAND graph, the second portion of the NAND graph corresponding to a second portion of the sub-logic circuit, and the second portion of the sub-logic circuit includes the first portion of the sub-logic circuit; and determining the logical equivalence between the first circuit and the second circuit by performing reasoning on the second component graph. In this way, incremental modeling and incremental reasoning of component graphs can be achieved, thereby reducing the size of a single component graph to improve reasoning efficiency.

[0009] In some embodiments of the first aspect, the method further includes: determining that the first circuit and the second circuit do not meet the logic equivalence requirement based on determining that there is a test vector that makes the reasoning successful; and performing root cause analysis based on the component graph. In this way, the root cause analysis can be performed based on the information of the circuit function module in the component graph, thereby improving the efficiency of the root cause analysis.

[0010] In some embodiments of the first aspect, the ATPG algorithm includes a fan-based ATPG algorithm. The fan-based ATPG algorithm can make decisions only at specific nodes, such as circuit function modules, and only propagate at other nodes, thereby reducing the decision space and improving reasoning efficiency. In some embodiments of the first aspect, the circuit function module includes at least one of the following: a full adder, a half adder, or a compressor. In this way, the scheme of the present disclosure can be advantageously applied in an operational circuit, and thus can be suitable for an artificial intelligence (AI) computing chip.

[0011] In some embodiments of the first aspect, determining the logical equivalence between the first circuit and the second circuit based on the component graph further includes: determining the logical equivalence between the first circuit and the second circuit based on a conjunctive normal form (CNF) obtained from the component graph. In this way, the solution of the present disclosure can be compatible with conventional CNF-based solvers, or can work with other CNF-based solvers for chip logic verification.

[0012] In a second aspect of the present disclosure, a device for chip logic verification is provided. The device includes: a NAND graph construction unit, configured to construct a NAND graph (AIG) representing a sub-logic circuit, the sub-logic circuit including at least a portion of a first circuit and at least a portion of a second circuit; a component graph determination unit, configured to determine a component graph based on the NAND graph, the component graph including nodes corresponding to circuit function modules in the sub-logic circuit, the circuit function modules including AND gates and inverters in the NAND graph; and a logic verification unit, configured to determine the logical equivalence between the first circuit and the second circuit based on the component graph.

[0013] In this way, by using component graphs to verify logical equivalence, circuit structure information can be used to assist in solving the logical equivalence verification problem, and the scale of the solution model can be reduced, thereby improving the efficiency of verifying logical equivalence and reducing resource consumption.

[0014] In some embodiments of the second aspect, the apparatus further comprises a simplification element configured to simplify the component graph by merging a plurality of nodes in the component graph into a new node.

[0015] In some embodiments of the second aspect, the sub-logic circuit further includes an XOR gate, the XOR gate connecting at least a portion of the first circuit and at least a portion of the second circuit. The logic verification unit is configured to: set the output value of the output node of the component graph to a predetermined value, the output node corresponds to the XOR gate, and the predetermined value indicates that the first circuit and the second circuit do not meet the logic equivalence requirement; perform reasoning on the component graph using an automatic test vector generation ATPG algorithm and the predetermined value to determine whether there is a test vector that makes the reasoning successful, the test vector corresponding to multiple output values ​​of multiple nodes in the component graph except the output node; and determine that the first circuit and the second circuit meet the logic equivalence requirement based on determining that there is no test vector that makes the reasoning successful.

[0016] In some embodiments of the second aspect, the logic verification unit includes: an inference learning unit, configured to: construct an implication graph based on the component graph, the implication graph indicating multiple results obtained by multiple decisions in the inference process; determine a conflict constraint for the component graph based on a conflict between the multiple results in the implication graph, the conflict constraint including a logical restriction relationship between output values ​​of at least two nodes in the component graph; and update at least one of the multiple decisions based on the conflict constraint.

[0017] In some embodiments of the second aspect, the component graph is a first component graph determined based on a first portion of the NAND graph, the first portion of the NAND graph corresponding to a first portion of the sub-logic circuit. The logic verification unit is configured to: determine that the first circuit and the second circuit partially meet the logic equivalence requirement based on a result of the reasoning performed on the first component graph; determine a second component graph based on a second portion of the NAND graph, the second portion of the NAND graph corresponding to a second portion of the sub-logic circuit, and the second portion of the sub-logic circuit includes the first portion of the sub-logic circuit; and determine the logic equivalence between the first circuit and the second circuit by performing reasoning on the second component graph.

[0018] In some embodiments of the second aspect, the apparatus further comprises a root cause analysis unit. The logic verification unit is configured to: determine that the first circuit and the second circuit do not meet the logic equivalence requirement based on determining that there is a test vector that makes the reasoning successful. The root cause analysis unit is configured to: perform root cause analysis based on the component graph.

[0019] In some embodiments of the second aspect, the ATPG algorithm comprises a fan-based ATPG algorithm. In some embodiments of the second aspect, the circuit functional module comprises at least one of the following: a full adder, a half adder, or a compressor. In some embodiments of the second aspect, the logic verification unit is further configured to: determine the logical equivalence between the first circuit and the second circuit based on a conjunctive normal form (CNF) obtained from the component graph.

[0020] In a third aspect of the present disclosure, an electronic device is provided, comprising: at least one computing unit; and at least one memory, wherein the at least one memory is coupled to the at least one computing unit and stores instructions for execution by the at least one computing unit, and when the instructions are executed by the at least one computing unit, the device implements the method provided in the first aspect.

[0021] In a fourth aspect of the present disclosure, a computer-readable storage medium is provided, on which a computer program is stored, wherein the computer program is executed by a processor to implement the method provided in the first aspect.

[0022] In a fifth aspect of the present disclosure, a computer program product is provided, comprising computer executable instructions, which implement part or all of the steps of the method of the first aspect when the instructions are executed by a processor.

[0023] It can be understood that the electronic device of the third aspect, the computer storage medium of the fourth aspect, or the computer program product of the fifth aspect provided above are all used to execute the method provided in the first aspect. Therefore, the explanation or description of the first aspect is also applicable to the third aspect, the fourth aspect, and the fifth aspect. In addition, the beneficial effects that can be achieved in the second aspect, the third aspect, the fourth aspect, and the fifth aspect can refer to the beneficial effects in the corresponding method, which will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The above and other features, advantages and aspects of the embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. In the accompanying drawings, the same or similar reference numerals represent the same or similar elements, wherein:

[0025] Figure 1 A flowchart showing the chip design and manufacturing process;

[0026] Figure 2 A flowchart showing an example process for chip logic verification according to some embodiments of the present disclosure is shown;

[0027] Figure 3 shows examples of NAND graphs and component graphs according to some embodiments of the present disclosure;

[0028] Figure 4 A schematic diagram showing an example value transmission method in an ATPG algorithm according to some embodiments of the present disclosure;

[0029] Figure 5 A schematic diagram showing an example process of verifying logical equivalence according to some embodiments of the present disclosure;

[0030] Figure 6 A schematic diagram showing a first performance representation of an ATPG solver according to some embodiments of the present disclosure;

[0031] Figure 7 A schematic diagram showing a second performance representation of an ATPG solver according to some embodiments of the present disclosure;

[0032] Figure 8 A schematic diagram showing applicable circuit features of an ATPG solver according to some embodiments of the present disclosure;

[0033] Fig. 9 A schematic diagram showing the memory usage performance of an ATPG solver according to some embodiments of the present disclosure is shown;

[0034] Fig.10 A schematic block diagram showing an apparatus for chip design according to some embodiments of the present disclosure; and

[0035] Fig.11 A block diagram of a computing device capable of implementing various embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0036] Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be construed as being limited to the embodiments described herein, which are instead provided for a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are only for exemplary purposes and are not intended to limit the scope of protection of the present disclosure.

[0037] In the description of the embodiments of the present disclosure, the term "including" and similar terms should be understood as open inclusion, that is, "including but not limited to". The term "based on" should be understood as "based at least in part on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The terms "first", "second", etc. may refer to different or the same objects. Other explicit and implicit definitions may also be included below.

[0038] As briefly mentioned above, a chip logic verification scheme is needed to efficiently verify the logical equivalence between two circuits. Generally speaking, "logical equivalence" means that when any vector is input into two circuits at the same time, the outputs of the two circuits are always equal. In other words, if a vector can be found that causes the outputs of the two circuits to be inconsistent after being input into the two circuits respectively, then it can be determined that the two circuits are not equivalent.

[0039] At present, some schemes have been proposed to verify logical equivalence. In some schemes, the entire search space can be traversed and all possible test vectors can be input one by one to verify logical equivalence. However, this scheme is obviously not suitable for large-scale circuits, because when a circuit has N pins, all possible test vectors have 2 N This will lead to state explosion.

[0040] In other schemes, the outputs of the two circuits can be connected to a virtual multi-input single-output XOR gate. Due to the nature of XOR, if the outputs of the two circuits are inconsistent, the output of XOR is 1, otherwise the output is 0. Therefore, the logical equivalence between the two circuits can be verified by determining whether there is an input to the circuit that makes the output of XOR 1. Generally, after connecting the two circuits to be verified to the virtual XOR gate, the combined circuit (also called a miter circuit) can be converted into an expression corresponding to a specific solver, and then the logical equivalence problem is solved by calling the corresponding solver. Examples of current commercial solvers include Boolean Satisfactory (SAT) solvers, binary decision diagrams (BDD) solvers, etc.

[0041] SAT solvers are used to solve the Boolean satisfiability problem, that is, to determine whether there is a set of variable assignments in a given truth equation such that the problem is satisfiable. The Boolean satisfiability problem is a deterministic problem and the first problem to be proven to be NP-complete. SAT solvers can be of the following two types:

[0042] 1) Traditional SAT solver based on symbolic calculation. When using this solver, it is necessary to first convert the miter circuit into a conjunctive normal form (CNF) in the form of a Boolean expression, and then solve it based on CNF. That is, determine whether CNF can meet the predetermined conditions, such as the variable value corresponding to the output of the XOR gate is 1. In CNF, variables and non-variables are called literals. Different literals are connected by logical OR (OR, ∨) to form clauses, and different clauses are connected by logical AND (AND, ∧) to form CNF. Since CNF is formed by some clauses being "AND", in order for CNF to meet the predetermined conditions, each clause must also meet the corresponding conditions. Since each clause is formed by some literals being "OR", only one literal is required to meet the corresponding condition.

[0043] 2) Circuit-based SAT solver: This SAT solver can directly perform reasoning on the miter circuit represented in the form of a netlist or an and-inverter graph (AIG) to determine whether the miter circuit can meet the predetermined conditions, such as the output of the XOR gate is 1.

[0044] However, in the above solution, the solver does not use constraints and information related to the structural properties of the circuit, resulting in the inability to solve the specific circuit in a targeted manner, thereby reducing the solution performance. For example, when the miter circuit is expanded into a NAND graph including only AND gates and inverters, the information of the circuit function modules such as intellectual property (IP) blocks in the circuit is lost.

[0045] In order to at least partially solve the above problems and other potential problems, various embodiments of the present disclosure provide a method, device, apparatus, medium and program product for chip logic verification. The method includes: constructing a NAND graph representing a sub-logic circuit, the sub-logic circuit including at least a portion of a first circuit and at least a portion of a second circuit; determining a component graph based on the NAND graph, the component graph including nodes corresponding to circuit function modules in the sub-logic circuit, the circuit function modules including AND gates and inverters in the NAND graph. The method also includes: determining the logical equivalence between the first circuit and the second circuit based on the component graph.

[0046] In this way, the information of the circuit function modules in the component graph can be used to solve the logic equivalence verification problem. In addition, compared with the NAND graph, the scale of the component graph is smaller, so verifying the logic equivalence based on the component graph can improve the solving efficiency.

[0047] Various exemplary embodiments of the present disclosure are described below with reference to the accompanying drawings. Figure 1A flow chart of a chip design and manufacturing process 100 is shown. The design and manufacturing process 100 begins with specification formulation 110. At the stage of specification formulation 110, the requirements for the functions and performances that the integrated circuit needs to achieve are determined. At the stage of chip design 120, circuit design is performed with the aid of EDA software to obtain, for example, a layout file for chip manufacturing. Based on the difference in circuits (e.g., digital circuits or analog circuits), the design 120 may include different design links. At the stage of manufacturing 140, integrated circuits are formed on wafers through processes such as photolithography, etching, ion implantation, thin film deposition, and polishing. At the stage of packaging 150, the wafer is cut to obtain a bare die, and the bare die is packaged to obtain a chip through processes such as pasting, welding, and mold sealing. The resulting chip is tested at the stage of testing 160 to ensure that the performance of the finished chip meets the requirements determined in the specification formulation 110. The chip 170 that has passed the test can be delivered to the customer. It can be understood that the above process is only illustrative and does not limit the scope of the present disclosure. In some cases, the design and manufacturing process of the chip may be different. For example, tape-out may be performed before manufacturing 140. A small number of chips obtained from the tape-out may be used for testing to verify whether the chip design meets expectations. If it does not meet expectations, this indicates that the tape-out has failed and the chip design may need to be adjusted or redesigned.

[0048] In some embodiments, the design 120 of the digital circuit may exemplarily include an architecture design 121, an RTL design 123, a functional simulation 125, a synthesis 127, a timing analysis 129, a DFT 131, a verification check 133, a layout 135, a design rule check (DRC) 137, and a layout 139. The architecture design 121 includes, for example, designing the architecture of the chip. For example, EDA software may be used to determine the categories and quantities of components or subcircuits included in the chip system, as well as the functions, connections, and interactions of each component or subcircuit. In the stage of RTL design 123, a hardware programming language such as Verilog or VHDL may be used to describe the determined chip architecture in code at the RTL level. Functional simulation 125 is also referred to as RTL-level behavioral simulation or front-end simulation. The purpose of functional simulation is to analyze the correctness of the logical relationship of the design circuit. In some cases, logical equivalence verification may be performed at the functional simulation 125 stage, such as performing logical equivalence verification on the RTL code design before and after modification. Synthesis 127 may convert the RTL into a gate-level netlist. Synthesis 127 may include, for example, translation, optimization, and mapping. In one embodiment, the EDA software used for synthesis may first convert the RTL code into a general Boolean equation and compile it. The netlist may be optimized according to constraints such as delay and area imposed by the designer, and then the RTL netlist may be mapped to the process library to generate a gate-level netlist.

[0049] Timing analysis 129 is usually static timing analysis, which mainly involves timing calculation and prediction of digital circuits. Timing analysis is performed on the paths in the digital circuit to determine whether timing convergence is achieved, thereby ensuring whether the timing of various circuits meets various timing requirements. The verification of such digital circuits is usually completed statically and does not require simulation of digital logic. At the stage of DFT 131, various hardware logics for improving chip testability (including controllability and observability) can be embedded in the design. By using this part of logic, test vectors can be generated to achieve the purpose of testing large-scale digital circuits. DFT can, for example, include a test method based on a scan chain or a built-in self-test circuit (BIST). At the stage of verification check 133, the circuit can be formally verified and / or equivalence checked. Formal verification can use mathematical methods to prove its correctness or incorrectness based on one or more formal specifications or attributes. Formal verification can, for example, include abstract interpretation, formal model checking (also known as characteristic checking) and theorem proving. Equivalence checking can be used to verify whether the register transfer level design is consistent with the gate level netlist, and whether the gate level netlist is consistent with the gate level netlist. Equivalence checking can include the above-mentioned logical equivalence verification, which is also called combinatorial equivalence checking. Equivalence checking can also include timing equivalence checking.

[0050] In the stage of layout and routing 135, the chip circuit can be laid out (placement) and routed (routing). The layout can reasonably arrange the gate-level netlist generated by logic synthesis 127 in a rectangular area corresponding to the chip based on considerations such as area, critical path delay length, and power consumption. After this, the various components or sub-circuits that have been laid out can be routed to connect them. Routing generally expects the total routing to be short, the routing delay to meet the timing requirements, and to comply with the routing rules in the process (such as routing density). Although layout and routing are described separately here, this is only illustrative and does not limit the scope of the present disclosure. In some cases, layout and routing can be performed simultaneously or alternately to achieve optimization of layout and routing.

[0051] At the DRC 137 stage, the layout can be checked for potential open circuits, short circuits or adverse effects caused by violations of design rules. After passing the DRC, a file representing the layout, such as a GDSII file, can be generated 139 by the EDA software. It can be understood that the above steps are only exemplary and not intended to limit the scope of the present disclosure. In the actual design process, the above steps can be added, deleted or modified according to design needs. In addition, some of the above steps can be implemented by different EDA software or integrated in one or more EDA software. The present disclosure does not limit this.

[0052] Figure 2 A flowchart of an example process 200 for chip logic verification according to some embodiments of the present disclosure is shown. Process 200 can be implemented by any suitable computing unit. For example, it can be executed by a computer or other electronic device with computing or circuit design capabilities. Specifically, for example, an EDA tool can be implemented by a processor of a computer according to data and / or instructions stored in a memory to execute process 200. Figure 1 An example process 200 for chip logic verification is described below.

[0053] In block 210, the processor constructs a NAND graph representing a sub-logic circuit, the sub-logic circuit including at least a portion of a first circuit and at least a portion of a second circuit. The first circuit and the second circuit are two circuits whose logical equivalence is to be verified. In some embodiments, the first circuit and the second circuit may correspond to different circuit designs. For example, the first circuit and the second circuit may be circuits before and after modifying circuit elements, respectively. In some embodiments, the first circuit and the second circuit may be representations of different abstraction levels for the same circuit design. For example, the first circuit is an RTL code design and the second circuit is a corresponding gate-level netlist.

[0054] A sub-logic circuit can be constructed based on at least a portion of the first circuit and at least a portion of the second circuit for verifying logical equivalence. In some embodiments, at least a portion of the first circuit may include a first logic cone, at least a portion of the second circuit may include a second logic cone, and the sub-logic circuit may include a first logic cone and a second logic cone. The corresponding first logic cone and second logic cone can be found (trace) in the first circuit and the second circuit by starting from the point to be compared and traversing the circuit forward with the comparison point as the output. In some embodiments, the sub-logic circuit may include a miter circuit as described above, which connects at least a portion of the first circuit to at least a portion of the second circuit through an XOR gate. For example, the sub-logic circuit may include a first logic cone and a second logic cone connected by an XOR gate. In some embodiments, the sub-logic circuit may include a plurality of logic cones from the first circuit and a plurality of logic cones from the second circuit. Based on the sub-logic circuit, a NAND graph characterizing the sub-logic circuit may be constructed. Any suitable method may be used to construct a NAND graph, and the scope of the present disclosure is not limited here.

[0055] In block 220, the processor determines a component graph based on the NAND graph, the component graph including nodes corresponding to circuit function modules in the sub-logic circuit, and the circuit function modules include AND gates and inverters in the NAND graph. In this article, the term "component graph" refers to a directed acyclic graph, which includes multiple nodes, and the multiple nodes include nodes corresponding to circuit function modules. A component graph is a data structure, each of which can represent a corresponding unit in a circuit, and the edges between the nodes can represent the logical relationship between the units in the circuit. In the component graph, the function and type of the node are not limited to the basic logic gate, but can correspond to the function and type of a specific circuit function module. In this article, the term "circuit function module" refers to a specific module in a circuit. Examples of circuit function modules may include modules of interest to the user, modules that appear frequently, known IPs, etc. In some embodiments, the circuit function module may include an operation unit. For example, the circuit function module may be a mixed circuit module containing an operation unit. Examples of operation units may include full adders, half adders, compressors, etc. In some embodiments, a library including predetermined circuit function modules may be established.

[0056] As is well known, the NAND graph is a directed acyclic graph that only includes two logics, an AND gate and an inverter (or NOT gate), so it cannot reflect the structural information in the circuit from the level of the circuit functional module. For example, it is not easy to determine that some areas in the NAND graph correspond to a certain circuit functional module. In contrast, the component graph according to the embodiment of the present disclosure includes nodes corresponding to the circuit functional modules, so the component graph can reflect richer information at the level of the circuit functional modules. For example, based on the component graph, the circuit functional module corresponding to the node can be directly determined. The information of the circuit functional module in the component graph can assist in verifying the logical equivalence, thereby improving the efficiency of logic verification. In addition, compared with the NAND graph, the scale of the component graph is smaller, so the resource consumption of reasoning or model solving based on the component graph is less.

[0057] Figure 3 3 shows an example of a NAND map 310 and a component map 320 according to some embodiments of the present disclosure. Figure 3 As shown, the nodes (e.g., node 9, node 10, node 11, node 12, etc.) in the example NAND graph 310 correspond to AND gates or inverters, and cannot reflect the circuit function modules in the circuit. On the contrary, the example component graph 320 includes nodes corresponding to the circuit function modules, such as nodes 24_22 corresponding to half adders, nodes 36_37 corresponding to full adders, and node 41 corresponding to XOR. In some embodiments, the corresponding component graph can be generated by extracting the subcircuit module (cut) corresponding to the circuit function module from the NAND graph 310. For example, the cut shown by the dotted box in the NAND graph 310 can be replaced by XOR in the corresponding component graph.

[0058] In some embodiments, a component graph can be determined according to an AND-NOT graph based on a truth table corresponding to a predetermined circuit function module. Specifically, a subcircuit module can be extracted from the AND-NOT graph. It can be checked whether the input vector and output vector of the subcircuit module match the truth table. If it is determined that the subcircuit module corresponds to a specific circuit function module, the subcircuit module can be represented by a node in the component graph. The subcircuit module corresponding to the predetermined circuit function module can be extracted by traversing the AND-NOT graph. It should be understood that any suitable method can be used to identify the area corresponding to the circuit function module from the AND-NOT graph, and the scope of the present disclosure is not limited thereto.

[0059] Additionally, the generated component graph can be simplified to further reduce the scale of the component graph. In some embodiments, the component graph can be simplified by merging multiple nodes in the component graph into a new node. In some embodiments, the component graph can be simplified using a sweeping algorithm. For example, a first group of nodes and a second group of nodes that are equivalent to each other can be identified in the component graph, and each group of nodes can include one or more nodes. The component graph can be simplified by replacing the first group of nodes and the second group of nodes with the same node. In some embodiments, the first group of nodes and the second group of nodes that may be equivalent can be identified by performing simulation in the component graph. Subcircuit modules that may be equivalent can be identified by inputting vectors to multiple subcircuit modules (cut), i.e., the first group of nodes and the second group of nodes that may be equivalent can be identified by comparing the output vectors of multiple subcircuit modules. Then, a binary decision diagram BDD can be constructed to complete the equivalence proof to clarify that the first group of nodes and the second group of nodes are equivalent to each other. In this way, multiple groups of nodes that are equivalent can be identified in the component graph for simplifying the component graph. It should be understood that any suitable method can be used to perform simplification of the graph, and the scope of the present disclosure is not limited here.

[0060] At block 230, the processor determines the logical equivalence between the first circuit and the second circuit based on the component graph. In some embodiments, the logical equivalence between the first circuit and the second circuit can be verified by performing reasoning on the component graph using an automatic test vector generation ATPG algorithm. As described above, the sub-logic circuit may include an XOR gate connecting at least a portion of the first circuit and at least a portion of the second circuit, and the component graph may include an output node corresponding to the XOR gate.

[0061] In this case, the output value of the output node of the component graph can be set to a predetermined value (for example, a value of 1), which indicates that the first circuit and the second circuit do not meet the logical equivalence requirement. The component graph can be reasoned using the ATPG algorithm and the predetermined value to determine whether there is a test vector that enables the reasoning to succeed. The test vector can correspond to multiple output values ​​of multiple nodes in the component graph except the output node. Successful reasoning means that multiple output values ​​of multiple nodes in the component graph can obtain the predetermined value of the output node along the directed edge in the directed acyclic graph. If it is determined that there is a test vector that makes the reasoning successful, it can be determined that the first circuit and the second circuit meet the logical equivalence requirement, for example, it can be determined that the first logic cone in the first circuit and the second logic cone in the second circuit are logically equivalent. On the contrary, if it is determined that there is no test vector that makes the reasoning successful, it can be determined that the first circuit and the second circuit meet the logical equivalence requirement.

[0062] ATPG algorithms are often used in design for testability ( Figure 1131) stage in the DFT. The ATPG algorithm can be used to find a specific input vector for a specified fault in the circuit, so that the input vector (i.e., the test vector) can stimulate the fault. In an embodiment of the present disclosure, the predetermined value of the output node in the component graph can be regarded as a virtual fault, and a specific input vector can be found for the predetermined value so that the input vector can generate the predetermined value of the output node. In this way, the ATPG algorithm can be applied to the scenario of logical equivalence verification. Using the ATPG algorithm, it is possible to efficiently infer forward from the predetermined value at the output node to obtain the input vector or determine that there is no suitable input vector.

[0063] In some embodiments, a fan-based ATPG algorithm can be used to perform reasoning on a component graph. The fan-based ATPG algorithm, also known as the FAN algorithm, uses path sensitization technology to find a path in the circuit so that errors in the path can be uniquely sensitized. The FAN algorithm is characterized by making decisions only at the headline and only propagating at other gates, thereby reducing the decision space. In an embodiment of the present disclosure, using the FAN algorithm, the output value of the output node corresponding to the XOR gate in the component graph can be directly set to a predetermined value, such as 1, without making a decision at the output node. In addition, the information of the circuit function module in the component graph can be used to choose to make a decision at a specific node and only propagate at a specific node, thereby improving the efficiency of reasoning.

[0064] Figure 4 A schematic diagram of an example value transmission method 400 in an ATPG algorithm according to some embodiments of the present disclosure is shown. Figure 4 The figure shows the unique value transmission method based on requirement driven in FAN algorithm, that is, propagation along the path that is uniquely sensitized by the fault. Figure 4 As shown, starting from the output node A=1, the values ​​of gates G1, G2, and G3 can be obtained in turn according to the truth table. It should be understood that any suitable ATPG algorithm can be applied in the embodiments of the present disclosure, and the scope of the present disclosure is not limited here. The process of performing reasoning according to the truth table in various APPG algorithms is not repeated in this article.

[0065] Continue to refer Figure 2In some embodiments, when reasoning is performed on a component graph, an implication graph can be constructed based on the component graph. The implication graph can indicate multiple results obtained by multiple decisions during the reasoning process. The implication graph can indicate the decisions made at each decision level during the reasoning process and the results caused by these decisions. Based on the conflicts between the multiple results, conflict constraints for the component graph can be determined. The conflict constraints can include a logical restriction relationship between the output values ​​of at least two nodes in the component graph. Based on the conflict constraints, at least one of the multiple decisions made previously can be updated to continue reasoning. The above operation can also be referred to as error-based learning. In this way, errors in previous decisions can be accumulated, conflict constraints can be generated, and reasoning can be assisted based on the conflict constraints, thereby improving the efficiency of reasoning.

[0066] In some embodiments, the symbolic calculation method in the SAT solver can be used to add implicit conflict constraints through error-based learning, and a backtrack node can be selected according to the online reasoning result. The implication graph can be constructed synchronously during the reasoning process, and the decision level corresponding to the decision can be added in the implication graph. When a conflict occurs, the forward reasoning can be carried out from the conflict node, and the decision level can be used as the judgment condition until there is only one node in the root cause at the current decision level, the search is stopped and the node is used as the backtrack node, otherwise, the corresponding multiple child nodes are replaced with the parent node and the search is continued. Starting from the conflict node to the backtrack node, all nodes that have not been replaced in the forward reasoning process are recorded, and the appropriate logical symbols between the nodes are selected according to the current logical value, so as to construct the conflict constraint. By synchronously constructing the implication graph during the reasoning process, the reasoning history can be recorded and the conflict constraint can be generated based on the conflict that has occurred. Using the generated conflict constraint, the search space can be narrowed to improve the efficiency of reasoning.

[0067] In some embodiments, if it is determined that there is a test vector that makes the reasoning successful, that is, it is determined that the first circuit and the second circuit do not meet the logical equivalence requirement, then a root cause analysis can be performed based on the component graph. A root cause analysis option can be provided to the user, so that the user can locate which parts of the circuit cause the two to be logically inequal based on the solution process and the solution. In some implementations, a user interface for root cause analysis can be provided to the user, in which at least a portion of the component graph is displayed. Since the component graph includes nodes corresponding to circuit functional modules, the user can refer to the circuit structure information to perform root cause analysis, thereby improving debug efficiency.

[0068] In some embodiments, component graphs can be constructed and incremental reasoning can be performed by incremental modeling. Unlike the SAT solver in which the entire AND-NOT graph is converted to CNF for reasoning, in the embodiments of the present disclosure, component graphs can be incrementally constructed based on the AND-NOT graph for reasoning. For example, the first component graph can be determined based on the first part of the AND-NOT graph, and the first part of the AND-NOT graph corresponds to the first part of the sub-logic circuit. If the result of the reasoning performed on the first component graph indicates that the first circuit and the second circuit partially meet the logical equivalence requirement, such as the logical equivalence of the two logic cones included in the first part of the sub-logic circuit, the second component graph can be constructed based on the larger second part of the AND-NOT graph and reasoning can be performed on the second component graph. The second part of the AND-NOT graph corresponds to the second part of the sub-logic circuit, and the second part of the sub-logic circuit includes the above-mentioned first part of the sub-logic circuit. By performing reasoning on the second component graph, the logical equivalence between the first circuit and the second circuit can be further verified. In this article, the term "incremental modeling" refers to constructing multiple component graphs and performing reasoning on each component graph in turn in the order of increasing circuit scale. In this way, the scale of a single component graph can be reduced, thereby improving the efficiency of reasoning. In addition, by using the incremental modeling approach, when reasoning about a subsequent component graph, the information of the previously successfully reasoned component graph can be used, thereby accelerating the reasoning.

[0069] In this article, an engine that performs reasoning on a component graph using an ATPG algorithm may be referred to as an ATPG solver for verifying logical equivalence. In some embodiments, an ATPG solver may verify logical equivalence independently. In some embodiments, an ATPG solver may verify logical equivalence in parallel with other solvers. Other solvers that verify logical equivalence in parallel with the ATPG solver may be any suitable solver. Other solvers may verify logical equivalence based on CNF or BDD, or may directly perform circuit reasoning based on AIG, and the scope of the present disclosure is not limited thereto.

[0070] Figure 5 A schematic diagram of an example process 500 for verifying logical equivalence according to some embodiments of the present disclosure is shown. Process 500 can be considered as a specific example of process 200. Process 500 can be implemented by any suitable computing unit. For example, it can be performed by a computer or other electronic device with computing or circuit design capabilities. Specifically, for example, an EDA tool can be implemented by a processor of a computer according to data and / or instructions stored in a memory to perform process 500.

[0071] like Figure 5As shown, in block 501, the processor may start from the points to be compared in each circuit, take the comparison points as output, and traverse the circuit forward to construct the corresponding logic cone. In block 502, the processor may convert the logic cone to be compared into the AIG format. During the conversion process, the logic cones to be compared may be connected through a virtual XOR, and it is assumed that the output of the XOR is 1, that is, it is assumed that the logic cones to be compared are not equivalent.

[0072] In block 503, the processor may perform equivalent functional module identification for a predetermined IP or a given library of circuit functional modules based on simulation. The library of predetermined circuit functional modules may include some circuit modules of interest to the user, such as various operation units. The processor may extract a subcircuit module (cut) from the AIG, and determine whether the input and output of the subcircuit module correspond to the truth table of the specific circuit functional module by simulating the subcircuit module. If it is determined that the subcircuit module corresponds to the specific circuit functional module, the subcircuit module may be used as an equivalent functional module.

[0073] In block 504, the processor may construct a component graph based on the recognition result. The component graph may be constructed by representing the subcircuit modules in the AND-NOT graph with corresponding nodes. In block 505, the processor may perform a sweeping algorithm on the component graph to perform simplification. The component graph may be simplified by merging multiple nodes in the component graph into one node.

[0074] At block 506, the processor may initiate an ATPG-driven circuit reasoning algorithm on the component graph. Based on the properties of the ATPG algorithm, the size M of the solution model used to perform reasoning on the component graph grows linearly with the size N of the logic cone. In contrast, in conventional SAT solvers, the size M of the solution model grows exponentially with the growth of N. An ATPG algorithm such as the FAN algorithm may be used to perform reasoning on the component graph to determine whether there is an input vector that makes the reasoning successful. The ATPG engine may be used as an ATPG solver to verify logical equivalence in parallel with other solvers. Figure 5As shown, other solvers may be CNF-based SAT solvers. In box 507, the processor may convert the component graph into CNF format for use in verifying logical equivalence using a SAT solver. Any suitable method may be used to obtain CNF based on the component graph, and the embodiments of the present disclosure are not limited thereto. In box 508, the processor may call a certain number of solvers to complete the solution according to memory constraints. For example, the processor may call k-1 SAT solvers to verify logical equivalence in parallel.

[0075] In box 509, the processor can determine whether the solution time of the solver reaches the time limit (reach timelimit). If the solution has been completed within the preset time limit, the processor can perform subsequent operations accordingly according to the solution result. In box 510, it can be determined whether the solution result indicates that there is no solution, that is, there is no input vector that makes the reasoning successful. If so, in box 511, it can be proved that the two circuits to be compared pass the LEC verification, that is, the two circuits are logically equivalent. On the contrary, if the solution result indicates that the input vector is found to make the reasoning successful, it can be proved that the two circuits are not equivalent. At box 512, the processor can turn on the debug mode so that the user can return to the original circuit to complete the root cause analysis.

[0076] If the solution is not completed within the preset time limit, for example, it is determined at block 512 that there is a comparison point that has been aborted due to a problem or failure, it can be determined that the coverage of the current comparison point is not completed. In some embodiments, the coverage rate can be counted. The coverage rate can be used to measure the solving performance of the solver. The coverage rate can be represented by the ratio of the number of comparison points that have completed verification to all comparison points.

[0077] References Figures 1 to 5 The principles and details of the scheme for chip logic verification according to the embodiment of the present disclosure are described. It should be understood that the above processes 200 and 500 are merely exemplary and do not constitute a limitation on the scope of the present disclosure. By using the component graph to verify the logical equivalence, the circuit structure information can be used to solve the logical equivalence verification problem, and the scale of the solution model can be reduced, thereby improving the efficiency of verifying the logical equivalence and reducing resource consumption. Using the scheme of the present disclosure, a component graph can be constructed in an industrial LEC tool, and the LEC proof engine can be implemented using ATPG technology to improve the proof coverage. In addition, the use of ATPG technology for industrial LEC verification can realize an interactive incremental solution process and corresponding functions.

[0078] Figure 6 A schematic diagram illustrating a first performance representation of an ATPG solver according to some embodiments of the present disclosure is shown. Figure 6 The test results of various solvers including ATPG solver for given test cases are shown 600. For 2400 test cases, three candidate solvers were tested, including ATPG solver according to an embodiment of the present disclosure, Qiuqi solver (first SAT solver) and Xingyun-kissat solver (second SAT solver). The test result 600 indicates that there are 754 test cases that can only be solved by ATPG solver (marked as Atpg only), 10 test cases that can only be solved by Xingyun-kissat solver (marked as Xingyun-kissat only), 4 test cases that can only be solved by ATPG solver and Qiuqi solver (marked as Atpg&Qiuqi shared), 57 test cases that can only be solved by ATPG solver and Xingyun-kissat solver (marked as ATPG&Xingyun-kissat shared), 21 test cases that can only be solved by Xingyun-kissat solver and Qiuqi solver (marked as Xingyun-kissat&Qiuqi shared), and 1829 test cases that can be solved by any of the above solvers (marked as ATPG&Xingyun-kissat&Qiuqi shared). Therefore, this test result 600 indicates that the ATPG solver according to the embodiment of the present disclosure can be widely used to verify the logical equivalence of various circuits.

[0079] Figure 7 A schematic diagram illustrating a second performance representation of an ATPG solver according to some embodiments of the present disclosure is shown. Figure 7 FIG. 7 shows test results 700 of various solvers including an ATPG solver. The test results 700 show the solving performance of each solver for different miters in a test case (TC). Figure 7As shown, for the test case number (TC_num) of TC1 and the test name (case_name) of FFTO, the number of miters (miter_num) included is 198644. Among these 198644 miters, the number of miters solved by the Kissat solver fastest (marked as Kissat_win) is 52113, the number of miters solved by the Qiuqi solver fastest (marked as Qiuqi_win) is 44901, and the number of miters solved by the ATPG solver fastest (marked as Atpg_win) is 101630. In addition, the time taken by the Kissat solver to complete the solution (labeled as Kissat_time) is 716671698 milliseconds, the time taken by the Qiuqi solver to complete the solution (labeled as Qiuqi_time) is 743593148 milliseconds, and the time taken by the ATPG solver to complete the solution (labeled as Atpg_time) is 284724722 milliseconds. In general, the test result 700 indicates that for more than 30% of the test cases, the ATPG solver according to the embodiment of the present disclosure has the best performance.

[0080] Figure 8 A schematic diagram 800 of applicable circuit features of an ATPG solver according to some embodiments of the present disclosure is shown. The circuit features applicable to the ATPG solver can be determined by a representation learning approach. The results show that the features used by the ATPG solver according to an embodiment of the present disclosure include the number of full adders (labeled as Num_full_adder), the depth of XOR (labeled as Max_depth_xor_tree), the number of XOR trees (labeled as Num_xor_tree), the number of XORs (labeled as Num_xor_tree), the width of the XOR tree (labeled as Max-width_xor_tree), and the number of half adders (labeled as Num_half_adder). The corresponding importance or weights of these features are 51%, 14%, 10%, 9%, 9%, and 7%, respectively.

[0081] Fig. 9 A schematic diagram showing the memory usage representation of an ATPG solver according to some embodiments of the present disclosure is shown. Fig. 9 The memory usage results 900 of an ATPG-based solver (labeled as ATPG-based) and a SAT-based solver (labeled as SAT-based) are shown. Fig. 9In FIG. 1 , the horizontal axis represents the circuit number, and the vertical axis represents the memory usage (in bytes B) required to solve the circuit. The memory usage result 900 indicates that for circuits 1 to 7 with gradually increasing circuit scales, the memory usage of the SAT solver increases exponentially with the increase of the circuit scale, while the memory usage of the ATPG solver increases linearly with the increase of the circuit scale. It can be seen that the solution disclosed in the present invention has an advantage in terms of memory utilization.

[0082] Example devices and equipment

[0083] Fig.10 FIG. 1 is a block diagram of an apparatus 1000 for chip logic verification according to an embodiment of the present disclosure. Specifically, the apparatus 1000 may be an EDA software apparatus. The apparatus 1000 may include multiple modules for executing the following steps: Figure 2 and Figure 5 The corresponding steps in the process discussed in Fig.10 As shown, the apparatus 1000 includes: a NAND graph construction unit 1010, configured to construct a NAND graph (AIG) representing a sub-logic circuit, wherein the sub-logic circuit includes at least a portion of a first circuit and at least a portion of a second circuit; a component graph determination unit 1020, configured to determine a component graph based on the NAND graph, wherein the component graph includes nodes corresponding to circuit function modules in the sub-logic circuit, wherein the circuit function modules include AND gates and inverters in the NAND graph; and a logic verification unit 1030, configured to determine the logical equivalence between the first circuit and the second circuit based on the component graph.

[0084] In this way, by verifying logical equivalence using component graphs, the logic equivalence verification problem can be solved using circuit structure information, and the scale of the solution model can be reduced, thereby improving the efficiency of verifying logical equivalence and reducing resource consumption.

[0085] In some embodiments, the apparatus 1000 further comprises a simplification unit configured to simplify the component graph by merging a plurality of nodes in the component graph into a new node. In some embodiments, the sub-logic circuit further comprises an XOR gate, the XOR gate connecting at least a portion of the first circuit and at least a portion of the second circuit. The logic verification unit 1030 is configured to set an output value of an output node of the component graph to a predetermined value, the output node corresponds to the XOR gate, the predetermined value indicates that the first circuit and the second circuit do not meet the logic equivalence requirement; perform reasoning on the component graph using an automatic test vector generation ATPG algorithm and the predetermined value, determine whether there is a test vector that makes the reasoning successful, the test vector corresponds to a plurality of output values ​​of a plurality of nodes in the component graph other than the output node; and determine that the first circuit and the second circuit meet the logic equivalence requirement based on the determination that there is no test vector that makes the reasoning successful.

[0086] In some embodiments, the logic verification unit 1030 includes: an inference learning unit, configured to: construct an implication graph based on the component graph, the implication graph indicating multiple results obtained by multiple decisions in the inference process; determine a conflict constraint for the component graph based on a conflict between the multiple results in the implication graph, the conflict constraint including a logical restriction relationship between output values ​​of at least two nodes in the component graph; and update at least one of the multiple decisions based on the conflict constraint.

[0087] In some embodiments, the component graph is a first component graph determined based on a first portion of the NAND graph, and the first portion of the NAND graph corresponds to a first portion of the sub-logic circuit. The logic verification unit 1030 is configured to: determine that the first circuit and the second circuit partially meet the logical equivalence requirement based on a result of the reasoning performed on the first component graph; determine a second component graph based on a second portion of the NAND graph, the second portion of the NAND graph corresponds to a second portion of the sub-logic circuit, and the second portion of the sub-logic circuit includes the first portion of the sub-logic circuit; and determine the logical equivalence between the first circuit and the second circuit by performing reasoning on the second component graph.

[0088] In some embodiments, the apparatus 1000 further comprises a root cause analysis unit. The logic verification unit 1030 is configured to: determine that the first circuit and the second circuit do not meet the logic equivalence requirement based on determining that there is a test vector that makes the reasoning successful. The root cause analysis unit is configured to: perform root cause analysis based on the component graph.

[0089] In some embodiments, the ATPG algorithm includes a fan-based ATPG algorithm. In some embodiments, the circuit function module includes at least one of the following: a full adder, a half adder, or a compressor. In some embodiments, the logic verification unit 1030 is further configured to: determine the logical equivalence between the first circuit and the second circuit based on a conjunctive normal form (CNF) obtained from a component graph.

[0090] Fig.11 A schematic block diagram of an example device 1100 that can be used to implement an embodiment of the present disclosure is shown. As shown, the device 1100 includes a computing unit 1101, which can perform various appropriate actions and processes according to computer program instructions stored in a random access memory (RAM) 1103 and / or a read-only memory (ROM) 1102 or computer program instructions loaded from a storage unit 1108 into the RAM 1103 and / or ROM 1102. In the RAM 1103 and / or ROM 1102, various programs and data required for the operation of the device 1100 can also be stored. The computing unit 1101 and the RAM 1103 and / or ROM 1102 are connected to each other via a bus 1104. An input / output (I / O) interface 1105 is also connected to the bus 1104.

[0091] A number of components in the device 1100 are connected to the I / O interface 1105, including: an input unit 1106, such as a keyboard, a mouse, etc.; an output unit 1107, such as various types of displays, speakers, etc.; a storage unit 1108, such as a disk, an optical disk, etc.; and a communication unit 1109, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 1109 allows the device 1100 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0092] The computing unit 1101 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the computing unit 1101 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, digital signal processors (DSPs), and any appropriate processors, controllers, microcontrollers, etc. The computing unit 1101 performs the various methods and processes described above, such as processes 200 and 500. For example, in some embodiments, processes 200 and 500 may be implemented as computer software programs, specifically EDA programs, which are tangibly contained in machine-readable media, such as storage unit 1108. In some embodiments, part or all of the computer program may be loaded and / or installed on the device 1100 via RAM and / or ROM and / or communication unit 1109. When the computer program is loaded into RAM and / or ROM and executed by the computing unit 1101, one or more steps of processes 200 and 500 described above may be performed. Alternatively, in other embodiments, the computing unit 1101 may be configured to perform processes 200 and 500 in any other appropriate manner (eg, by means of firmware).

[0093] In the above embodiments, the method flow can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented by software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a server or terminal, the process or function described in the embodiment of the present application is generated in whole or in part. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website site, computer, server or data center to another website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a server or terminal or a data storage device such as a server or data center that includes one or more available media integrated. The available medium can be a magnetic medium (such as a floppy disk, a hard disk and a tape, etc.), an optical medium (such as a digital video disk (digital video disk, DVD), etc.), or a semiconductor medium (such as a solid-state hard disk, etc.).

[0094] In addition, although each operation is described in a specific order, this should be understood as requiring such operation to be performed in the specific order shown or in a sequential order, or requiring that all illustrated operations should be performed to obtain desired results. Under certain circumstances, multitasking and parallel processing may be advantageous. Similarly, although some specific implementation details are included in the above discussion, these should not be interpreted as limiting the scope of the present disclosure. Some features described in the context of a separate embodiment can also be implemented in a single implementation in combination. On the contrary, the various features described in the context of a single implementation can also be implemented in multiple implementations individually or in any suitable sub-combination mode.

[0095] Although the subject matter has been described in language specific to structural features and / or methodological logical actions, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. On the contrary, the specific features and actions described above are merely example forms of implementing the claims.

Claims

1. A method for chip logic verification, characterized in that: include: constructing a NAND graph (AIG) representing a sub-logic circuit, the sub-logic circuit including at least a portion of the first circuit and at least a portion of the second circuit; Determining a component graph based on the NAND graph, the component graph including nodes corresponding to circuit function modules in the sub-logic circuit, the circuit function modules including AND gates and inverters in the NAND graph; and Based on the component graph, a logical equivalence between the first circuit and the second circuit is determined.

2. The method according to claim 1, characterized in that The method further comprises: The component graph is simplified by merging multiple nodes in the component graph into a new node.

3. The method according to any one of claims 1 to 2, characterized in that The sub-logic circuit further includes an XOR gate, the XOR gate connecting at least a portion of the first circuit and at least a portion of the second circuit; Based on the component graph, determining the logical equivalence between the first circuit and the second circuit includes: Setting an output value of an output node of the component graph to a predetermined value, the output node corresponding to the XOR gate, the predetermined value indicating that the first circuit and the second circuit do not meet a logical equivalence requirement; Performing reasoning on the component graph using an automatic test vector generation ATPG algorithm and the predetermined value to determine whether there is a test vector that makes the reasoning successful, the test vector corresponding to a plurality of output values ​​of a plurality of nodes in the component graph except the output node; as well as Based on determining that there is no test vector that makes the reasoning successful, determining that the first circuit and the second circuit meet the logical equivalence requirement.

4. The method according to claim 3, characterized in that Performing inference on the component graph includes: constructing an implication graph based on the component graph, wherein the implication graph indicates multiple results obtained from multiple decisions during the reasoning process; Based on the conflicts between the multiple results, determining a conflict constraint for the component graph, the conflict constraint comprising a logical restriction relationship between output values ​​of at least two nodes in the component graph; and At least one decision of the plurality of decisions is updated based on the conflicting constraint.

5. The method according to any one of claims 3 to 4, characterized in that The component map is a first component map determined based on a first portion of the NAND map, the first portion of the NAND map corresponding to a first portion of the sub-logic circuit; The determining the logical equivalence between the first circuit and the second circuit comprises: determining, based on a result of the reasoning performed on the first component graph, that the first circuit and the second circuit partially satisfy the logical equivalence requirement; determining a second component map based on a second portion of the NAND map, the second portion of the NAND map corresponding to a second portion of the sub-logic circuit, and the second portion of the sub-logic circuit includes the first portion of the sub-logic circuit; and The logical equivalence between the first circuit and the second circuit is determined by performing inference on the second component graph.

6. The method according to any one of claims 3 to 5, characterized in that The method further comprises: Based on determining that there is a test vector that makes the reasoning successful, determining that the first circuit and the second circuit do not meet the logical equivalence requirement; and Based on the component graph, a root cause analysis is performed.

7. The method according to any one of claims 3 to 6, characterized in that The ATPG algorithm includes a fan-based ATPG algorithm.

8. The method according to any one of claims 1 to 7, characterized in that The circuit function module includes at least one of the following: a full adder, a half adder or a compressor.

9. The method according to any one of claims 1 to 8, characterized in that The determining, based on the component graph, the logical equivalence between the first circuit and the second circuit further comprises: The logical equivalence between the first circuit and the second circuit is determined based on a conjunctive normal form (CNF) obtained from the component graph.

10. A device for chip logic verification, characterized in that: include: a NAND graph construction unit configured to construct a NAND graph (AIG) representing a sub-logic circuit, the sub-logic circuit including at least a portion of the first circuit and at least a portion of the second circuit; a component graph determining unit configured to determine a component graph based on the NAND graph, wherein the component graph includes nodes corresponding to circuit function modules in the sub-logic circuit, and the circuit function modules include AND gates and inverters in the NAND graph; as well as A logic verification unit is configured to determine logical equivalence between the first circuit and the second circuit based on the component graph.

11. The apparatus according to claim 10, further comprising a simplification element configured to: The component graph is simplified by merging multiple nodes in the component graph into a new node.

12. The device according to any one of claims 10 to 11, characterized in that The sub-logic circuit further includes an XOR gate, the XOR gate connecting at least a portion of the first circuit and at least a portion of the second circuit; The logic verification unit is configured to: Setting an output value of an output node of the component graph to a predetermined value, the output node corresponding to the XOR gate, the predetermined value indicating that the first circuit and the second circuit do not meet a logical equivalence requirement; Performing reasoning on the component graph using an automatic test vector generation ATPG algorithm and the predetermined value to determine whether there is a test vector that makes the reasoning successful, the test vector corresponding to a plurality of output values ​​of a plurality of nodes in the component graph except the output node; as well as Based on determining that there is no test vector that makes the reasoning successful, determining that the first circuit and the second circuit meet the logical equivalence requirement.

13. The device according to claim 12, characterized in that The logic verification unit includes: an inference learning unit, configured to: constructing an implication graph based on the component graph, wherein the implication graph indicates multiple results obtained from multiple decisions during the reasoning process; Determining a conflict constraint for the component graph based on a conflict between the plurality of results in the implication graph, the conflict constraint comprising a logical restriction relationship between output values ​​of at least two nodes in the component graph; and At least one decision of the plurality of decisions is updated based on the conflicting constraint.

14. The device according to any one of claims 12 to 13, characterized in that The component map is a first component map determined based on a first portion of the NAND map, the first portion of the NAND map corresponding to a first portion of the sub-logic circuit; The logic verification unit is configured to: determining, based on a result of the reasoning performed on the first component graph, that the first circuit and the second circuit partially satisfy the logical equivalence requirement; determining a second component map based on a second portion of the NAND map, the second portion of the NAND map corresponding to a second portion of the sub-logic circuit, and the second portion of the sub-logic circuit includes the first portion of the sub-logic circuit; as well as The logical equivalence between the first circuit and the second circuit is determined by performing inference on the second component graph.

15. The device according to any one of claims 12 to 14, characterized in that The device also includes a root cause analysis unit; The logic verification unit is configured to: determine that the first circuit and the second circuit do not meet the logic equivalence requirement based on determining that there is a test vector that makes the reasoning successful; as well as The root cause analysis unit is configured to perform a root cause analysis based on the component graph.

16. The device according to any one of claims 12 to 15, characterized in that The ATPG algorithm includes a fan-based ATPG algorithm.

17. The device according to any one of claims 10 to 16, characterized in that The circuit function module includes at least one of the following: a full adder, a half adder or a compressor.

18. The device according to any one of claims 10 to 17, characterized in that The logic verification unit is further configured to: The logical equivalence between the first circuit and the second circuit is determined based on a conjunctive normal form (CNF) obtained from the component graph.

19. An electronic device comprising: at least one computing unit; At least one memory, the at least one memory being coupled to the at least one computing unit and storing instructions for execution by the at least one computing unit, the instructions, when executed by the at least one computing unit, causing the electronic device to execute the method according to any one of claims 1 to 9.

20. A computer-readable storage medium having a computer program stored thereon, wherein the program, when executed by a processor, implements the method according to any one of claims 1 to 9.

21. A computer program product comprising computer executable instructions, wherein the computer executable instructions, when executed by a processor, implement the method according to any one of claims 1 to 9.

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