OPC correction method for improving publishing efficiency

Abstract

The invention provides an OPC (optical proximity correction) method for improving publishing efficiency, which comprises the following steps: a post OPC layout is provided, the post OPC layout comprises a standard pattern area and a non-standard pattern area positioned at the periphery of the standard pattern area, and the standard pattern area is provided with a standard pattern and a marking pattern covering the whole standard pattern area; expanding the marked graph outwards for a preset range so as to obtain a visible graph area surrounding the standard graph area in the non-standard graph area; cutting out the standard graph area and the visible graph area to obtain a first auxiliary graph, and remaining other areas only including a main graph of the non-standard graph area; performing data layer conversion processing on the first secondary graph to obtain a second secondary graph; performing OPC correction on the second secondary graph to obtain a third secondary graph; extracting a mask pattern which only reaches a target value after OPC (optical proximity correction) of the standard pattern region from the third secondary pattern; and combining the mask pattern with the main part pattern to obtain a new complete layout. Through the layout publishing method and device, the problem that existing layout publishing efficiency is low is solved.

Description

Technical Field

[0001] The invention relates to the field of semiconductor technology, and in particular to an OPC correction method for improving publishing efficiency. Background Art

[0002] Model-based OPC correction methods play an important role in the field of resolution enhancement technology. OPC tools can reduce edge position errors by moving the edges of layout graphics. In the OPC development stage of advanced processes, time is tight, tasks are heavy, processes are complex, and linkage between upper and lower layers is required. Inline detection and evaluation results cannot be fed back in time. OPC often faces the situation where the target of standard graphics needs to be adjusted near TO. In this case, fullchip needs to be re-run with OPC. However, if fullchip re-run with OPC takes a long time, it will lead to low publishing efficiency. Summary of the invention

[0003] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide an OPC correction method for improving publishing efficiency, so as to solve the problem of low efficiency of existing layout publishing.

[0004] To achieve the above-mentioned object and other related objects, the present invention provides an OPC correction method for improving publishing efficiency, the method comprising:

[0005] A postOPC layout is provided, which includes a standard graphic area and a non-standard graphic area located outside the standard graphic area, wherein the standard graphic area has a standard graphic and a mark graphic covering the entire standard graphic area;

[0006] Expanding the marking graphic outward by a preset range to obtain a visible graphic area surrounding the standard graphic area in the non-standard graphic area;

[0007] Cut out the standard graphic area and the visible graphic area to obtain a first secondary graphic including the standard graphic area and the visible graphic area, and the remaining other areas only include the main graphic of the non-standard graphic area;

[0008] Performing data layer conversion processing on the first secondary partial graphic to obtain a second secondary partial graphic including the standard graphic and a postOPC graphic, wherein the postOPC graphic is a graphic located in the visible graphic area;

[0009] Performing OPC correction on the second subsidiary pattern to obtain a third subsidiary pattern, wherein the third subsidiary pattern includes a mask pattern obtained by correcting the standard pattern;

[0010] Extracting the mask pattern in which only the standard pattern area reaches the target value after OPC correction from the third subsidiary pattern;

[0011] The mask pattern is merged with the main pattern to obtain a new complete layout.

[0012] Optionally, the method of expanding the mark graphic outward by a preset range to obtain a visible graphic area surrounding the standard graphic area in the non-standard graphic area includes:

[0013] The marking pattern was enlarged outward by 2 μm.

[0014] Optionally, the visible graphics area is annular, and the area is defined to the OPCblock layer.

[0015] Optionally, the method of performing data layer conversion processing on the first secondary partial graphic to obtain a second secondary partial graphic including the standard graphic and the postOPC graphic includes:

[0016] Distinguishing the standard graphics area from the visible graphics area, and extracting the standard graphics and the postOPC graphics respectively;

[0017] The standard graphic and the postOPC graphic are merged into the same layer to obtain the second subsidiary graphic.

[0018] Optionally, when performing OPC correction on the third secondary pattern, only the standard pattern is corrected.

[0019] Optionally, the method further comprises the steps of performing OPC inspection and layout repair on the new complete layout.

[0020] Optionally, when repairing the new complete layout, layout repair is performed on the mask pattern at the boundary of the mark pattern.

[0021] Optionally, the standard pattern is a simple repeated pattern.

[0022] Optionally, the standard pattern includes an SRAM pattern.

[0023] Optionally, applicable technology nodes include 55nm, 40nm, and less than or equal to 28nm.

[0024] As described above, the OPC correction method for improving publishing efficiency of the present invention can reduce the OPC processing layout area through the OPC correction method provided by the present invention, and the standard graphic is a simple repeated graphic. Compared with re-running OPC globally for the complete layout, while ensuring the same quality, the OPC operation processing time can be shortened by 50% to 70%, thereby shortening the publishing process and improving OPC publishing efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 Shown is a flow chart of the OPC correction method for improving publishing efficiency of the present invention. DETAILED DESCRIPTION

[0026] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0027] See also Figure 1 It should be noted that the illustrations provided in this embodiment are only schematic illustrations of the basic concept of the present invention. Although the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation, the form, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the component layout may also be more complicated.

[0028] like Figure 1 As shown, this embodiment provides an OPC correction method for improving publishing efficiency, the method comprising:

[0029] A postOPC layout is provided, which includes a standard graphic area and a non-standard graphic area located outside the standard graphic area, wherein the standard graphic area has a standard graphic and a mark graphic covering the entire standard graphic area;

[0030] Expanding the marking graphic outward by a preset range to obtain a visible graphic area surrounding the standard graphic area in the non-standard graphic area;

[0031] Cut out the standard graphic area and the visible graphic area to obtain a first secondary graphic including the standard graphic area and the visible graphic area, and the remaining other areas only include the main graphic of the non-standard graphic area;

[0032] Performing data layer conversion processing on the first secondary partial graphic to obtain a second secondary partial graphic including the standard graphic and a postOPC graphic, wherein the postOPC graphic is a graphic located in the visible graphic area;

[0033] Performing OPC correction on the second subsidiary pattern to obtain a third subsidiary pattern, wherein the third subsidiary pattern includes a mask pattern obtained by correcting the standard pattern;

[0034] Extracting the mask pattern in which only the standard pattern area reaches the target value after OPC correction from the third subsidiary pattern;

[0035] The mask pattern is merged with the main pattern to obtain a new complete layout.

[0036] Specifically, the method of expanding the mark pattern outward by a preset range to obtain a visible graphic area surrounding the standard graphic area in the non-standard graphic area includes: expanding the mark pattern outward by 2 μm.

[0037] Specifically, the visible graphic area is annular, and the area is defined to the OPCblock layer.

[0038] In this embodiment, the purpose of defining the visible graphic area to the OPCblock layer is to facilitate viewing the environment structure of the visible graphic area when performing OPC processing on the standard graphic later.

[0039] Specifically, the method of performing data layer conversion processing on the first sub-partial graphic to obtain a second sub-partial graphic including the standard graphic and the postOPC graphic includes: distinguishing the standard graphic area and the visible graphic area, and extracting the standard graphic and the postOPC graphic respectively; merging the standard graphic and the postOPC graphic into the same layer to obtain the second sub-partial graphic.

[0040] Specifically, when performing OPC correction on the third auxiliary pattern, only the standard pattern is corrected.

[0041] Specifically, the method further includes the steps of performing OPC inspection and layout repair on the new complete layout.

[0042] Specifically, when the new complete layout is repaired, the layout repair is performed on the mask pattern at the boundary of the mark pattern.

[0043] In this embodiment, complete and accurate layout data can be obtained by performing an OPC check on the data of the new complete layout and performing layout repair on the mask pattern at the boundary of the mark pattern.

[0044] Specifically, the standard pattern is a simple repeated pattern.

[0045] More specifically, the standard pattern includes an SRAM pattern. In this embodiment, the SRAM pattern is a first metal layer line SRAM pattern.

[0046] Specifically, applicable technology nodes include 55nm, 40nm and less than or equal to 28nm.

[0047] In summary, the OPC correction method for improving publishing efficiency of the present invention can reduce the OPC processing layout area through the OPC correction method provided by the present invention, and the standard pattern is a simple repeated pattern. Compared with the global re-running of OPC on the complete layout, under the premise of ensuring the same quality, the OPC operation processing time can be shortened by 50% to 70%, the publishing process can be shortened, and the OPC publishing efficiency can be improved. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0048] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. An OPC correction method for improving publishing efficiency, characterized in that: The method comprises: A postOPC layout is provided, which includes a standard graphic area and a non-standard graphic area located outside the standard graphic area, wherein the standard graphic area has a standard graphic and a mark graphic covering the entire standard graphic area; Expanding the marking graphic outward by a preset range to obtain a visible graphic area surrounding the standard graphic area in the non-standard graphic area; Cut out the standard graphic area and the visible graphic area to obtain a first secondary graphic including the standard graphic area and the visible graphic area, and the remaining other areas only include the main graphic of the non-standard graphic area; Performing data layer conversion processing on the first secondary partial graphic to obtain a second secondary partial graphic including the standard graphic and a postOPC graphic, wherein the postOPC graphic is a graphic located in the visible graphic area; Performing OPC correction on the second subsidiary pattern to obtain a third subsidiary pattern, wherein the third subsidiary pattern includes a mask pattern obtained by correcting the standard pattern; Extracting the mask pattern in which only the standard pattern area reaches the target value after OPC correction from the third subsidiary pattern; The mask pattern is merged with the main pattern to obtain a new complete layout.

2. The OPC correction method for improving publishing efficiency according to claim 1, characterized in that: The method of expanding the marking graphic outwardly to a preset range to obtain a visible graphic area surrounding the standard graphic area in the non-standard graphic area includes: The marking pattern was enlarged outward by 2 μm.

3. The OPC correction method for improving publishing efficiency according to claim 1, characterized in that: The visible graphics area is annular and is defined to the OPCblock layer.

4. The OPC correction method for improving publishing efficiency according to claim 1, characterized in that: The method of performing data layer conversion processing on the first secondary partial graphic to obtain a second secondary partial graphic including the standard graphic and the postOPC graphic comprises: Distinguishing the standard graphics area from the visible graphics area, and extracting the standard graphics and the postOPC graphics respectively; The standard graphic and the postOPC graphic are merged into the same layer to obtain the second subsidiary graphic.

5. The OPC correction method for improving publishing efficiency according to claim 1, characterized in that: When performing OPC correction on the third subsidiary pattern, only the standard pattern is corrected.

6. The OPC correction method for improving publishing efficiency according to claim 1, characterized in that: The method also includes the steps of performing OPC inspection and layout repair on the new complete layout.

7. The OPC correction method for improving publishing efficiency according to claim 6, characterized in that: When the new complete layout is repaired, the layout repair is performed on the mask pattern at the boundary of the mark pattern.

8. The OPC correction method for improving publishing efficiency according to claim 1, characterized in that: The standard pattern is a simple repeated pattern.

9. The OPC correction method for improving publishing efficiency according to claim 8, characterized in that: The standard pattern includes an SRAM pattern.

10. The OPC correction method for improving publishing efficiency according to claim 1, characterized in that: Applicable technology nodes include 55nm, 40nm and less than or equal to 28nm.

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