Multilayer ceramic capacitor and preparation method thereof

Abstract

The invention provides a multilayer ceramic capacitor and a preparation method thereof. According to the preparation method, a photoetching process is adopted to replace a traditional silk-screen mode to form the electrode layer, pattern deformation caused by the silk-screen process is avoided, and it is ensured that an accurate electrode pattern is formed. And moreover, the electrode layers and the dielectric layers are formed layer by layer in a slurry brushing and baking mode, so that the problem of interlayer displacement generated by a stacking process is effectively avoided, and the staggered area between the upper electrode layer and the lower electrode layer is favorably controlled. In addition, end electrodes are formed through photoetching while the electrode layer is photoetched, the adjacent end electrodes are connected and can be directly used as end face inner electrodes after being cut, and an impregnation process does not need to be independently executed. Therefore, the preparation method not only improves the preparation efficiency, but also improves the conductivity of the inner electrode and the outer electrode, and optimizes the radio frequency characteristic of the device.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a multilayer ceramic capacitor and a preparation method thereof. Background Art

[0002] Multi-layer ceramic capacitors (MLCC) are capacitors made of stacked ceramic dielectric diaphragms. They have the advantages of small size, light weight, and good high-frequency characteristics. They are widely used in various electronic devices.

[0003] See also Figure 1 The multilayer electrode layer 100 in the existing multilayer ceramic capacitor is formed by silk-screening metal electrodes on the dielectric layer 101 and then stacking them in multiple layers. However, during the manufacturing process, since the steel mesh material itself is prone to deformation, the silk-screen patterned electrode layer 100 will be locally deformed, which in turn affects the capacitor performance. In addition, during the multi-layer stacking process, due to the tension difference and volatility of the machine's operation on the printed thin strip, and the limitations of the machine's peeling and alignment accuracy, there will inevitably be a shift offset between the upper and lower electrodes during the thin strip stacking process, which affects the interlaced area between the two adjacent electrode layers 100, resulting in a low hit rate of the capacitor main gauge.

[0004] In addition, the original process is to form the end face inner electrode layer 102 by a dipping process alone after the green embryo crystal grain is formed. Then, the nickel layer 103 and the tin layer 104 are formed in sequence by an electroplating process to serve as the end face outer electrode layer. Among them, the end face inner electrode layer 102 needs to be connected with each electrode layer 100 stacked in the green embryo crystal grain, but the preparation method of dipping is likely to cause poor overlap between the inner and outer electrodes, affecting the device yield. In addition, the material of the existing end face inner electrode layer 102 is generally copper material. In order to improve the bonding strength with the ceramic substrate, glass components are added to the copper material, which is also likely to affect the conductive performance of the inner and outer electrodes, and also limit the radio frequency characteristics of the capacitor.

[0005] Therefore, a new method for preparing multilayer ceramic capacitors is urgently needed to solve the above problems. Summary of the invention

[0006] The object of the present invention is to provide a multilayer ceramic capacitor and a method for preparing the same, so as to solve at least one of the problems of how to avoid deformation of the electrode layer, how to avoid interlayer displacement of the upper and lower electrode layers, ensure the staggered area, how to improve the connection effect of the internal and external electrodes, and how to improve the radio frequency characteristics of the capacitor.

[0007] In order to solve the above technical problems, the present invention provides a method for preparing a multilayer ceramic capacitor, comprising:

[0008] providing a cover layer;

[0009] A main structure is formed on the cover layer; the main structure comprises multiple layers of alternately formed electrode layers and dielectric layers; wherein some layers of the electrode layers are etched to form internal electrodes and terminal electrodes; adjacent layers of the internal electrodes are separated by the dielectric layer; adjacent layers of the terminal electrodes are connected and are at least located on the cutting path of the main structure;

[0010] The main structure and the cover plate layer are cut along the cutting path to be divided into a plurality of crystal grains; and each of the terminal electrodes exposed on the side and top of the crystal grain constitutes an end surface inner electrode of the crystal grain;

[0011] An end surface outer electrode is formed on the end surface inner electrode of each of the crystal grains.

[0012] Optionally, in the method for preparing the multilayer ceramic capacitor, the process of forming the main structure on the cover layer includes:

[0013] Step 1: forming an electrode layer, wherein the electrode layer covers the surface of the cover layer;

[0014] Step 2: etching the electrode layer using a photolithography process to form a patterned electrode layer; wherein the patterned electrode layer includes the inner electrode and the terminal electrode;

[0015] Step 3: forming a dielectric layer, wherein the dielectric layer covers the patterned electrode layer;

[0016] Step 4: etching the dielectric layer using a photolithography process to form a patterned dielectric layer; wherein the patterned dielectric layer exposes the terminal electrode;

[0017] Step 5: forming an electrode layer, wherein the electrode layer covers the patterned dielectric layer and is connected to the exposed terminal electrode;

[0018] Step 6: Repeat step 2 and step 5 until the preparation of the preset number of electrode layers and dielectric layers is completed;

[0019] Step 7: etching the electrode layer at the top layer by photolithography to form a top terminal electrode; the top terminal electrode is connected to the terminal electrode of the next adjacent layer, and the top terminal electrode also extends a preset distance along the surface of the dielectric layer;

[0020] Step eight: forming a dielectric layer; the dielectric layer covers the top terminal electrode and the next adjacent dielectric layer.

[0021] Optionally, in the method for preparing the multilayer ceramic capacitor, in the same patterned electrode layer, the end electrodes are provided on opposite sides of the inner electrode, and one side of the inner electrode is connected to the adjacent end electrode, and the other side is separated from the adjacent end electrode.

[0022] Optionally, in the method for preparing the multilayer ceramic capacitor, in the process of preparing two adjacent patterned electrode layers, different masks are used to photolithography the corresponding electrode layers so that the two vertically adjacent layers of the internal electrodes are respectively connected to the end electrodes on different sides.

[0023] Optionally, in the method for preparing the multilayer ceramic capacitor, the dielectric layer and the electrode layer are both photosensitized; and, during the photolithography process, the pH value of the exposure developer used is >6; and the ion concentration range of the developer is: 0.1% to 30%.

[0024] Optionally, in the method for preparing the multilayer ceramic capacitor, the process of cutting the main structure and the cover layer along the cutting path to divide them into a plurality of the crystal grains includes:

[0025] Cutting the main structure and the cover plate layer by laser, and exposing the terminal electrode and the top terminal electrode located on the side of the main structure to serve as the end surface inner electrode of the grain;

[0026] The end surface inner electrode is in an "L" shape and covers two opposite sides of the grain.

[0027] Optionally, in the method for preparing the multilayer ceramic capacitor, the thickness range of the cover layer and the dielectric layer is 0.1 micrometer to 100 micrometers; the thickness range of the electrode layer is 0.1 micrometer to 10 micrometers; and the size of the electrode inside the end surface satisfies the following formula:

[0028] Z1≤H3; Y1≤W3; X2<50%L3; Y2≤W3;

[0029] Wherein, Z1 refers to the height of the electrode inside the end surface located on the side of the grain;

[0030] Y1 refers to the width of the electrode on the end surface of the part located on the side of the grain;

[0031] X2 refers to the length of the top terminal electrode;

[0032] Y2 refers to the width of the top terminal electrode;

[0033] H3 refers to the height of the grain;

[0034] W3 refers to the width of the grain;

[0035] L3 refers to the length of the grain.

[0036] Optionally, in the method for preparing the multilayer ceramic capacitor, after forming the main structure on the cover layer and before cutting the main structure and the cover layer, the method for preparing the multilayer ceramic capacitor further includes:

[0037] Baking the main structure and the cover layer at a preset temperature;

[0038] Cooling the main structure and the cover layer;

[0039] At the preset temperature, pressing the main structure and the cover plate layer with a preset pressure;

[0040] Among them, the preset temperature range is: 50℃~200℃; the baking time range is: 0.5H~10H; the preset pressure range is: 0.1Kpa~1000Mpa; the pressing time range is: 1min~120min.

[0041] Optionally, in the method for preparing the multilayer ceramic capacitor, after cutting the main structure and the cover layer, the method for preparing the multilayer ceramic capacitor further includes:

[0042] performing a debinding sintering process on the grains;

[0043] Performing a grinding process on the crystal grains to round the corners of the crystal grains and to flatten the surface of the end surface inner electrode;

[0044] An end surface outer electrode is formed on the end surface inner electrode of each of the crystal grains by using an electroplating process.

[0045] Based on the same concept, the present invention also provides a multilayer ceramic capacitor, characterized in that it is prepared by using the preparation method of the multilayer ceramic capacitor, and the multilayer ceramic capacitor comprises:

[0046] A crystal grain; the crystal grain comprises a cover layer and a main structure located on the cover layer; wherein the main structure comprises multiple layers of electrode layers and dielectric layers formed alternately; a part of the electrode layers is etched to form an internal electrode and an end electrode; the internal electrodes of adjacent layers are separated by the dielectric layer; the end electrodes of adjacent layers are connected to serve as an end surface internal electrode;

[0047] End surface outer electrode; the end surface outer electrode covers the end surface inner electrode.

[0048] In summary, the present invention provides a multilayer ceramic capacitor and a preparation method thereof. Compared with the prior art, the preparation method adopts a photolithography process to replace the traditional silk screen printing method to form the electrode layer, thereby avoiding the graphic deformation caused by the silk screen printing process and ensuring the formation of a precise electrode pattern. In addition, the electrode layer and the dielectric layer are formed layer by layer by brushing slurry and baking, which effectively avoids the problem of interlayer displacement caused by the stacking process and is conducive to controlling the interlaced area between the upper and lower electrode layers. In addition, while photolithography is being performed on the electrode layer, the end electrode is also photolithographically formed, and the end electrodes of adjacent layers are connected, and after cutting, they can be directly used as end surface internal electrodes, without the need for a separate immersion process. Therefore, the preparation method not only improves the preparation efficiency, but also improves the conductivity of the internal and external electrodes, and optimizes the radio frequency characteristics of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Those skilled in the art will appreciate that the drawings are provided for a better understanding of the present invention, but do not constitute any limitation on the scope of the present invention.

[0050] Figure 1 It is a schematic diagram of the structure of a multilayer ceramic capacitor in the prior art.

[0051] Figure 2 4 is a flow chart of a method for preparing a multilayer ceramic capacitor in an embodiment of the present invention.

[0052] Figure 3 , 5 19 are schematic structural diagrams corresponding to the steps of preparing a multilayer ceramic capacitor in an embodiment of the present invention.

[0053] Figure 4 It is a flowchart of each sub-step in step 2 in an embodiment of the present invention.

[0054] And, in the attached drawings:

[0055] 100 - electrode layer; 101 - dielectric layer; 102 - end surface inner electrode layer; 103 - nickel layer; 104 - tin layer;

[0056] 20-crystal grain; 200-cover plate layer; 201-electrode layer; 201a-inner electrode; 201b-terminal electrode; 201b'-top terminal electrode; 202-dielectric layer;

[0057] 21-first metal layer; 22-second metal layer;

[0058] S-cutting road; M1-first light mask; M2-second light mask; M3-third light mask; M4-fourth light mask. DETAILED DESCRIPTION

[0059] In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different proportions are used. It should also be understood that, unless otherwise specified or indicated, the terms "first", "second", "third", etc. in the specification are only used to distinguish between the various components, elements, steps, etc. in the specification, and are not used to represent the logical relationship or sequential relationship between the various components, elements, steps, etc.

[0060] Also, in this specification, the X-axis, Y-axis and Z-axis directions are three directions perpendicular to each other in a three-dimensional space, and the vertical direction refers to the Z-axis direction, and the horizontal direction refers to the X-axis and / or Y-axis direction.

[0061] See also Figure 2 , this embodiment provides a method for preparing a multilayer ceramic capacitor, comprising:

[0062] Step 1 S10: providing a cover layer;

[0063] Step 2 S20: forming a main structure on the cover layer; the main structure comprises multiple layers of electrode layers and dielectric layers formed alternately; wherein, some layers of the electrode layers are etched to form internal electrodes and terminal electrodes; adjacent layers of the internal electrodes are separated by the dielectric layer; adjacent layers of the terminal electrodes are connected and are at least located on the cutting path of the main structure;

[0064] Step three S30: cutting the main structure and the cover layer along the cutting path to separate them into a plurality of crystal grains; and each of the terminal electrodes exposed on the side and top of the crystal grain constitutes an end surface inner electrode of the crystal grain;

[0065] Step 4 S40: forming an end surface outer electrode on the end surface inner electrode of each of the crystal grains.

[0066] Based on this, the method for preparing the multilayer ceramic capacitor provided in this embodiment not only improves the preparation efficiency, but also improves the conductivity of the internal and external electrodes and optimizes the radio frequency characteristics of the device.

[0067] The following is combined with Figures 2 to 19 , specifically describe the method for preparing the multilayer ceramic capacitor provided in this embodiment.

[0068] Step 1 S10: Please refer to Figure 3 , providing a cover layer 200.

[0069] The cover layer 200 is an insulating substrate, and its preparation material can be silicon, silicon dioxide, lithium niobate, barium titanate and other materials as the main material or doped materials. In the preparation process, a layer of wet ink photosensitive ceramic slurry with a thickness of 0.1 micron to 100 microns can be formed on the separated substrate by coating or screen printing, and then the cover layer 200 is formed after light curing and baking.

[0070] Step 2 S20: Please refer to Figures 4 to 15 , a main structure is formed on the cover layer 200; the main structure includes multiple layers of electrode layers 201 and dielectric layers 202 formed alternately; wherein, some layers of the electrode layers 201 are etched to form internal electrodes 201a and end electrodes 201b; adjacent layers of the internal electrodes 201a are separated by the dielectric layer 202; adjacent layers of the end electrodes 201b are connected and are at least located on the cutting path S of the main structure.

[0071] It should be noted that the working principle of the capacitor is to use the capacitance effect of the medium to store charge. When a voltage is applied between two electrodes, an electric field will be formed in the medium, and the charge between the two poles of the capacitor will be stored between the two electrodes and the medium respectively. When the voltage disappears, the capacitor will continue to hold the charge. The multilayer ceramic capacitor is based on this working principle, forming a multilayer interlaced electrode layer 201 and the dielectric layer 202, so as to have the advantages of large capacitance value and high stability.

[0072] Specifically, the step 2 S20 includes:

[0073] Sub-step 1 S201: Please refer to Figure 5 , forming an electrode layer 201 , wherein the electrode layer 201 covers the surface of the cover layer 200 .

[0074] The electrode layer 201 is in the form of a fluid metal or metal alloy slurry before sintering, preferably a wet ink photosensitive electrode slurry. That is, the material of the electrode layer 201 has good photosensitivity, so that a preset electrode pattern can be formed by a photolithography process. Based on this, in the process of preparing the electrode layer 201, a layer of wet ink photosensitive electrode slurry with a thickness of 0.1 micron to 10 microns is first screen-printed on the cured cover layer 200. Then, the electrode layer 201 is formed by a low-temperature baking process in a protective atmosphere.

[0075] Sub-step 2 S202: Please refer to Figure 6 and Figure 7 , the electrode layer 201 is etched by a photolithography process to form a patterned electrode layer 201; wherein the patterned electrode layer 201 includes the inner electrode 201a and the terminal electrode 201b.

[0076] Since the electrode layer 201 is a photosensitive material, a preset electrode pattern can be directly formed in a photolithography process. Exemplarily, the electrode layer 201 is a positive material; that is, the electrode layer 201 exposed to light will dissolve. Figure 6 As shown, part of the electrode layer 201 is dissolved by light irradiation, exposing the cover layer 200 located at the bottom layer; the remaining part of the electrode layer 201 is retained under the blocking of the first mask M1, thereby forming a patterned electrode layer 201. In other examples, the electrode layer 201 may also be a positive material. Preferably, in the photolithography development process, the pH value of the exposure developer used is >6; and the ion concentration range of the developer is: 0.1% to 30%. And, the material of the inner electrode 201a includes but is not limited to a metal mixed with one or more of Ag, Cu, Ni, Mo, Wu, and Ti; the material of the end electrode 201b includes but is not limited to a metal mixed with one or more of Cu, Ag, Ni, and Sn. Exemplarily, in this embodiment, the material of the inner electrode 201a and the end electrode 201b is the same, both including Cu.

[0077] Furthermore, the patterned electrode layer 201 includes the inner electrode 201a and the terminal electrode 201b. It can be understood that the inner electrode 201a is located inside the main structure and is used as an internal electrode to conduct charges. The terminal electrode 201b is located on part of the side edge of the main structure and part of the cutting path S and is used as a connection interface between the inner electrode 201a and the external circuit. Therefore, the inner electrode 201a in the patterned electrode layer 201 needs to be connected to a corresponding terminal electrode 201b. Figure 6 and Figure 7 As shown, in the same patterned electrode layer 201, the end electrodes 201b are arranged on opposite sides of the inner electrode 201a, and one side of the inner electrode 201a is connected to the adjacent end electrode 201b, and the other side is spaced from the adjacent end electrode 201b, so as to ensure that the inner electrode 201a can be electrically connected to one of the end electrodes 201b. Preferably, the connected inner electrode 201a and the end electrode 201b are integrally formed, which has a good conduction effect.

[0078] Furthermore, based on the structure of the multilayer ceramic capacitor, which has two opposite electrical connection terminals for connecting to an external circuit, the terminal electrode 201b does not need to be provided on part of the cutting path S, and the terminal electrode 201b only needs to be formed on the cutting path S used to prepare the electrical connection terminal. Figure 7In the structure shown, the position of the cutting line S in the Y-axis direction is used as the electrical connection end of the capacitor in the future, and the terminal electrode 201b is formed. However, the position of the cutting line S in the X-axis direction is not used as the electrical connection end in the future, so there is no need to form the terminal electrode 201b. In order to protect the inner electrode 201a, the electrode material on the cutting line S area corresponding to the electrical connection end needs to be photoetched away so that the side of the inner electrode 201a is wrapped by the dielectric layer 202 formed in the future.

[0079] As can be seen from the above, the preparation method provided in this embodiment uses photolithography to replace the traditional screen printing method to form the patterned electrode layer 201, avoiding the pattern deformation caused by the screen printing process, thereby ensuring that the patterned electrode layer 201 has precise morphological dimensions. In addition, the end electrode 201b formed simultaneously by the photolithography process is used as a connection interface between the internal and external electrodes, and there is no need to use a separate immersion process to form the end surface internal electrode. Not only does it improve the preparation efficiency, but it can also improve the conduction performance of the internal and external electrodes and optimize their radio frequency characteristics.

[0080] Sub-step 3 S203: Please refer to Figure 8 , forming a dielectric layer 202 , wherein the dielectric layer 202 covers the patterned electrode layer 201 .

[0081] The dielectric layer 202 is the ceramic dielectric in the multilayer ceramic capacitor, which is used to store charge. Preferably, the material of the dielectric layer 202 is the same as that of the cover layer 200, both of which are insulating materials and have photosensitivity. Therefore, in the process of preparing the dielectric layer 202, a layer of wet ink photosensitive ceramic slurry with a thickness of 0.1 microns to 100 microns is coated or screen-printed on the surface of the patterned electrode layer 201, and the dielectric layer 202 is formed after light curing and baking. And based on the fluidity of the slurry of the dielectric layer 202, the dielectric layer 202 will fill and cover each exposed surface of the patterned electrode layer 201. Figure 8 As shown, the dielectric layer 202 is attached to the surface of the electrode layer 201 and the surface of a portion of the first cover plate 200 exposed by photolithography.

[0082] Sub-step 4 S204: Please refer to Fig. 9 and Fig.10 , the dielectric layer 202 is etched by a photolithography process to form a patterned dielectric layer 202; wherein the patterned dielectric layer 202 exposes the terminal electrode 201b.

[0083] As can be seen from the above, the end electrode 201b formed by photolithography is used as an end surface inner electrode, that is, a connection interface between inner and outer electrodes. Therefore, each electrode layer 201 needs to be connected in sequence to form a connected end surface inner electrode.

[0084] Based on this, in order to achieve the connection between the upper and lower adjacent end electrodes 201b, it is necessary to open up the dielectric layer 202 between the corresponding end electrodes 201b in the two electrode layers 201. Fig. 9 and Fig.10 As shown, the dielectric layer 202 provided in this embodiment is photosensitive. For example, if the dielectric layer 202 is a positive material, the portion of the dielectric layer 202 exposed under light irradiation will dissolve, and the portion of the dielectric layer 202 blocked by the second mask M2 will be retained, thereby forming a patterned dielectric layer 202. Among them, the patterned dielectric layer 202 needs to expose all the end electrodes 201b located in the lower layer thereof, so that the end electrodes 201b located thereon can be connected accordingly. In other examples, the dielectric layer 202 may also be a negative material. Preferably, in the photolithography development process, the pH value of the exposure developer used is >6; and the ion concentration range of the developer is: 0.1% to 30%.

[0085] Sub-step 5 S205: Please refer to Fig.11 , forming an electrode layer 201, wherein the electrode layer 201 covers the patterned dielectric layer 202 and is connected to the exposed terminal electrode 201b.

[0086] The preparation method of the electrode layer 201 is the same as the preparation method in the sub-step 1 S201, and will not be described in detail in this embodiment. Since the slurry for preparing the electrode layer 201 has fluidity, during the formation process, the slurry of the electrode layer 201 will cover the patterned dielectric layer 202 and connect with the end electrode 201b in the next layer of the electrode layer 201 exposed by the patterned dielectric layer 202, that is, the through connection of the upper and lower adjacent end electrodes 201b is achieved.

[0087] Sub-step 6 S206: Please refer to Fig.12 and Fig.13 , repeat the sub-step 2 S202 and the step 5 S205 until the preparation of the preset number of electrode layers 201 and the dielectric layer 202 is completed.

[0088] Since the multilayer ceramic capacitor needs to be provided with multiple layers of staggered electrode layers 201 and dielectric layers 202, and the overlapping area of ​​the two adjacent electrode layers 201 directly affects the capacitance of the capacitor. Therefore, after executing the sub-step five S205, the electrode layer 201 located at the top layer is patterned by continuing to use the photolithography process. Among them, the pattern required to be formed by the electrode layer 201 in sub-step five S205 is not consistent with the pattern formed by the electrode layer 201 in sub-step two S202. That is, in the process of preparing the two adjacent patterned electrode layers 201, different masks are used to lithography the corresponding electrode layers 201, so that the two vertically adjacent layers of the inner electrodes 201a are respectively connected to the end electrodes 201b on different sides.

[0089] Please compare for details. Figure 6 and Fig.12 , the opening position of the first mask M1 used in sub-step 2 S202 is close to the central area, while the opening position of the fourth mask M4 used in sub-step 5 S205 is close to the edge area. Therefore, the dielectric layer 202 exposed by the patterned electrode layer 201 on the upper surface of the dielectric layer 202 is located at the side of the entire top surface, while the dielectric layer 202 exposed by the patterned electrode layer 201 on the lower surface of the dielectric layer 202 is close to the center of the entire bottom surface. Of course, Figure 6 and Fig.12 This is only an example. Depending on the layout distribution, the photolithography pattern may be different, but after cutting to form a single crystal grain, the inner electrodes 201a of each layer in each crystal grain are staggered and connected to the end electrodes 201b on both sides. That is, two adjacent inner electrodes 201a are connected to the end electrodes 201b located on different sides. However, the end electrodes 201b located on the same side are still connected in sequence to ensure that the corresponding inner electrodes 201a can be fully connected.

[0090] Further, in the formation Fig.12 After the patterned electrode layer 201 is formed, a dielectric layer 202 may be formed on the patterned electrode layer 201 located on the top layer, and the dielectric layer 202 may be photoetched to expose the terminal electrode 201b of the lower layer. Subsequently, the electrode layer 201 may be formed on the patterned dielectric layer 202, and the dielectric layer 202 may be photoetched to expose the terminal electrode 201b of the lower layer. Figure 6 The first mask M1 is used to photolithography the electrode layer 201. This is repeated to form Fig.13The main structure shown. The main structure includes multiple overlapping electrode layers 201 and dielectric layers 202. The specific number of electrode layers 201 and dielectric layers 202 is not limited in this embodiment and can be determined according to the capacity of the capacitor. Among them, the inner electrodes 201a in each electrode layer 201 are separated by the dielectric layer 202, and the end electrodes 201b in each electrode layer 201 are connected to the end electrodes 201b of the corresponding adjacent layer.

[0091] And from the above, it can be known that each layer of electrode layer 201 and dielectric layer 202 stacked in the main structure is patterned by photolithography. Compared with the pattern processing process using screen printing, the preparation method provided in this embodiment effectively ensures the accuracy of the pattern and avoids pattern deformation. In addition, this embodiment forms the electrode layer 201 and the dielectric layer 202 layer by layer by brushing slurry and baking, which avoids the problem of interlayer displacement caused by the stacking process and is conducive to controlling the interlaced area between the upper and lower electrode layers 201. In addition, while photolithography the electrode layer 201, the end electrode 201b is also photolithographically formed, and the adjacent layers of the end electrodes 201b are connected to serve as the end surface internal electrode, so there is no need to perform a separate immersion process. Therefore, the preparation method provided in this embodiment not only improves the preparation efficiency, but also improves the conductivity of the internal and external electrodes, and optimizes the radio frequency characteristics of the device.

[0092] Sub-step 7 S207: Please refer to Fig.14 The electrode layer 201 at the top layer is etched by photolithography to form a top terminal electrode 201b'; the top terminal electrode 201b' is connected to the terminal electrode 201b of the adjacent next layer, and the top terminal electrode 201b' extends along the surface of the dielectric layer 202 for a preset distance.

[0093] like Fig.14 As shown, after all the electrode layers 201 are prepared, the electrode layer 201 located at the top layer does not need to be photolithographically formed into the inner electrode 201a, and only the end electrode 201b needs to be etched out to facilitate electrode extraction. And because the end surface inner electrode in the existing process is based on the immersion process and only covers the side wall of the capacitor, the electrical connection effect of the existing end surface inner electrode is not good, so this embodiment uses the photolithography process to form the end electrode 201b synchronously as the end surface inner electrode, which effectively improves the connection effect with the internal and external electrodes.

[0094] In order to further improve the connection effect of the internal and external electrodes, in this embodiment, when the electrode layer 201 located at the top layer is photoetched, the end electrode 201b is extended to one side close to the surface of the dielectric layer 202 to form the top end electrode 201b'. In other words, the top end electrode 201b' is connected to the adjacent end electrode 201b of the next layer in the plane where the Y-axis-Z-axis direction is located, and extends a preset distance along the plane where the X-axis-Y-axis direction is located, which is conducive to increasing the contact area with the end surface external electrode, thereby improving the connection effect of the internal and external electrodes. Therefore, it can be adopted Fig.14 The fourth photomask M4 shown is used as a mask to photolithography the electrode layer 201 at the top layer to remove part of the electrode layer 201 located in the middle area between the cutting line S and / or the side of the main structure, and retain part of the electrode layer 201 located on the cutting line S and the side of the main structure.

[0095] Sub-step 8 S208: Please refer to Fig.15 , forming a layer of the dielectric layer 202; the dielectric layer 202 covers the top terminal electrode 201b' and the adjacent next layer of the dielectric layer 202.

[0096] It is understandable that the material of the top terminal electrode 201b' is metal, such as copper, which is easily oxidized. Therefore, before performing subsequent processes, a dielectric layer 202 needs to be formed on the surface of the top terminal electrode 201b' to wrap the top terminal electrode 201b' to prevent it from being oxidized by contact with air and affecting conductivity.

[0097] Furthermore, after forming the dielectric layer 202 located at the top, the preparation of the main structure is completed. The formed main structure and the cover layer 200 are green embryo structures. In order to improve the bonding tightness of each membrane layer in the green embryo structure, the green embryo structure needs to be placed at a preset temperature and baked for a period of time. Then, take out the green embryo structure and wait for it to cool down, and then place it in a high-pressure and high-temperature environment for pressing for 1min to 120min to achieve full compaction of each membrane layer in the green embryo structure. Optionally, the preset temperature range is: 50℃~200℃; the baking time range is: 0.5H~10H; the preset pressure range of the high-pressure environment is: 0.1Kpa~1000Mpa; and the temperature range of the high-temperature environment during pressing can be the same as the baking temperature range: 50℃~200℃.

[0098] Step 3 S30: Please refer to Figures 16 to 18 The main structure and the cover layer 200 are cut along the cutting path S to be divided into a plurality of crystal grains 20 ; and each of the terminal electrodes 201 b exposed on the side and top of the crystal grain 20 constitutes an end surface inner electrode of the crystal grain 20 .

[0099] Since the preparation process of the green structure is to simultaneously prepare the cover layer 200, the inner electrode 201a, the terminal electrode 201b and the dielectric layer 202 of the plurality of multilayer ceramic capacitors, it is necessary to cut out the structure of a single multilayer ceramic capacitor along the preset cutting path S. Fig.16 and Fig.17 As shown, the green structure is cut along the cutting line S by using a laser cutting process to form a plurality of crystal grains 20. Each of the crystal grains 20 can form a multilayer ceramic capacitor.

[0100] It should be noted that, during the cutting process, the terminal electrode 201b located in the cutting path S will be cut into two along the plane where the Z-axis-Y-axis is located, so that the side walls of the two adjacent grains 20 are attached with the terminal electrode 201b to serve as the end surface internal electrode on the corresponding grain 20. In addition, during the cutting process, the dielectric layer 202 located on the top layer will also be cut off along the plane where the X-axis-Y-axis is located to expose the top layer terminal electrode 201b'. Based on this, the terminal electrodes 201b coated on the two opposite side walls of each of the grains 20 and the top layer terminal electrode 201b' located on the same top surface constitute the two end surface internal electrodes of the grain 20. Fig.17 As shown, the end face internal electrode covers the side wall and part of the top surface of the grain 20 and is in an "L" shape. Compared with the prior art in which a layer of metal is impregnated on the side wall of each grain 20 as the end face internal electrode after being cut into grains 20, the preparation method provided in this embodiment is to simultaneously form the internal electrode 201a and the end electrode 201b through a photolithography process. Not only is the preparation efficiency high and the connection effect with the internal electrode 201a is good, but it is also designed to be in an "L" shape, which can increase the connection area with the end face external electrode, improve the connectivity effect of the internal and external electrodes, and thus optimize the RF characteristics of the device.

[0101] like Fig.18 As shown, the size of the end surface inner electrode after cutting satisfies the following formula:

[0102] Z1≤H3; Y1≤W3; X2<50%L3; Y2≤W3;

[0103] Among them, Z1 refers to the height of the end surface inner electrode located on the side of the grain 20; Y1 refers to the width of the end surface inner electrode located on the side of the grain 20; X2 refers to the length of the top terminal electrode 201b'; Y2 refers to the width of the top terminal electrode 201b'; H3 refers to the height of the grain 20; W3 refers to the width of the grain 20; L3 refers to the length of the grain 20.

[0104] Furthermore, after the cutting process is completed, it is necessary to perform a debinding and sintering process on each of the crystal grains 20. That is, each of the crystal grains 20 is subjected to a high-temperature heat treatment to remove organic matter such as adhesives, so as to avoid problems such as delamination and cracking caused by the rapid volatilization of organic matter during the subsequent sintering process. And after debinding, each of the crystal grains 20 is sintered at a high temperature to improve the mechanical strength and electrical performance of the device. In addition, after the crystal grains 20 are cooled, the crystal grains 20 can be ground to round the corners of the crystal grains 20 and to flatten the surface of the end surface inner electrode, thereby optimizing the performance and reliability of the device.

[0105] Step 4 S40: Please refer to Fig.19 , an end surface outer electrode is formed on the end surface inner electrode of each of the crystal grains 20.

[0106] Since the end surface inner electrode exposed by the crystal grain 20 is easily oxidized in the air, after grinding, it is necessary to plate the first metal layer 21 on the end surface outer electrode by electroplating or other processes to wrap the end surface inner electrode to prevent it from affecting the electrical connection due to oxidation. In addition, in order to facilitate connection with an external circuit, a second metal layer 22 is also required to be plated on the outside of the first metal layer 21 for welding. Preferably, the material of the first metal layer 21 includes Ni; the material of the second metal layer 22 includes Sn, and the first metal layer 21 and the second metal layer 22 constitute the end surface outer electrode.

[0107] Please continue reading Fig.19 Based on the same concept, this embodiment also provides a multilayer ceramic capacitor. The multilayer ceramic capacitor is prepared by the above-mentioned preparation method of the multilayer ceramic capacitor, and the multilayer ceramic capacitor includes: a grain 20 and an end surface external electrode. The grain 20 is the power storage body of the capacitor, and the end surface external electrode is used for electrical connection, so that the capacitor can be connected to an external circuit. Specifically, the grain 20 includes a cover layer 200 and a main structure located on the cover layer 200. Among them, the main structure includes multiple layers of alternately formed electrode layers 201 and dielectric layers 202. Part of the electrode layer 201 is etched to form an internal electrode 201a and an end electrode 201b. The adjacent layers of the internal electrodes 201a are separated by the dielectric layer 202; and the adjacent layers of the end electrodes 201b are connected to serve as the end surface internal electrodes. And, the end surface external electrode covers the end surface internal electrode.

[0108] In summary, the present embodiment provides a multilayer ceramic capacitor and a preparation method thereof. Among them, the preparation method adopts a photolithography process to replace the traditional screen printing method to form the electrode layer 201, avoiding the graphic deformation caused by the screen printing process and ensuring the formation of a precise electrode pattern. In addition, the electrode layer 201 and the dielectric layer 202 are formed layer by layer by brushing slurry and baking, which effectively avoids the problem of interlayer displacement caused by the stacking process and is conducive to controlling the interlaced area between the upper and lower electrode layers 201. In addition, while photolithography the electrode layer 201, the end electrode 201b is also photolithographically formed, and the adjacent layers of the end electrodes 201b are connected, and after cutting, they can be directly used as end surface inner electrodes, without the need to perform a separate dipping process. Further, the end surface inner electrode is "L" shaped, not only covering the side of the grain 20 but also covering part of its top surface, which is conducive to increasing the contact with the end surface outer electrode and improving the conductive effect. Therefore, the preparation method not only improves the preparation efficiency, but also improves the conductivity of the internal and external electrodes, and optimizes the radio frequency characteristics of the device.

[0109] In addition, it should be recognized that although the present invention has been disclosed as a preferred embodiment, the above embodiment is not intended to limit the present invention. For any technician familiar with the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiment according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still belongs to the scope of protection of the technical solution of the present invention.

Claims

1. A method for preparing a multilayer ceramic capacitor, characterized in that: include: providing a cover layer; A main structure is formed on the cover layer; the main structure comprises multiple layers of alternately formed electrode layers and dielectric layers; wherein some layers of the electrode layers are etched to form internal electrodes and terminal electrodes; adjacent layers of the internal electrodes are separated by the dielectric layer; adjacent layers of the terminal electrodes are connected and are at least located on the cutting path of the main structure; The main structure and the cover plate layer are cut along the cutting path to be divided into a plurality of crystal grains; and each of the terminal electrodes exposed on the side and top of the crystal grain constitutes an end surface inner electrode of the crystal grain; An end surface outer electrode is formed on the end surface inner electrode of each of the crystal grains.

2. The method for preparing a multilayer ceramic capacitor according to claim 1, characterized in that: The process of forming the main structure on the cover layer includes: Step 1: forming an electrode layer, wherein the electrode layer covers the surface of the cover layer; Step 2: etching the electrode layer using a photolithography process to form a patterned electrode layer; wherein the patterned electrode layer includes the inner electrode and the terminal electrode; Step 3: forming a dielectric layer, wherein the dielectric layer covers the patterned electrode layer; Step 4: etching the dielectric layer using a photolithography process to form a patterned dielectric layer; wherein the patterned dielectric layer exposes the terminal electrode; Step 5: forming an electrode layer, wherein the electrode layer covers the patterned dielectric layer and is connected to the exposed terminal electrode; Step 6: Repeat step 2 and step 5 until the preparation of the preset number of electrode layers and dielectric layers is completed; Step 7: etching the electrode layer at the top layer by photolithography to form a top terminal electrode; the top terminal electrode is connected to the terminal electrode of the next adjacent layer, and the top terminal electrode also extends a preset distance along the surface of the dielectric layer; Step eight: forming a dielectric layer; the dielectric layer covers the top terminal electrode and the next adjacent dielectric layer.

3. The method for preparing a multilayer ceramic capacitor according to claim 2, characterized in that: In the same patterned electrode layer, the terminal electrodes are disposed on opposite sides of the inner electrode, and one side of the inner electrode is connected to the adjacent terminal electrode, and the other side is spaced from the adjacent terminal electrode.

4. The method for preparing a multilayer ceramic capacitor according to claim 3, characterized in that: In the process of preparing two adjacent patterned electrode layers, different masks are used to photoetch the corresponding electrode layers, so that the two vertically adjacent internal electrodes are respectively connected to the terminal electrodes on different sides.

5. The method for preparing a multilayer ceramic capacitor according to claim 2, characterized in that: The dielectric layer and the electrode layer are both photosensitized; and, during the photolithography process, the pH value of the exposure developer used is greater than 6; and the ion concentration range of the developer is: 0.1% to 30%.

6. The method for preparing a multilayer ceramic capacitor according to claim 2, characterized in that: The process of cutting the main structure and the cover layer along the cutting path to divide the main structure and the cover layer into a plurality of the die includes: Cutting the main structure and the cover plate layer by laser, and exposing the terminal electrode and the top terminal electrode located on the side of the main structure to serve as the end surface inner electrode of the grain; Wherein, the end surface inner electrode is in an "L" shape and covers two opposite sides of the grain.

7. The method for preparing a multilayer ceramic capacitor according to claim 2, characterized in that: The thickness range of the cover plate layer and the dielectric layer is 0.1 micrometer to 100 micrometers; the thickness range of the electrode layer is 0.1 micrometer to 10 micrometers; and the size of the electrode inside the end surface satisfies the following formula: Z1≤H3; Y1≤W3; X2<50%L3; Y2≤W3; Wherein, Z1 refers to the height of the electrode inside the end surface located on the side of the grain; Y1 refers to the width of the electrode on the end surface of the part located on the side of the grain; X2 refers to the length of the top terminal electrode; Y2 refers to the width of the top terminal electrode; H3 refers to the height of the grain; W3 refers to the width of the grain; L3 refers to the length of the grain.

8. The method for preparing a multilayer ceramic capacitor according to claim 1, wherein: After forming the main structure on the cover layer and before cutting the main structure and the cover layer, the method for preparing the multilayer ceramic capacitor further includes: Baking the main structure and the cover layer at a preset temperature; Cooling the main structure and the cover layer; At the preset temperature, pressing the main structure and the cover plate layer with a preset pressure; Among them, the preset temperature range is: 50℃~200℃; the baking time range is: 0.5H~10H; the preset pressure range is: 0.1Kpa~1000Mpa; the pressing time range is: 1min~120min.

9. The method for preparing a multilayer ceramic capacitor according to claim 1, characterized in that: After cutting the main structure and the cover layer, the method for preparing the multilayer ceramic capacitor further includes: performing a debinding sintering process on the grains; Performing a grinding process on the crystal grains to round the corners of the crystal grains and to flatten the surface of the end surface inner electrode; An end surface outer electrode is formed on the end surface inner electrode of each of the crystal grains by using an electroplating process.

10. A multilayer ceramic capacitor, characterized in that: The multilayer ceramic capacitor is prepared by the preparation method of any one of claims 1 to 9, and the multilayer ceramic capacitor comprises: A crystal grain; the crystal grain comprises a cover layer and a main structure located on the cover layer; wherein the main structure comprises multiple layers of electrode layers and dielectric layers formed alternately; a part of the electrode layers is etched to form an internal electrode and an end electrode; the internal electrodes of adjacent layers are separated by the dielectric layer; the end electrodes of adjacent layers are connected to serve as an end surface internal electrode; End surface outer electrode; the end surface outer electrode covers the end surface inner electrode.

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