Semiconductor structure and forming method thereof

Abstract

A method of forming a semiconductor structure includes performing a plasma treatment on a first wafer, performing a treatment process on the first wafer, where the treatment process makes the first wafer more hydrophobic than before the treatment process; pre-bonding the first wafer to a second wafer by wafer-to-wafer bonding; and performing an annealing process to bond the first wafer to the second wafer. The embodiment of the invention also provides a semiconductor structure.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to semiconductor structures and methods of forming the same. Background Art

[0002] Fusion bonding and hybrid bonding are common bonding schemes for bonding two package components (such as wafers and / or dies) to each other. In the bonding process, the package components are first bonded by pre-bonding at a lower temperature, and then an annealing process is performed at a higher temperature to bond the package components together. Summary of the invention

[0003] Some embodiments of the present disclosure provide a method for forming a semiconductor structure, the method comprising: performing plasma treatment on a first wafer; performing a first treatment process on the first wafer, wherein the first treatment process makes the first wafer more hydrophobic than before the first treatment process; pre-bonding the first wafer to a second wafer by wafer-to-wafer bonding; and performing an annealing process to bond the first wafer to the second wafer.

[0004] Other embodiments of the present disclosure provide a semiconductor structure comprising: a first packaging component including a first dielectric layer; and a second packaging component including a second dielectric layer bonded to the first dielectric layer, wherein the first dielectric layer and the second dielectric layer include an interface region, the interface region including: a first portion of the first dielectric layer; and a second portion of the second dielectric layer, wherein the interface region includes a first carbon concentration, and wherein the first portion of the first dielectric layer and the second portion of the second dielectric layer form an interface, and the interface has a second carbon concentration higher than the first carbon concentration, and wherein the second carbon concentration is a peak carbon concentration.

[0005] Yet another embodiment of the present disclosure provides a semiconductor structure comprising: a first device die comprising a first silicon-containing dielectric layer; and a second device die comprising a second silicon-containing dielectric layer, the second silicon-containing dielectric layer being bonded to the first silicon-containing dielectric layer to form a bonding interface, wherein the first silicon-containing dielectric layer and the second silicon-containing dielectric layer comprise: carbon having a peak carbon concentration at the bonding interface, wherein the carbon concentration decreases in the interface region and in a direction pointing away from the bonding interface, and wherein the interface region comprises the bonding interface and portions of the first silicon-containing dielectric layer and the second silicon-containing dielectric layer; and nitrogen having a minimum concentration at the bonding interface, wherein the nitrogen concentration increases in the interface region and in a direction pointing away from the bonding interface. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, aspects of the present disclosure can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0007] Figures 1 to 6 A cross-sectional view is shown of an intermediate stage in the formation of a package including a bonding process, in accordance with some embodiments.

[0008] Figure 7 A bonding scheme including two bonding pads and a dielectric layer is shown in accordance with some embodiments.

[0009] Figure 8 , Fig. 9 and Fig.10 Peak concentrations of carbon, nitrogen, and oxygen at the bonding interface of different bonding layers according to some embodiments are shown.

[0010] Fig.11 A device wafer is shown bonded to a carrier wafer in accordance with some embodiments.

[0011] Fig.12 A carrier wafer is shown bonded to a reconstructed wafer in accordance with some embodiments.

[0012] Fig.13 A reconstructed wafer is shown bonded to a device wafer in accordance with some embodiments.

[0013] Fig.14 The bonding of two device wafers is shown in accordance with some embodiments.

[0014] Fig.15 The bonding of two reconstructed wafers is shown in accordance with some embodiments.

[0015] Fig.16 Processing of a wafer using hexamethyldisilazane (HMDS) is shown in accordance with some embodiments.

[0016] Fig.17 Treatment of a wafer using aminopropyltriethoxysilane (APTES) is shown in accordance with some embodiments.

[0017] Fig.18 Processing of a wafer using (3-mercaptopropyl)trimethoxysilane (MPTMS) is shown in accordance with some embodiments.

[0018] Figures 19 to 22 The pattern and location of processing regions in a wafer are shown according to some embodiments.

[0019] Fig.23 A process flow for forming a package according to some embodiments is shown. DETAILED DESCRIPTION

[0020] The following disclosure provides many different embodiments or examples for implementing the different components of the present application. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly in contact with each other, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the individual embodiments and / or configurations discussed.

[0021] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," and "upper" may be used herein to describe the relationship of one element or component to another element or component as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0022] A method of performing surface treatment on a wafer to prepare the wafer for bonding, and a structure resulting therefrom, are provided. According to some embodiments of the present disclosure, a surface treatment is performed on a wafer using chemicals, so that the surface of the wafer is modified from a hydrophilic surface to a hydrophobic surface. Because the bonding wave velocity on a wafer with a hydrophilic surface during pre-bonding is high, distortion may occur and the distortion is more severe. In an embodiment of the present disclosure, the treatment modifies the hydrophilic surface into a hydrophobic surface, and reduces the bonding wave velocity and distortion.

[0023] The embodiments discussed herein are intended to provide examples so that the subject matter of the present disclosure can be made or used, and those of ordinary skill in the art will readily appreciate the modifications that can be made while remaining within the intended scope of the different embodiments. Throughout the various views and illustrative embodiments, the same reference numerals are used to represent the same elements. Although the method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

[0024] Figures 1 to 6 A cross-sectional view is shown of an intermediate stage in forming a package having a processed surface according to some embodiments of the present disclosure. Fig.23 The corresponding process is also schematically reflected in the process flow shown.

[0025] Figure 1A cross-sectional view of wafer 20 is shown. According to some embodiments, wafer 20 is or includes a device wafer including active devices and possible passive devices, which are shown as integrated circuit devices 26. Wafer 20 may include a plurality of dies 20', and details of one of the dies 20' are shown. According to an optional embodiment, wafer 20 is a carrier wafer, which may include a silicon wafer (without metal components and active devices) and a bonding layer thereon.

[0026] According to an optional embodiment, wafer 20 is an interposer wafer that does not contain active devices and may or may not include passive devices. According to some other optional embodiments, wafer 20 is or includes a reconstructed wafer that includes device dies encapsulated therein, and the device dies are sealed in an encapsulant (such as a molding compound).

[0027] In the subsequent discussion, device wafer 20 will be used as an example. Embodiments may also be applied to other types of wafers as described above.

[0028] According to some embodiments, wafer 20 includes a semiconductor substrate 24 and features formed at a top surface of semiconductor substrate 24. Semiconductor substrate 24 may be formed of or include crystalline silicon, crystalline germanium, crystalline silicon germanium, carbon-doped silicon, III-V compound semiconductors, etc. Semiconductor substrate 24 may also be a bulk semiconductor substrate or a semiconductor-on-insulator (SOI) substrate.

[0029] According to some embodiments, wafer 20 includes integrated circuit devices 26 formed at a top surface of semiconductor substrate 24. According to some embodiments, integrated circuit devices 26 may include complementary metal oxide semiconductor (CMOS) transistors, resistors, capacitors, diodes, etc. Details of integrated circuit devices 26 are not shown herein.

[0030] Interconnect structure 28 is formed over semiconductor substrate 24. According to some embodiments, interconnect structure 28 includes a plurality of dielectric layers 30, and a plurality of conductive features 34 in dielectric layers 30. Dielectric layers 30 may include an interlayer dielectric (ILD) that fills spaces between gate stacks of transistors in integrated circuit device 26 (if formed). According to some embodiments, the ILD is formed of silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG), etc. The ILD may be formed using spin coating, flowable chemical vapor deposition (FCVD), chemical vapor deposition (CVD), etc.

[0031] Conductive component 34 may include metal lines and vias. When wafer 20 includes integrated circuit device 26, conductive component 34 may also be connected to integrated circuit device 26 (if formed). Metal lines located at the same level are collectively referred to as metal layers below. According to some embodiments, interconnect structure 28 includes multiple metal layers interconnected by vias. Metal lines and vias may be formed of copper, copper alloys, and / or other metals.

[0032] The interconnect structure 28 may also include a passivation layer located above the low-k dielectric layer, which may be formed of a non-low-k dielectric material. The passivation layer may be formed of undoped silicate glass (USG), silicon nitride, silicon oxide, etc., or a multilayer thereof, or the passivation layer may include undoped silicate glass (USG), silicon nitride, silicon oxide, etc., or a multilayer thereof. There may also be a metal pad (such as an aluminum-copper pad), a post-passivation interconnect (PPI), etc., which are referred to as conductive components.

[0033] According to some embodiments, a bonding pad 38 is formed at the top surface of the wafer 20. The bonding pad 38 may be formed by plating, and has a vertical and straight sidewall. According to an alternative embodiment in which fusion bonding is to be performed, the bonding pad 38 is not formed. Accordingly, the bonding pad 38 is shown as a dotted line to indicate that the bonding pad 38 may or may not be formed.

[0034] Further references Figure 1 , the bonding layer 42 is deposited above the interconnect structure 28. The top surface of the bonding layer 42 is coplanar with the top surface of the bonding pad 38. This is achieved by performing a chemical mechanical polishing (CMP) process during the formation of the bonding pad 38 when the bonding pad 38 is formed. When the bonding pad 38 is not formed, the CMP process may or may not be performed. According to some embodiments, the bonding layer 42 may be formed of a silicon-based dielectric material, which may include one or more of oxygen, carbon and nitrogen. For example, the bonding layer 42 may be formed of SiON, SiN, SiOCN, SiCN, SiOC, SiC, TiN, TiO, etc., or the bonding layer 42 may include SiON, SiN, SiOCN, SiCN, SiOC, SiC, TiN, TiO, etc. After the CMP process, the wafer 20 is cleaned using, for example, deionized (DI) water. The CMP process and the use of ID water to clean the wafer are also referred to as wet processes.

[0035] According to some embodiments, a plasma treatment process 44 may be performed on the top surface of the wafer 20. According to some embodiments, the plasma treatment process 44 is performed by generating plasma from a process gas and treating the top surface of the wafer 20 with the plasma. According to some embodiments, the process gas may include nitrogen (N2), oxygen (O2), argon, He, H2, NH3, or a combination thereof, such as a mixture of N2 and H2 (expressed as N2 / H2), H2 / He, N2 / He, etc. The treatment may be performed with or without applying a bias power. Through the plasma treatment process 44, dangling bonds are generated on the top surface of the wafer 20.

[0036] According to some embodiments, after the plasma treatment process 44 , the wafer 20 may be exposed to water / moisture, for example, through a rinsing process, so that dangling bonds of silicon atoms may form Si—OH bonds at the surface of the wafer 20 .

[0037] The wet process (including the CMP process) and the plasma treatment process 44 can make the top surface of the wafer 20 hydrophilic. In the subsequent pre-bonding process, when the hydrophilic surfaces of the two wafers contact each other, the respective bonding waves may have too high a propagation speed, thereby causing distortion. According to some embodiments, as Figure 1 As shown, a treatment process 46 is performed using chemicals to convert the hydrophilic surface into a hydrophobic surface. Fig.23 The corresponding process is shown as process 202 in the illustrated process flow 200 .

[0038] According to some embodiments, the treatment process 46 is performed using a chemical selected from hexamethyldisilazane (HMDS, with a linear molecular formula of ([(CH3)3Si]2NH), aminopropyltriethoxysilane (APTES, with a linear molecular formula of H2N(CH2)3Si(OC2H5)3), (3-mercaptopropyl)trimethoxysilane (MPTMS, with a linear molecular formula of HS(CH2)3Si(OCH3)3), etc. or a combination thereof. The circle 39 at the surface of the wafer 20 indicates that the treatment process 46 has been performed and indicates the functional groups of the treatment chemicals attached to the surface of the wafer 20.

[0039] Fig.16 20 is shown in accordance with some embodiments using HMDS to process an exemplary process of wafer 20. The wafers are represented as wafer 20 / 120 to indicate that both wafer 20 and wafer 120 ( Figure 2 ) at least one or two of them. In the following discussion, the processing of wafer 20 is used as an example. The surface of wafer 20 has OH groups, and the OH groups are bonded to bonding layer 42 ( Figure 1) in the wafer 20. Wafer 20 may be at room temperature, for example, in a range between about 18°C ​​and about 22°. Next, HMDS is directed to wafer 20, for example, in the form of hot vapor. The temperature of the hot vapor may be in a range between about 100°C and about 150°C. The duration of exposure of wafer 20 to the hot HMDS vapor may be in a range between about 5 seconds and about 600 seconds.

[0040] The wafer 20 can then be cooled, for example, by contacting the back side of the wafer 20 with a cold plate at room temperature. The cooling time can range between about 5 seconds and about 600 seconds. By exposure to hot HMDS vapor, the OH groups are destroyed and the functional groups Si-CH3 in the HMDS are attached to the Si-O bonds. The resulting wafer 20 includes silicon atoms bonded to CH3 groups. This creates a hydrophobic surface.

[0041] Fig.17 FIG. 2 shows an exemplary process of using APTES to process wafer 20 (or wafer 120) according to some embodiments. The surface of wafer 20 also has OH groups, which are bonded to bonding layer 42 ( Figure 1 ) in the wafer 20. The wafer 20 may be at room temperature, for example, in a range between about 18°C ​​and about 22°C. Next, hot APTES vapor is introduced to expose the wafer 20 to the APTES vapor. The hot vapor may be generated from a solution having ethanol and water, in which APTES is dissolved to generate the solution. The temperature of the vapor may be in a range between about 100°C and about 200°C. The duration of exposure of the wafer 20 to the hot vapor may be in a range between about 5 seconds and about 600 seconds.

[0042] The wafer 20 may then be cooled, for example, by contacting the back side of the wafer 20 with a cold plate at room temperature. The cooling time may be in a range between about 5 seconds and about 600 seconds. By exposure to the hot APTES vapor, the OH groups are destroyed and the functional groups NH2 are attached to the Si-O bonds, such as Fig.17 This creates a hydrophobic surface.

[0043] According to an optional embodiment in which the processing chemical includes APTES, the following process may be performed. First, the wafer 20 may have its back side contacted with a hot plate to remove water (if any) from its surface by evaporation. The hot plate may have a temperature in a range between about 100° C. to about 150° C. The duration may be in a range between about 5 seconds to about 600 seconds.

[0044] Then, the wafer 20 can be placed in a solution including APTES dissolved in a solvent. The solvent can include anhydrous toluene, methanol, ethanol, hexane, deionized water, etc., or a combination thereof. The solution can be at a temperature in the range of about 20°C to about 100°. The duration of placing the wafer 20 in the solution is in the range of about 5 seconds to about 600 seconds. Then, for example, the wafer 20 is rinsed with a solvent including toluene, methanol, ethanol, hexane, deionized water, etc., so that the APTES on the wafer 20 is removed.

[0045] Fig.18 FIG. 2 shows an exemplary process of using MPTMS to process wafer 20 according to some embodiments. The surface of wafer 20 has OH groups, and the OH groups are bonded to bonding layer 42 ( Figure 1 ) in the wafer. First, the wafer 20 may have its back side contacted with a hot plate to remove water (if any) from its surface by evaporation. The hot plate may have a temperature in the range of about 100° C. to about 150° C. The duration may be in the range of about 5 seconds to about 600 seconds.

[0046] Then, the wafer 20 can be placed in a solution including MPTMS dissolved in a solvent. The solvent can include anhydrous toluene, methanol, ethanol, hexane, deionized water, etc., or a combination thereof. The solution can be at a temperature in the range of about 20°C to about 100°. The duration of placing the wafer 20 in the solution is in the range of about 5 seconds to about 600 seconds. The wafer 20 is then rinsed, for example, using a solvent including toluene, methanol, ethanol, hexane, deionized water, etc., so that the MPTMS on the wafer 20 is removed.

[0047] Return to reference Figure 1 , the treatment process 46 may be performed on the entire top surface of the wafer 20 and / or on a selected area of ​​the wafer 20. When the treatment process is performed on the entire wafer 20, the treatment process has the function of slowing down the propagation of the bonding wave on the entire surface of the wafer 20. When the treatment process is performed on a selected (but not all) portion of the wafer 20, the treatment process 46 has the function of slowing down the bonding wave speed of the selected portion of the wafer 20 (in which the bonding wave speed is higher than the untreated portion of the wafer 20). The resulting effect may be that the bonding wave may propagate from the center of the wafer 20 to the edge of the wafer at a uniform speed, and the bonding wave at any moment may be as close to a perfect circle as possible.

[0048] Figures 19 to 22 Some wafers and processed portions (processed by process 46) according to some embodiments are shown. Fig.19 As shown, the entire wafer 20 / 120 (in Figure 2 In the process shown, the processing wafer 120 is fully processed by the processing process 46. Fig. 20 In the embodiment, some strip portions 51 of the carrier wafer 20 / 120 are processed by the processing process 46, while the remaining portions are not processed. The overlapped regions of the processed strip portions 51 having a length direction in the X direction may overlap with the processed strip portions 51 having a length direction in the Y direction. Fig.21 An embodiment is shown in which a circular portion 51 (or a plurality of circular regions) is treated by the treatment process 46, while the remaining portions are not treated. Fig. 22 An embodiment is shown in which a selected and isolated portion 51 is treated by the treatment process 46, while the remaining portions are not treated.

[0049] According to some embodiments, the selective treatment process 46 is performed by forming a mask (such as a photoresist) on the wafer 20 / 120, patterning the mask to expose portions of the surface to be processed while leaving other portions covered by the mask. The treatment process 46 is then performed as described above. The mask may then be removed.

[0050] According to some embodiments, when HMDS is used, the wafer may be fully processed (e.g. Fig.19 as shown) or local treatment (as Figure 20 to Figure 22 When APTES and MPTMS are used, global processing is performed instead of local processing.

[0051] Figure 2 The formation and processing of wafer 120 according to some embodiments are shown. Wafer 120 can also be selected from a device wafer, a reconstructed wafer, an interposer wafer, a carrier, etc. In the illustrated example, a device wafer is shown as an example. According to some embodiments, wafer 120 has a structure similar to wafer 20. The structure and materials of the components in wafer 120 can be found with reference to the same components in wafer 20, where the same components in wafer 120 are marked by adding the number "1" in front of the reference number of the corresponding component in wafer 20. For example, the substrate in wafer 20 is marked as 24, and accordingly, the substrate in wafer 120 is marked as 124.

[0052] According to some embodiments, wafer 120 includes through-vias 125 (also referred to as through-silicon vias (TSVs) or through-semiconductor vias (also referred to as TSVs)) extending from a top surface of semiconductor substrate 124 to an intermediate level between the top and bottom surfaces of semiconductor substrate 124 .

[0053] Wafer 120 may include device die 120' and include integrated circuit devices 126, interconnect structures 128, bonding pads 138, and bonding layers 142. The details of these components may be similar to corresponding components in wafer 20 and are not repeated here. According to some embodiments, treatment process 44, treatment process 46, or both treatment processes 44 and 46 are performed on wafer 120. Fig.23 The corresponding process is shown as process 204 in the illustrated process flow 200. The details of the processing process 44 and the processing process 46 may be selected from the same group of candidate processes for processing the wafer 20, and the details are not repeated here.

[0054] According to some embodiments, wafer 20 is processed by treatment process 46, and wafer 120 is not processed by treatment process 46. According to alternative embodiments, wafer 120 is processed by treatment process 46, and wafer 20 is not processed by treatment process 46. According to still other alternative embodiments, both wafers 20 and 120 are processed by treatment process 46. Circles 139 at the surface of wafer 120 indicate that treatment process 46 has been performed, and represent functional groups of treatment chemicals attached to the surface of wafer 120.

[0055] In subsequent processes, such as Figure 3 As shown, wafer 120 is turned upside down and bonded to wafer 20. In the example shown, a hybrid bonding process is performed so that bonding pad 38 is bonded to bonding pad 138 by metal-to-metal bonding, and bonding layer 42 is bonded to bonding layer 142 by fusion bonding (forming Si-O-Si bonds). According to alternative embodiments, other types of bonding (such as fusion bonding) may be performed instead of metal-to-metal bonding.

[0056] The wafer bonding process includes the pre-bonding process. Fig.23 The corresponding process is shown as process 206 in the illustrated process flow 200. According to some embodiments, during pre-bonding, wafer 120 is brought into contact with wafer 20, and pressure is applied to press wafers 20 and 120 together. Pre-bonding can be performed at room temperature (between about 20° C. and about 25° C.), and higher temperatures can also be used.

[0057] Pre-bonding may start by contacting the center of wafer 120 with the center of wafer 20. The contact propagates from the contact point to the edges of wafers 20 and 120, which generates a bonding wave that propagates from the contact point to the edges. As the bonding wave propagates from the contact point to the edges, the air between wafers 20 and 120 is gradually squeezed out, so that no bubbles or moisture remain between wafers 20 and 120.

[0058] According to some embodiments, by performing treatment process 46 on one or both of wafers 20 and 120, the bonding wave velocity (i.e., the propagation speed of the bonding wave) is reduced. This allows the bonding wave to propagate more uniformly in different directions with reduced distortion. It also reduces the entrapment of bubbles or moisture.

[0059] After the pre-bonding process, an annealing process is performed. Thus, Si-O-Si bonds are formed between the bonding layers 42 and 142, so that the bonding layers 42 and 142 are bonded to each other. Fig.23 The corresponding process is shown as process 208 in the illustrated process flow 200. According to some embodiments, the annealing process is performed at a temperature in a range between about 250° C. and about 300° C. According to some embodiments, the annealing duration may be in a range between about 5 minutes and about 30 minutes. Thus, the wafers 20 and 120 are bonded to each other to form the bonding interface 165.

[0060] Next, for example, a backside grinding process is performed on the substrate 124 of the wafer 120a by a chemical mechanical polishing (CMP) process or a mechanical polishing process until the through hole 125 is exposed. Fig.23 The corresponding process is shown as process 210 in the illustrated process flow 200 .

[0061] Next, if Figure 4 As shown, the semiconductor substrate 124 in the wafer 120 may be recessed during an etching process so that the top of the TSV 125 protrudes above the semiconductor substrate 124. A dielectric isolation layer 148 may then be formed to surround the top of the TSV 125. Fig.23 The corresponding process is shown as process 212 in the illustrated process flow 200. The formation of dielectric isolation layer 148 may include a deposition process to deposit a dielectric layer onto semiconductor substrate 124 so that the protruding portion of TSV 125 is located in the dielectric layer, followed by a planarization process. The portion of the dielectric layer above TSV 125 is removed, and the remaining portion of the dielectric layer forms dielectric isolation layer 148, which becomes part of die 120' and wafer 120.

[0062] Next, a backside interconnect structure 152 is formed, which includes a dielectric layer 154 and a redistribution line (RDL) 156. Fig.23The corresponding process is shown as process 214 in the illustrated process flow 200. The dielectric layer 154 may include an organic dielectric material such as polybenzoxazole (PBO), polyimide, etc. or an inorganic dielectric material such as SiO, SiN, SiOC, SiON, SiC, SiOCN, etc. The formation process may include depositing the dielectric material, patterning the dielectric material to expose the underlying conductive features, forming a metal seed layer, forming a plating mask, plating the RDL 156, removing the plating mask, and removing the exposed portion of the metal seed layer.

[0063] refer to Figure 5 , forming electrical connections 158 (such as solder areas) to form a reconstructed wafer 160. Fig.23 The corresponding process is shown as process 216 in the illustrated process flow 200. The electrical connector 158 may include a solder region, a metal post, a metal post covered with a pre-solder layer, etc. The electrical connector 158 may include copper, and may or may not include titanium, nickel, palladium, etc.

[0064] Then, if Figure 6 As shown, a singulation process may be performed to separate the reconstructed wafer 160 into identical discrete packages 160'. The singulation process may be performed by a sawing process using a blade. Fig.23 A corresponding process is shown as process 218 in the illustrated process flow 200 .

[0065] Figure 7 Shows Figure 6 FIG. 1 shows an enlarged view of the region at the bonding interface. FIG. 1 shows a bonding interface region 162 (also see Figure 6 ), the bonding interface region 162 includes the bonding layers 42 and 142 and the bonding interface 165 therebetween. Figure 8 , Fig. 9 and Fig.10 Details of the components of the indicated regions are discussed.

[0066] Figure 8 , Fig. 9 and Fig.10 The concentrations of carbon, nitrogen, and oxygen are shown as a function of the position at the bonding interface between wafers 20 and 120 (and between device dies 20' and 120'). The positions shown are given by Figure 7 The arrow 164 in the interface region 162 indicates that the X-axis represents concentration, and in the X-axis, the concentration increases. The Y-axis represents position, where the bonding layers 42 and 142 and the bonding interface 165 are marked. Figure 8 , Fig. 9 and Fig.10 The data shown in ref ects energy dispersive X-ray spectroscopy (EDS) line scan results obtained when surface treatment is performed on wafer 20 and / or wafer 120 using HMDS.

[0067] It is understood that the atomic percentages of elements have the same trend as the concentrations of these elements. For example, the peak concentration may appear at the same position as the peak atomic percentage, and when the concentration decreases (or increases), the atomic percentage may also decrease (or increase) accordingly.

[0068] Figure 8 1 shows the results obtained from a sample where both bonding layers 42 and 142 are formed of silicon oxide according to some embodiments. In the interface region 162, oxygen is present due to the plasma treatment process 44 (which can cause silicon oxide to grow at the outermost surface) and the rinsing process (which causes OH groups to grow at the outermost surface). At the bonding interface 165, since CH3 groups are bonded to silicon atoms, as shown in FIG. Fig.16 As shown, the carbon atomic percentage suddenly increases and thus forms a peak. On the other hand, due to the sudden increase in the carbon atomic percentage (since the total atomic percentage of all elements is 100%), the oxygen atomic percentage suddenly decreases and has a valley (minimum). The shown curves of carbon and oxygen indicate that the surface treatment process 46 has been performed.

[0069] Fig. 9 Results obtained from a sample in which both bonding layers 42 and 142 are formed of SiON according to some embodiments are shown. In the interface region 162, due to the plasma treatment process 44 (which can cause silicon oxide to grow at the outermost surface) and rinsing (which causes OH groups to grow at the outermost surface), the oxygen atomic percentage increases in the bonding interface region 162, and increases in a region slightly away from the bonding interface 165. Due to the growth of silicon oxide, some N atoms are covered with OH groups, and thus the nitrogen atomic percentage has a valley value (minimum value, decrease) at the bonding interface 165.

[0070] On the other hand, Fig.16 As shown in FIG. 1 , due to the presence of CH3 groups, the carbon atomic percentage increases suddenly at the bonding interface 165, and a Fig. 9 On the other hand, the oxygen atomic percentage suddenly decreases and has a valley value due to the sudden increase in the carbon atomic percentage at the bonding interface 165. The shown curves of carbon, nitrogen and oxygen indicate that the surface treatment process 46 has been performed.

[0071] Fig.10Results obtained from a sample in which both bonding layers 42 and 142 are formed of SiCN according to some embodiments are shown. In the interface region 162, due to the plasma treatment process 44 (which can cause silicon oxide to grow at the outermost surface) and rinsing (which causes OH groups to grow at the outermost surface), the oxygen atomic percentage increases at the bonding interface 165. Due to the growth of silicon oxide, some N atoms and C atoms are covered by OH groups, and thus the nitrogen atomic percentage and the C atomic percentage have a valley value (minimum value, decrease) at the bonding interface 165.

[0072] On the other hand, Fig.16 As shown, because the CH3 group is added at the bonding interface 165, the carbon atomic percentage increases suddenly, and thus a peak is formed at the bonding interface 165, which is also located in the valley value of the carbon atomic percentage. Accordingly, the carbon atomic percentage shows a double valley decrease in the interface region 162, but a peak appears at the bonding interface 165. On the other hand, the oxygen atomic percentage increases sharply and a peak appears. The graphical curves of carbon, nitrogen and oxygen indicate that the surface treatment process 46 has been performed.

[0073] Figures 11 to 15 Some embodiments are shown in which different types of wafer combinations are bonded to each other. Figure 1 and Figure 2 The processing steps 44 and 46 shown may be applied to Figures 11 to 15 Either or both of the wafers shown. Fig.11 An embodiment is shown in which wafer 20 comprises a carrier wafer, and wafer 120 comprises a device wafer including TSVs therein.

[0074] Fig.12 An embodiment is shown in which wafer 20 comprises a carrier wafer 20, and wafer 120 comprises a reconstructed wafer. Reconstructed wafer 120 comprises device wafer 170 and device die 172 bonded to device wafer 170. Device die 172 is located in gap-fill dielectric region 174.

[0075] Fig.13 An embodiment is shown in which wafer 20 includes device wafer 20, and wafer 120 includes reconstructed wafer 120. Reconstructed wafer 120 includes device die 172. Device die 172 is located in gap-fill dielectric region 174.

[0076] Fig.14 An embodiment is shown in which wafer 20 includes device wafer 20 , and device wafer 120 is bonded to device wafer 20 .

[0077] Fig.15An embodiment is shown in which wafer 20 includes a reconstructed wafer including device die 172 therein, and reconstructed wafer 120 bonded to reconstructed wafer 20. Reconstructed wafers 20 and 120 include device dies 172 and 172', respectively, with device dies 172 and 172' located in gap-fill regions 174 and 174', respectively.

[0078] In the above embodiments, some processes and features are discussed according to some embodiments of the present disclosure to form a three-dimensional (3D) package. Other components and processes may also be included. For example, a test structure may be included to help perform verification testing on a 3D package or 3DIC device. The test structure may include, for example, a test pad formed in a redistribution layer or on a substrate, which allows testing of the 3D package or 3DIC, using a probe and / or a probe card, etc. The verification test may be performed on an intermediate structure as well as a final structure. In addition, the structures and methods disclosed herein may be used in conjunction with a test method for intermediate verification of a known good die to increase yield and reduce cost.

[0079] The embodiments of the present disclosure have some advantageous features. By performing a surface treatment process on the wafer, the wafer has a slowed bonding wave speed when the wafer is pre-bonded. Therefore, the distortion of the wafer is reduced.

[0080] According to some embodiments of the present disclosure, a method includes performing a plasma treatment on a first wafer; performing a first treatment process on the first wafer, wherein the first treatment process makes the first wafer more hydrophobic than before the first treatment process; pre-bonding the first wafer to a second wafer by wafer-to-wafer bonding; and performing an annealing process to bond the first wafer to the second wafer. In an embodiment, the first treatment process is configured to reduce a bonding wave velocity, and wherein the bonding wave velocity is a propagation velocity of a pre-bonded bonding wave. In an embodiment, the first treatment process is performed using HMDS.

[0081] In an embodiment, a first treatment process is performed by directing hot vapor generated by HMDS to a first wafer. In an embodiment, the first treatment process is performed comprehensively on the entire bonding surface of the first wafer. In an embodiment, the first treatment process includes: masking a first portion of the first wafer; and performing local treatment on a second portion of the first wafer using HMDS. In an embodiment, the first treatment process is performed using APTES. In an embodiment, the first treatment process is performed using MPTMS. In an embodiment, the method further includes performing a second treatment process on a second wafer, wherein the second treatment process makes the second wafer more hydrophobic than before the second treatment process.

[0082] According to some embodiments of the present disclosure, a structure includes a first packaging component including a first dielectric layer; and a second packaging component including a second dielectric layer bonded to the first dielectric layer, wherein the first dielectric layer and the second dielectric layer include an interface region, the interface region including: a first portion of the first dielectric layer; and a second portion of the second dielectric layer, wherein the interface region includes a first carbon concentration, and wherein the first portion of the first dielectric layer and the second portion of the second dielectric layer form an interface, and the interface has a second carbon concentration higher than the first carbon concentration, and wherein the second carbon concentration is a peak carbon concentration.

[0083] In an embodiment, the interface region further comprises two minimum carbon concentrations, a first minimum carbon concentration of the two minimum carbon concentrations being located in the first portion of the first dielectric layer, and a second minimum carbon concentration of the two minimum carbon concentrations being located in the second portion of the second dielectric layer. In an embodiment, both the first dielectric layer and the second dielectric layer comprise SiCN. In an embodiment, the interface region comprises a higher oxygen concentration, and wherein the interface has a minimum oxygen concentration that is lower than the higher oxygen concentration.

[0084] In an embodiment, the interface region further comprises a higher nitrogen concentration, and wherein the interface has a minimum nitrogen concentration below the higher nitrogen concentration. In an embodiment, the first package component and the second package component are bonded to each other by a bond comprising fusion bonding. In an embodiment, the bonding that bonds the first package component to the second package component further comprises metal-to-metal direct bonding.

[0085] According to some embodiments of the present disclosure, a structure includes a first device die including a first silicon-containing dielectric layer; and a second device die including a second silicon-containing dielectric layer, which is bonded to the first silicon-containing dielectric layer to form a bonding interface, wherein the first silicon-containing dielectric layer and the second silicon-containing dielectric layer include: carbon having a peak carbon concentration at the bonding interface, wherein the carbon concentration decreases in an interface region and in a direction pointing away from the bonding interface, wherein the interface region includes the bonding interface and portions of the first silicon-containing dielectric layer and the second silicon-containing dielectric layer; and nitrogen having a minimum concentration at the bonding interface, wherein the nitrogen concentration increases in the interface region and in a direction pointing away from the bonding interface.

[0086] In an embodiment, the first silicon-containing dielectric layer and the second silicon-containing dielectric layer include SiCN. In an embodiment, the carbon has two minimum carbon concentrations on opposite sides of the bonding interface. In an embodiment, the structure further includes oxygen having a peak oxygen concentration at the bonding interface.

[0087] Some embodiments of the present application provide a method, comprising: performing plasma treatment on a first wafer; performing a first treatment process on the first wafer, wherein the first treatment process makes the first wafer more hydrophobic than before the first treatment process; pre-bonding the first wafer to a second wafer by wafer-to-wafer bonding; and performing an annealing process to bond the first wafer to the second wafer.

[0088] In some embodiments, the first treatment process is configured to reduce the bonding wave velocity, and wherein the bonding wave velocity is the propagation velocity of the pre-bonded bonding wave. In some embodiments, the first treatment process is performed using hexamethyldisilazane (HMDS). In some embodiments, the first treatment process is performed by directing hot vapor generated by the hexamethyldisilazane to the first wafer. In some embodiments, the first treatment process is performed comprehensively on the entire bonding surface of the first wafer. In some embodiments, the first treatment process includes: masking a first portion of the first wafer; and performing local treatment on a second portion of the first wafer using the hexamethyldisilazane. In some embodiments, the first treatment process is performed using aminopropyltriethoxysilane (APTES). In some embodiments, the first treatment process is performed using (3-mercaptopropyl)trimethoxysilane (MPTMS). In some embodiments, the method further includes performing a second treatment process on the second wafer, wherein the second treatment process makes the second wafer more hydrophobic than before the second treatment process.

[0089] Other embodiments of the present application provide a structure including: a first packaging component including a first dielectric layer; and a second packaging component including a second dielectric layer bonded to the first dielectric layer, wherein the first dielectric layer and the second dielectric layer include an interface region, the interface region including: a first portion of the first dielectric layer; and a second portion of the second dielectric layer, wherein the interface region includes a first carbon concentration, and wherein the first portion of the first dielectric layer and the second portion of the second dielectric layer form an interface, and the interface has a second carbon concentration higher than the first carbon concentration, and wherein the second carbon concentration is a peak carbon concentration.

[0090] In some embodiments, the interface region further comprises two minimum carbon concentrations, a first minimum carbon concentration of the two minimum carbon concentrations being located in a first portion of the first dielectric layer, and a second minimum carbon concentration of the two minimum carbon concentrations being located in a second portion of the second dielectric layer. In some embodiments, both the first dielectric layer and the second dielectric layer comprise SiCN. In some embodiments, the interface region comprises a higher oxygen concentration, and wherein the interface has a minimum oxygen concentration lower than the higher oxygen concentration. In some embodiments, the interface region further comprises a higher nitrogen concentration, and wherein the interface has a minimum nitrogen concentration lower than the higher nitrogen concentration. In some embodiments, the first package component and the second package component are bonded to each other by a bond comprising a fusion bond. In some embodiments, the bond that bonds the first package component to the second package component further comprises a metal-to-metal direct bond.

[0091] Still other embodiments of the present application provide a structure comprising: a first device die comprising a first silicon-containing dielectric layer; and a second device die comprising a second silicon-containing dielectric layer, the second silicon-containing dielectric layer being bonded to the first silicon-containing dielectric layer to form a bonding interface, wherein the first silicon-containing dielectric layer and the second silicon-containing dielectric layer comprise: carbon having a peak carbon concentration at the bonding interface, wherein the carbon concentration decreases in an interface region and in a direction pointing away from the bonding interface, and wherein the interface region comprises the bonding interface and portions of the first silicon-containing dielectric layer and the second silicon-containing dielectric layer; and nitrogen having a minimum concentration at the bonding interface, wherein the nitrogen concentration increases in the interface region and in a direction pointing away from the bonding interface.

[0092] In some embodiments, the first silicon-containing dielectric layer and the second silicon-containing dielectric layer include SiCN. In some embodiments, the carbon has two minimum carbon concentrations on opposite sides of the bonding interface. In some embodiments, the semiconductor structure further includes oxygen, the oxygen having a peak oxygen concentration at the bonding interface.

[0093] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method for forming a semiconductor structure, comprising: performing a plasma process on the first wafer; performing a first treatment process on the first wafer, wherein the first treatment process makes the first wafer more hydrophobic than before the first treatment process; pre-bonding the first wafer to a second wafer by wafer-to-wafer bonding; and An annealing process is performed to bond the first wafer to the second wafer.

2. The method according to claim 1, wherein: The first treatment process is configured to reduce a bonding wave velocity, and wherein the bonding wave velocity is a propagation velocity of the bonding wave of the pre-bonding.

3. The method according to claim 1, wherein: The first treatment process is performed using hexamethyldisilazane (HMDS).

4. The method according to claim 3, wherein: The first treatment process is performed by directing hot vapor generated from the hexamethyldisilazane to the first wafer.

5. The method according to claim 3, wherein: The first treatment process is comprehensively performed on the entire bonding surface of the first wafer.

6. The method according to claim 3, wherein: The first treatment process comprises: masking a first portion of the first wafer; and A localized treatment is performed on a second portion of the first wafer using the hexamethyldisilazane.

7. The method according to claim 1, wherein: The first treatment process is performed using aminopropyltriethoxysilane (APTES).

8. The method according to claim 1, wherein: The first treatment process is performed using (3-mercaptopropyl)trimethoxysilane (MPTMS).

9. A semiconductor structure comprising: A first packaging component including a first dielectric layer; as well as A second package assembly comprising a second dielectric layer bonded to the first dielectric layer, wherein the first dielectric layer and the second dielectric layer include an interface region, the interface region comprising: a first portion of the first dielectric layer; and a second portion of the second dielectric layer, wherein the interface region comprises a first carbon concentration, and wherein the first portion of the first dielectric layer and the second portion of the second dielectric layer form an interface, and the interface has a second carbon concentration higher than the first carbon concentration, and wherein the second carbon concentration is a peak carbon concentration.

10. A semiconductor structure comprising: a first device die comprising a first silicon-containing dielectric layer; as well as A second device die, comprising a second silicon-containing dielectric layer, the second silicon-containing dielectric layer being bonded to the first silicon-containing dielectric layer to form a bonding interface, wherein the first silicon-containing dielectric layer and the second silicon-containing dielectric layer comprise: carbon having a peak carbon concentration at the bonding interface, wherein the carbon concentration decreases in an interface region and in a direction pointing away from the bonding interface, and wherein the interface region includes the bonding interface and portions of the first silicon-containing dielectric layer and the second silicon-containing dielectric layer; and Nitrogen has a minimum concentration at the bonding interface, wherein the nitrogen concentration increases in the interface region and in a direction pointing away from the bonding interface.

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