Wafer test method capable of avoiding focusing offset

Abstract

The invention discloses a wafer test method capable of avoiding focusing offset, which relates to the technical field of wafer test and comprises the following steps: S1, preparing a wafer; s2, performing automatic focusing and imaging; s3, defect detection; s4, data processing and analysis; s5, automatically testing and recording; and S6, evaluating a result. According to the wafer testing method capable of avoiding focusing offset, multiple defect types can be comprehensively tested, surface defect types, some tiny internal defects and complex defect modes can be accurately captured, the wafer testing result is more accurate, automatic focusing and imaging are matched, and in the imaging process, the imaging accuracy is improved. According to the technical scheme, the imaging device is dynamically adjusted to ensure that the test probe always accurately contacts with the contact on the crystal grain, so that the influence of focusing offset on the test result is avoided, the accuracy of the test result is further improved, the possibility of misjudgment of the crystal grain is effectively reduced, and the condition that the final product quality is influenced due to misjudgment is avoided.

Description

Technical Field

[0001] The invention relates to the technical field of wafer testing, and in particular to a wafer testing method for avoiding focus offset. Background Art

[0002] Wafer refers to the silicon chip used in the manufacture of silicon semiconductor integrated circuits. Because of its round shape, it is called a wafer. The original material of the wafer is silicon, and there is an inexhaustible supply of silicon dioxide on the surface of the earth's crust. These silicon dioxide ores are refined in an electric arc furnace, chlorinated with hydrochloric acid, and distilled to produce high-purity polysilicon with a purity of up to 99.999999999%. The wafer manufacturing plant then melts the polysilicon, plants seed crystals in the melt, and then slowly pulls it out to form a cylindrical single crystal silicon rod. After the silicon rod is cut, rolled, sliced, chamfered, polished, laser engraved, and packaged, it becomes the basic raw material of the integrated circuit factory - silicon wafer, which is the "wafer".

[0003] Wafer testing is an important step in the wafer production process. Specifically, each die on the wafer is tested by needle testing. A probe made of gold wire as thin as a hair is installed on the test head to contact the pad on the die to test its electrical characteristics. Unqualified die will be marked. When the wafer is cut into independent die by die, the unqualified die marked with a mark will be eliminated and will not be used for the next process to avoid increasing manufacturing costs.

[0004] For example, the patent document with publication number CN115840134A discloses a wafer testing method, which includes: obtaining a wafer to be tested and determining the test requirements; setting a programmable logic device between each designated port group of the wafer to be tested; assigning a value to each programmable logic device based on the test requirements, providing a numerical value to each port group, and forming a test template; using a wafer tester to test the test template. The wafer testing method of the present application sets a programmable logic device between the ports of the wafer, and before the wafer is tested, the programmable logic device provides port data to the wafer to be tested, so that the port of the wafer to be tested is in a connection template specific to the electrical function to be tested, and does not rely on the storage wafer to provide port data. The wafer test can be performed before 3D packaging. When the test fails, rework and disassembly are not required, which reduces the production cost.

[0005] However, in the actual testing process, the existing wafer testing methods can often only test specific defect types. It is difficult to capture some tiny internal defects or complex defect patterns, resulting in inaccurate test results. In addition, focus offset is prone to occur during testing, resulting in the test probe being unable to accurately contact the contacts on the grain, thereby failing to accurately test the electrical characteristics of the grain. This also affects the accuracy of the test results from another perspective, so that originally qualified grains may be misjudged as unqualified and eliminated, increasing manufacturing costs, while some unqualified grains may be misjudged as qualified and enter the next process, affecting the quality of the final product.

[0006] Therefore, there is an urgent need to improve this shortcoming. The present invention studies and improves the existing technology and its shortcomings, and provides a wafer testing method that avoids focus offset. Summary of the invention

[0007] The object of the present invention is to provide a wafer testing method for avoiding focus offset, so as to solve the problems raised in the above background technology.

[0008] To achieve the above object, the present invention provides the following technical solution: a wafer testing method for avoiding focus offset, comprising the following steps:

[0009] S1. Wafer preparation:

[0010] Clean and dry the wafer to remove impurities and contaminants on the surface to ensure the accuracy of the test results, and fix the wafer on the stage of the test equipment to ensure that the position of the wafer is stable and accurate to reduce movement and vibration during the test;

[0011] S2. Autofocus and imaging:

[0012] According to the characteristics of the wafer and the test requirements, the focus parameters of the imaging equipment, such as focal length and aperture, are preset to avoid focus offset, and the wafer is scanned and imaged using high-resolution imaging equipment to ensure that the subtle structures and internal defects on the wafer surface can be captured;

[0013] S3. Defect detection:

[0014] S31, Optical inspection: Use a high-resolution optical microscope to scan the wafer surface to identify surface defects such as scratches, particles, cracks, etc., and conduct preliminary screening of the wafers;

[0015] S32, Electron beam inspection: For inspections that require higher resolution, electron beam inspection technology is used for inspection. The electron beam scans the surface of the wafer and identifies smaller defects by detecting the signal generated by the interaction between the electron beam and the wafer;

[0016] S33, X-ray detection: For defects inside the wafer, such as voids and inclusions, X-ray detection technology is used for detection. X-rays penetrate the wafer and internal defects are identified by analyzing the scattering and absorption of X-rays.

[0017] S34, AFM (atomic force microscope) detection: For surface morphology detection that requires extremely high resolution, AFM detection technology is used for detection. AFM obtains the morphology information of the wafer surface by contacting the probe with the wafer surface and measuring the displacement of the probe;

[0018] S4. Data processing and analysis:

[0019] S41, Image comparison: Compare the image obtained by optical or electron beam inspection with the standard defect image library to determine the type and location of defects on the wafer;

[0020] S42, signal processing: processing and analyzing the signals obtained by electron beam, X-ray and probe detection to extract characteristic information related to defects;

[0021] S43. Defect classification and quantification: Classify and quantify defects based on the extracted feature information, evaluate the severity of defects and their impact on product performance. Quantitative indicators include defect density (the number of defects per unit area), defect size (the actual size of the defect), and defect severity (rated according to the degree of impact of the defect on chip performance);

[0022] S5. Automated testing and recording:

[0023] Use automated test equipment (such as ATE) to conduct comprehensive tests on wafers, including DC parameter tests, AC parameter tests, functional tests, etc., and record various parameters and results during the test process, and generate detailed test reports to provide a basis for subsequent analysis and improvement;

[0024] S6. Result evaluation:

[0025] The test results are used to evaluate the performance and quality of the wafer and determine if there are any defective chips or areas.

[0026] Furthermore, in step S2, during the imaging process, real-time focusing technology is used to dynamically adjust the imaging device to ensure that a clear imaging effect can be maintained in the entire scanning area, thereby avoiding the influence of focus offset on the test results.

[0027] Furthermore, in step S32, the specific operation of electron beam detection is as follows: using an electron gun (electron beam source) to generate a high-energy electron beam (these electron beams are usually accelerated and focused to form an extremely fine beam spot with a beam spot diameter of up to nanometers), controlling the electron beam to perform two-dimensional scanning on the wafer surface in a point-by-point scanning or line scanning manner, and the electron beam interacts with the wafer surface to generate various signals, such as secondary electrons, backscattered electrons, characteristic X-rays, etc. These signals are closely related to the material properties, morphology and defects of the wafer surface, and are detected and collected using detectors such as secondary electron detectors and X-ray spectrometers. At the same time, the detectors convert the signals into electrical signals or digital signals for subsequent processing and analysis.

[0028] Furthermore, in step S33, the specific operation of X-ray detection is as follows: the X-ray source in the X-ray detection equipment emits a high-energy X-ray beam. When the X-ray penetrates the wafer, it interacts with the material inside the wafer, such as scattering, absorption, etc., and generates a signal carrying information about the internal structure of the wafer. Detectors such as scintillator detectors and direct detectors are used to capture the signals generated by the interaction between the X-rays and the wafer. After conversion and processing, these signals become data that can be analyzed.

[0029] Furthermore, in step S34, the specific operation of AFM detection is as follows: the AFM probe (consisting of a micro-cantilever and a needle tip) gently contacts the wafer surface, and performs a two-dimensional scan on the wafer surface under the drive of the control system. During the scanning process, the probe moves up and down with the ups and downs of the wafer surface, and the displacement information of the probe is recorded at the same time. The displacement information of the probe is converted into an electrical signal or an optical signal through the deformation of the micro-cantilever, and is captured by the AFM detector and converted into a digital signal.

[0030] Furthermore, in the step S41, the specific operation of image comparison is as follows: performing preprocessing operations such as denoising and contrast enhancement on the wafer image obtained by scanning with the optical microscope and the electron beam detection equipment to improve the image quality, and then comparing the preprocessed image with the image in the standard defect image library, and identifying the defect type and location on the wafer through a pattern recognition algorithm, wherein the pattern recognition algorithm includes a template matching algorithm, a feature-based matching algorithm, a machine learning algorithm, a deep learning algorithm, and a statistical pattern recognition algorithm.

[0031] Furthermore, in step S42, the specific operation of signal processing is: performing preprocessing operations such as filtering and denoising on the electrical signal or image signal related to the defect obtained by electron beam, X-ray or probe detection to eliminate interference signals and improve signal quality, and then using signal processing techniques such as Fourier transform and wavelet transform to analyze the preprocessed signal to extract characteristic information related to the defect, such as frequency, amplitude, phase, etc.

[0032] Furthermore, in step S43, the classification method includes rule-based classification and machine learning classification, and the rule-based classification is to classify defects according to preset rules or thresholds, and the machine learning classification is to train a large amount of defect data using a machine learning algorithm to achieve automatic classification.

[0033] Furthermore, in step S5, before testing, the ATE equipment must be calibrated to ensure the accuracy and reliability of the test results, and to check whether key components of the ATE, such as power supply, signal generator, and measuring instruments, are in good working condition.

[0034] Further, in step S5, the test includes a DC parameter test, an AC parameter test, and a functional test;

[0035] The DC parameter test is used to evaluate the electrical characteristics of the chip under static conditions, including but not limited to the following items:

[0036] Power supply voltage test: measure whether the chip's power supply voltage is within the specified range;

[0037] Static power consumption test: measure the power consumption of the chip when there is no signal input;

[0038] Input / output current test: measures the current at the chip input and output to evaluate its current consumption and load capacity;

[0039] Bias current test: measures the current of the chip's internal bias circuit to evaluate its stability and reliability;

[0040] The AC parameter test is used to evaluate the electrical performance of the chip under dynamic conditions, including but not limited to the following items:

[0041] Gain test: measure the gain of the chip, that is, the amplification ratio between the input signal and the output signal;

[0042] Bandwidth test: measures the highest frequency that the chip can handle to evaluate its performance under high-frequency signals;

[0043] Rise / fall time test: measures the time required for a signal to change from a low level to a high level (or vice versa) to evaluate the response speed of the chip;

[0044] Phase margin test: measures the stability of the system to ensure that the chip remains stable under various operating conditions;

[0045] The functional test is used to verify whether the logic functions and performance indicators of the chip meet the design requirements, including but not limited to the following items:

[0046] Logical function test: According to the chip's truth table or functional description, set the ATE test vector to verify whether the chip's logical function is correct;

[0047] Boundary test: Test under the boundary conditions of the chip, such as maximum input voltage, minimum input voltage, etc., to evaluate the stability and reliability of the chip;

[0048] Random test: Input a series of randomly combined test patterns to detect whether the output signal matches the expected pattern data, so as to determine whether the circuit function is normal.

[0049] The present invention provides a wafer testing method for avoiding focus offset, which has the following beneficial effects:

[0050] The present invention can comprehensively test a variety of defect types, not only for surface defect types, but also for some tiny internal defects and complex defect patterns, which can be accurately captured, making the wafer test results more accurate. In conjunction with automatic focus and imaging, the imaging device can be dynamically adjusted during the imaging process to ensure that the test probe always accurately contacts the contacts on the crystal grain, thereby avoiding the impact of focus offset on the test results, further improving the accuracy of the test results, and effectively reducing the possibility of misjudgment of crystal grains, thereby avoiding the situation where misjudgment affects the quality of the final product. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Figure 1 The present invention provides an operation flow of a wafer testing method for avoiding focus offset;

[0052] Figure 2 This is a logic block diagram of steps S2-S3 of a wafer testing method for avoiding focus offset according to the present invention. DETAILED DESCRIPTION

[0053] The following embodiments of the present invention are described in further detail in conjunction with the accompanying drawings and examples. The following examples are used to illustrate the present invention, but are not intended to limit the scope of the present invention.

[0054] like Figure 1-Figure 2 As shown, a wafer testing method for avoiding focus offset includes the following steps:

[0055] S1. Wafer preparation:

[0056] Clean and dry the wafer to remove impurities and contaminants on the surface to ensure the accuracy of the test results, and fix the wafer on the stage of the test equipment to ensure that the position of the wafer is stable and accurate to reduce movement and vibration during the test;

[0057] S2. Autofocus and imaging:

[0058] According to the characteristics of the wafer and the test requirements, the focus parameters of the imaging equipment, such as focal length and aperture, are preset to avoid focus offset. The wafer is scanned and imaged using high-resolution imaging equipment to ensure that the subtle structure and internal defects on the wafer surface can be captured. During the imaging process, real-time focus technology is used to dynamically adjust the imaging equipment to ensure that clear imaging effects can be maintained throughout the scanning area, thereby avoiding the impact of focus offset on the test results;

[0059] S3. Defect detection:

[0060] S31, Optical inspection: Use a high-resolution optical microscope to scan the wafer surface to identify surface defects such as scratches, particles, cracks, etc., and conduct preliminary screening of the wafers;

[0061] S32. Electron beam detection: For detection that requires higher resolution, electron beam detection technology is used for detection. The electron beam scans the wafer surface and identifies smaller defects by detecting the signal generated by the interaction between the electron beam and the wafer. Specific operations: Use an electron gun (electron beam source) to generate a high-energy electron beam (these electron beams are usually accelerated and focused to form an extremely fine beam spot with a beam spot diameter of up to nanometers), control the electron beam to perform two-dimensional scanning on the wafer surface in a point-by-point scanning or line scanning manner, and the electron beam interacts with the wafer surface to generate various signals, such as secondary electrons, backscattered electrons, characteristic X-rays, etc. These signals are closely related to the material properties, morphology and defects of the wafer surface, and are detected and collected using detectors such as secondary electron detectors and X-ray spectrometers. At the same time, the detector converts the signal into an electrical signal or a digital signal for subsequent processing and analysis;

[0062] S33, X-ray detection: For defects inside the wafer, such as voids, inclusions, etc., X-ray detection technology is used for detection. X-rays penetrate the wafer, and internal defects are identified by analyzing the scattering and absorption of X-rays. Specific operation: The X-ray source in the X-ray detection equipment emits a high-energy X-ray beam. When the X-rays penetrate the wafer, they interact with the materials inside the wafer, such as scattering and absorption, and generate signals carrying information about the internal structure of the wafer. Scintillator detectors or direct detectors are used to capture the signals generated by the interaction between X-rays and the wafer. After conversion and processing, these signals become data that can be analyzed;

[0063] S34, AFM (atomic force microscope) detection: For surface morphology detection that requires extremely high resolution, AFM detection technology is used for detection. AFM contacts the wafer surface with a probe and measures the displacement of the probe to obtain the morphology information of the wafer surface. Specific operation: The AFM probe (consisting of a micro-cantilever and a needle tip) gently contacts the wafer surface and performs a two-dimensional scan on the wafer surface under the drive of the control system. During the scanning process, the probe moves up and down with the ups and downs of the wafer surface, and the displacement information of the probe is recorded at the same time. The displacement information of the probe is converted into an electrical signal or an optical signal through the deformation of the micro-cantilever, and is captured by the AFM detector and converted into a digital signal.

[0064] S4. Data processing and analysis:

[0065] S41, image comparison: compare the image obtained by optical or electron beam inspection with the standard defect image library to determine the type and location of defects on the wafer; specific operation: perform pre-processing operations such as denoising and contrast enhancement on the wafer image obtained by scanning with the optical microscope and electron beam inspection equipment to improve the image quality, and then compare the pre-processed image with the image in the standard defect image library, and identify the type and location of defects on the wafer through the pattern recognition algorithm;

[0066] In this embodiment, the recognition operation is specifically performed through the following pattern recognition algorithm:

[0067] Template matching algorithm: compares a small block (or "template") in the image to be tested with the templates in the standard defect image library to find the best match. It is suitable for situations where the shape and position of the defect are relatively fixed. Defects are identified by comparing the similarity between images.

[0068] Feature-based matching algorithm: first extract the features (such as edges, corners, textures, etc.) in the image to be tested and the standard defect image, and then compare and match these features. It is suitable for situations where the defects have significant features and the features are easy to extract, and can more accurately identify the type and location of the defects;

[0069] Machine learning algorithm: Use machine learning techniques (such as neural networks, support vector machines, decision trees, etc.) to train a large number of labeled defect images so that the model can automatically learn and identify defects;

[0070] Deep learning algorithm: As a branch of machine learning, deep learning algorithms (such as convolutional neural networks (CNNs)) automatically learn and extract high-level feature representations from raw images by building a multi-level neural network structure, and then perform defect recognition. In the field of wafer testing, it can process high-resolution wafer images and accurately identify tiny defects.

[0071] Statistical pattern recognition algorithm: Based on the principles and methods of statistics, it analyzes and compares statistical features such as pixel values ​​and gray levels in images to identify defects. It is suitable for situations where the image data volume is large and the feature dimension is high, and can detect abnormal areas in the image through statistical analysis;

[0072] S42. Signal processing: Process and analyze the signals obtained by electron beam, X-ray and probe detection to extract characteristic information related to the defect; Specific operations: Perform pre-processing operations such as filtering and denoising on the electrical signals or image signals related to the defect obtained by electron beam, X-ray or probe detection to eliminate interference signals and improve signal quality, and then use signal processing techniques such as Fourier transform and wavelet transform to analyze the pre-processed signals to extract characteristic information related to the defect, such as frequency (in the frequency domain diagram, the characteristic frequency related to the defect can be identified through the frequency distribution of the signal), amplitude (the amplitude of different frequency components reflects the strength of the signal at that frequency, and a high amplitude indicates the presence of a significant defect), phase (can provide clues about the location or nature of the defect), etc.;

[0073] In this embodiment, when analyzing the signal collected by the X-ray or AFM equipment, the signal is converted from the time domain to the frequency domain through Fourier transform to observe whether there is a specific frequency component related to the defect in the signal; at the same time, the wavelet transform is used to extract the time-varying feature information related to the defect, and its feature extraction includes: time-frequency analysis (wavelet transform can provide the time domain and frequency domain information of the signal at the same time, so that the analyst can observe the change of the defect over time), multi-scale analysis (by selecting different wavelet basis functions and scale parameters, the signal can be analyzed at multiple scales, so as to observe the characteristics of the defect at different scales), and detail extraction (wavelet transform can capture the details in the signal, which is of great significance for detecting tiny defects);

[0074] S43. Defect classification and quantification: Defects are classified and quantified based on the extracted feature information to evaluate the severity of defects and their impact on product performance. Quantitative indicators include defect density (the number of defects per unit area), defect size (the actual size of the defect) and defect severity (rated according to the impact of the defect on chip performance). Classification methods include rule-based classification and machine learning classification. Rule-based classification is to classify defects according to preset rules or thresholds, and machine learning classification is to use machine learning algorithms to train a large amount of defect data to achieve automatic classification.

[0075] S5. Automated testing and recording:

[0076] Use ATE equipment to conduct comprehensive tests on wafers. Before testing, ATE equipment is calibrated to ensure the accuracy and reliability of test results. Key components such as ATE power supply, signal generator, and measuring instruments are checked to see if they are in good working condition. Various parameters and results during the test are recorded, and detailed test reports are generated to provide a basis for subsequent analysis and improvement.

[0077] In this embodiment, the test includes a DC parameter test, an AC parameter test, and a functional test;

[0078] 1) Evaluate the electrical characteristics of the chip under static conditions through DC parameter testing, including the following items: power supply voltage test (measure whether the power supply voltage of the chip is within the specified range), static power consumption test (measure the power consumption of the chip when there is no signal input), input / output current test (measure the current at the input and output ends of the chip to evaluate its current consumption and load capacity), bias current test (measure the current of the bias circuit inside the chip to evaluate its stability and reliability);

[0079] 2) Evaluate the electrical performance of the chip under dynamic conditions through AC parameter testing, including the following items: gain test (measure the gain of the chip, that is, the amplification ratio between the input signal and the output signal), bandwidth test (measure the highest frequency that the chip can handle to evaluate its performance under high-frequency signals), rise / fall time test (measure the time required for the signal to change from low level to high level (or vice versa) to evaluate the response speed of the chip), phase margin test (measure the stability of the system to ensure that the chip can remain stable under various working conditions);

[0080] 3) Verify whether the logic function and performance indicators of the chip meet the design requirements through functional testing, including the following items: logic function test (according to the chip's truth table or functional description, set the ATE test vector to verify whether the chip's logic function is correct), boundary test (test under the chip's boundary conditions, such as maximum input voltage, minimum input voltage, etc., to evaluate the chip's stability and reliability), random test (input a series of randomly combined test patterns, detect whether the output signal is consistent with the expected pattern data, so as to determine whether the circuit function is normal);

[0081] S6. Result evaluation:

[0082] The test results are used to evaluate the performance and quality of the wafer and determine if there are any defective chips or areas.

[0083] The embodiments of the present invention are given for the purpose of illustration and description, and are not intended to be exhaustive or to limit the invention to the disclosed forms. Many modifications and variations will be apparent to those of ordinary skill in the art. The embodiments are selected and described in order to better illustrate the principles and practical applications of the present invention and to enable those of ordinary skill in the art to understand the present invention and thereby design various embodiments with various modifications suitable for specific uses.

Claims

1. A wafer testing method for avoiding focus offset, characterized in that: The following steps are involved: S1. Wafer preparation: Clean and dry the wafer to remove surface impurities and contaminants, and secure the wafer on the stage of the test equipment; S2. Autofocus and imaging: According to the characteristics of the wafer and the test requirements, the focus parameters of the imaging equipment are preset, and the wafer is scanned and imaged using a high-resolution imaging device to ensure that the subtle structure and internal defects on the wafer surface can be captured; S3. Defect detection: S31, Optical inspection: Use a high-resolution optical microscope to scan the wafer surface to identify scratches, particles, and cracks on the surface and conduct preliminary screening of the wafers; S32, Electron beam inspection: For inspections that require higher resolution, electron beam inspection technology is used for inspection. The electron beam scans the surface of the wafer and identifies smaller defects by detecting the signal generated by the interaction between the electron beam and the wafer; S33, X-ray detection: For defects inside the wafer, X-ray detection technology is used for detection. X-rays penetrate the wafer and internal defects are identified by analyzing the scattering and absorption of X-rays. S34, AFM detection: For surface morphology detection that requires extremely high resolution, AFM detection technology is used for detection. AFM obtains the morphology information of the wafer surface by contacting the probe with the wafer surface and measuring the displacement of the probe; S4. Data processing and analysis: S41, Image comparison: Compare the image obtained by optical or electron beam inspection with the standard defect image library to determine the type and location of defects on the wafer; S42, signal processing: processing and analyzing the signals obtained by electron beam, X-ray and probe detection to extract characteristic information related to defects; S43, Defect classification and quantification: Classify and quantify defects based on the extracted feature information, evaluate the severity of defects and their impact on product performance. Quantitative indicators include defect density, defect size and defect severity; S5. Automated testing and recording: Use automated testing equipment to conduct comprehensive testing on wafers, record various parameters and results during the testing process, and generate detailed test reports; S6. Result evaluation: The test results are used to evaluate the performance and quality of the wafer and determine if there are any defective chips or areas.

2. A wafer testing method for avoiding focus shift according to claim 1, characterized in that: In step S2, during the imaging process, real-time focusing technology is used to dynamically adjust the imaging device to ensure that a clear imaging effect can be maintained in the entire scanning area.

3. A wafer testing method for avoiding focus shift according to claim 1, characterized in that: In step S32, the specific operation of electron beam detection is as follows: using an electron gun to generate a high-energy electron beam, controlling the electron beam to perform two-dimensional scanning on the wafer surface in a point-by-point scanning or line scanning manner, the electron beam interacts with the wafer surface to generate various signals, and using a detector to detect and collect these signals, and the detector converts the signals into electrical signals or digital signals.

4. The wafer testing method for avoiding focus shift according to claim 1, characterized in that: In step S33, the specific operation of X-ray detection is as follows: the X-ray source in the X-ray detection equipment emits a high-energy X-ray beam. When the X-ray penetrates the wafer, it interacts with the material inside the wafer and generates a signal carrying information about the internal structure of the wafer. The detector is used to capture the signal generated by the interaction between the X-ray and the wafer.

5. The wafer testing method for avoiding focus offset according to claim 1, characterized in that: In step S34, the specific operation of AFM detection is as follows: the probe of AFM lightly contacts the surface of the wafer, and performs a two-dimensional scan on the surface of the wafer under the drive of the control system. During the scanning process, the probe moves up and down with the ups and downs of the wafer surface, and the displacement information of the probe is recorded at the same time. The displacement information of the probe is converted into an electrical signal or an optical signal through the deformation of the micro-cantilever, and is captured by the detector of AFM and converted into a digital signal.

6. The wafer testing method for avoiding focus shift according to claim 1, characterized in that: In the step S41, the specific operation of image comparison is: preprocessing the wafer image obtained by scanning with the optical microscope and the electron beam detection equipment, and then comparing the preprocessed image with the image in the standard defect image library, and identifying the defect type and location on the wafer through a pattern recognition algorithm, wherein the pattern recognition algorithm includes a template matching algorithm, a feature-based matching algorithm, a machine learning algorithm, a deep learning algorithm, and a statistical pattern recognition algorithm.

7. The wafer testing method for avoiding focus shift according to claim 1, characterized in that: In step S42, the specific operation of signal processing is: preprocessing the electrical signal or image signal related to the defect obtained by electron beam, X-ray or probe detection, and then using signal processing technology to analyze the preprocessed signal to extract characteristic information related to the defect.

8. The wafer testing method for avoiding focus shift according to claim 1, characterized in that: In step S43, the classification method includes rule-based classification and machine learning classification, and the rule-based classification is to classify defects according to preset rules or thresholds, and the machine learning classification is to train a large amount of defect data using a machine learning algorithm to achieve automatic classification.

9. The wafer testing method for avoiding focus shift according to claim 1, characterized in that: In step S5, before testing, the ATE equipment must be calibrated to ensure the accuracy and reliability of the test results, and to check whether key components of the ATE, such as power supply, signal generator, and measuring instruments, are in good working condition.

10. The wafer testing method for avoiding focus offset according to claim 1, characterized in that: In step S5, the test includes a DC parameter test, an AC parameter test, and a functional test; The DC parameter test is used to evaluate the electrical characteristics of the chip under static conditions, including but not limited to the following items: Power supply voltage test: measure whether the chip's power supply voltage is within the specified range; Static power consumption test: measure the power consumption of the chip when there is no signal input; Input / output current test: measures the current at the chip input and output to evaluate its current consumption and load capacity; Bias current test: measures the current of the chip's internal bias circuit to evaluate its stability and reliability; The AC parameter test is used to evaluate the electrical performance of the chip under dynamic conditions, including but not limited to the following items: Gain test: measure the gain of the chip, that is, the amplification ratio between the input signal and the output signal; Bandwidth test: measures the highest frequency that the chip can handle to evaluate its performance under high-frequency signals; Rise / fall time test: measures the time required for a signal to change from a low level to a high level to evaluate the response speed of the chip; Phase margin test: measures the stability of the system to ensure that the chip remains stable under various operating conditions; The functional test is used to verify whether the logic functions and performance indicators of the chip meet the design requirements, including but not limited to the following items: Logical function test: According to the chip's truth table or functional description, set the ATE test vector to verify whether the chip's logical function is correct; Boundary test: Test under the boundary conditions of the chip, such as maximum input voltage, minimum input voltage, etc., to evaluate the stability and reliability of the chip; Random test: Input a series of randomly combined test patterns to detect whether the output signal matches the expected pattern data, so as to determine whether the circuit function is normal.

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