Method for forming copper barrier layer, copper-containing conductive structure and forming method of copper-containing conductive structure
By forming a CoW alloy copper barrier layer on the semiconductor device, the problems of copper plating hole defects and poor copper diffusion in small-sized processes in traditional processes are solved, and more uniform deposition and lower resistance values are achieved.
Patent Information
- Application Number
- CN202311543170.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-11-16
- Publication Date
- 2025-05-16
AI Technical Summary
The traditional copper barrier layer formation process can easily lead to copper plating hole defects in small-size processes and has poor effect on blocking copper diffusion.
The Co layer is formed by a chemical vapor deposition (CVD) process, and the W layer is formed on the Co layer by a physical vapor deposition (PVD) process, followed by annealing to form a CoW alloy copper barrier layer.
It improves the uniformity of the metal layer, avoids hole defects caused by uneven deposition, enhances the copper barrier effect, is suitable for small-size processes, and improves the conductivity of the copper-containing conductive structure.
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Figure CN120015694A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the technical field of semiconductor device manufacturing, and in particular, to a method for forming a copper barrier layer and a copper-containing conductive structure and a method for forming the same. Background Art
[0002] The traditional copper barrier layer formation process includes: dual damascene etching-PVD barrier layer TaN / Ta deposition-PVD seed layer Cu deposition-copper plating. However, both the barrier layer and the seed layer are traditionally formed by PVD process, which is inherently limited by the problem of step coverage, resulting in uneven deposition layer, thick openings of grooves and holes, and thin sidewalls, which in turn makes subsequent copper plating prone to holes, and the problem becomes more and more obvious in advanced processes with smaller and smaller sizes. Summary of the invention
[0003] The purpose of the present disclosure is to provide a method for forming a copper barrier layer and a copper-containing conductive structure and a method for forming the same, which can solve the problem of easy hole defects caused by copper plating in small-size processes and have a good effect in blocking copper diffusion.
[0004] In order to achieve the above object, the present disclosure provides a method for forming a copper barrier layer in a first aspect, comprising the following steps:
[0005] S1, performing dual damascene processing on the dielectric layer of the semiconductor device to etch holes and grooves in the dielectric layer;
[0006] S2. Depositing a Co layer on the surface of the etched semiconductor device by chemical vapor deposition in the presence of a Co precursor;
[0007] S3, depositing a W layer on the surface of the Co layer by physical vapor deposition in the presence of a W precursor;
[0008] S4, performing annealing treatment to form a CoW alloy copper barrier layer on the surface of the semiconductor device.
[0009] Optionally, in step S1, the dielectric layer of the semiconductor device is disposed on a substrate; optionally, the material of the substrate is selected from one or more semiconductor materials; optionally, the semiconductor material is selected from silicon;
[0010] The material of the dielectric layer is selected from one or more low dielectric constant oxides; optionally, the dielectric constant of the low dielectric constant oxide is 1.5-3.
[0011] Optionally, in step S2, the Co precursor is selected from one or both of Co2(CO)8 and (3,3-dimethyl-1-butyne) dicobalt hexacarbonyl;
[0012] Preferably, the chemical vapor deposition conditions include: in the chemical vapor deposition furnace, the reaction gas flow rate is 10-500 sccm, the gas pressure in the furnace is 0.001-600 Torr, the temperature is 20-500° C., and the processing time is 1-1200 sec.
[0013] Optionally, the Co layer formed in step S2 has a thickness of 5-300 Å.
[0014] Optionally, in step S3, the W target is a pure W target;
[0015] Preferably, the conditions for physical vapor deposition include: in the physical vapor deposition furnace, the reaction gas flow rate is 5-500 sccm, the gas pressure in the furnace is 0.5-100 mTorr, the temperature is 25-500° C., and the processing time is 0.1-300 sec.
[0016] Optionally, the thickness of the W layer formed in step S3 is 5-300A;
[0017] Preferably, the total thickness of the Co layer and the W layer is 10-500 Å; further preferably, the thickness ratio of the Co layer to the W layer is 1:0.01-5.
[0018] Optionally, in step S4, the annealing treatment conditions include: first raising the temperature to 100-500°C for a heating time of 30-10800 seconds; and then cooling down to 10-50°C.
[0019] A second aspect of the present disclosure provides a method for forming a copper-containing conductive structure, comprising the following steps:
[0020] S5. Forming a copper seed layer on the copper barrier layer of the semiconductor device by physical vapor deposition; the copper barrier layer is formed by the method described in the first aspect of the present disclosure;
[0021] S6. Depositing metallic copper on the surface of the semiconductor device having the copper seed crystal layer formed thereon.
[0022] A third aspect of the present disclosure provides a copper-containing conductive structure of a dual damascene structure, comprising a copper barrier layer disposed between a dielectric layer and a copper interconnect line, wherein the copper barrier layer comprises a CoW alloy.
[0023] Optionally, the copper barrier layer has a thickness of 10-500 Å.
[0024] Through the above technical scheme, the present disclosure provides a method for forming a copper barrier layer and a copper-containing conductive structure and a method for forming the same. The present disclosure forms a Co layer by adopting a CVD (chemical vapor deposition) process and forms a W layer on the Co layer by adopting a PVD (physical vapor deposition) process, and then obtains a CoW alloy layer by annealing. The use of different deposition processes can be more suitable for the formation of different metal layers, and can improve the uniformity of the metal layer, prevent uneven deposition in the grooves and holes of the substrate, thick openings, and thin side walls, avoid negative impacts on subsequent copper plating effects, and is more adaptable to small-size processes, with better step coverage and lower resistance, which can improve the conductivity of the copper-containing conductive structure.
[0025] Other features and advantages of the present disclosure will be described in detail in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] The accompanying drawings are used to provide a further understanding of the present disclosure and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present disclosure but do not constitute a limitation of the present disclosure. In the accompanying drawings:
[0027] Figure 1 is a flow chart of a method for forming a copper barrier layer provided by the present disclosure;
[0028] Figure 2 is a schematic diagram of a process flow for forming a CoW alloy copper barrier layer provided by the present disclosure;
[0029] Figure 3 is a schematic diagram of a process flow for forming a copper-containing conductive structure provided by the present disclosure;
[0030] Figure 4 is a schematic diagram of a conventional process for depositing a copper barrier layer;
[0031] Figure 5 is a flow chart of forming a copper-containing conductive structure provided by the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS
[0033] 1-Co layer, 2-W layer, 3-CoW alloy copper barrier layer, 4-substrate + dielectric layer, 5-copper seed layer, 6-copper, 7-TaN / Ta barrier layer, 8-copper seed layer. DETAILED DESCRIPTION
[0034] The specific embodiments of the present disclosure are described in detail below. It should be understood that the specific embodiments described herein are only used to illustrate and explain the present disclosure, and are not used to limit the present disclosure.
[0035] In the conventional process, the substrate is first processed by a dual Damascene etching process, and then TaN / Ta is deposited by a PVD deposition process to form a TaN / Ta barrier layer 7; and then a copper seed layer 8 is formed on the barrier layer by a PVD deposition process. The PVD deposition process is prone to uneven deposition thickness at the step position of the etched trench structure, for example Figure 4 In the case shown in the dashed box, the unevenness of the barrier layer and the seed layer leads to holes in the subsequent copper plating layer, which in turn leads to reduced conductivity. The inventors of the present disclosure have found through research that using CoW alloy as a copper barrier layer can effectively reduce the resistance value of the copper-containing conductive structure, and by using appropriate deposition technology for different metal layers, the resistance value can be reduced to the greatest extent while ensuring the uniformity of the deposited layer.
[0036] like Figure 1 As shown, the first aspect of the present disclosure provides a method for forming a copper barrier layer, comprising the following steps:
[0037] S1, performing dual damascene processing on the dielectric layer of the semiconductor device to etch holes and grooves in the dielectric layer;
[0038] S2, depositing a Co layer 1 on the surface of the etched semiconductor device by chemical vapor deposition in the presence of a Co (cobalt) precursor;
[0039] S3, depositing a W layer 2 on the surface of the Co layer 1 by physical vapor deposition in the presence of a W (tungsten) precursor;
[0040] S4, performing annealing treatment to form a CoW alloy (cobalt tungsten alloy) copper barrier layer 3 on the surface of the semiconductor device.
[0041] The present disclosure provides a method for forming a copper barrier layer, by forming a Co layer by a CVD (chemical vapor deposition) process and forming a W layer on the Co layer by a PVD (physical vapor deposition) process, and then obtaining a CoW alloy layer by annealing. The use of different deposition processes can be more suitable for the formation of different metal layers, and can improve the uniformity of the metal layer, prevent uneven deposition in the grooves of the substrate, avoid negative impact on the subsequent copper plating effect, and be more suitable for small-size processes, with better step coverage and lower resistance, which can improve the conductivity of the copper-containing conductive structure. Figure 3 As shown, the copper seed layer 5 obtained by PVD deposition of Cu covers the CoW alloy copper barrier layer 3 evenly, especially the boundary of the "step coverage" is clear; after the copper plating treatment, there is no covered blank area at the "step" position of the copper substrate, and the copper plating effect is better.
[0042] In a specific embodiment, in step S1, the dielectric layer of the semiconductor device is disposed on a substrate; optionally, the material of the substrate is selected from one or more semiconductor materials, for example, silicon or other semiconductor materials known in the art; optionally, the material of the dielectric layer is selected from one or more low dielectric constant oxides, for example, silicon dioxide or other low dielectric constant oxides known in the art; optionally, the dielectric constant of the low dielectric constant oxide is 1.5-3.
[0043] The dielectric layer in the present disclosure may be formed by conventional techniques in the art.
[0044] In one embodiment, in step S2, the Co precursor is selected from one or more of Co2(CO)8 and (3,3-dimethyl-1-butyne) dicobalt hexacarbonyl (CCTBA); preferably (3,3-dimethyl-1-butyne) dicobalt hexacarbonyl;
[0045] Preferably, the conditions of the chemical vapor deposition include: in the chemical vapor deposition furnace, the reaction gas flow rate is 10-500sccm, the gas pressure in the furnace is 0.001-600Torr, the temperature is 20-500°C, and the processing time is 1-1200sec. In the present disclosure, in the chemical vapor deposition furnace, the reaction gas flow rate can be but not limited to 10sccm, 50sccm, 100sccm, 150sccm, 200sccm, 250sccm, 300sccm, 350sccm, 400sccm, 450sccm and 500sccm, etc.; the gas pressure in the furnace can include but not limited to 0.001Torr, 0.5Torr, 1Torr, 10Torr, 20Torr, 50Torr, 100Torr, 1 The temperature may include but is not limited to 20°C, 40°C, 60°C, 80°C, 100°C, 200°C, 300°C, 400°C and 500°C, etc. The processing time may include but is not limited to 1sec, 50sec, 100sec, 300sec, 500sec, 700sec, 900sec, 1100sec and 1200sec, etc.
[0046] In a preferred embodiment, the chemical vapor deposition conditions include: in the chemical vapor deposition furnace, the reaction gas flow rate is 100-200 sccm, the gas pressure in the furnace is 0.001-10 Torr, the temperature is 200-400°C, and the processing time is 5-30 sec.
[0047] In the present disclosure, the chemical vapor deposition device adopts a device with a conventional structure in the art.
[0048] In one embodiment, the thickness of the Co layer formed in step S2 is 5-300A. In the present disclosure, the thickness of the Co layer may include but is not limited to 5A, 10A, 50A, 100A, 150A, 200A, 250A and 300A.
[0049] In one embodiment, in step S3, the W target is a pure W target;
[0050] Preferably, the conditions of the physical vapor deposition include: in the physical vapor deposition furnace, the reaction gas flow rate is 5-500sccm, the gas pressure in the furnace is 0.5-100mTorr, the temperature is 25-500°C, and the processing time is 0.1-300sec. In the present disclosure, in the physical vapor deposition furnace, the reaction gas flow rate may include but is not limited to 5sccm, 10sccm, 50sccm, 100sccm, 150sccm, 200sccm, 250sccm, 300sccm, 350sccm, 400sccm, 450sccm and 500sccm, etc.; the gas pressure in the furnace may include but is not limited to 0.5mTorr, 1mTorr, 5mTorr, 10mTorr, 20mTorr, 40mTorr, etc. The temperature may include but is not limited to 25°C, 40°C, 60°C, 80°C, 100°C, 200°C, 300°C, 400°C and 500°C, etc.; the processing time may include but is not limited to 0.1sec, 0.5sec, 1sec, 50sec, 80sec, 100sec, 120sec, 150sec, 180sec, 210sec, 230sec, 260sec and 300sec, etc.
[0051] In a preferred embodiment, the conditions of the physical vapor deposition include: a reaction gas flow rate of 10-200 sccm, a gas pressure in the furnace of 1-30 mTorr, a temperature of 100-200° C., and a processing time of 10-30 sec.
[0052] The physical vapor deposition apparatus in the present disclosure adopts an apparatus of conventional structure in the art.
[0053] In one embodiment, the thickness of the W layer formed in step S3 is 5-300A. In the present disclosure, the thickness of the W layer may include but is not limited to 5A, 10A, 50A, 100A, 150A, 200A, 250A and 300A.
[0054] In a preferred embodiment, the total thickness of the Co layer and the W layer is 10-500A; further preferably, the thickness ratio of the Co layer to the W layer is 1:0.01-5, preferably 1:0.01-0.1. In the present disclosure, the total thickness of the Co layer and the W layer may include but is not limited to 10A, 50A, 100A, 150A, 200A, 250A, 300A, 350A, 400A, 450A, 500A, etc.; the thickness ratio of the Co layer to the W layer may include but is not limited to 1:0.01, 1:0.05, 1:0.1, 1:0.5, 1:1, 1:1.5, 1:2, 1:2.5, 1:3, 1:3.5, 1:4, 1:4.5, 1:5, etc.
[0055] In one embodiment, in step S4, the annealing treatment conditions include: first raising the temperature to 100-500°C, preferably 200-400°C, for a heating time of 30-10800 seconds, preferably 60-1800 seconds; and then cooling to 10-50°C. In the present disclosure, the temperature can be increased to 100°C, 150°C, 200°C, 250°C, 300°C, 350°C, 400°C, 450°C, 500°C, etc. during the annealing treatment, and the heating time can include but is not limited to 30sec, 500sec, 1000sec, 1500sec, 2000sec, 2500sec, 3000sec, 3500sec, 4000sec, 5000sec, 6000sec, 7000sec, 8000sec, 9000sec, 10000sec and 10800sec, etc.; and then cooled to 10°C, 20°C, 30°C, 40°C and 50°C, etc.
[0056] like Figure 5 As shown, the second aspect of the present disclosure provides a method for forming a copper-containing conductive structure, comprising the following steps:
[0057] S5. Forming a copper seed layer on the copper barrier layer of the semiconductor device by physical vapor deposition; the copper barrier layer is formed by the method described in the first aspect of the present disclosure;
[0058] S6. Depositing metallic copper on the surface of the semiconductor device having the copper seed crystal layer formed thereon.
[0059] In one embodiment, in step S5, the conditions for the physical vapor deposition treatment of the copper seed crystal include: in the physical vapor deposition furnace, the reaction gas flow rate is 5-300sccm, the gas pressure in the furnace is 0.5-500mTorr, the temperature is 10-50°C, and the treatment time is 0.1-300sec; optionally, the copper precursor is a pure copper target.
[0060] In the present disclosure, the reaction gas flow rate of the copper seed crystal physical vapor deposition process may include but is not limited to 5sccm, 10sccm, 50sccm, 100sccm, 150sccm, 200sccm, 250sccm and 300sccm, and the gas pressure in the furnace may include but is not limited to 0.5mTorr, 1mTorr, 10mTorr, 40mTorr, 80mTorr, 100mTorr, 150mTorr, 200mTorr, 250mTorr, etc. orr, 300mTorr, 350mTorr, 400mTorr, 450mTorr and 500mTorr; the temperature may include but is not limited to 10℃, 20℃, 30℃, 40℃ and 50℃, etc., and the processing time may include but is not limited to 0.1sec, 0.5sec, 1sec, 50sec, 80sec, 100sec, 120sec, 150sec, 180sec, 210sec, 230sec, 260sec and 300sec, etc.
[0061] In a preferred embodiment, in step S5, the conditions for the physical vapor deposition treatment of the copper seed crystal include: a reaction gas flow rate of 10-200 sccm, a gas pressure in the furnace of 1-30 mTorr, a temperature of 20-30° C., and a treatment time of 10-50 sec.
[0062] In a specific embodiment, the thickness of the copper seed layer obtained in step S5 is 100-800A, preferably 400-800A. In the present disclosure, the thickness of the copper seed layer can be but not limited to 100A, 200A, 300A, 400A, 500A, 600A, 700A, and 800A.
[0063] By depositing a copper seed layer on the CoW alloy copper barrier layer obtained according to the method provided in the present disclosure, a more uniform seed layer deposition effect can be achieved and the occurrence of void defects can be avoided.
[0064] In one embodiment, the step of depositing metallic copper in step S6 may be carried out by a conventional electroplating method in the art.
[0065] A third aspect of the present disclosure provides a copper-containing conductive structure of a dual damascene structure, comprising a copper barrier layer disposed between a dielectric layer and a copper interconnect line, wherein the copper barrier layer comprises a CoW alloy.
[0066] In a preferred embodiment, the thickness of the copper barrier layer is 10-500A. In the present disclosure, the thickness of the copper barrier layer can be, but is not limited to, 10A, 50A, 100A, 150A, 200A, 250A, 300A, 350A, 400A, 450A, and 500A.
[0067] The present disclosure is further described in detail by way of examples. The raw materials used in the examples can all be obtained through commercial sources.
[0068] Example 1
[0069] (1) Damascus inlay treatment: The dielectric layer of the substrate is subjected to Damascus inlay treatment to obtain a first substrate having a channel and groove structure; wherein the substrate is made of semiconductor material silicon, the dielectric layer is made of low dielectric constant oxide silicon dioxide, the dielectric constant is 1.5-3, and the thickness of the dielectric layer is 2-5 μm;
[0070] (2) CVD deposition of Co layer: The Co precursor is (3,3-dimethyl-1-butyne) dicobalt hexacarbonyl (CCTBA), and the chemical vapor deposition conditions include: reaction gas flow rate of 10-500sccm, gas pressure in the furnace of 0.001-600Torr, temperature of 20-500°C, and processing time of 1-1200sec; the thickness of the deposited Co layer is 5-300A;
[0071] (3) PVD deposition of W layer: The W target material is pure W target material, and the conditions of physical vapor deposition treatment include: reaction gas flow rate of 5-500sccm, gas pressure in the furnace of 0.5-100mTorr, temperature of 25-500℃, and treatment time of 0.1-300sec; the thickness of the deposited W layer is 5-300A;
[0072] The total thickness of the Co layer and the W layer is 10-500A; the thickness ratio of the Co layer to the W layer is 1:0.01-5.
[0073] (4) Annealing treatment: first increase the temperature to 100-500°C for 30-10800 seconds; then cool down to 10-50°C to obtain a CoW alloy copper barrier layer, the thickness of the obtained CoW alloy copper barrier layer is 10-500A.
[0074] (5) PVD deposition of copper seed layer: The Cu target material is a pure copper target material, and the conditions of physical vapor deposition treatment include: the reaction gas flow rate is 10-200 sccm, the gas pressure in the furnace is 1-30 mTorr, the temperature is 20-30°C, and the treatment time is 10-50 sec to obtain a copper seed layer, and the thickness of the copper seed layer is 100-800 Å;
[0075] (6) Electroplating and deposition of metallic copper: using conventional electroplating methods in the art.
[0076] The copper diffusion depth and conductivity of the copper-containing conductive structure obtained in Example 1 were tested, and the test results showed that: compared with the conventional process, the copper-containing conductive structure obtained in Example 1 using the method provided by the present disclosure has fewer hole defects, lower resistivity, and better copper diffusion barrier effect; compared with the process of depositing Co and W using CVD, the method provided by the present disclosure has the effect of higher purity of the deposited layer (such as the W layer) and lower resistance.
[0077] The preferred embodiments of the present disclosure are described in detail above; however, the present disclosure is not limited to the specific details in the above embodiments. Within the technical concept of the present disclosure, a variety of simple modifications can be made to the technical solution of the present disclosure, and these simple modifications all fall within the protection scope of the present disclosure.
[0078] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the present disclosure will not further describe various possible combinations.
[0079] In addition, various embodiments of the present disclosure may be arbitrarily combined, and as long as they do not violate the concept of the present disclosure, they should also be regarded as the contents disclosed by the present disclosure.
Claims
1. A method for forming a copper barrier layer, characterized in that: The following steps are involved: S1, performing dual damascene processing on the dielectric layer of the semiconductor device to etch holes and grooves in the dielectric layer; S2. Depositing a Co layer on the surface of the etched semiconductor device by chemical vapor deposition in the presence of a Co precursor; S3, depositing a W layer on the surface of the Co layer by physical vapor deposition in the presence of a W target; S4, performing annealing treatment to form a CoW alloy copper barrier layer on the surface of the semiconductor device.
2. The method according to claim 1, characterized in that In step S1, the dielectric layer of the semiconductor device is disposed on a substrate; optionally, the material of the substrate is selected from one or more semiconductor materials; optionally, the semiconductor material is selected from silicon; The material of the dielectric layer is selected from one or more low dielectric constant oxides; optionally, the dielectric constant of the low dielectric constant oxide is 1.5-3.
3. The method according to claim 1, characterized in that In step S2, the Co precursor is selected from one or both of Co2(CO)8 and (3,3-dimethyl-1-butyne) dicobalt hexacarbonyl; Preferably, the chemical vapor deposition conditions include: in the chemical vapor deposition furnace, the reaction gas flow rate is 10-500 sccm, the gas pressure in the furnace is 0.001-600 Torr, the temperature is 20-500° C., and the processing time is 1-1200 sec.
4. The method according to claim 1, characterized in that: The thickness of the Co layer formed in step S2 is 5-300 Å.
5. The method according to claim 1, characterized in that In step S3, the W target is a pure W target; Preferably, the conditions for physical vapor deposition include: in the physical vapor deposition furnace, the reaction gas flow rate is 5-500 sccm, the gas pressure in the furnace is 0.5-100 mTorr, the temperature is 25-500° C., and the processing time is 0.1-300 sec.
6. The method according to claim 1, characterized in that The thickness of the W layer formed in step S3 is 5-300 Å; Preferably, the total thickness of the Co layer and the W layer is 10-500 Å; further preferably, the thickness ratio of the Co layer to the W layer is 1:0.01-5.
7. The method according to claim 1, characterized in that In step S4, the annealing treatment conditions include: firstly raising the temperature to 100-500°C for a heating time of 30-10800 seconds; and then lowering the temperature to 10-50°C.
8. A method for forming a copper-containing conductive structure, characterized in that: The following steps are involved: S5. Forming a copper seed layer on the copper barrier layer of the semiconductor device by physical vapor deposition; the copper barrier layer is formed by the method according to any one of claims 1 to 7; S6. Depositing metallic copper on the surface of the semiconductor device having the copper seed crystal layer formed thereon.
9. A copper-containing conductive structure of a dual Damascus structure, characterized in that: The invention comprises a copper barrier layer arranged between a dielectric layer and a copper interconnection line, wherein the copper barrier layer comprises a CoW alloy.
10. The copper-containing conductive structure according to claim 9, characterized in that: The thickness of the copper barrier layer is 10-500 Å.