Semiconductor structure and forming method thereof

Abstract

The method includes forming a first device die, including: forming an integrated circuit on a semiconductor substrate; and forming an interconnection structure on the semiconductor substrate. The interconnect structure has a plurality of metal layers. The method further includes bonding the second device die to the first device die; and forming a gap-fill region surrounding the second device die. In a first formation process, a first TSV is formed to penetrate a semiconductor substrate, where the first TSV has a first width. In a second formation process, a second TSV is formed to penetrate the semiconductor substrate. The second TSV has a second width different from the first width. The embodiment of the invention also relates to a semiconductor structure and a forming method thereof.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor structures and methods of forming the same. Background Art

[0002] Through silicon vias (TSVs) are used as part of an electrical path in a device die so that conductive features on opposite sides of the device die can be interconnected. The formation process of TSVs may include: etching a semiconductor substrate to form an opening; filling the opening with a conductive material to form the TSV; performing a backside grinding process to remove a portion of the semiconductor substrate from the backside and to expose the TSV; and forming an electrical connector on the backside of the semiconductor substrate to connect to the TSV. Summary of the invention

[0003] Some embodiments of the present application provide a method for forming a semiconductor structure, comprising: forming a first device die, comprising: forming an integrated circuit on a semiconductor substrate; and forming an interconnect structure on the semiconductor substrate, wherein the interconnect structure comprises a plurality of metal layers; bonding a second device die to the first device die; forming a gap-filling region around the second device die; in a first forming process, forming a first through-silicon via (TSV) penetrating the semiconductor substrate, wherein the first through-silicon via has a first width; and in a second forming process, forming a second through-silicon via penetrating the semiconductor substrate, wherein the second through-silicon via has a second width different from the first width.

[0004] Other embodiments of the present application provide a semiconductor structure, including: a first device die, including: a semiconductor substrate; an integrated circuit device, located on the semiconductor substrate; an interconnect structure, located on the integrated circuit device, wherein the interconnect structure includes multiple metal layers; and a first through silicon via (TSV) and a second through silicon via, wherein the first through silicon via and the second through silicon via are bonded on different metal layers of the multiple metal layers; and a second device die, connected to the first device die, wherein the first through silicon via and the second through silicon via are electrically connected to the second device die.

[0005] Some other embodiments of the present application provide a semiconductor structure, comprising: a first device die, comprising: a semiconductor substrate; an integrated circuit device, located on the semiconductor substrate; an interconnect structure, located on the integrated circuit device, wherein the interconnect structure comprises a plurality of metal layers; a first through silicon via (TSV), penetrating the semiconductor substrate, wherein the first through silicon via has a first wider end and a first narrower end narrower than the first wider end, and wherein the first wider end is located on the front side of the semiconductor substrate; and a second through silicon via, having a second wider end and a second narrower end narrower than the second wider end, wherein the second wider end is located on the back side of the semiconductor substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the disclosed embodiments can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0007] Figures 1 to 15 A cross-sectional view illustrating an intermediate stage in the formation of a package and through silicon vias according to some embodiments.

[0008] Figures 16 to 31 A cross-sectional view illustrating an intermediate stage in the formation of a package and through silicon vias according to some embodiments.

[0009] Figure 32 to Figure 34 A cross-sectional view illustrating an intermediate stage in the formation of a package and through silicon vias according to some embodiments.

[0010] Figure 35 to Figure 37 A cross-sectional view illustrating an intermediate stage in the formation of a package and through silicon vias according to some embodiments.

[0011] Figures 38 to 41 A cross-sectional view of a package including a through silicon via is shown in accordance with some embodiments.

[0012] Fig.42 A process flow for forming a package according to some embodiments is shown. DETAILED DESCRIPTION

[0013] The following disclosure provides many different embodiments or examples for realizing different features of the disclosed embodiments. Specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the disclosed embodiments may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0014] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0015] A package and a method for forming the same are provided. According to some embodiments of the present disclosure, a device die is formed, wherein a plurality of through silicon vias (TSVs, also referred to as through holes, substrate through vias, or semiconductor through vias) are formed to penetrate the semiconductor substrate of the device die. A plurality of TSVs may be formed using different processes, such as a first TSV process, a middle TSV process, a last TSV process, and the like. In addition, a plurality of TSVs may have different bonding levels. By adjusting the formation process, the TSVs in the device die may have different widths (lateral dimensions) to meet customized requirements for conducting power and signals while keeping the chip area occupied by the TSVs as small as possible.

[0016] The embodiments discussed herein are intended to provide examples of the subject matter of the disclosed embodiments that can be manufactured or used, and those of ordinary skill in the art will readily appreciate the modifications that can be made while remaining within the contemplation of the different embodiments. Throughout the various views and illustrative embodiments, the same reference numerals are used to represent the same elements. Although the method embodiments may be discussed as being implemented in a particular order, other method embodiments may be implemented in any logical order.

[0017] Figures 1 to 15 A cross-sectional view of an intermediate stage in the formation of a package according to some embodiments of the present disclosure is shown. The process includes forming a first TSV by a TSV-first process and forming a second TSV by a TSV-last process. The package may also involve face-to-back bonding.

[0018] refer to Figure 1 , forming a package assembly 20. According to some embodiments, the package assembly 20 is a device die sawn from a device wafer. According to an optional embodiment, the package assembly 20 is an interposer die, which has no active devices and may or may not include passive devices. According to some other optional embodiments, the package assembly 20 is or includes a package such as an integrated fan-out (InFO) package, a redistribution structure including redistribution lines, etc. Therefore, the package assembly 20 may also be referred to as a device die 20 hereinafter, and it may also have other types.

[0019] According to some embodiments, package assembly 20 includes a semiconductor substrate 24 and components formed at a top surface of semiconductor substrate 24. Semiconductor substrate 24 may be formed of or include crystalline silicon, crystalline germanium, crystalline silicon germanium, carbon-doped silicon, III-V compound semiconductors, etc. Semiconductor substrate 24 may also be a bulk semiconductor substrate or a semiconductor on insulator (SOI) substrate.

[0020] According to some embodiments, package assembly 20 may or may not include an integrated circuit device 26 formed at the front side (top side as shown) of semiconductor substrate 24. According to some embodiments, integrated circuit device 26 may include complementary metal oxide semiconductor (CMOS) transistors, resistors, capacitors, diodes, etc. Details of integrated circuit device 26 are not shown herein.

[0021] According to some embodiments, package assembly 20 includes TSVs 28 (with one TSV 28 shown as an example). TSVs 28 may be electrically connected to integrated circuit device 26. According to some embodiments, TSVs 28 extend from a top surface ( Figure 1 The top surface shown in FIG. 2 extends to an intermediate level of the semiconductor substrate 24. The intermediate level of the semiconductor substrate 24 is located between the top surface and the bottom surface of the semiconductor substrate 24.

[0022] Each of the TSVs 28 may include a TSV liner 28A and a metal material 28B. The TSV liner 28A may include a dielectric isolation layer (such as a SiN layer, a SiO layer, etc.) and a conductive diffusion barrier layer (such as a TiN layer). The metal material 28B may include copper, tungsten, cobalt, etc.

[0023] An interconnect structure 32 is formed over semiconductor substrate 24 and integrated circuit device 26. Interconnect structure 32 may include an interlayer dielectric (ILD, not separately labeled) that fills the spaces between gate stacks (not shown) of transistors in integrated circuit device 26. According to some embodiments, the ILD is formed of silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG), etc. The ILD may be formed using spin coating, flowable chemical vapor deposition (FCVD), etc. According to some embodiments of the present disclosure, the ILD may also be formed using deposition methods such as plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), etc.

[0024] Contact plugs (not shown) are formed in the ILD for electrically connecting the integrated circuit device 26 to the metal lines and vias above. According to some embodiments of the present disclosure, the contact plugs are formed of or include a conductive material selected from tungsten, aluminum, copper, titanium, tantalum, titanium nitride, tantalum nitride, alloys thereof, and / or multilayers thereof. The formation of the contact plugs may include: forming a contact opening in the ILD; filling the conductive material into the contact opening; and performing a planarization process (such as a chemical mechanical polishing (CMP) process or a mechanical grinding process) to make the top surface of the contact plug flush with the top surface of the ILD.

[0025] According to some embodiments, interconnect structure 32 also includes a plurality of dielectric layers above the ILD and a plurality of conductive features in the dielectric layers, such as metal lines / pads and vias. According to some embodiments, the dielectric layer may include a low-k dielectric layer (also referred to as an intermetallic dielectric (IMD)). For example, the dielectric constant (k value) of the low-k dielectric layer may be lower than about 3.5 or 3.0. The low-k dielectric layer may include a carbon-containing low-k dielectric material, hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), etc.

[0026] The formation of metal lines and vias in interconnect structure 32 may include a single damascene process and / or a dual damascene process. Thus, the metal lines and vias may include copper and may also include a diffusion barrier layer formed of TiN, Ti, TaN, Ta, or the like.

[0027] According to some embodiments, interconnect structure 32 includes a top conductive (metal) feature 36, such as a metal line, a metal pad, or a via, in a top dielectric layer (denoted as a dielectric layer), which is a top layer of dielectric layers in interconnect structure 32. According to some embodiments, TSV 28 extends to top metal feature 36, which may be located in the top metal layer. TSV 28 may physically contact top metal feature 36, or may be connected to top metal feature 36 through a via (not shown). Top metal feature 36 in the top dielectric layer may also be formed of copper or a copper alloy, and may have a dual damascene structure or a single damascene structure.

[0028] According to some embodiments, TSV 28 is formed by a mid-TSV process, where the TSV is formed after a large portion of interconnect structure 32 has been formed. For example, the TSV may be formed after a metal layer immediately below the top metal layer has been formed, and before forming top metal feature 36. The formation process may include: etching a dielectric layer in interconnect structure 32 to form a TSV opening; depositing a conformal dielectric liner; depositing a barrier seed layer; and filling the remaining TSV opening with a metal material. A planarization process such as a CMP process is then performed to remove excess material and form TSV 28. Top conductive features (metal pads) 36 are then formed, for example, in a damascene process.

[0029] According to alternative embodiments, TSV 28 may be formed in a TSV-first process, and TSV 28 may be formed before forming interconnect structure 32 , or after forming contact plugs and ILDs of interconnect structure 32 but before forming other metal layers in interconnect structure 32 . Figure 1 A possible hierarchy 40 is shown when TSVs 28 are formed using a TSV-first process.

[0030] According to still other alternative embodiments, some TSVs 28 are formed using the mid-TSV process, while some other TSVs 28 are formed using the first-TSV process. As will be discussed in subsequent processes, TSVs formed using the mid-TSV process are taller (and may be wider) than TSVs formed using the first-TSV process.

[0031] The interconnect structure 32 may also include a passivation layer (not shown) covering the top metal feature 36. The passivation layer may be formed of a non-low-k dielectric material, which may include silicon and another element including oxygen, nitrogen, carbon, etc. For example, the passivation layer may be formed of or include SiON, SiN, SiOCN, SiCN, SiOC, SiC, etc.

[0032] According to some embodiments, each of TSVs 28 is surrounded by a guard ring 42 that completely surrounds the corresponding TSV 28 when viewed from the top. According to some embodiments, each guard ring 42 includes a metal ring in each of the metal layers and each of the via layers into which it extends. The metal rings in multiple via layers and multiple metal layers are interconnected to form a solid metal ring.

[0033] According to some embodiments, the topmost end of the guard ring 42 is located in a metal layer lower than the top end of the corresponding TSV 28. For example, when the TSV 28 extends to the bottom of the top metal feature 36, the guard ring 42 includes a portion (referred to as M (top-1), not separately shown) located in the metal layer immediately below the top metal feature 36. According to some embodiments, the guard ring 42 includes a contact plug portion located in the ILD and at the same level as the contact plug. There may or may not be a metal silicide ring that is lower than the contact plug portion of the guard ring 42 and connected to the contact plug portion of the guard ring 42. According to an optional embodiment, the guard ring 42 has a bottommost surface that is higher than the ILD. The guard ring 42 may be electrically grounded, or may be electrically floating.

[0034] According to some embodiments, a guard ring 44 is also formed in the same process of forming the interconnect structure 32. The guard ring 44 may also include a metal ring in a metal layer and a via ring between the metal rings, wherein the metal ring and the via ring are interconnected to form a solid ring. A metal pad 46 is formed on the guard ring 44 and vertically aligned with the guard ring 44. The guard ring 44 is used to surround the TSV to be formed by a post-TSV process that is subsequently implemented. The metal pad 46 is used to engage the subsequently formed TSV and is used as an etch stop layer for etching a dielectric layer to form a TSV opening. In comparison, in the etching of the TSV opening in which the TSV 28 (formed by a first TSV or a middle TSV process) is formed, an etch stop layer is not used, and the etching stops inside the semiconductor substrate 24.

[0035] refer to Figure 2 , the device die 20 is attached to the carrier 22, wherein the front side of the device die 20 (such as a dielectric bonding film (not shown)) faces and is attached to the carrier 22. The corresponding process is shown as Fig.42 Process 202 in process flow 200 is shown in FIG. 2. It should be understood that although one device die 20 is shown, there are multiple device dies 20 attached, and the multiple device dies 20 may be arranged in an array.

[0036] According to some embodiments, carrier 22 includes a bulk semiconductor carrier such as a silicon carrier and a bonding layer on the bulk semiconductor carrier. The bonding layer may be formed of a silicon-containing dielectric material selected from SiO, SiC, SiN, SiON, SiOC, SiCN, SiOCN, etc. or a combination thereof. According to some embodiments, device die 20 may be attached to carrier 22 by fusion bonding, wherein a surface bonding layer of device die 20 is bonded to a bonding layer in carrier 22.

[0037] According to an alternative embodiment, carrier 22 includes a transparent substrate, such as a glass substrate. An adhesive such as a light-to-heat conversion (LTHC) material (not shown) is applied on carrier 22, wherein the LTHC material is configured to decompose under the heat of light, such as a laser beam.

[0038] Next, as Figure 2 As shown in , a gap filling process is performed to fill the gaps between adjacent device dies 20 and to seal the device dies 20 in a gap filling layer 48 (also referred to as a sealant). The corresponding process is shown as Fig.42 204 of the process flow 200 shown in FIG. 204. According to some embodiments, the gap-filling layer 48 includes a dielectric liner and a dielectric gap-filling layer over the dielectric liner. The dielectric liner and the dielectric gap-filling layer are not shown separately.

[0039] The dielectric liner may be formed of a material that has good adhesion to the device die 20. According to some embodiments, the dielectric liner is formed of or includes silicon nitride. The dielectric liner may be formed in a conformal deposition process and may therefore be a conformal layer. The dielectric gap fill layer may be formed of an oxide-based dielectric material, such as silicon oxide, silicon oxynitride, silicate glass, etc. The dielectric liner and the dielectric gap fill layer may be formed by a deposition process.

[0040] According to alternative embodiments, the gap-fill layer 48 is formed of or includes a molding compound, a molded underfill, etc. A corresponding process may include: dispensing a dielectric material in a flowable form; and curing the dielectric material.

[0041] After the gap filling process, a patterned etching mask 50 is formed. The corresponding process is shown as follows Fig.42 The process 206 in the process flow 200 shown in FIG. The patterned etch mask 50 may include a patterned photoresist and may be a single-layer etch mask, a double-layer etch mask including a bottom anti-reflective coating and a photoresist, or a triple-layer etch mask including a bottom layer, a middle layer, and a top layer. The device die 20 is located directly below the opening 52 in the etch mask 50.

[0042] Next, if Figure 3 As shown in FIG. 5 , the portion of the gap filling layer 48 directly above the semiconductor substrate 24 is etched through the opening 52 to expose the semiconductor substrate 24. The corresponding process is shown as follows: Fig.42 The process 208 in the process flow 200 is shown in FIG. Then, the etching mask 50 is removed, for example, in an ashing process, an etching process, or the like.

[0043] refer to Figure 4A planarization process such as a CMP process or a mechanical polishing process is performed to remove excess portions of the semiconductor substrate 24 and the gap filling layer 48. Thus, the TSV 28 is exposed. The corresponding process is shown as follows Fig.42 The remaining portion of gap-fill layer 48 is referred to hereinafter as gap-fill region 48 or encapsulant 48 .

[0044] refer to Figure 5 , a pad layer 54 and a hard mask 56 are formed by deposition. According to some embodiments, the pad layer 54 may be formed of or include silicon oxide. The hard mask 56 may be formed of or include silicon nitride, boron nitride, etc., however other suitable materials may be used.

[0045] Figures 6 to 9 The formation of TSVs by a TSV-last process is shown in accordance with some embodiments. The process is so named because the formation of the TSVs is after the formation of the front-side structures of the device die 20. Figure 6 , an etching process is performed to form a TSV opening 58. The corresponding process is shown as follows Fig.42 The etching may be performed using a patterned etch mask (not shown) such as a patterned photoresist, which defines the pattern, location, and size of the plurality of TSV openings 58 .

[0046] The etching is performed by an anisotropic etching process, and hard mask 56, pad layer 54, and semiconductor substrate 24 are etched. After the etching process, the patterned etching mask is removed, for example, by ashing, etching, etc. In the etching process, metal pad 46 serves as an etching stop layer. TSV opening 58 is surrounded by preformed guard ring 44 and is spaced apart from preformed guard ring 44 by a dielectric material.

[0047] In the subsequent process, a dielectric isolation film 60 is formed. The corresponding process is shown as follows. Fig.42 The process 214 in the process flow 200 shown in FIG. The formation process may include: a conformal deposition process to conformally deposit the dielectric isolation film 60 ; and an anisotropic etching process to remove the horizontal portion of the dielectric isolation film 60 to expose the metal pad 46 .

[0048] refer to Figure 7 , for example, forming a barrier seed layer 62 in a conformal deposition process. The corresponding process is also shown as Fig.42214 in the process flow 200 shown in FIG. The barrier seed layer 62 may include a conductive barrier layer such as a TiN layer, a TaN layer, etc. and a metal seed layer over the conductive barrier layer. The metal seed layer may include copper and may or may not include a titanium layer. According to some embodiments, the barrier seed layer 62 may be formed by physical vapor deposition (PVD).

[0049] Next, refer to Figure 8 , for example, by depositing a metal material through a plating process to fill the TSV opening. The corresponding process is shown as Fig.42 Process 216 in process flow 200 is shown in FIG. According to some embodiments, metal material 64 includes copper, tungsten, cobalt, or the like.

[0050] In a subsequent process, a planarization process such as a CMP process or a mechanical process is performed to remove excess portions of the metal material 64, the barrier seed layer 62, and the dielectric isolation film 60. The pad layer 54 and the hard mask 56 may also be removed by the planarization process, wherein the semiconductor substrate 24 may be used as a CMP stop layer. The remaining portions of the barrier seed layer 62 and the metal material 64 together form a TSV 66, which is surrounded by the dielectric isolation film 60. The resulting structure is Fig. 9 The corresponding process is shown as Fig.42 Process 218 in process flow 200 is shown in FIG.

[0051] In subsequent processes, such as Fig.10 As shown in FIG. 1 , the semiconductor substrate 24 in the device die 20 may be recessed so that the top portions of the TSVs 28 and 66 protrude above the semiconductor substrate 24. The corresponding process is shown as Fig.42 2. Meanwhile, gap-fill region 48 may or may not be recessed. According to some embodiments, TSV 66 protrudes higher than TSV 28.

[0052] refer to Fig.11 and Fig.12 , forming a dielectric isolation film 68. The corresponding process is shown as follows Fig.42 The process 222 in the process flow 200 shown in FIG. The formation of the dielectric isolation film 68 may include performing a deposition process to deposit the dielectric isolation film 68 into the recess such that the protruding portions of the TSVs 28 and 66 are located in the dielectric isolation film 68, such as Fig.11 as shown in .

[0053] Next, if Fig.12 As shown in FIG. 1 , a planarization process is performed. The portion of the dielectric isolation film 68 located above the TSVs 28 and 66 is removed, and the remaining portion of the dielectric isolation film 68 forms the dielectric isolation film 68, as shown in FIG. Fig.12as shown in .

[0054] refer to Fig.12 and Fig.13 , a redistribution structure 70 electrically connected to the TSVs 28 and 60 is formed over the TSVs 28 and 60. The corresponding process is shown as follows Fig.42 224 in the process flow 200 shown in . According to some embodiments, the redistribution structure 70 includes a dielectric layer 72 and a conductive feature 74 in the dielectric layer 72. According to some embodiments, the dielectric layer 72 may include an inorganic dielectric material that may be selected from SiO, SiC, SiN, SiON, SiOC, SiCN, SiOCN, etc. or a combination thereof. Alternatively, the dielectric layer 72 may include an organic dielectric material such as a polymer, which may include polyimide, polybenzoxazole (PBO), etc.

[0055] For example, Fig.12 As shown in FIG. 1 , a metal pad 74 is formed as part of a conductive component 74. A dielectric layer 72 is also formed, wherein the metal pad 74 is located in the dielectric layer 72. The formation process may include a damascene process. Next, more dielectric layers 72 and conductive components 74 may be formed, such as Fig.13 Conductive features 74 may include metal pads, redistribution lines, etc., and may include bonding pads as top features of redistribution structure 70 .

[0056] refer to Fig.13 , device die 76 (also referred to as top die) is bonded to device die 20. The corresponding process is shown as Fig.42 200. Although one device die 76 is shown, the device die 76 shown represents a plurality of device dies 76, each located above and bonded to one of the underlying device dies 20. The bonding may be performed by a face-to-back bonding process, in which the front side of the device die 76 is bonded to the back side of the device die 20. According to some embodiments, each of the device dies 76 may be a logic die, which may be a central processing unit (CPU) die, a microcontroller (MCU) die, an input-output (IO) die, a baseband die, etc. The device die 76 may also include a memory die.

[0057] Device die 76 may include a semiconductor substrate 78, which may be a silicon substrate. Device die 76 includes integrated circuit devices (such as transistors) 80 and interconnect structures 82 for connecting to active and passive devices in device die 76. Interconnect structures 82 include metal lines and vias 83, as schematically shown.

[0058] Each of the device dies 76 includes a bonding pad 84 and a bonding layer 86 (also referred to as a bonding film) located at the bottom surface of the device die 76. The bonding can be achieved by hybrid bonding. For example, the bonding pad 84 is bonded to the conductive component 74 by metal-to-metal direct bonding. According to some embodiments, the metal-to-metal direct bonding includes copper-to-copper direct bonding. In addition, the bonding layer 86 of the device die 76 is bonded to the dielectric layer 72 by fusion bonding, for example, wherein Si-O-Si bonds are generated.

[0059] According to some embodiments, Fig.13 As shown in FIG. 1 , a plurality of dummy dies 88 are also attached to the underlying structure. The corresponding process is also shown as Fig.42 226 in the process flow 200 shown in FIG. According to some embodiments, each of the dummy dies 88 is attached by a layer 90. The layer 90 may be a bonding layer including a silicon-containing dielectric material, which may be selected from SiO, SiC, SiN, SiON, SiOC, SiCN, SiOCN, etc., or a combination thereof. The attachment may be performed by bonding the bonding layer 90 to the dielectric layer 72 by fusion bonding.

[0060] According to an alternative embodiment, the entire dummy die 88 is formed of a homogeneous material without other materials and structures. The dummy die 88 may be formed of Si, SiC, SiO, SiN, etc., which may be directly bonded to the dielectric layer 72 by fusion bonding.

[0061] refer to Fig.14 , a gap filling region 92 (also referred to as a sealant) is formed in the gap filling process. The corresponding process is shown as follows Fig.42 228 in the process flow 200 shown in . The formation process, structure and material of the gap fill region 92 can be selected from the candidate formation process, candidate structure and candidate material of the gap fill region 48. For example, the gap fill region 92 can include a dielectric liner and a dielectric gap fill layer above the dielectric liner. Optionally, the gap fill region 92 can include a molding compound, a molded underfill, etc. A planarization process is performed to make the top surfaces of the semiconductor substrate 78 of the device die 76, the dummy die 88 and the gap fill region 92 flush. Throughout the description, the structure above the carrier 22 is referred to as the reconstructed wafer 100.

[0062] Then, the reconstituted wafer 100 is peeled off from the carrier 22. The corresponding process is shown as follows. Fig.42200. According to some embodiments where the carrier 22 includes a silicon wafer, the carrier 22 may be removed by a smart cutting process, which includes, for example, implanting the carrier 22 with hydrogen to generate a stress concentration layer; and annealing the carrier 22 so that the carrier 22 may be separated at the stress concentration layer. The remaining portion of the carrier 22 may be removed by, for example, an etching process, a CMP process, or a mechanical grinding process.

[0063] According to an alternative embodiment where carrier 22 is a glass carrier, reconstituted wafer 100 may be peeled from carrier 22 by projecting a laser beam onto the LTHC coating material, causing the LTHC coating material to decompose, releasing reconstituted wafer 100 from carrier 22 .

[0064] Next, if Fig.15 As shown in , an electrical connector 94 is formed. The electrical connector 94 may include a solder area, a metal column, etc. The corresponding process is shown as Fig.42 The process 232 in the process flow 200 shown in FIG.

[0065] In the subsequent process, Fig.15 As shown in , the reconstructed wafer 100 is singulated in a sawing process to form discrete packages 100 ′. Discrete packages 100 ′ include device dies 20 and 76 , and may also include dummy die 88 , in accordance with some embodiments.

[0066] Figures 16 to 31 A cross-sectional view of an intermediate stage in the formation of a package according to an optional embodiment of the present disclosure is shown. These processes and structures (rather than including TSVs formed by middle TSV (or first TSV) and post TSV processes) include two post TSV processes to produce TSVs with different sizes and bonding positions. Unless otherwise stated, the materials, structures, and formation processes of the components in these embodiments are substantially the same as the same components represented by the same reference numerals in the aforementioned embodiments. Throughout the description, the details of the materials, structures, and formation processes provided in each of the embodiments can be applied to any other embodiment whenever applicable.

[0067] refer to Fig.16 , device die 20 is formed and attached to carrier 22. Device die 20 includes semiconductor substrate 24, and may (or may not) include integrated circuit device 26. In addition, guard ring 44 (including guard rings 44A and 44B) and metal pad 46 (including metal pad 46A and 46B) are formed. According to some embodiments, guard ring 44A has a smaller height than guard ring 44B and extends into fewer metal layers than guard ring 44B.

[0068] The lateral dimension LD1 (such as a diameter depending on the top view shape) of the guard ring 44A can be smaller than the lateral dimension LD2 (such as a diameter depending on the top view shape) of the guard ring 44B. For example, the ratio LD2 / LD1 can be in the range between about 1 and about 70, and can be in the range between about 5 and about 60 or about 10 and about 50.

[0069] Furthermore, according to some embodiments, metal pad 46A may be located at a higher position than metal pad 46B. For example, metal pad 46A may be located immediately below the ILD and may be in contact with the ILD. On the other hand, metal pad 46B may be located in any metal layer between the ILD and the top metal layer (when device die 20 is viewed upside down), or may be located in the top metal layer.

[0070] like Fig.16 As further shown in FIG. 4 , a gap fill layer 48 is formed, followed by an etch mask 50. The etch mask 50 is then patterned, and an opening 52 is formed to overlap the device die 20, as shown in FIG. Fig.17 The next step is as shown in Fig.18 As shown in FIG. 1 , the portion of gap fill layer 48 exposed to opening 52 is removed in an etching process. Etch mask 50 is then removed, followed by a planarization process to expose semiconductor substrate 24. The resulting structure is Fig.19 Shown in.

[0071] Figure 20 to Figure 23 A first post-TSV process for forming TSV 66A according to some embodiments is shown. Fig. 20 , a pad layer 54A and a hard mask 56A are formed by a deposition process. The materials and formation of the pad layer 54A and the hard mask 56A may be respectively Figure 7 The pad layer 54A and the hard mask 56A are substantially the same. The pad layer 54A and the hard mask 56A and the underlying semiconductor substrate 24 are then etched to form an opening 58A, which is surrounded by the guard ring 44A. Fig.21 As shown in , metal pad 46A is exposed.

[0072] Fig.21 Also shown is the formation of dielectric isolation film 60A, which involves depositing a dielectric layer and removing horizontal portions of the dielectric layer by an anisotropic etching process. The bottom portion of the dielectric layer on metal pad 46A is thus removed, exposing metal pad 46A.

[0073] Fig. 22 The formation of the barrier seed layer 62A and the deposition of the conductive material 64A, for example, by plating are shown. The materials and formation processes of the barrier seed layer 62A and the conductive material 64A may be respectively as shown in FIG. Figure 8The materials and formation processes of the barrier seed layer 62 and the conductive material 64 shown in FIG. Fig.23 As shown in FIG. 5 , a planarization process is performed to remove excess portions of the dielectric isolation film 60A, the barrier seed layer 62A, and the conductive material 64A. Thus, a TSV 66A is formed by the first TSV-last process. In the planarization process, the pad layer 54A may be used as a CMP stop layer.

[0074] Figure 24 to Figure 26 It is shown that TSV 66B is formed by a second TSV-last process according to some embodiments. The materials and processes of TSV 66B may be substantially the same as those of TSV 66A and are not repeated here. Fig.24 The formation of pad layer 54B and hard mask 56B is shown. Fig.25 The formation of dielectric isolation film 60B, barrier liner layer 62B, and metal material 64B is shown. Fig.26 A planarization process is shown to remove excess portions of the dielectric isolation film 60B, the barrier seed layer 62B, and the conductive material 64B. Thus, the TSV 66B is formed by the second TSV-last process.

[0075] In the processes discussed above, the openings of TSV 66A and 66B are formed in different processes and are also filled in different processes. According to an optional embodiment, the openings of TSV 66A (with corresponding openings 58) and TSV 66B (with corresponding openings, not shown) can be formed in different processes and filled in a common process. Therefore, dielectric liners 60A and 60B can be formed in different processes or in a common deposition process. Therefore, dielectric liners 60A and 60B can have the same or different materials and / or the same or different thicknesses. Barrier seed layers 62A and 62B can have the same or different materials and / or the same or different thicknesses.

[0076] Figures 27 to 30 The formation of structures over device die 20 is shown. Fig. 27 Semiconductor substrate 24 is shown recessed such that TSVs 66A and 66B protrude from the backside of semiconductor substrate 24 . Fig.28 Deposition of dielectric isolation film 68 is shown, followed by a planarization process to remove excess portions of dielectric isolation film 68 such that top surfaces of TSVs 66A and 66B are exposed.

[0077] Fig.29 and Fig.30 Also shown is the formation of redistribution structure 70 and the subsequent bonding of device die 76 and dummy die 88. Then, gap fill region 92 is formed, as shown in FIG. Fig.30 As shown in , to form a reconstructed wafer 100 .

[0078] In the subsequent process, the reconstituted wafer 100 is peeled off from the carrier 22, followed by forming the electrical connector 94, such as Fig.31 Then, the reconstructed wafer 100 is sawn into packages 100 ′.

[0079] Figure 32 to Figure 34 1 shows a cross-sectional view of an intermediate stage in the formation of a package according to some embodiments of the present disclosure. Figures 1 to 15 The embodiment shown in is basically the same as that shown in (which includes a middle TSV (or TSV first) process and a last TSV process), except that a face-to-face bonding is implemented instead of a face-to-back bonding. Therefore, the details can be obtained from Figures 1 to 15 A discussion of the embodiments shown in is found.

[0080] refer to Fig.32 , device die 20 is bonded to device die 76 by a surface-to-surface bonding process. TSV 28 is formed by a TSV-first process, for example, by contacting TSV 28 to a metal pad in a metal layer (M0 or M1) closest to semiconductor substrate 24. Gap-fill region 48 is formed to seal device die 76. Then, the structure including device dies 20 and 76 is attached to carrier 22.

[0081] refer to Fig.33 , thinning the semiconductor substrate 24, followed by forming TSV 66 by a post-TSV process. The details of the formation process can be referred to Figures 5 to 9 turn up. Fig.34 The formation of electrical connectors 94 is shown according to some embodiments. Reconstructed wafer 100 is thus formed. In subsequent processing, reconstructed wafer 100 is peeled from carrier 22 and may be sawn into packages.

[0082] Figure 35 to Figure 37 1 shows a cross-sectional view of an intermediate stage in the formation of a package according to an alternative embodiment of the present disclosure. Figures 16 to 31 The embodiment shown in (which includes two post-TSV processes) is essentially the same, except that face-to-face bonding is performed instead of face-to-back bonding. Therefore, the details can be obtained from Figures 16 to 31 A discussion of the embodiments shown in is found.

[0083] refer to Fig.35 , forming device die 20. Device die 20 includes metal pads 46A and 46B in different metal layers and guard rings 44A and 44B having different lateral dimensions LD1 and LD2. Device die 76 is bonded to device die 20 by surface-to-surface bonding, for example, where bonding pads are bonded to each other and dielectric bonding layers are bonded to each other.

[0084] refer to Fig.36, gap fill region 48 is formed to seal device die 76, and the resulting structure is attached to carrier 22. TSV 66B is formed by a first TSV-last process, where TSV 66B is bonded to metal pad 46B in the top metal layer (when the device die is viewed upside down, as shown in FIG. Fig.35 ), the top metal layer is furthest from semiconductor substrate 24 than the other metal layers. The structure including device dies 20 and 76 is then attached to carrier 22.

[0085] Fig.37 The formation of TSV 66A by the second TSV-last process is shown. TSV 66A may be bonded to metal pad 46A in the metal layer (M0 or M1) closest to semiconductor substrate 24. The details of the formation process may be referred to Figure 20 to Figure 26 Then, you can implement Figures 27 to 31 The process shown in is performed to complete the formation and sawing process of the reconstructed wafer 100 .

[0086] In the process discussed above, two or more TSV formation processes may be implemented, each selected from a first TSV process, a middle TSV process, and a last TSV process. Dividing the formation of TSV into different formation processes can advantageously allow the TSV to have different lateral dimensions, and / or to be bonded to metal pads in different metal layers without unnecessarily and unfavorably increasing their lateral dimensions. This may be suitable for customized circuit requirements. For example, a power TSV for conducting power may need to have a larger lateral dimension to conduct high currents. Therefore, the power TSV may occupy a large chip area. On the other hand, the signal TSV can be formed narrower without sacrificing its function of conducting signals. In addition, more signal TSVs may be required than power TSVs.

[0087] According to an embodiment of the present disclosure, by forming TSVs through two or more formation processes, TSVs can be formed to have the maximum aspect ratio (ratio of height to width) allowed by the corresponding formation processes, while still having two or more different width types to meet circuit requirements with minimal chip area usage. For example, Fig.15 and Fig.34 TSV 28 and Fig.31 and Fig.37 TSV 66B in FIG. 5 may be used to form a power TSV and may be taller and wider. Fig.15 and Fig.34 TSV66 and Fig.31 and Fig.37 The TSV 66A in may be used to form a signal TSV and may be shorter and narrower.

[0088] According to some embodiments, TSVs formed using different processes may still have the same aspect ratio when having different heights and different lateral dimensions, which is the maximum aspect ratio allowed by the formation technology.

[0089] Fig.38 A package formed by surface-to-surface bonding according to some embodiments is shown, and includes TSVs 28 formed by a mid-TSV process and TSVs 66 formed by a last-TSV process. Fig.39 A package formed by surface-to-surface bonding according to some embodiments is shown, and includes TSVs 66A and TSVs 66B formed by two TSV-last processes.

[0090] It should be understood that it is possible to discover and determine from the structure whether the TSV is formed by a TSV-first, TSV-middle, or TSV-last process. For example, when the TSV-first or TSV-middle process is used, the portion of the TSV closer to the front side of the semiconductor substrate is wider than the portion of the TSV closer to the back side of the semiconductor substrate, which is opposite to the TSV formed by the TSV-last process. In addition, it is possible to determine whether the TSV-first or TSV-middle process is used from the position of the metal pad to which the TSV is bonded. For example, when the metal pad is closer to the semiconductor substrate, it can be determined that the TSV-first process is used, and when the metal pad is far away from the semiconductor substrate, it can be determined that the TSV-last process is used.

[0091] Fig.40 and Fig.41 Some details of TSVs, guard rings and metal pads and corresponding metal layers are shown according to some embodiments. TSV 28 includes dielectric liner 28DL, barrier seed layer 28BS and fill metal 28FM. Corresponding layers of TSVs 66, 66A and 66B are also shown and labeled.

[0092] It should be understood that although TSVs formed using a TSV-first process or a TSV-middle process, TSVs formed using a first TSV-last process, and TSVs formed using a second TSV-last process are shown through different embodiments, these TSVs can be formed in the same device die in any combination to accommodate different circuit requirements.

[0093] In the embodiments shown above, some processes and components are discussed according to some embodiments of the present disclosure to form a three-dimensional (3D) package. Other components and processes may also be included. For example, a test structure may be included to help 3D packages or 3DIC devices perform verification tests. The test structure may include, for example, test pads formed in a redistribution layer or on a substrate, which allow testing of 3D packages or 3DICs, using probes and / or probe cards, etc. Verification tests may be implemented on intermediate structures as well as final structures. In addition, the structures and methods disclosed herein may be used in combination with test methods that incorporate intermediate verification of known good dies to increase yield and reduce costs.

[0094] The embodiments of the present disclosure have some advantageous features. By separating the formation of TSVs with different functions into different TSV formation processes, the resulting TSVs can have the largest aspect ratio, thus having the advantageous feature of occupying the smallest possible chip area, while still meeting the different requirements required by the circuit.

[0095] According to some embodiments of the present disclosure, a method includes: forming a first device die, including: forming an integrated circuit on a semiconductor substrate; and forming an interconnect structure on the semiconductor substrate, wherein the interconnect structure includes a plurality of metal layers; bonding a second device die to the first device die; forming a gap-filling region around the second device die; in a first forming process, forming a first TSV penetrating the semiconductor substrate, wherein the first TSV has a first width; and in a second forming process, forming a second TSV penetrating the semiconductor substrate, wherein the second TSV has a second width different from the first width. In an embodiment, the first TSV and the second TSV are formed to have different heights and the same aspect ratio.

[0096] In an embodiment, both the first TSV and the second TSV are formed using a TSV-last process. In an embodiment, forming the first TSV includes a first etching process to etch the semiconductor substrate and to form a first opening penetrating the semiconductor substrate; and forming the second TSV includes a second etching process to etch the semiconductor substrate and to form a second opening penetrating the semiconductor substrate, wherein the first opening and the second opening are formed in different etching processes. In an embodiment, the first TSV is formed before the second device die is bonded to the first device die, and the second TSV is formed after the second device die is bonded to the first device die, and the second TSV extends from the back side of the semiconductor substrate into the semiconductor substrate.

[0097] In an embodiment, the method further comprises: forming a first guard ring surrounding the first TSV before the second device die is bonded to the first device die; and forming a second guard ring surrounding the gap filled with dielectric material, wherein the second TSV is formed to be inserted into the gap surrounded by the second guard ring. In an embodiment, the first TSV is formed using a mid-TSV process, and the second TSV is formed using a post-TSV process.

[0098] In an embodiment, the first TSV is formed using a TSV-first process, and the second TSV is formed using a TSV-last process. In an embodiment, the second device die is bonded to the first device die by face-to-back bonding, wherein the front side of the second device die faces the back side of the first device die. In an embodiment, the second device die is bonded to the first device die by face-to-face bonding, wherein the front side of the second device die faces the front side of the first device die.

[0099] According to some embodiments of the present disclosure, a structure includes: a first device die, including: a semiconductor substrate; an integrated circuit device, located on the semiconductor substrate; an interconnect structure, located on the integrated circuit device, wherein the interconnect structure includes a plurality of metal layers; and a first TSV and a second TSV, wherein the first TSV and the second TSV are bonded on different metal layers of the plurality of metal layers; and a second device die, connected to the first device die, wherein the first TSV and the second TSV are electrically connected to the second device die. In an embodiment, the first TSV has a first wider end and a first narrower end narrower than the first wider end, wherein the first wider end is located on the front side of the semiconductor substrate; and the second TSV has a second wider end and a second narrower end narrower than the second wider end, and wherein the second wider end is located on the back side of the semiconductor substrate.

[0100] In an embodiment, the first TSV has a first wider end and a first narrower end narrower than the first wider end; and the second TSV has a second wider end and a second narrower end narrower than the second wider end, wherein the first wider end and the second wider end are both located on the back side of the semiconductor substrate. In an embodiment, the first TSV has a first wider end and a first narrower end narrower than the first wider end; and the second TSV has a second wider end and a second narrower end narrower than the second wider end, wherein the first narrower end and the second narrower end are located at different levels of the first device die. In an embodiment, the first TSV and the second TSV have different heights.

[0101] According to some embodiments of the present disclosure, a structure includes: a first device die, including: a semiconductor substrate; an integrated circuit device, located on the semiconductor substrate; an interconnect structure, located on the integrated circuit device, wherein the interconnect structure includes multiple metal layers; a first TSV, penetrating the semiconductor substrate, wherein the first TSV has a first wider end and a first narrower end narrower than the first wider end, and wherein the first wider end is located on the front side of the semiconductor substrate; and a second TSV, having a second wider end and a second narrower end narrower than the second wider end, wherein the second wider end is located on the back side of the semiconductor substrate.

[0102] In an embodiment, the structure further comprises: a second device die bonded to the first device die, wherein the second device die is located on the back side of the semiconductor substrate. In an embodiment, the structure further comprises: a first metal pad contacting the first TSV; and a second metal pad contacting the second TSV, wherein the first metal pad and the second metal pad are located in different metal layers of the interconnect structure. In an embodiment, the first TSV is surrounded by a first dielectric liner, and the second TSV is surrounded by a second dielectric liner, and the first dielectric liner and the second dielectric liner are formed of different materials. In an embodiment, the first TSV comprises a first barrier layer, and the second TSV comprises a second barrier layer, and the first barrier layer and the second barrier layer comprise different materials.

[0103] Some embodiments of the present application provide a method, comprising: forming a first device die, comprising: forming an integrated circuit on a semiconductor substrate; and forming an interconnect structure on the semiconductor substrate, wherein the interconnect structure comprises a plurality of metal layers; bonding a second device die to the first device die; forming a gap-filling region around the second device die; in a first forming process, forming a first through-silicon via (TSV) penetrating the semiconductor substrate, wherein the first through-silicon via has a first width; and in a second forming process, forming a second through-silicon via penetrating the semiconductor substrate, wherein the second through-silicon via has a second width different from the first width.

[0104] In some embodiments, the first through silicon via and the second through silicon via are formed to have different heights and the same aspect ratio. In some embodiments, the first through silicon via and the second through silicon via are both formed using a post-through silicon via process. In some embodiments, forming the first through silicon via includes a first etching process to etch the semiconductor substrate and to form a first opening penetrating the semiconductor substrate; and forming the second through silicon via includes a second etching process to etch the semiconductor substrate and to form a second opening penetrating the semiconductor substrate, wherein the first opening and the second opening are formed in different etching processes. In some embodiments, the first through silicon via is formed before the second device die is bonded to the first device die, and the second through silicon via is formed after the second device die is bonded to the first device die, and the second through silicon via extends from the back side of the semiconductor substrate into the semiconductor substrate. In some embodiments, the method further includes: before the second device die is bonded to the first device die, forming a first guard ring surrounding the first through silicon via; and forming a second guard ring surrounding a gap filled with a dielectric material, wherein the second through silicon via is formed to be inserted into the gap surrounded by the second guard ring. In some embodiments, the first through silicon via is formed using a mid-through silicon via process, and the second through silicon via is formed using a last through silicon via process. In some embodiments, the first through silicon via is formed using a first through silicon via process, and the second through silicon via is formed using a last through silicon via process. In some embodiments, the second device die is bonded to the first device die by face-to-back bonding, wherein the front side of the second device die faces the back side of the first device die. In some embodiments, the second device die is bonded to the first device die by face-to-face bonding, wherein the front side of the second device die faces the front side of the first device die.

[0105] Other embodiments of the present application provide a structure comprising: a first device die, comprising: a semiconductor substrate; an integrated circuit device, located on the semiconductor substrate; an interconnect structure, located on the integrated circuit device, wherein the interconnect structure comprises a plurality of metal layers; and a first through silicon via (TSV) and a second through silicon via, wherein the first through silicon via and the second through silicon via are bonded to different metal layers of the plurality of metal layers; and a second device die, connected to the first device die, wherein the first through silicon via and the second through silicon via are electrically connected to the second device die.

[0106] In some embodiments, the first through silicon via has a first wider end and a first narrower end narrower than the first wider end, wherein the first wider end is located on the front side of the semiconductor substrate; and the second through silicon via has a second wider end and a second narrower end narrower than the second wider end, and wherein the second wider end is located on the back side of the semiconductor substrate. In some embodiments, the first through silicon via has a first wider end and a first narrower end narrower than the first wider end; and the second through silicon via has a second wider end and a second narrower end narrower than the second wider end, wherein both the first wider end and the second wider end are located on the back side of the semiconductor substrate. In some embodiments, the first through silicon via has a first wider end and a first narrower end narrower than the first wider end; and the second through silicon via has a second wider end and a second narrower end narrower than the second wider end, wherein the first narrower end and the second narrower end are located at different levels of the first device die. In some embodiments, the first through silicon via and the second through silicon via have different heights.

[0107] Still other embodiments of the present application provide a structure comprising: a first device die comprising: a semiconductor substrate; an integrated circuit device located on the semiconductor substrate; an interconnect structure located on the integrated circuit device, wherein the interconnect structure comprises a plurality of metal layers; a first through silicon via (TSV) penetrating the semiconductor substrate, wherein the first through silicon via has a first wider end and a first narrower end narrower than the first wider end, and wherein the first wider end is located on the front side of the semiconductor substrate; and a second through silicon via having a second wider end and a second narrower end narrower than the second wider end, wherein the second wider end is located on the back side of the semiconductor substrate.

[0108] In some embodiments, the structure further comprises: a second device die bonded to the first device die, wherein the second device die is located on the back side of the semiconductor substrate. In some embodiments, the structure further comprises: a first metal pad contacting the first through silicon via; and a second metal pad contacting the second through silicon via, wherein the first metal pad and the second metal pad are located in different metal layers of the interconnect structure. In some embodiments, the first through silicon via is surrounded by a first dielectric liner, and the second through silicon via is surrounded by a second dielectric liner, and the first dielectric liner and the second dielectric liner are formed of different materials. In some embodiments, the first through silicon via comprises a first barrier layer, and the second through silicon via comprises a second barrier layer, and the first barrier layer and the second barrier layer comprise different materials.

[0109] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the embodiments of the present disclosure. Those skilled in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A method for forming a semiconductor structure, comprising: Forming a first device die, comprising: forming an integrated circuit on a semiconductor substrate; and forming an interconnect structure on the semiconductor substrate, wherein the interconnect structure comprises a plurality of metal layers; bonding a second device die to the first device die; forming a gap-fill region around the second device die; In a first forming process, forming a first through silicon via (TSV) penetrating the semiconductor substrate, wherein the first through silicon via has a first width; and In a second forming process, a second through silicon via is formed penetrating the semiconductor substrate, wherein the second through silicon via has a second width different from the first width.

2. The method according to claim 1, wherein: The first through silicon via and the second through silicon via are formed to have different heights and the same aspect ratio.

3. The method according to claim 1, wherein: The first through silicon via and the second through silicon via are both formed by using a through silicon via last process.

4. The method according to claim 3, wherein: Forming the first through silicon via comprises a first etching process to etch the semiconductor substrate and to form a first opening penetrating the semiconductor substrate; as well as Forming the second through silicon via includes a second etching process to etch the semiconductor substrate and to form a second opening penetrating the semiconductor substrate, wherein the first opening and the second opening are formed in different etching processes.

5. The method according to claim 1, wherein: The first TSV is formed before the second device die is bonded to the first device die, and the second TSV is formed after the second device die is bonded to the first device die, and the second TSV extends from a back side of the semiconductor substrate into the semiconductor substrate.

6. The method according to claim 5, further comprising: Before the second device die is bonded to the first device die, forming a first guard ring surrounding the first through silicon via; as well as A second guard ring is formed surrounding the space filled with the dielectric material, wherein the second through silicon via is formed to be inserted into the space surrounded by the second guard ring.

7. The method according to claim 5, wherein: The first through silicon via is formed using a middle through silicon via process, and the second through silicon via is formed using a last through silicon via process.

8. The method according to claim 5, wherein: The first through silicon via is formed using a through silicon via first process, and the second through silicon via is formed using a through silicon via last process.

9. A semiconductor structure comprising: A first device die, comprising: Semiconductor substrate; an integrated circuit device, located on the semiconductor substrate; an interconnect structure located on the integrated circuit device, wherein the interconnect structure includes a plurality of metal layers; and A first through silicon via (TSV) and a second through silicon via, wherein the first through silicon via and the second through silicon via are bonded to different metal layers of the plurality of metal layers; and A second device die is connected to the first device die, wherein the first through silicon via and the second through silicon via are electrically connected to the second device die.

10. A semiconductor structure comprising: A first device die, comprising: Semiconductor substrate; an integrated circuit device, located on the semiconductor substrate; an interconnect structure located on the integrated circuit device, wherein the interconnect structure includes a plurality of metal layers; a first through silicon via (TSV) penetrating the semiconductor substrate, wherein the first through silicon via has a first wider end and a first narrower end narrower than the first wider end, and wherein the first wider end is located on a front side of the semiconductor substrate; and The second through silicon via has a second wider end and a second narrower end narrower than the second wider end, wherein the second wider end is located on the back side of the semiconductor substrate.

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