Method for preparing gallium nitride diamond CMOS (Complementary Metal Oxide Semiconductor) device by adopting Cu-Cu bonding and application thereof

Abstract

The invention provides a method for preparing a gallium nitride diamond CMOS (Complementary Metal Oxide Semiconductor) device by adopting Cu-Cu bonding and application of the gallium nitride diamond CMOS device. The method comprises the following steps: (1) preparing Cu-Pads on the surfaces of a planar p-diamond MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) wafer and a planar GaN-HEMT (High Electron Mobility Transistor) MOSFET wafer respectively to obtain a planar p-diamond MOSFET device containing a first Cu-Pads and a planar GaN-HEMT MOSFET device containing a second Cu-Pads; and (2) aligning the first Cu-Pads and the second Cu-Pads oppositely, and carrying out Cu-Cu bonding connection at a preset temperature and a preset pressure to obtain the gallium nitride diamond CMOS device. According to the method provided by the invention, different devices can be manufactured separately, so that the technical problem of epitaxy of the GaN film on the diamond substrate is avoided, and the production difficulty and cost can be reduced.

Description

Technical Field

[0001] The present invention relates to the field of electronic technology, and in particular to a method for preparing a gallium nitride diamond CMOS device by using Cu-Cu bonding and an application thereof. Background Art

[0002] CMOS (Complementary Metal-Oxide-Semiconductor) devices are core components of modern electronic technology and are widely used in various electronic devices. The core of CMOS circuits is to use the complementary characteristics of P-type MOSFET and N-type MOSFET to realize logical functions. It is currently the most widely used integrated circuit technology. Almost all modern microprocessors, microcontrollers, memory chips and various other integrated circuits are manufactured using CMOS technology.

[0003] Among them, silicon-based materials are widely used in CMOS devices due to their excellent electrical properties, thermal stability and mature manufacturing processes. They are characterized by low cost, high integration, and miniaturization. However, silicon-based materials also have their shortcomings: for example, 1) silicon-based CMOS devices have low thermal conductivity and are prone to performance degradation and failure at high temperatures; 2) the physical properties of silicon materials limit the application of silicon-based CMOS devices in high frequency and high power.

[0004] With the development of technology, gallium nitride (GaN) materials and diamond materials have also been applied to CMOS devices. Gallium nitride diamond CMOS devices (GaN diamond CMOS devices) are semiconductor devices that combine gallium nitride (GaN) and diamond materials, and are compatible with complementary metal oxide semiconductor (CMOS) processes. This device utilizes the excellent electrical properties of GaN materials and the efficient heat dissipation performance of diamond materials, aiming to achieve high-performance, high-power density and high-reliability electronic devices. However, there are very large technical bottlenecks in growing high-quality GaN films on diamond substrates. In addition, the process flow for preparing GaN diamond CMOS is complicated, the device preparation cost is high, and the product yield is low, which limits its large-scale application. Summary of the invention

[0005] The present invention aims to solve at least one of the technical problems in the related art to a certain extent. The present invention proposes a method for preparing a gallium nitride diamond CMOS device by Cu-Cu bonding. The method provided connects the metal pads (pads) of a planar GaN-HEMTMOSFET device and the metal pads of a planar p-diamond MOSFET device together by means of high temperature and external pressure to form a CMOS device. The method provided by the present invention aims to combine the high electron mobility, high breakdown voltage and high frequency characteristics of GaN with the extremely high thermal conductivity, high breakdown voltage and chemical inertness of diamond to prepare a CMOS device with ultra-high power density, ultra-high energy conversion efficiency, high thermal stability and high frequency and high power at the same time.

[0006] Specifically, the present invention provides the following technical solutions:

[0007] In a first aspect of the present invention, a method for preparing a gallium nitride diamond CMOS device using Cu-Cu bonding is provided, comprising:

[0008] (1) growing Cu-Pads on the surfaces of a planar p-diamond MOSFET wafer and a planar GaN-HEMT MOSFET wafer, respectively, so as to obtain a planar p-diamond MOSFET device containing first Cu-Pads and a planar GaN-HEMT MOSFET device containing second Cu-Pads;

[0009] (2) Aligning the first Cu-Pads of the planar p-diamond MOSFET device containing the first Cu-Pads and the second Cu-Pads of the planar GaN-HEMT MOSFET device containing the second Cu-Pads toward each other, and performing Cu-Cu bonding connection at a predetermined temperature and a predetermined pressure to obtain a gallium nitride diamond CMOS device.

[0010] According to an embodiment of the present invention, step (2) further comprises:

[0011] (2-1) The first Cu-Pads of the planar p-diamond MOSFET device containing the first Cu-Pads and the second Cu-Pads of the planar GaN-HEMT MOSFET device containing the second Cu-Pads are aligned facing each other, and a pressure of 50 N / cm3 is applied under the protection of an inert gas at a vacuum pressure of 0.1 Pa to 0.5 Pa. 2 ~150N / cm 2 The Cu-Cu bonding is performed by applying a pressure and heating at a temperature of 200 to 400°C for 20 to 50 minutes;

[0012] (2-2) Annealing is performed, and then the bonded product is heated at a temperature of 200 to 400° C. for 40 to 100 minutes under the protection of an inert gas.

[0013] According to an embodiment of the present invention, step (1) further comprises:

[0014] (1-1) growing dielectric layers on the surfaces of a planar p-diamond MOSFET wafer and a planar GaN-HEMT MOSFET wafer respectively;

[0015] (1-2) etching the dielectric layers respectively to form vertical metal connection holes at the metal pads of the planar p-diamond MOSFET wafer and the planar GaN-HEMT MOSFET wafer;

[0016] (1-3) continuing to perform etching treatment on the dielectric layers respectively to remove portions of the dielectric layers so as to form patterns in the dielectric layers respectively;

[0017] (1-4) depositing Ti and Cu on the entire surface of the planar p-diamond MOSFET wafer and the planar GaN-HEMTMOSFET wafer containing the pattern close to the pattern side to form a Ti layer and a Cu layer, wherein the Cu layer is located on the surface of the Ti layer, and polishing the surface of the formed Cu layer;

[0018] (1-5) Repeat the above steps (1-1) to (1-4) to obtain a planar p-diamond MOSFET device containing the first Cu-Pads and a planar GaN-HEMT MOSFET device containing the second Cu-Pads, respectively.

[0019] According to an embodiment of the present invention, the thickness of the dielectric layer is 1.5 to 4 micrometers. Furthermore, through the above repetition, the thickness of the dielectric layer becomes 3 to 8 micrometers.

[0020] According to an embodiment of the present invention, the dielectric layer is obtained by oxide deposition or polymer spin coating.

[0021] According to an embodiment of the present invention, the oxide is selected from at least one of silicon dioxide, hafnium dioxide, aluminum oxide, and silicon nitride.

[0022] According to an embodiment of the present invention, the polymer is selected from at least one of polyimide, benzocyclobutene, polybenzo-bisoxazole and fluorinated aromatic AL-X 2010.

[0023] According to an embodiment of the present invention, the surface roughness of the Cu surface after polishing is less than 1.0 nm Ra.

[0024] According to an embodiment of the present invention, the polishing process is performed by chemical mechanical polishing.

[0025] According to an embodiment of the present invention, the etching process in step (1-2) and step (1-3) is performed by photolithography and oxide etching.

[0026] According to an embodiment of the present invention, step (1-4) is deposited on the entire wafer by thermal evaporation, magnetron sputtering or electron beam evaporation to form a Ti layer and a Cu layer.

[0027] A second aspect of the present invention provides a gallium nitride diamond CMOS device, comprising:

[0028] A planar p-diamond MOSFET wafer and a planar GaN-HEMT MOSFET wafer arranged in alignment with each other;

[0029] A first dielectric layer and a second dielectric layer, wherein the first dielectric layer is disposed on a surface of the planar p-diamond MOSFET wafer, and the second dielectric layer is grown on a surface of the planar GaN-HEMT MOSFET wafer, and the first dielectric layer and the second dielectric layer are disposed opposite to each other;

[0030] A first Cu-Pad and a second Cu-Pad, wherein the first Cu-Pad is located on the surface of the planar p-diamond MOSFET wafer and distributed in the first dielectric layer, the second Cu-Pad is located on the surface of the planar GaN-HEMTMOSFET wafer and distributed in the second dielectric layer, the first Cu-Pad and the second Cu-Pad are aligned toward each other, and the first Cu-Pad and the second Cu-Pad are Cu-Cu bonded.

[0031] According to an embodiment of the present invention, the thickness of the first dielectric layer and the second dielectric layer are respectively 3-8 microns.

[0032] According to an embodiment of the present invention, the first dielectric layer and the second dielectric layer are obtained by oxide or polymer deposition.

[0033] According to an embodiment of the present invention, the oxide is selected from at least one of silicon dioxide, hafnium dioxide, aluminum oxide, and silicon nitride.

[0034] According to an embodiment of the present invention, the polymer is selected from at least one of polyimide, benzocyclobutene, polybenzo-bisoxazole and fluorinated aromatic AL-X 2010. According to an embodiment of the present invention, the polymer is prepared according to the method described in the first aspect.

[0035] According to a third aspect of the present invention, there is provided application of the gallium nitride diamond CMOS device described in the second aspect in the field of electronics.

[0036] The beneficial effects achieved by the present invention are at least:

[0037] (1) The method provided by the present invention uses Cu-Cu bonding technology to achieve the preparation of GaN diamond CMOS devices. This method can achieve the separate manufacture of planar GaN-HEMT MOSFET devices and planar p-diamond MOSFET devices, avoiding the technical difficulties of epitaxy of GaN thin films on diamond substrates and the influence of GaN / diamond interface defects on device performance.

[0038] (2) The provided method reduces the complexity of the process flow of GaN diamond CMOS, reduces the production difficulty and cost, and improves the product yield of GaN diamond CMOS.

[0039] (3) The method provided by the present invention uses Cu-Cu bonding technology to prepare GaN diamond CMOS devices, which can be applied in a variety of technical fields. For example, in high-speed digital circuits and high-frequency communication systems, it can significantly reduce signal transmission loss, improve signal integrity, and ensure the quality of high-speed data transmission. In high-power integrated circuits and power electronic devices, Cu-Cu bonding can effectively dissipate heat, reduce chip junction temperature, and improve device reliability and life. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 A schematic diagram of a method for preparing Cu-Pads on the surface of a MOSFET device according to an embodiment of the present invention.

[0041] Figure 2 Cu-Cu bonding is accomplished for the planar p-diamond MOSFET device and the planar GaN-HEMTMOSFET device provided according to embodiments of the present invention.

[0042] Figure 3 It is a schematic diagram of preparing a dielectric layer according to an embodiment of the present invention.

[0043] Figure 4 A schematic diagram of preparing a metal connection hole according to an embodiment of the present invention.

[0044] Figure 5 A schematic diagram of rewiring in a dielectric layer according to an embodiment of the present invention.

[0045] Figure 6 Schematic diagram of metal deposition and CMP polishing according to an embodiment of the present invention.

[0046] Figure 7 Schematic diagram of rewiring and forming Cu-Pads in a dielectric layer according to an embodiment of the present invention.

[0047] Figure 8 Schematic diagrams of surface layout and cross-sectional morphology of a planar p-diamond MOSFET device and a planar GaN-HEMTMOSFET device provided according to an embodiment of the present invention, a and b are both top views, and c and d are both front views.

[0048] Fig. 9 This is a schematic structural diagram of a gallium nitride diamond CMOS device formed after Cu-Cu bonding is completed according to an embodiment of the present invention, wherein a is a top view and b is a front view.

[0049] Fig.10 It is a schematic structural diagram of a gallium nitride diamond CMOS device provided according to an embodiment of the present invention, wherein reference numeral 1 is a planar p-diamond MOSFET wafer, reference numeral 2 is a first dielectric layer, reference numeral 3 is a first Cu-Pads, reference numeral 4 is a second Cu-Pads, reference numeral 5 is a second dielectric layer, and reference numeral 6 is a planar GaN-HEMT MOSFET wafer. DETAILED DESCRIPTION

[0050] Embodiments of the present invention are described in detail below. Examples of the embodiments are shown in the accompanying drawings. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, but should not be construed as limiting the present invention.

[0051] In this article, "first" and "second" are only used for descriptive purposes and are not used to indicate order or importance.

[0052] The present invention provides a method for preparing a gallium nitride diamond CMOS device. The method provided can combine the high power characteristics of GaN with the excellent heat dissipation ability of diamond, can achieve extremely high power density, and can simultaneously achieve high frequency and high power operation; and the low on-resistance of GaN and the good heat dissipation of diamond jointly improve the energy conversion efficiency. The provided gallium nitride diamond CMOS device can achieve effective heat dissipation and material stability, jointly ensuring the reliability of the device in a high power and high temperature environment; and both GaN and diamond have a very high breakdown voltage, further improving the device's withstand voltage capability.

[0053] According to a specific embodiment, the provided GaN-diamond CMOS device can be prepared by the following method, including:

[0054] (1) preparing Cu-Pads on the surfaces of a planar p-diamond MOSFET wafer and a planar GaN-HEMT MOSFET wafer, respectively, so as to obtain a planar p-diamond MOSFET device containing the first Cu-Pads and a planar GaN-HEMT MOSFET device containing the second Cu-Pads;

[0055] (2) Aligning the first Cu-Pads of the planar p-diamond MOSFET device containing the first Cu-Pads and the second Cu-Pads of the planar GaN-HEMT MOSFET device containing the second Cu-Pads toward each other, and performing Cu-Cu bonding connection at a predetermined temperature and a predetermined pressure to obtain a gallium nitride diamond CMOS device.

[0056] According to a specific embodiment, step (2) further comprises:

[0057] (2-1) The first Cu-Pads of the planar p-diamond MOSFET device containing the first Cu-Pads and the second Cu-Pads of the planar GaN-HEMT MOSFET device containing the second Cu-Pads are aligned facing each other, and a pressure of 50 N / cm3 is applied under the protection of an inert gas at a vacuum pressure of 0.1 Pa to 0.5 Pa. 2 ~150N / cm 2 The Cu-Cu bonding is performed by applying a pressure and heating at a temperature of 200 to 400°C for 20 to 50 minutes;

[0058] (2-2) Annealing is performed, and then the bonded product is heated at a temperature of 200 to 400° C. for 40 to 100 minutes under the protection of an inert gas.

[0059] During the Cu-Cu bonding process, the bonding needs to be performed under vacuum pressure to prevent the Cu surface from being oxidized.

[0060] According to an embodiment of the present invention, step (1) further comprises:

[0061] (1-1) growing dielectric layers on the surfaces of a planar p-diamond MOSFET wafer and a planar GaN-HEMT MOSFET wafer respectively;

[0062] (1-2) etching the dielectric layers respectively to form vertical metal connection holes at the metal pads of the planar p-diamond MOSFET wafer and the planar GaN-HEMT MOSFET wafer;

[0063] (1-3) continuing to perform etching treatment on the dielectric layers respectively to remove portions of the dielectric layers so as to form patterns in the dielectric layers respectively;

[0064] (1-4) depositing Ti and Cu on the entire surface of the planar p-diamond MOSFET wafer and the planar GaN-HEMTMOSFET wafer containing the pattern, respectively, close to the pattern side, so as to form a Ti layer and a Cu layer, wherein the Ti layer and the Cu layer are distributed in the dielectric layer, the Cu layer is located on the surface of the Ti layer, and the formed Cu surface is polished;

[0065] (1-5) Repeat the above steps (1-1) to (1-4) to obtain a planar p-diamond MOSFET device containing the first Cu-Pads and a planar GaN-HEMT MOSFET device containing the second Cu-Pads, respectively.

[0066] It should be noted that, whether it is a p-diamond MOSFET wafer or a planar GaN-HEMT MOSFET wafer, each MOSFET has its own Cu-Pads, but these original Cu-Pads are not suitable for directly completing Cu-Cu bonding. By forming vertical metal connection holes in the dielectric layer (connecting the original Cu-Pads) and the above-mentioned rewiring in the dielectric layer (rewiring can easily change the position of Cu-Pads), and then forming vertical metal connection holes, the final Cu-Pads are finally formed, which can be used for Cu-Cu bonding.

[0067] The thickness of the dielectric layer is 1.5 to 4 micrometers; through the above-mentioned repeated steps, the thickness of the dielectric layer can reach 3 to 8 micrometers. The dielectric layer is obtained by oxide deposition or polymer spin coating.

[0068] The oxides mentioned include but are not limited to silicon dioxide, hafnium dioxide (HfO2), aluminum oxide (Al2O3), silicon nitride (Si3N4), etc. The polymers mentioned include but are not limited to polyimide (PI), such as PWDC 1000 (DowCorning), which is a high-performance polyimide material with excellent high temperature resistance and mechanical properties; benzocyclobutene (BCB), such as cyclotene 4024-40 (Dow Chemical); polybenzo-bisoxazole (PBO), such as HD-8930 (HD Micro Systems); fluorinated aromatic AL-X 2010 (Asahi Glass Corporation), etc.

[0069] According to a specific embodiment, the surface roughness Ra of the Cu surface after polishing is less than 1.0 nm. The polishing process can be carried out by a method commonly used in the art, for example, the polishing process can be carried out by chemical mechanical polishing. Chemical mechanical polishing (CMP) is an ultra-precision polishing technology that combines mechanical friction and chemical corrosion. Its basic principle is to achieve the flattening and smoothing of the workpiece surface through the combined effect of mechanical grinding and chemical liquid dissolution. The main process includes: (1) Chemical corrosion: The oxidant and catalyst in the polishing liquid react chemically with the workpiece surface material to form a layer of easily removable chemical reaction film on the workpiece surface; (2) Mechanical grinding: The abrasive particles and polymer materials in the polishing pad remove the chemical reaction film through mechanical action, so that the workpiece surface is exposed again; (3) Repeated alternation: Chemical action and mechanical action are performed alternately to finally complete the polishing of the workpiece surface. The polishing liquid used can be purchased commercially and usually includes: ultrafine abrasive particles (such as SiO2, used for physical grinding); chemical corrosive agents (such as nitric acid, hydrofluoric acid, etc., used for chemical corrosion); dispersants and stabilizers (used to maintain the stability and uniformity of the polishing liquid) and pH adjusters (to control the pH value of the polishing liquid).

[0070] The deposition of the metal layer Ti layer and the Cu layer can be carried out by methods commonly used in the art, including but not limited to thermal evaporation, magnetron sputtering or electron beam evaporation. Thermal evaporation can be achieved by a high-temperature wire rod or a boat-type evaporator, with simple equipment requirements and low cost. Magnetron sputtering is a technology that uses a magnetic field to control the movement of metal ions. This method can achieve deposition in a high vacuum environment, avoid gas collisions and reactions, and thus obtain high-quality films. Electron beam evaporation uses an electron beam to heat the material, causing it to evaporate and condense into a thin film on a substrate.

[0071] The thickness of the formed Ti layer may be 25 nm, and the thickness of the Cu layer may be 1.5 micrometers.

[0072] According to a specific embodiment, step (1-2) and step (1-3) perform the etching process by photolithography and oxide etching.

[0073] The present invention also provides a gallium nitride diamond CMOS device. Fig.10 As shown, according to a specific embodiment, the provided GaN-diamond CMOS device includes:

[0074] A planar p-diamond MOSFET wafer 1 and a planar GaN-HEMT MOSFET wafer 6 are arranged in alignment with each other;

[0075] A first dielectric layer 2 and a second dielectric layer 5, wherein the first dielectric layer 2 is disposed on the surface of the planar p-diamond MOSFET wafer 1, and the second dielectric layer 5 is grown on the surface of the planar GaN-HEMT MOSFET wafer 6, and the first dielectric layer 2 and the second dielectric layer 5 are disposed opposite to each other;

[0076] The first Cu-Pads 3 and the second Cu-Pads 4, the first Cu-Pads are located on the surface of the planar p-diamond MOSFET wafer and distributed in the first dielectric layer, the second Cu-Pads are located on the surface of the planar GaN-HEMTMOSFET wafer and distributed in the second dielectric layer, the first Cu-Pads and the second Cu-Pads are aligned toward each other, and the Cu-Cu bonding of the first Cu-Pads and the second Cu-Pads is performed.

[0077] In this article, Cu-Cu bonding refers to direct contact and bonding of copper surfaces.

[0078] According to a specific embodiment, the thickness of the first dielectric layer and the second dielectric layer are respectively 3 to 8 microns.

[0079] The gallium nitride diamond CMOS device provided by the present invention is characterized by electrical properties, thermal properties (such as thermal conductivity, junction temperature peak), reliability (such as radiation tolerance, long-term stability, etc.) and physical properties (such as X-ray diffraction). The results show that the gallium nitride diamond CMOS device provided by the present invention exhibits faster switching speed and higher efficiency in high-frequency and high-voltage applications compared to simple unbonded gallium nitride or unbonded diamond devices. Moreover, due to the integration of diamond devices, the heat dissipation capacity of gallium nitride devices is significantly improved, so that the provided gallium nitride diamond CMOS device can still maintain a low junction temperature at high power density.

[0080] The GaN-diamond CMOS devices provided above can be used in the electronic field and have important value, including but not limited to high power amplifiers, switching power supplies and RF power amplifiers, 5G base stations, satellite communications and radar systems, electric vehicle power conversion systems and charging infrastructure, solar inverters and wind power generation systems, laptop computer high-efficiency chargers, military communications, navigation, electronic warfare and aerospace applications, as well as oil drilling and deep space exploration.

[0081] The technical scheme of the present invention is described below by specific examples. It should be noted that these examples are only used to facilitate the understanding of those skilled in the art and should not be regarded as limiting the scope of protection of the present invention. Unless otherwise specified, the reagents used in the examples can be obtained commercially.

[0082] Example 1

[0083] Example 1 A gallium nitride diamond CMOS device is prepared using a Cu-Cu bonding process. First, Cu-Pads are prepared on the surface of a planar GaN-HEMT MOSFET device and a planar p-diamond MOSFET device, respectively. Then, Cu-Cu bonding is completed at a certain temperature and pressure to prepare a gallium nitride diamond CMOS device.

[0084] (1) Reference Figure 1 As shown, Cu-Pads are prepared on the surface of a planar GaN-HEMT MOSFET device and a planar p-diamond MOSFET device, respectively. Whether Cu-Pads are prepared on the surface of a planar GaN-HEMT MOSFET device or on the surface of a planar p-diamond MOSFET device, the method is similar. Therefore, for the convenience of description below, only another device is shown in brackets to indicate that it is prepared by a similar method, which specifically includes the following steps:

[0085] 1) Prepare an 8-inch planar GaN-HEMT MOSFET (planar p-diamond MOSFET) wafer.

[0086] 2) A 5 μm thick SiO2 dielectric layer is grown on the surface of a planar GaN-HEMT MOSFET (planar p-diamond MOSFET) wafer by plasma enhanced chemical vapor deposition (PECVD); a schematic diagram of this step and the resulting structure is shown in FIG. Figure 3 shown.

[0087] 3) If Figure 4 As shown, vertical metal connection holes are formed at the metal pads of the planar GaN-HEMT MOSFET (p-type diamond MOSFET) wafer through photolithography and oxide etching processes.

[0088] 4) Again through the photolithography and oxide etching process, a pattern is formed in the dielectric layer to facilitate rewiring in the dielectric layer. Its structure is as follows Figure 5 shown.

[0089] 5) Sputter Ti and Cu on the entire wafer by magnetron sputtering and electrochemical deposition (ECD) Cu to complete the wiring in the dielectric layer (wherein the thickness of the formed Ti layer is 25 nm and the thickness of the Cu layer is 1.5 μm).

[0090] The wafer surface is polished using a chemical mechanical polishing (CMP) process, and the roughness of the Cu surface after polishing is less than 1.0nm Ra. Figure 6 shown.

[0091] 6) Repeat steps 2) to 5) to rewire the dielectric layer and obtain Cu-Pads on the wafer surface. The process steps are as follows: Figure 7 shown.

[0092] 7) Complete rewiring in the dielectric layer and prepare planar p-diamond MOSFET devices with Cu-Pads and planar GaN-HEMT MOSFET devices with Cu-Pads.

[0093] The surface layout and cross-sectional morphology of the planar p-diamond MOSFET device with Cu-Pads are shown in Figure 2. Figure 8 (a) and (c); the surface layout and cross-sectional morphology of the planar GaN-HEMT MOSFET device with Cu-Pads are shown in Figure 8, respectively. Figure 8 (b) and 8(d).

[0094] (3) Cu-Cu bonding

[0095] References Figure 2 As shown, the two Cu-Pads are aligned, and a pressure of 25kN is applied to the wafer under the protection of N2 atmosphere with a vacuum pressure of 0.1Pa, and the wafer is heated at 300℃ for 30min. After bonding, the bonded wafer is annealed and heated at 300℃ for 60min under the protection of N2 atmosphere. The schematic diagram of the CMOS structure after Cu-Cu bonding is shown in FIG. Fig. 9 As shown, Fig. 9 (a) is a schematic diagram of the surface layout after Cu-Cu bonding. Fig. 9 (b) Schematic diagram of the cross-sectional morphology of CMOS after Cu-Cu bonding.

[0096] The structural diagram of the prepared GaN-diamond CMOS device is shown in Fig.10 As shown. Characterization shows that the GaN-diamond CMOS device provided by the present invention has faster switching speed and higher efficiency in high-frequency and high-voltage applications compared to simple unbonded GaN or unbonded diamond devices, and can still maintain a lower junction temperature at high power density.

[0097] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "specific implementation methods", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example.

[0098] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present invention.

Claims

1. A method for preparing a gallium nitride diamond CMOS device using Cu-Cu bonding, characterized in that: include: (1) preparing Cu-Pads on the surfaces of a planar p-diamond MOSFET wafer and a planar GaN-HEMT MOSFET wafer, respectively, so as to obtain a planar p-diamond MOSFET device containing the first Cu-Pads and a planar GaN-HEMT MOSFET device containing the second Cu-Pads; (2) Aligning the first Cu-Pads of the planar p-diamond MOSFET device containing the first Cu-Pads and the second Cu-Pads of the planar GaN-HEMT MOSFET device containing the second Cu-Pads toward each other, and performing Cu-Cu bonding connection at a predetermined temperature and a predetermined pressure to obtain a gallium nitride diamond CMOS device.

2. The method according to claim 1, characterized in that Step (2) further comprises: (2-1) The first Cu-Pads of the planar p-diamond MOSFET device containing the first Cu-Pads and the second Cu-Pads of the planar GaN-HEMT MOSFET device containing the second Cu-Pads are aligned facing each other, and a pressure of 50 N / cm3 is applied under the protection of an inert gas at a vacuum pressure of 0.1 Pa to 0.5 Pa. 2 ~150N / cm 2 The Cu-Cu bonding is performed by applying a pressure and heating at a temperature of 200 to 400°C for 20 to 50 minutes; (2-2) Annealing is performed, and then the bonded product is heated at a temperature of 200 to 400° C. for 40 to 100 minutes under the protection of an inert gas.

3. The method according to claim 1, characterized in that Step (1) further comprises: (1-1) growing dielectric layers on the surfaces of a planar p-diamond MOSFET wafer and a planar GaN-HEMT MOSFET wafer respectively; (1-2) etching the dielectric layers respectively so as to form vertical metal connection holes at the metal pads of the planar p-diamond MOSFET wafer and the planar GaN-HEMT MOSFET wafer respectively; (1-3) continuing to perform etching treatment on the dielectric layers respectively to remove portions of the dielectric layers so as to form patterns in the dielectric layers respectively; (1-4) depositing Ti and Cu on the entire surface of the planar p-diamond MOSFET wafer and the planar GaN-HEMT MOSFET wafer containing the pattern, respectively, close to the pattern side, so as to form a Ti layer and a Cu layer, wherein the Ti layer and the Cu layer are distributed in the dielectric layer, the Cu layer is located on the surface of the Ti layer, and the surface of the formed Cu layer is polished; (1-5) Repeat the above steps (1-1) to (1-4) to obtain a planar p-diamond MOSFET device containing the first Cu-Pads and a planar GaN-HEMT MOSFET device containing the second Cu-Pads, respectively.

4. The method according to claim 3, characterized in that The thickness of the dielectric layer is 1.5 to 4 microns; Optionally, the dielectric layer is obtained by oxide deposition or polymer spin coating; Optionally, the oxide is selected from at least one of silicon dioxide, hafnium dioxide, aluminum oxide, and silicon nitride; Optionally, the polymer is selected from at least one of polyimide, benzocyclobutene, polybenzo-bisoxazole and fluorinated aromatic AL-X 2010.

5. The method according to claim 3, characterized in that: The surface roughness Ra of the Cu surface after polishing is less than 1.0 nm; Optionally, the polishing process is performed by chemical mechanical polishing.

6. The method according to claim 3, characterized in that Step (1-2) and step (1-3) perform the etching process by photolithography and oxide etching; Optionally, step (1-4) is performed by thermal evaporation, magnetron sputtering or electron beam evaporation to form the Ti layer and the Cu layer.

7. A gallium nitride diamond CMOS device, characterized in that: include: A planar p-diamond MOSFET wafer and a planar GaN-HEMT MOSFET wafer arranged in alignment with each other; A first dielectric layer and a second dielectric layer, wherein the first dielectric layer is disposed on a surface of the planar p-diamond MOSFET wafer, and the second dielectric layer is disposed on a surface of the planar GaN-HEMT MOSFET wafer, and the first dielectric layer and the second dielectric layer are disposed opposite to each other; A first Cu-Pad and a second Cu-Pad, wherein the first Cu-Pad is located on the surface of the planar p-diamond MOSFET wafer and distributed in the first dielectric layer, the second Cu-Pad is located on the surface of the planar GaN-HEMT MOSFET wafer and distributed in the second dielectric layer, the first Cu-Pad and the second Cu-Pad are aligned toward each other, and Cu-Cu bonding is performed between the first Cu-Pad and the second Cu-Pad.

8. The GaN-diamond CMOS device according to claim 7, characterized in that: The thickness of the first dielectric layer and the second dielectric layer are 3 to 8 microns respectively; Optionally, the first dielectric layer and the second dielectric layer are obtained by oxide deposition or polymer spin coating; Optionally, the oxide is selected from at least one of silicon dioxide, hafnium dioxide, aluminum oxide, and silicon nitride; Optionally, the polymer is selected from at least one of polyimide, benzocyclobutene, polybenzo-bisoxazole and fluorinated aromatic AL-X 2010.

9. The GaN-diamond CMOS device according to claim 7, characterized in that: Prepared according to the method according to any one of claims 1 to 6.

10. Application of the gallium nitride diamond CMOS device according to any one of claims 7 to 9 in the field of electronics.

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