Semiconductor substrate
By forming semiconductor elements with inclined growth surfaces on the base substrate and bonding and peeling with support substrates with inclined opposite surfaces, the problem of low yield in semiconductor element manufacturing is solved, and reliable transfer of semiconductor elements and improvement of yield is achieved.
Patent Information
- Application Number
- CN202510136611.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2019-02-28
- Filing Date
- 2020-02-28
- Publication Date
- 2025-05-16
AI Technical Summary
When the conventional semiconductor element manufacturing method peels off the semiconductor element from the base substrate, it is easy to cause electrode peeling and transfer unreliable, resulting in low yield.
A semiconductor element with an inclined growth surface is formed on the base substrate, and bonding and peeling are performed using a support substrate with an inclined opposite surface. The semiconductor element and the support substrate are bonded by pressurization and heating, and the connection portion is broken to peel off the base substrate.
The yield of semiconductor components is improved, reliable transfer of semiconductor components to the support substrate is ensured, and mechanical stress on semiconductor components is reduced, and electrode peeling is avoided.
Smart Images
Figure CN120015705A_ABST
Abstract
Description
[0001] This application is a divisional application of the invention patent application with the application date of February 28, 2020, application number 202080016757.3, and invention name “Method for manufacturing semiconductor element and semiconductor element body”. Technical Field
[0002] The present disclosure relates to a method for manufacturing a semiconductor element and a semiconductor element body. Background Art
[0003] A conventional method for manufacturing a semiconductor element is described in Patent Document 1, for example.
[0004] Prior Art Literature
[0005] Patent Literature
[0006] Patent Document 1: Japanese Patent No. 4638958 Summary of the invention
[0007] The manufacturing method of the semiconductor element disclosed in the present invention may also include: an element forming step, forming a semiconductor element on a base substrate, wherein the semiconductor element is connected to the base substrate via a connecting portion and has an upper surface inclined relative to the growth surface of the base substrate; a preparation step, preparing a supporting substrate having an opposing surface opposite to the base substrate; a bonding step, pressing the upper surface of the semiconductor element against the opposing surface of the supporting substrate and heating it to bond the upper surface of the semiconductor element to the supporting substrate; and a peeling step, peeling the semiconductor element from the base substrate.
[0008] The manufacturing method of the semiconductor element disclosed in the present invention may also include: an element forming step, forming a semiconductor element on a base substrate and connected to the base substrate via a connecting portion; preparing a supporting substrate having an opposing surface, wherein the opposing surface is inclined relative to the growth surface of the base substrate when opposed to the base substrate; a bonding step, pressing the upper surface of the semiconductor element against the opposing surface of the supporting substrate and heating it to bond the upper surface of the semiconductor element to the supporting substrate; and a peeling step, peeling the semiconductor element from the base substrate.
[0009] The manufacturing method of the semiconductor element disclosed in the present invention may also include: an element forming step, forming a semiconductor element on a base substrate and connected to the base substrate via a connecting portion; a preparation step, preparing a supporting substrate having an opposing surface opposite to the base substrate and a step portion provided on the opposing surface; a bonding step, pressing the upper surface of the semiconductor element against the opposing surface of the supporting substrate and heating the semiconductor element so that the upper surface of the semiconductor element and the step portion of the opposing surface of the supporting substrate are in contact, thereby bonding the upper surface of the semiconductor element to the supporting substrate; and a peeling step, peeling the semiconductor element from the base substrate.
[0010] The semiconductor element body disclosed in the present invention may also include: a supporting substrate; and a semiconductor element layer having a first surface and a second surface located on the opposite side of the first surface, one side of the first surface is fixed to the supporting substrate, and the second surface is inclined relative to the surface of the supporting substrate.
[0011] The semiconductor element body of the present disclosure may include: a support substrate having an inclined surface; and a semiconductor element layer having a first surface and a second surface located on the opposite side to the first surface, wherein one side of the first surface is fixed to the inclined surface of the support substrate.
[0012] The semiconductor element body disclosed in the present invention may also include: a supporting substrate; and a semiconductor element layer, having a first surface and a second surface located on the opposite side of the first surface, one side of the first surface is fixed to the supporting substrate, and at least the first surface among the first surface and the second surface is inclined relative to the surface of the supporting substrate.
[0013] Effects of the Invention
[0014] According to the method for manufacturing a semiconductor element disclosed in the present invention, the yield rate of the semiconductor element can be improved.
[0015] According to the semiconductor element body of the present disclosure, it is easy to separate into individual semiconductor elements, and the yield of semiconductor elements can be improved. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] Figure 1 It is a process diagram of a method for manufacturing a semiconductor element according to an embodiment of the present disclosure.
[0017] Figure 2A It is a cross-sectional view showing the element forming process according to the first embodiment.
[0018] Figure 2B It is a cross-sectional view showing the element forming process according to the first embodiment.
[0019] Figure 2C It is a cross-sectional view showing the element forming process according to the first embodiment.
[0020] Figure 3 This is a photograph of a semiconductor device layer formed on a base substrate.
[0021] Figure 4 It is a graph showing the slope of the upper surface of the semiconductor element layer.
[0022] Figure 5 It is a cross-sectional view showing the preparation step according to the first embodiment.
[0023] Fig. 6A It is a cross-sectional view showing the joining process according to the first embodiment.
[0024] Figure 6B It is a cross-sectional view showing the joining process according to the first embodiment.
[0025] Figure 7 It is a cross-sectional view showing the peeling step according to the first embodiment.
[0026] Fig. 8A It is a cross-sectional view showing the element forming process according to the second embodiment.
[0027] Figure 8B It is a cross-sectional view showing the element forming process according to the second embodiment.
[0028] Figure 8C It is a cross-sectional view showing the element forming process according to the second embodiment.
[0029] Fig. 9 It is a cross-sectional view showing the preparation step according to the second embodiment.
[0030] Fig. 10A It is a cross-sectional view showing a joining process according to the second embodiment.
[0031] Fig. 10B It is a cross-sectional view showing a joining process according to the second embodiment.
[0032] Fig.11 It is a cross-sectional view showing the peeling step according to the second embodiment.
[0033] Fig.12 It is a cross-sectional view showing a preparation step according to the third embodiment.
[0034] Fig.13A It is a cross-sectional view showing a joining process according to the third embodiment.
[0035] Fig. 13B It is a cross-sectional view showing a joining process according to the third embodiment.
[0036] Fig.14It is a cross-sectional view showing a peeling step according to the third embodiment. DETAILED DESCRIPTION
[0037] The objects, features and advantages of the present invention will become more apparent from the following detailed description and accompanying drawings.
[0038] In the semiconductor element and its manufacturing method based on the present disclosure, a mask having stripe-shaped slits is formed on a base substrate such as sapphire or GaN (gallium nitride), and then a semiconductor is epitaxially grown from the substrate exposed from the slits, and the formed semiconductor element is transferred to a supporting substrate.
[0039] In the technology based on the present disclosure, when the grown semiconductor element is transferred to the support substrate, after the semiconductor element is bonded to the support substrate, a force in a vertical direction is applied to the base substrate and each surface of the support substrate to break the connection between the base substrate and the semiconductor element. At this time, if a force is applied between the support substrate and the semiconductor element, the electrode of the semiconductor element may be peeled off, and the transfer of the semiconductor element to the support substrate may not be reliably performed. As a result, there is a concern that the yield of the semiconductor element cannot be improved.
[0040] Hereinafter, embodiments according to the present disclosure will be described with reference to schematically illustrated drawings. Figure 1 This is a basic process diagram of a method for manufacturing a semiconductor element according to an embodiment of the present disclosure. The method for manufacturing a semiconductor element according to the present disclosure includes an element forming step S1 of forming a semiconductor element on a base substrate, a preparation step S2 of preparing a support substrate, a bonding step S3 of bonding the semiconductor element on the base substrate to the support substrate, and a stripping step S4 of stripping the semiconductor element from the base substrate. The element forming step S1 and the preparation step S2 may not be performed in this order, for example, the element forming step S1 and the preparation step S2 may be performed in parallel.
[0041] (First embodiment)
[0042] (1) Element forming process S1
[0043] Figure 2A to Figure 2C 1 is a cross-sectional view showing the element forming process involved in the first embodiment. Figure 2AAs shown, first prepare a base substrate 11. As the base substrate 11, for example, a GaN template substrate is used. For example, the base substrate 11 is an off substrate, and the normal direction of the growth surface 11a of the base substrate 11 (or the surface perpendicular to the thickness direction of the base substrate 11) is tilted by 0.3° from the a-axis (<11-20>) direction. In the present embodiment, the off angle relative to the a-axis is 0.3°, but a substrate with an off angle of 0.1° to 1°, that is, the growth surface 11a of the base substrate 11 can also use a surface that is a crystal surface with an off angle relative to the normal of the growth surface 11a. Such a base substrate 11 can use, for example, a GaN substrate cut from a GaN single crystal ingot (ingot) so that the growth surface 11a of the base substrate is in a given plane direction. As the base substrate 11, any nitride semiconductor substrate is sufficient. In addition, it can also be an n-type substrate or a p-type substrate in which impurities are doped in the nitride semiconductor. The "nitride semiconductor" referred to here is, for example, Al x Ga y In z N (0≤x≤1; 0≤y≤1; 0≤z≤1; x+y+z=1), and the same applies to the “nitride semiconductor” described below. In addition, as the GaN template substrate, for example, sapphire, Si, or SiC can be used.
[0044] Next, a mask 12 is formed on the base substrate 11. First, silicon oxide (e.g., SiO2) as the material of the mask is deposited on the base substrate 11 using a PCVD (Plasma Chemical Vapor Deposition) method, i.e., a SiO2 layer is stacked on the growth surface 11a by about 100 nm. Next, the SiO2 layer is patterned by wet etching using photolithography and buffered hydrofluoric acid (BHF) to form a Figure 2A The mask 12 shown. The mask 12 is a stripe shape in which a plurality of strip-shaped portions 12a are arranged in parallel at a given interval. The width of the opening 12b between adjacent strip-shaped portions 12a is, for example, about 5 μm. The width of the strip-shaped portion 12a is, for example, about 50 μm to 200 μm. In addition, the width of the opening 12b is, for example, about 2 μm to 20 μm.
[0045] The mask material used to form the mask 12 may be any material other than SiO2 as long as the semiconductor layer is not grown from the mask material by vapor phase growth. For example, ZrO2, which can be patterned, can be used as the mask material. X 、TiO X or AlO XOxides such as W and Cr or transition metals such as W and Cr. As a lamination method of the mask layer, a method suitable for the mask material, such as vapor deposition, sputtering or coating curing, can be used as appropriate.
[0046] Next, if Figure 2B As shown, a semiconductor element layer 13 as a crystal growth layer of semiconductor crystal is vapor-grown from the growth surface 11a exposed from the opening 12b. The semiconductor element layer 13 of the present disclosure is a nitride semiconductor layer.
[0047] The crystal growth method can use vapor phase growth VPE (Vapor Phase Epitaxy) based on the chloride transport method using chloride in the group III raw material or MOCVD (Metal Organic Chemical Vapor Deposition) using organic metal in the group III raw material. It is also possible to change the ratio of the raw material gas of the group III element, the ratio of the raw material gas of the impurity, etc. in the growth process to form the semiconductor element layer 13 into a multilayer film that functions as an LED or LD.
[0048] If the grown crystal exceeds the opening 12b of the mask 12, the crystal also grows in the lateral direction along the upper surface 12c of the mask. The crystal growth ends before the semiconductor element layer 13 grown from the growth surface 11a overlaps with the adjacent semiconductor element layer 13. In this way, a semiconductor element layer 13 of a nitride semiconductor grown by the ELO (Epitaxial Lateral Overgrowth) method is obtained. The width of the semiconductor element layer 13 is, for example, about 50 μm to 200 μm, and the height is about 10 μm to 50 μm.
[0049] Figure 3 This is a photograph of a semiconductor element layer formed on a base substrate, and is a photograph of a semiconductor element layer formed on a mask by the above-mentioned method as viewed from the upper surface. Figure 4 is a graph showing the slope of the upper surface of the semiconductor element layer, and is a graph showing the Figure 3The distance between the upper surface of the semiconductor element layer and the reference plane is measured in a graph. The width W of the semiconductor element layer 13 formed in a strip shape is 35 μm. In the width direction, the right end side is higher than the left end side, and the height difference between the two ends is 150 nm. The inclination angle of the first surface 13a (upper surface) of the semiconductor element layer 13 is 0.25°. The deviation angle of the base substrate 11 used in the growth of the semiconductor element layer 13 is 0.22°, and the inclination angle of the first surface 13a corresponds to the deviation angle of the base substrate 11. In this way, it is suitable to give the base substrate 11 an deviation angle to grow the semiconductor element layer 13 in terms of achieving a semiconductor element layer 13 of excellent quality crystal. The semiconductor element layer 13 has a first surface 13a and a second surface 13c located on the opposite side of the first surface 13a.
[0050] After the semiconductor element layer 13 is grown, Figure 2B As shown, a metal layer 14 is formed on the first surface 13a of the semiconductor element layer 13. First, the entire upper surface of the base substrate 11, the mask 12 and the semiconductor element layer 13 is covered with a resist film. Then, an opening is set using a photolithography method to expose the first surface 13a of the semiconductor element layer 13. Then, in the opening, for example, a Cr layer and an AuSn layer which is an alloy of gold and tin are sequentially vapor-deposited. Then, by a lift-off method, the unnecessary metal layer is removed together with the resist film to form a metal layer 14. The thickness of the metal layer is about 1μm to 5μm.
[0051] After the metal layer 14 is formed, the base substrate 11, the mask 12 formed on the base substrate 11, the semiconductor element layer 13, and the metal layer 14 are immersed in BHF for about 10 minutes, and the mask 12 is removed. Figure 2C As shown, a semiconductor element 15 is formed on a base substrate 11. The semiconductor element 15 is connected to the base substrate 11 via a portion of the semiconductor element layer 13 grown in the opening 12b of the mask 12, that is, a columnar connection portion 13b. The metal layer 14 can be used as an electrode of the semiconductor element 15. However, depending on the structure of the semiconductor element 15, the metal layer 14 does not necessarily have to be used as an electrode. The upper surface 15a of the semiconductor element 15 is inclined in the same manner as the first surface 13a of the semiconductor element layer 13. The semiconductor element layer 13 has a first surface 13a and a second surface 13c located on the opposite side thereof.
[0052] (2) Preparation process S2
[0053] Figure 51 is a cross-sectional view showing the preparation process involved in the first embodiment. Next, a support substrate 16 for connection with the semiconductor element 15 is prepared. The support substrate 16 uses a silicon substrate as a base 16a. A metal layer 16b such as Au is formed on one surface of the base 16a, and the surface of the metal layer 16b is an opposing surface 16c facing the base substrate 11. The metal layer 16b makes it easy to bond the semiconductor element 15 to the support substrate 16.
[0054] Next, the semiconductor element 15 is connected to the support substrate 16 using a substrate bonding device (not shown). First, the base substrate 11 and the support substrate 16 are mounted on the substrate bonding device so that the growth surface 11a of the base substrate 11 and the facing surface 16c of the support substrate 16 are parallel.
[0055] (3) Joining process S3
[0056] Fig. 6 is a cross-sectional view showing the bonding process according to the first embodiment. Next, as shown in Fig. 6(a), the opposing surface 16c of the support substrate 16 is brought into contact with the upper surface 15a of the semiconductor element 15. As described above, since the first surface 13a of the semiconductor element layer 13 is inclined, the upper surface 15a of the semiconductor element 15 formed thereon as the upper surface of the metal layer 14 is also inclined.
[0057] Next, as shown in FIG6(b), the support substrate 16 is pressurized to combine the metal layer 14 with the support substrate 16, and then heated to 300°C, for example, to perform AuSn bonding. However, this bonding is not limited to AuSn bonding, and various bonding methods using other materials can be used. At this time, the semiconductor element 15 is displaced so that the entire surface of the upper surface 15a of the semiconductor element 15 abuts against the opposing surface 16c. As a result, a large stress is generated in the connection portion 13b of the semiconductor element layer 13, and the connection portion 13b is broken.
[0058] (4) Peeling step S4
[0059] Figure 7 1 is a cross-sectional view showing the peeling process involved in the first embodiment. After the substrate bonding device is cooled, the base substrate 11 and the support substrate 16 are taken out from the substrate bonding device. At this time, the semiconductor element 15 is bonded to the support substrate 16, and the connecting portion 13b is broken, so the base substrate 11 can be easily peeled off. In the accompanying drawings, the columnar connecting portion 13b is attached to the semiconductor element layer 13. It is conceivable that the connecting portion 13b remains on the base substrate 11 side, the semiconductor element 15 side, or both sides depending on the state of the breakage. Therefore, after peeling, the connecting portion 13b remaining on the semiconductor element 15 is removed by grinding or the like.
[0060] In the semiconductor element body 17 bonded and peeled by the above method, the first surface 13a of the semiconductor element layer 13 is parallel to the opposite surface 16c which is the surface of the support substrate 16. On the other hand, the second surface 13c of the semiconductor element layer 13 is inclined relative to the surface of the support substrate 16 corresponding to the inclination of the first surface 13a of the semiconductor element layer 13. Here, if the first surface 13a of the semiconductor element layer 13 is inclined less than 0.5° relative to the surface of the support substrate 16, it is considered to be parallel.
[0061] Thus, the semiconductor element body 17 of the first embodiment includes the support substrate 16, the first surface 13a, and the second surface 13c located on the opposite side to the first surface 13a, and one side of the first surface 13a is fixed to the support substrate 16. In addition, the semiconductor element body 17 includes the semiconductor element layer 13 in which the second surface 13c is inclined relative to the surface of the support substrate 16. Thus, a semiconductor element layer 13 of excellent quality can be realized by a simple support structure.
[0062] In this way, since the semiconductor element 15 has an upper surface 15a inclined with respect to the growth surface 11a of the base substrate 11, when pressurization is performed in the bonding step S3, shear stress is concentrated on the end of the columnar connection portion 13b and sheared. Therefore, even without applying a force in the vertical direction to the surface of the base substrate 11 by ultrasonic waves or the like, the semiconductor element 15 can be reliably separated from the base substrate 11 only by applying pressure. In this way, even without applying an excessive force to the semiconductor element 15, the semiconductor element 15 can be reliably transferred to the support substrate 16, so that the yield rate of the semiconductor element 15 can be improved.
[0063] (Second embodiment)
[0064] (1) Element forming process S1
[0065] Figure 8A to Figure 8C 2 is a cross-sectional view showing the element forming process according to the second embodiment. Fig. 8A As shown, first, a base substrate 21 is prepared. As the base substrate 21, a GaN template substrate is used, for example, as in the first embodiment. However, there is no deviation angle in the crystal plane of the growth surface 21a of the base substrate 21. In the same process as in the first embodiment, a mask 22 is formed. The growth surface 21a is exposed through the opening 22b of the strip 22a of the mask 22.
[0066] Then, if Figure 8BAs shown, similarly to the first embodiment, a semiconductor element layer 23 as a crystal growth layer of a nitride semiconductor is vapor-grown from the growth surface 20a exposed from the opening 22b of the strip-shaped body 22a. Then, a metal layer 24 such as an AuSn alloy is formed on the first surface 23a of the semiconductor element layer 23.
[0067] Next, if Figure 8C As shown, the mask 22 on the base substrate 21 is etched to form a semiconductor element 25 on the base substrate 21. The first surface 23a of the semiconductor element layer 23 and the upper surface 25a of the semiconductor element 25 are substantially parallel to the growth surface 21a of the base substrate 21. Even in the second embodiment, similarly to the first embodiment, the semiconductor element layer 23 has the first surface 23a and the second surface 23c located on the opposite side thereof.
[0068] (2) Preparation process S2
[0069] Fig. 9 : is a cross-sectional view showing the preparation process involved in the second embodiment. Next, a support substrate 26 for bonding with the semiconductor element 25 is prepared. A silicon substrate is used as the base 26a of the support substrate 26, for example. A silicon substrate, for example, a deviated substrate having a plane direction with an off angle of (111) to 0.3°, that is, the support substrate 26 has an opposing surface 26c opposed to the base substrate 21. The support substrate 26 can use a deviated substrate in which the opposing surface 26c is a crystal plane having an off angle relative to the normal line of the opposing surface 26c. A stripe-shaped photoresist film is formed on such a deviated substrate, and anisotropic etching is performed with a KOH (potassium hydroxide) aqueous solution, thereby providing an inclined surface 26d on the base 26a. Furthermore, a metal layer 26b such as gold is formed on the silicon substrate by a vapor deposition method or the like. The support substrate 26 formed in this way has an opposing surface 26c having an inclined inclined surface 26d. The inclination angle α of the inclined surface 26d is substantially the same as the off angle.
[0070] The facing surface 26c of the support substrate 26 is inclined relative to the base substrate 21 by an amount corresponding to the angle α. The facing surface 26c is formed for each row of the semiconductor elements 25 arranged on the base substrate 21. Therefore, it is preferable that the pitch of the semiconductor elements 25 arranged on the base substrate 21 is consistent with the pitch of the plurality of inclined surfaces 26d formed on the support substrate 26. Next, the semiconductor element 25 is connected to the support substrate 16 using a substrate bonding device (not shown). First, it is mounted on the substrate bonding device so that the growth surface 21a of the base substrate 21 and the facing surface 26c of the support substrate 26 are opposite.
[0071] (3) Joining process S3
[0072] Fig. 10A as well as Fig. 10B2 is a cross-sectional view showing the bonding process involved in the second embodiment. Fig. 10A As shown in FIG. 2 , the facing surface 26c of the support substrate 26 is brought into contact with the upper surface 25a of the semiconductor element 25. Since the facing surface 26c of the support substrate 26 is inclined, a portion of the upper surface 25a of the semiconductor element 25 is brought into contact with the facing surface 26c. Fig. 10B As shown, the support substrate 26 is pressurized, and the upper surface 25a of the semiconductor element 25 is pressed against the opposing surface 26c of the support substrate 26 and bonded, for example, by heating to 300°C to perform AuSn bonding. At this time, the semiconductor element 25 is displaced so that the entire surface of the upper surface 25a of the semiconductor element 25 abuts against the opposing surface 26c. As a result, a large shear stress is generated at the end of the connection portion 23b of the semiconductor element layer 23, and the connection portion 23b is broken.
[0073] (4) Peeling step S4
[0074] Fig.11 2 is a cross-sectional view showing a peeling process according to the second embodiment. After the substrate bonding device is cooled, if the base substrate 21 and the support substrate 26 are taken out from the substrate bonding device, the semiconductor element 25 is bonded to the opposing surface 26c of the support substrate 26, and the connecting portion 23b is broken, so that the base substrate 21 can be easily peeled off. In the drawings, for example, the columnar connecting portion 23b is attached to the semiconductor element layer 23, but the connecting portion 23b can be removed by grinding or the like.
[0075] Thus, before the bonding step S3, the opposing surface 26c of the support substrate 26 is inclined relative to the growth surface 21a of the base substrate 21 or the upper surface 25a of the semiconductor element 25. Therefore, in the bonding step S3, when the upper surface 25a of the semiconductor element 25 is pressed against the opposing surface 26c of the support substrate 26, shear stress is concentrated at the end of the connection portion 23b and sheared. Therefore, even without applying a force such as ultrasonic waves, the semiconductor element 25 can be reliably separated from the base substrate 21 by applying pressure only by the substrate bonding device. In this way, the semiconductor element 25 can be reliably transferred to the support substrate 26 by applying only a smaller force than before to the semiconductor element 25. Thus, the yield rate of the semiconductor element 25 can be improved.
[0076] In the semiconductor element body 27 bonded and separated by the above-described method, a portion of the facing surface 26 c of the support substrate 26 is inclined.
[0077] Thus, the semiconductor element body 27 of the second embodiment includes the support substrate 26, the first surface 23a, and the second surface 23c located on the opposite side to the first surface 23a, and one side of the first surface 23a is fixed to the support substrate 26. In addition, the semiconductor element body 27 includes the semiconductor element layer 23 whose second surface 23c is inclined relative to the surface of the support substrate 26. Thus, the support substrate 26 also has an inclined surface, so that the semiconductor element body 27 is easy to cleave, etc., and the operation of separating into individual semiconductor elements 25 becomes easy.
[0078] (Third embodiment)
[0079] (1) Element forming process S1
[0080] In the third embodiment, the base substrate used in the element forming step S1 and the semiconductor element formed are the same as those in the second embodiment, and thus the description thereof is omitted, and the same reference numerals are used.
[0081] (2) Preparation process S2
[0082] Fig.12 : is a cross-sectional view showing the preparation process involved in the third embodiment. A support substrate 36 for bonding with a semiconductor element 25 is prepared. A silicon substrate is used as the base 36a of the support substrate 36, for example. A c-plane substrate with a plane direction of (100) is used as the base 36a. First, a layer having Ti (titanium) as a base layer and an Au layer stacked thereon is formed on the base 36a, for example. A stripe-shaped mask is made on the formed layer, for example, AuSn is vapor-deposited. Then, by using a vapor deposition stripping method in which the Au layer vapor-deposited on the mask is removed together with the mask, a support substrate 36 having an opposing surface 36c formed with a metal layer 36b having stripe-shaped concave and convex shapes is obtained. It is preferred that the spacing of the semiconductor elements 25 arranged on the base substrate 21 is consistent with the spacing of the stripe-shaped concave and convex of the support substrate 36. A step portion 36d is formed at the boundary between the concave portion and the convex portion of the opposing surface 36c.
[0083] (3) Joining process S3
[0084] The semiconductor element 25 and the support substrate 36 are bonded together using a substrate bonding device (not shown). Fig.13A as well as Fig. 13B 2 is a cross-sectional view showing the bonding process involved in the third embodiment. Fig.13A As shown in FIG. 1 , the facing surface 36c of the support substrate 36 is brought into contact with the upper surface 25a of the semiconductor element 25. The facing surface 36c of the support substrate 36 has a step portion 36d. Therefore, a portion of the upper surface 25a of the semiconductor element 25 is brought into contact with the facing surface 36c. Next, as shown in FIG. Fig. 13BAs shown, the support substrate 36 is pressurized, the upper surface 25a is pressed against the support substrate 36, and the AuSn bonding is performed by heating to 300°C. At this time, the step portion 36d of the opposing surface 36c abuts against the upper surface 25a of the semiconductor element 25, and the semiconductor element 25 is displaced so that the upper surface 25a of the semiconductor element 25 approaches the concave portion of the opposing surface 36c. As a result, a large shear stress is generated in the connection portion 23b of the semiconductor element layer 23, and the connection portion 23b is broken.
[0085] (4) Peeling step S4
[0086] Fig.14 2 is a cross-sectional view showing a peeling process according to the third embodiment. After the substrate bonding device is cooled, if the base substrate 21 and the support substrate 36 are taken out from the substrate bonding device, the semiconductor element 25 is bonded to the support substrate 36, and the connecting portion 23b is broken, so the base substrate 21 can be easily peeled off. At this time, in the bonding process S3, the opposing surface 36c is flat, and the metal layer 36b and the metal layer 24 are integrated. That is, the first surface 23a of the semiconductor element layer 23 is also fixed to the opposing surface 36c as the surface of the support substrate 36 via the metal. In the drawings, for example, the columnar connecting portion 23b is attached to the semiconductor element layer 23, but the connecting portion 23b can be removed by grinding or the like.
[0087] In this way, the facing surface 36c of the support substrate 36 has a step portion 36d. Therefore, in the bonding step S3, when the upper surface 25a of the semiconductor element 25 is pressed against the facing surface 36c, shear stress is concentrated on the end of the connecting portion 23b on the base substrate 21 side, and the connecting portion 23b is sheared. Therefore, even without applying a force such as ultrasonic waves, the semiconductor element 25 can be reliably separated from the base substrate 21 by only applying pressure. In this way, the semiconductor element 25 can be reliably transferred to the support substrate 36 by only applying a smaller force than before, and the yield rate of the semiconductor element 25 can be improved.
[0088] In the semiconductor element body 37 bonded and peeled by the above method, the first surface 23 a of the semiconductor element layer 23 is inclined with respect to the facing surface 36 c which is the surface of the support substrate 36 due to the structure of the step portion 36 d .
[0089] Thus, the semiconductor element body 37 of the third embodiment includes the support substrate 36, the first surface 23a, and the second surface 23c located on the opposite side to the first surface 23a, and one side of the first surface 23a is fixed to the support substrate 26. Moreover, in the semiconductor element body 37, among the first surface 23a and the second surface 23c, at least the first surface 23a is inclined relative to the surface of the support substrate 36. Thus, the support substrate 26 can also have an inclined surface by a simple structure, and similarly to the second embodiment, the semiconductor element body 37 can be easily split, etc., and the operation of separating into individual semiconductor elements 25 becomes easy.
[0090] Although the present disclosure has been described in detail above, the present disclosure is not limited to the above-mentioned embodiments, and various changes and improvements can be made without departing from the scope of the present disclosure. Therefore, the above-mentioned embodiments are merely illustrative in all aspects, and the scope of the present invention is the scope indicated in the claims, and is not subject to any restrictions in the main text of the specification. Furthermore, all deformations and changes belonging to the claims are within the scope of the present invention.
[0091] Explanation of symbols
[0092] S1: Component forming process;
[0093] S2: preparation process;
[0094] S3: bonding process;
[0095] S4: stripping process;
[0096] 11, 21: base substrate;
[0097] 13, 23: semiconductor element layer;
[0098] 13a, 23a: Page 1;
[0099] 13b, 23b: connecting part;
[0100] 13c, 23c: Side 2;
[0101] 14, 24, 16b, 26b, 36b: metal layer;
[0102] 15, 25: semiconductor components;
[0103] 15a, 25a: upper surface;
[0104] 16, 26, 36: Support base plate;
[0105] 16c, 26c, 36c: opposite surfaces;
[0106] 17, 27, 37: Semiconductor element body.
Claims
1. A semiconductor substrate comprising: base substrate; A mask having a plurality of strip-shaped portions located on the base substrate and opening portions located between adjacent strip-shaped portions; and a semiconductor element layer extending from the growth surface of the base substrate exposed from the opening and extending along the upper surface of the mask, The semiconductor element layer has an upper surface that is located on the opposite side of a surface along the upper surface of the mask and is inclined in one direction with respect to the growth surface.
2. The semiconductor substrate according to claim 1, wherein The mask has a stripe shape in which the strip-shaped portions are arranged at given intervals.
3. A semiconductor substrate comprising: a base substrate comprising a growth surface; and a semiconductor element layer extending from the growth surface, The semiconductor element layer has: a first surface as an upper surface; and a second surface located on the opposite side of the first surface and facing the base substrate with a gap therebetween. The first surface is inclined with respect to the growth surface.
4. The semiconductor substrate according to claim 1 or 3, wherein: The semiconductor element layer includes a columnar connection portion grown from the growth surface.
5. The semiconductor substrate according to claim 4, wherein: When the semiconductor element layer is pressed, the connection portion is tilted with respect to the base substrate, and stress is concentrated on the end of the connection portion, so that the connection portion is broken.
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JP1971038958B1