Chip packaging structure

Abstract

The invention provides a chip packaging structure, and belongs to the technical field of chip packaging heat dissipation, the chip packaging structure comprises a wafer stacking structure and a three-dimensional heat dissipation structure, the wafer stacking structure comprises at least two wafer layers which are stacked, and the three-dimensional heat dissipation structure comprises an interlayer heat dissipation layer and a side surface heat dissipation layer. The interlayer heat dissipation layer covers the upper surface of each wafer layer, and the periphery of the interlayer heat dissipation layer at least extends to the peripheral edge of each wafer layer. And the side surface heat dissipation layer covers the side surface of the wafer stacking structure and is connected with each interlayer heat dissipation layer. According to the technical scheme of the invention, an interconnected and intercommunicated three-dimensional heat dissipation structure can be formed between the layers and the side surfaces of the stacked wafers, and the packaging requirement of high integration density can be met on the premise of remarkably improving the heat dissipation performance.

Description

Technical Field

[0001] The present application relates to the field of chip packaging and heat dissipation technology, and in particular to a chip packaging structure. Background Art

[0002] With the rapid development of information technology, the amount of data is showing an explosive growth trend, which has led to a continuous increase in the demand for computing chips. The performance improvement of computing chips requires more power consumption support. In order to ensure the performance stability of computing chips, efficient heat dissipation technology has become the key. Chip-level heat dissipation technology came into being. It is a heat dissipation measure implemented on the surface or inside of the chip. Compared with traditional heat dissipation methods, it has the advantage of transferring heat more directly and quickly, and will not greatly increase the volume of the final package.

[0003] The mainstream chip-level cooling technologies on the market currently include heat pipes, VC heat spreaders, diamond and graphene cooling technologies, etc. Heat pipe cooling technology uses the phase change of the working fluid inside the heat pipe to transfer heat, and has the advantages of high heat transfer efficiency and simple structure; VC heat spreader cooling technology evenly distributes heat through the flow of steam inside the heat spreader, which can effectively reduce the temperature gradient on the chip surface; diamond and graphene cooling technologies use the excellent thermal conductivity of these two materials to achieve efficient heat dissipation.

[0004] However, although these materials have excellent thermal conductivity, the current heat dissipation technology still has shortcomings. Under the 2.5D and 3D packaging architecture, the integration density of the chip is greatly improved, the heat is more concentrated, and the heat dissipation path is more complicated. Existing heat dissipation technology is difficult to meet the needs of high heat dissipation efficiency at the same time when faced with such a high integration density packaging form. For example, heat pipe and VC temperature plate heat dissipation technology may be subject to space constraints in high integration density packaging and cannot give full play to its heat dissipation advantages; and although diamond and graphene heat dissipation technologies have high thermal conductivity, there are still some technical bottlenecks in the integration with the chip and the design of the heat dissipation structure, which makes it impossible to fully meet the stringent requirements for heat dissipation performance under 2.5D and 3D packaging in practical applications. Summary of the invention

[0005] The purpose of the present application is to provide a chip packaging structure, which can form an interconnected three-dimensional heat dissipation structure between stacked chip layers and sides, and can meet the packaging requirements of high integration density while significantly improving the heat dissipation performance.

[0006] The present application provides a chip packaging structure, including a wafer stacking structure and a three-dimensional heat dissipation structure, wherein the wafer stacking structure includes at least two wafer layers stacked, and the three-dimensional heat dissipation structure includes an interlayer heat dissipation layer and a side heat dissipation layer. The interlayer heat dissipation layer covers the upper surface of each wafer layer, and its four sides extend at least to the peripheral edge of each wafer layer. The side heat dissipation layer covers the side of the wafer stacking structure and connects each interlayer heat dissipation layer.

[0007] In an implementable solution, the chip packaging structure further includes a heat dissipation cover, which covers the chip stacking structure; wherein the side heat dissipation layer and the uppermost interlayer heat dissipation layer are tightly fitted to the inner wall of the heat dissipation cover.

[0008] In an implementable solution, the bottom of the side heat dissipation layer extends in all directions to contact the bottom surface of the side wall of the heat dissipation cover.

[0009] In an practicable solution, when the heat dissipation cover is provided to cover the wafer stacking structure, the protruding parts of the heat dissipation layers between the layers are connected to each other by mechanical pressing to form a side heat dissipation layer, which is in close contact with the inner wall of the heat dissipation cover.

[0010] In an implementable solution, a heat dissipation unit is provided on the upper surface and / or side surface of the exterior of the heat dissipation cover.

[0011] In an implementable solution, a liquid cooling channel for circulating coolant is provided in the heat dissipation cover.

[0012] In one feasible solution, adjacent wafer layers are interconnected horizontally by micro-bumps or hybrid bonding.

[0013] In an implementable solution, a vertical conductive structure for vertically penetrating conduction is provided in the wafer layer, and an opening corresponding to the vertical conductive structure is provided in the interlayer heat dissipation layer, and the size of the opening is larger than the size of the vertical conductive structure.

[0014] In an implementable solution, the wafer layer at the bottom of the wafer stack structure is the first wafer layer, and the wafer layer above the first wafer layer is the second wafer layer;

[0015] The first wafer layer includes one or more logic wafers, and each second wafer layer includes one or more memory wafers.

[0016] In an implementable solution, the interlayer heat dissipation layer and the side heat dissipation layer are graphene films.

[0017] Compared with the prior art, the beneficial effects of the present application include at least: in the chip packaging structure of the present application, by setting an interlayer heat dissipation layer on the surface of the chip layer, and setting a side heat dissipation layer connected to the interlayer heat dissipation layer on the side wall of the chip stacking structure, an interconnected three-dimensional heat dissipation structure can be established between the layers and the sides of the chip stacking structure. The interlayer heat dissipation layer transfers the interlayer heat to the side heat dissipation layer, thereby significantly improving the thermal conductivity and heat dissipation performance, while also being able to meet the packaging requirements of high integration density. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0019] Figure 1 It is a structural schematic diagram of a chip packaging structure according to an embodiment of the present application;

[0020] Figure 2 for Figure 1 A schematic diagram of a chip packaging structure provided with a substrate;

[0021] Figure 3 for Figure 1 A schematic diagram of a chip package structure provided with a heat dissipation cover;

[0022] Figure 4 is a relative schematic diagram of a vertical conductive structure and an interlayer heat dissipation layer according to an embodiment of the present application;

[0023] Figure 5 It is a structural schematic diagram of another chip packaging structure according to an embodiment of the present application;

[0024] Figure 6 for Figure 5 A schematic diagram of a chip packaging structure provided with a substrate;

[0025] Figure 7 for Figure 6 Schematic diagram of a chip package structure with a heat dissipation cover

[0026] Figure 8 It is a structural schematic diagram of a chip packaging structure with a heat dissipation unit according to an embodiment of the present application;

[0027] Fig. 9 It is a structural schematic diagram of a chip packaging structure in which a heat dissipation cover has a liquid cooling channel according to an embodiment of the present application;

[0028] Fig.10 It is a schematic diagram of a local structure of a wafer layer and its bonding interface according to an embodiment of the present application;

[0029] Fig.11 It is a schematic diagram of the local structure of another wafer layer and its bonding interface according to an embodiment of the present application.

[0030] In the figure: 10, substrate; 1, chip stacking structure; 11, chip layer; 111, first chip layer; 112, second chip layer; 12, vertical conductive structure; 113, bonding dielectric layer; 114, bonding gasket; 2, three-dimensional heat dissipation structure; 21, interlayer heat dissipation layer; 211, opening; 22, side heat dissipation layer; 3, heat dissipation cover; 31, liquid cooling channel; 32, heat dissipation fins. DETAILED DESCRIPTION

[0031] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0032] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0033] like Figure 1 and Figure 5 As shown, an embodiment of the present application provides a chip packaging structure, including a chip stacking structure 1 and a three-dimensional heat dissipation structure 2.

[0034] The wafer stacking structure 1 includes at least two wafer layers 11 stacked together. For example, Figure 1 The wafer stacking structure 1 includes two wafer layers 11. For example, Figure 5 The wafer stack structure 1 in FIG. 1 includes five wafer layers 11 .

[0035] The three-dimensional heat dissipation structure 2 includes an interlayer heat dissipation layer 21 and a side heat dissipation layer 22. The interlayer heat dissipation layer 21 covers the upper surface of each wafer layer 11, and its periphery at least extends to the peripheral edge of each wafer layer 11. The side heat dissipation layer 22 covers the side of the wafer stacking structure 1 and connects each interlayer heat dissipation layer 21.

[0036] In the chip packaging structure of the present application, an interlayer heat dissipation layer 21 is arranged on the surface of the chip layer 11, and a side heat dissipation layer 22 connected to the interlayer heat dissipation layer 21 is arranged on the side wall of the chip stacking structure 1, so that an interconnected three-dimensional heat dissipation structure 2 can be established between the layers and the sides of the chip stacking structure 1. The interlayer heat dissipation layer 21 transfers the interlayer heat to the side heat dissipation layer 22, thereby significantly improving the thermal conductivity and heat dissipation performance, while also being able to meet the packaging requirements of high integration density.

[0037] In one embodiment, if Figure 2 and Figure 6 As shown, the chip packaging structure includes a substrate 10, and the wafer stacking structure 1 is disposed on the substrate 10. A redistribution layer (RDL) may be disposed in the substrate 10 to optimize the circuit distribution.

[0038] In one embodiment, each wafer layer 11 may include one or more wafers.

[0039] In one embodiment, if Figure 2 and Figure 6 As shown, the wafer layer 11 at the bottom of the wafer stacking structure 1 is the first wafer layer 111, and the wafer layer above the first wafer layer 111 is the second wafer layer 112. The first wafer layer 111 may include one or more logic wafers (such as microprocessors, CPUs, etc.), and each second wafer layer 112 includes one or more memory wafers (such as SRAM wafers, DRAM wafers, MRAM wafers, other types of memory wafers or combinations thereof, etc.).

[0040] In some embodiments, the first chip layer 111 at the bottom generates more heat than the second chip layer 112 at the top. The three-dimensional heat dissipation structure 2 constructed by this embodiment can optimize the heat transfer and heat dissipation effect and improve the performance.

[0041] In one embodiment, the interlayer heat dissipation layer 21 and the side heat dissipation layer 22 preferably adopt a thin film structure made of graphene, which has excellent heat transfer performance and can be made very thin. For example, in this embodiment, the thickness of the interlayer heat dissipation layer 21 and the side heat dissipation layer 22 made of graphene material is preferably 1-10 microns, such as 1 micron, 2 microns, 3 microns, 5 microns, 8 microns, etc. In addition, the interlayer heat dissipation layer 21 and / or the side heat dissipation layer 22 can be manufactured by a graphene deposition process.

[0042] In one embodiment, adjacent wafer layers 11 are interconnected horizontally by micro-bumps or hybrid bonding.

[0043] In one embodiment, if Figure 4As shown, a vertical conductive structure 12 for vertically penetrating conduction is provided in the wafer layer 11, and an opening 211 corresponding to the vertical conductive structure 12 is provided in the interlayer heat dissipation layer 21, and the size of the opening 211 is larger than the size of the vertical conductive structure 12. The vertical conductive structure 12 may include a through silicon via (TSV) or other types of vertical conductive structures.

[0044] The vertical conductive structure 12 can be prefabricated before the wafer layer 11 is bonded, or it can be fabricated after the wafer layer 11 is bonded. Both processes have their own advantages and disadvantages, and a flexible choice can be made based on actual conditions.

[0045] In one embodiment, if Figure 3 and Figure 7 As shown, the chip packaging structure may further include a heat dissipation cover 3, which covers the chip stacking structure 1. The side heat dissipation layer 22 and the uppermost interlayer heat dissipation layer 21 are tightly fitted with the inner wall of the heat dissipation cover 3. The heat dissipation cover 3 itself can be used as an external heat dissipation structure, or the heat dissipation cover 3 can be connected to other external heat dissipation structures, and because the heat dissipation cover 3 is tightly fitted with the three-dimensional heat dissipation structure 2, the heat transferred by the three-dimensional heat dissipation structure 2 can be more effectively dissipated, thereby improving the heat dissipation performance.

[0046] In one embodiment, if Figure 3 and Figure 7 As shown, the bottom of the side heat dissipation layer 22 extends in all directions and contacts the bottom surface of the side wall of the heat dissipation cover 3, that is, the bottom of the side wall of the heat dissipation cover 3 presses part of the side heat dissipation layer 22, thereby further ensuring the close combination of the three-dimensional heat dissipation structure 2, thereby maximizing the heat dissipation performance.

[0047] It should be noted that, assuming that the interlayer heat dissipation layer 21 and the side heat dissipation layer 22 are made of graphene material or other conductive materials, due to their good conductivity, those skilled in the art need to make good insulation isolation between the heat dissipation layer and the circuit layer and conductive structure of the chip to avoid affecting the normal function of the chip. Among them, the conductive structure of the chip can be a micro-bump or a hybrid bonding pad (or a copper contact for hybrid bonding).

[0048] In one embodiment, if the wafer layers 11 are connected by micro-bumps, when the interlayer heat dissipation layer 21 is made, as the stacking proceeds, heat dissipation material can be deposited on the upper surface of each wafer layer 11 to form the interlayer heat dissipation layer 21, which is equivalent to the interlayer heat dissipation layer 21 and the wafer layer 11 being an independent layer structure. At the same time, part of the heat dissipation material can also be deposited on the outer side of the edge of the wafer layer 11, which can be called the protruding part of the interlayer heat dissipation layer 21 extending from the periphery of the wafer layer 11. In addition, the circumferential dimension of the inner wall of the heat dissipation cover 3 is slightly larger than the circumferential dimension of the wafer stacking structure 1. Preferably, the circumferential dimension of the inner wall of the heat dissipation cover 3 is slightly larger than the circumferential dimension of the wafer stacking structure 1 by 1-10 microns. When the heat dissipation cover 3 is subsequently installed, when the heat dissipation cover 3 covers the wafer stacking structure 1, the heat dissipation cover 3 will squeeze the protruding parts of the periphery of each wafer layer 11, that is, the protruding parts of each interlayer heat dissipation layer 21 are connected to each other by mechanical pressing of the heat dissipation cover 3 to form a side heat dissipation layer 22, and are in close contact with the inner wall of the heat dissipation cover 3.

[0049] In addition, if the present embodiment uses a graphene film as a heat dissipation layer, and the wafer layers 11 are connected by micro-bumps, the graphene film needs to avoid the micro-bump area, mainly covering the blank area (non-circuit area) of the wafer, or embedded between the micro-bump arrays as an interlayer filling material. Preferably, a graphene grid can be formed in the non-circuit area around the micro-bumps as an interlayer heat dissipation layer 21 to laterally export heat to the edge of the package.

[0050] In one embodiment, if the wafer layers 11 are connected by hybrid bonding, assuming that the heat dissipation layer is a high thermal conductivity dielectric material (such as an oxide layer filled with a thermally conductive polymer) that is compatible with the hybrid bonding process, it is not necessary to embed the interlayer heat dissipation layer 21 in the bonding interface layer of the wafer layer 11. Assuming that the heat dissipation layer is made of a graphene film, the interlayer heat dissipation layer 21 can be in the bonding interface layer of each wafer layer 11. Fig.11 As shown, the bonding interface layer includes a bonding dielectric layer 113 surrounding the bonding pad 114, and the interlayer heat dissipation layer 21 can be directly made as a part of the bonding dielectric layer 113 (see Fig.11 ), or the surface of the bonding dielectric layer 113 covering the bonding pad 114 (see Fig.10 ).

[0051] For example, Fig.10 As shown in FIG. 1 , a graphene film layer may be formed only on the surface of the bonding medium layer 113; or as shown in FIG. Fig.11 As shown, multiple graphene film layers can be embedded in the bonding dielectric layer 113, and the multiple graphene film layers can accelerate the lateral diffusion of heat. It should be noted that no matter how many layers of the interlayer heat dissipation layer 21 there are, it is ultimately necessary to ensure the coplanarity of the bonding pad (copper contact) and the bonding interface layer.

[0052] Fig.10 and Fig.11 The structure is equivalent to using the interlayer heat dissipation layer 21 as a part of the bonding interface layer on the upper surface of the wafer layer 11, thereby adapting the hybrid bonding process to meet the vertical high-density integrated stacking as much as possible. The interlayer heat dissipation layer 21 can also be set on the surface of the bonding medium layer 113 on the lower surface of the wafer layer 11 or between the layers, but in order to improve the integration density, it is preferred to set the interlayer heat dissipation layer 21 only in the bonding interface layer on the upper surface of the wafer layer 11.

[0053] In addition, after the hybrid bonding connection, the side heat dissipation layer 22 can still be formed by forming a protruding portion of heat dissipation material on the periphery of the wafer layer 11 and then mechanically pressing the heat dissipation cover 3.

[0054] In one embodiment, a heat dissipation unit may be provided on the upper surface and / or side surface of the heat dissipation cover 3, and the heat dissipation unit may include one or more combinations of heat dissipation fins, a heat spreader, and a heat pipe. Figure 8 As shown, heat dissipation fins 32 may be provided on the upper surface and side surfaces of the heat dissipation cover 3 to enhance the heat dissipation performance.

[0055] In one embodiment, if Fig. 9 As shown, a liquid cooling channel 31 for cooling liquid circulation may be provided in the heat dissipation cover 3 to further improve the heat dissipation performance.

[0056] It should be noted that the drawings are only schematic diagrams and are not drawn according to accurate proportions. In order to highlight the structural features, some layer structures or conductive contacts are exaggerated. At the same time, in order to highlight only the main features of the technical solution of this application, the drawings do not show the well-known protective layers, insulating layers and other structures. In actual applications, those skilled in the art can flexibly select and design the structural layers not shown in the drawings according to design requirements and design experience.

[0057] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A chip packaging structure, characterized in that: include: A wafer stacking structure (1), comprising at least two wafer layers (11) stacked together; The three-dimensional heat dissipation structure (2) comprises: An interlayer heat dissipation layer (21) covers the upper surface of each wafer layer (11), and its periphery at least extends to the peripheral edge of each wafer layer (11); A side heat dissipation layer (22) covers the side of the chip stacking structure (1) and connects each of the interlayer heat dissipation layers (21).

2. The chip packaging structure according to claim 1, characterized in that: The chip packaging structure also includes a heat dissipation cover (3) which covers the chip stacking structure (1); The side heat dissipation layer (22) and the uppermost interlayer heat dissipation layer (21) are tightly fitted to the inner wall of the heat dissipation cover (3).

3. The chip packaging structure according to claim 2, characterized in that: The bottom of the side heat dissipation layer (22) extends in all directions and contacts the bottom surface of the side wall of the heat dissipation cover (3).

4. The chip packaging structure according to claim 2, characterized in that: When the heat dissipation cover (3) covers the wafer stacking structure (1), the protruding parts of the interlayer heat dissipation layers (21) are connected to each other by mechanical pressing to form the side heat dissipation layer (22), which is in close contact with the inner wall of the heat dissipation cover (3).

5. The chip packaging structure according to claim 2, characterized in that: A heat dissipation unit is provided on the upper surface and / or side surface of the exterior of the heat dissipation cover (3).

6. The chip packaging structure according to claim 2, characterized in that: The heat dissipation cover (3) is provided with a liquid cooling channel (31) for circulating cooling liquid.

7. The chip packaging structure according to claim 1, characterized in that: Adjacent wafer layers (11) are interconnected horizontally between layers through micro-bumps or hybrid bonding.

8. The chip packaging structure according to claim 1, characterized in that: The wafer layer (11) is provided with a vertical conductive structure (12) for vertically penetrating conduction, and the interlayer heat dissipation layer (21) is provided with an opening (211) corresponding to the vertical conductive structure (12), and the size of the opening (211) is larger than the size of the vertical conductive structure (12).

9. The chip packaging structure according to claim 1, characterized in that: The wafer layer (11) at the bottom of the wafer stacking structure (1) is a first wafer layer (111), and the wafer layer above the first wafer layer (111) is a second wafer layer (112); The first wafer layer (111) includes one or more logic wafers, and each of the second wafer layers (112) includes one or more memory wafers.

10. The chip packaging structure according to claim 1, characterized in that: The interlayer heat dissipation layer (21) and the side heat dissipation layer (22) are graphene films.

Images