FCBGA packaging structure

Abstract

The invention relates to the field of chip packaging, in particular to an FCBGA packaging structure. Comprising a substrate used for installing an MXG100 chip. Two memory pin connection areas are arranged on the substrate in an axial symmetry mode, and the symmetry axis of the two memory pin connection areas coincides with the symmetry axis of the two dynamic random access memory interface areas. According to the method, firstly, according to the characteristic of symmetric layout of GDDR PHY in the MXG100 chip, two memory pin connection areas are arranged in an axial symmetry manner, so that the connection scheme in the two memory pin connection areas can be reused; meanwhile, the pin arrangement modes in each unit pin connection area in each memory pin connection area are the same, so that the reuse rate of the pin arrangement scheme in the connection scheme can be improved. In addition, when simulation verification is carried out in the later period, only one connection scheme with the longest wiring distance needs to be carried out. Therefore, the simulation verification frequency is reduced, and the development efficiency of the GPU is improved.

Description

Technical Field

[0001] The invention relates to the field of chip packaging, and in particular to an FCBGA packaging structure. Background Art

[0002] With the development of technology, some technologies with high requirements for graphics rendering acceleration have gradually emerged, such as Ai drawing and metaverse. In order to meet the usage requirements of the above scenarios, existing graphics cards are designed with large-size FCBGA (Flip Chip Ball Grid Array, a packaging format of flip chip ball grid array) packaging design structure, and the graphics card has a display chip with higher computing performance and more video memory. The display chip determines the functions that the graphics card can provide and its basic performance, and the performance of the graphics card depends largely on the video memory. The capacity of the video memory determines the resolution of the image, and the computing power of the display chip determines the efficiency of the image. This improves the efficiency of rendering and the resolution of the image.

[0003] However, in the prior art, when designing a GPU (graphics processing unit), GDDRPHY (Graphics Double Data Rate Physical, a chip for the external signal interface of the video memory) and GDDR (Graphics Double Data Rate, video memory) particles are placed irregularly, resulting in the need to perform layout and wiring design for each channel separately during package design and product PCB board design, which in turn results in different layout and wiring schemes corresponding to each channel, so all channels of the entire board need to be simulated and verified in the later stage. This ultimately results in a large number of verification operations, which is time-consuming and labor-intensive and prone to errors, reducing the development efficiency of the GPU. Summary of the invention

[0004] In view of this, the present invention provides a FCBGA packaging structure, which at least partially solves the problems existing in the prior art.

[0005] According to one aspect of the present invention, there is provided a FCBGA packaging structure, comprising:

[0006] The substrate is used to install the MXG100 chip. Two memory pin connection areas are axially symmetrically arranged on the substrate. The two memory pin connection areas are respectively arranged close to two dynamic random access memory interface areas in the MXG100 chip. The dynamic random access memory interface area is the placement area of ​​the PHY corresponding to the dynamic random access memory in the MXG100 chip. The symmetry axes of the two memory pin connection areas coincide with the symmetry axes of the two dynamic random access memory interface areas.

[0007] The memory pin connection area includes four identical rectangular unit pin connection areas, three of which are arranged end to end along their own length direction to form a rectangular strip connection area, and the long side of the remaining unit pin connection area is arranged adjacent to the short side of the rectangular strip area to form an L-shaped pin connection area.

[0008] The arrangement of various types of pins in each unit pin connection area is the same, and each pin in each unit pin connection area is electrically connected to a pin in a corresponding PHY in the MXG100 chip.

[0009] Furthermore, the unit pin connection area includes a data line connection pin, an address line connection pin and a digital ground connection pin.

[0010] The data line connection pins are arranged close to one side of the MXG100 chip placement area, and the address line connection pins are arranged close to one side of the edge of the substrate.

[0011] A corresponding digital ground connection pin is arranged adjacently on each side around each data line connection pin.

[0012] At least three corresponding digital ground connection pins are arranged adjacently around each address line connection pin.

[0013] Furthermore, the unit pin connection area includes a data line connection pin, an address line connection pin and a digital ground connection pin.

[0014] The data line connection pins are arranged close to one side of the MXG100 chip placement area, and the address line connection pins are arranged close to one side of the edge of the substrate.

[0015] A plurality of data line connection pins belonging to the same group are sequentially and adjacently arranged in a corresponding first preset data pin area.

[0016] A plurality of address line connection pins belonging to the same group are sequentially and adjacently arranged in a corresponding second preset data pin area.

[0017] A corresponding third preset data pin region is sandwiched between any two adjacent first preset data pin regions.

[0018] A corresponding third preset data pin region is sandwiched between any two adjacent second preset data pin regions. The third preset data pin region is a straight-line pin region formed by a plurality of digital ground connection pins arranged adjacent to each other in sequence.

[0019] Furthermore, the dynamic random access memory is GDDR6 DRAM.

[0020] Furthermore, at least two circuit routing layers are arranged inside the substrate, the routing of the data line connection pins is located in the inner circuit routing layer, and the routing of the data line connection pins and the digital ground connection pins are located in the same circuit routing layer.

[0021] Furthermore, a chip power pin area and a plurality of other device pin areas are also provided on the substrate.

[0022] The chip power pin area is the pin area corresponding to the orthographic projection area below the MXG100 chip installation position in the substrate.

[0023] A plurality of other device pin regions are respectively arranged in the pin connection regions above and below the chip power pin region.

[0024] Furthermore, it also includes:

[0025] PCB graphics card mainboard, the substrate is electrically connected to the PCB graphics card mainboard.

[0026] 16 GDDR6 DRAMs, 8 GDDR6 DRAMs are arranged on the surface of both sides of the PCB graphics card motherboard.

[0027] The eight GDDR6 DRAMs on the same side surface of the PCB graphics card motherboard are divided into two groups and arranged symmetrically. The symmetry axes of the two groups of GDDR6 DRAMs are the same as the symmetry axes of the two memory pin connection areas.

[0028] The arrangement position of each GDDR6 DRAM in the same group has the same relative position with the corresponding rectangular unit pin connection area. Each GDDR6 DRAM has the same connection routing with the corresponding rectangular unit pin connection area.

[0029] Furthermore, the PCB graphics card motherboard includes multiple layers of circuit routing layers.

[0030] The connection traces between the address line connection pins and the GDDR6 DRAM are located on the upper surface circuit trace layer of the PCB graphics card motherboard.

[0031] Furthermore, the connection traces between the data line connection pins and the GDDR6 DRAM are located on the inner circuit trace layer of the PCB graphics card motherboard.

[0032] Furthermore, other device pin areas include: pin areas corresponding to the PCIe module, the Display module and the Serdes module respectively.

[0033] The technical solution of the present invention has at least the following beneficial effects:

[0034] The packaging structure of the present invention uses an MXG100 chip, which includes 8 GDDR PHYs, and is divided into two groups that are symmetrically distributed about the center line of the MXG100 chip. Based on the layout characteristics of the GDDR PHY in the chip, two memory pin connection areas are also axially symmetrically arranged on the substrate, which are used to connect the pins with the GDDRPHY in the two groups. At the same time, according to the L-shaped layout of each memory pin connection area, it is divided into 4 identical rectangular unit pin connection areas, and these 4 rectangular unit pin connection areas are arranged in an L-shaped distribution. And the pins of various categories in each unit pin connection area are arranged in the same way.

[0035] like Figure 8 As shown, since each GDDR PHY is connected to the corresponding external GDDR particles, the functions implemented in the later use are also the same. Therefore, if the placement space allows, the reuse rate of the connection scheme (pin arrangement and connection routing scheme) between each GDDRPHY and the corresponding external GDDR particles can be maximized. Therefore, there is no need to repeat the simulation verification of the reused connection scheme in the later stage, and the number of errors in the connection scheme design can also be reduced, thereby improving the development efficiency of the GPU.

[0036] In the present invention, firstly, according to the characteristics of the symmetrical layout of the GDDR PHY in the MXG100 chip, two memory pin connection areas are also axially symmetrically arranged, so that the connection schemes in the two memory pin connection areas can be reused. At the same time, the pin arrangement modes in each unit pin connection area in each memory pin connection area are the same, so that the reuse rate of the pin arrangement scheme in the connection scheme can also be improved. In addition, the number of simulation verifications can be reduced, and the development efficiency of the GPU can be improved.

[0037] In addition, since the routing schemes between each unit pin connection area and the corresponding GDDR PHY in the same memory pin connection area are only different in routing distance, during the later simulation verification, as long as the connection scheme with the longest routing distance meets the use requirements, the other connection schemes will also meet the use requirements. This can further reduce the number of simulation verifications and improve the efficiency of GPU development. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0039] Figure 1Schematic diagram of the arrangement structure of the device pin areas on the substrate in one embodiment of the present application.

[0040] Figure 2 This is a schematic diagram of the connection structure between the substrate and the MXG100 chip in another embodiment of the present application.

[0041] Figure 3 This is a schematic diagram of the connection structure between the DQ and CA pins in the GDDR PHY in the MXG100 chip and the corresponding pins on the substrate in another embodiment of the present application, and the right side is a partial enlarged view of the boxed area on the left side.

[0042] Figure 4 This is a schematic diagram of an arrangement of the pins in the unit pin connection area in another embodiment of the present application, in which the pins are generally arranged in the form of DQ:VSS=1:1 and CA:VSS=1:1.

[0043] Figure 5 This is a schematic diagram of an arrangement of the pins in the unit pin connection area in another embodiment of the present application, in which the pins are generally arranged in the form of DQ:VSS=2:1 and CA:VSS=2:1.

[0044] Figure 6 It is the result of the inter-group crosstalk experiment when the unit pin connection area is arranged according to two pin arrangements in another embodiment of the present application, wherein the horizontal axis is the communication frequency of the DQ pin, and the vertical axis is the crosstalk value of the DQ pin.

[0045] Figure 7 This is a schematic diagram of the connection between the FCBGA packaging structure and the PCB graphics card motherboard in another embodiment of the present application.

[0046] Figure 8 This is a schematic diagram of GPU reuse design in another embodiment of the present application.

[0047] Fig. 9 This is a pin distribution diagram of a GDDR6 DRAM chip in another embodiment of the present application.

[0048] Reference numerals

[0049] 1. Substrate; 10. Chip power pin area; 11. Unit pin connection area; 12. Memory pin connection area; 13. Other device pin areas; 2. MXG100 chip; 3. PCB graphics card motherboard; 4. Dynamic random access memory. DETAILED DESCRIPTION

[0050] The embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0051] It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict. Moreover, all other embodiments obtained by ordinary technicians in the field without creative work based on the embodiments in the present disclosure are within the scope of protection of the present disclosure.

[0052] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein may be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on the present disclosure, it should be understood by those skilled in the art that an aspect described herein may be implemented independently of any other aspect, and two or more of these aspects may be combined in various ways. For example, any number of aspects described herein may be used to implement the device and / or practice the method. In addition, other structures and / or functionalities other than one or more of the aspects described herein may be used to implement this device and / or practice this method.

[0053] As an embodiment of the present invention, Figure 1 and Figure 2 As shown, a FCBGA packaging structure is provided, including: a substrate 1.

[0054] The substrate 1 is used to mount the MXG100 chip 2. Specifically, the MXG100 chip 2 is packaged and connected with the substrate 1 using FCBGA. The substrate 1 is provided with a chip power pin area 10 and a plurality of other device pin areas 13.

[0055] like Figure 1 As shown, the chip power pin area 10 ( Figure 1 The dotted line area is the pin area corresponding to the positive projection area below the mounting position of the MXG100 chip 2 in the substrate 1. Figure 1 The solid line framed area) is respectively arranged in the pin connection area above and below the chip power pin area 10. The other device pin area 13 includes: the pin areas corresponding to the PCIe module, the Display module and the Serdes module respectively.

[0056] In the MXG100 chip 2, there are multiple PHY modules distributed around it, including PCIe (Peripheral Component Interconnect express, a high-speed serial computer expansion bus standard) module, Display module, Serdes (SERializer / DESerializer, the abbreviation of serializer / deserializer) module and GDDR module.

[0057] Moreover, the layout positions of these modules have the following characteristics: The PHYs of the PCIe module, Display module, and Serdes module are basically concentrated in the upper and lower boundary areas of the MXG100 chip 2, and the PHY layout in the upper boundary area is mainly concentrated in the middle position. The remaining multiple GDDR PHYs are symmetrically distributed in the left and right boundary areas of the MXG100 chip 2 and the idle part of the upper boundary area. Thus, an inverted "L"-shaped arrangement area is formed.

[0058] Based on the layout characteristics of each PHY in the above chip, two memory pin connection areas 12 ( Figure 1 The dashed line selects the area), and the symmetry axis is Figure 1 As shown by the dotted lines in the figure, the two memory pin connection areas 12 are respectively arranged near the two dynamic random access memory 4 interface areas in the MXG100 chip 2, and the dynamic random access memory 4 interface area is the placement area of ​​the PHY corresponding to the dynamic random access memory 4 in the MXG100 chip 2. The symmetry axes of the two memory pin connection areas 12 coincide with the symmetry axes of the two dynamic random access memory 4 interface areas. The dynamic random access memory 4 is a GDDR6 DRAM. Specifically, the GDDR6 DRAM chip can be: Samsung K4ZAF325BC-SC24 or K4ZAF325BC-SC20 or K4ZAF325BC-SC16.

[0059] like Figure 1 As shown, the memory pin connection area 12 includes four identical rectangular unit pin connection areas 11, of which three unit pin connection areas 11 are arranged end to end in sequence along their own length direction to form a rectangular strip connection area, and the long side of the remaining unit pin connection area 11 is arranged adjacent to the short side of the rectangular strip area to form an L-shaped pin connection area.

[0060] The arrangement of various types of pins in each unit pin connection area 11 is the same, and each pin in each unit pin connection area 11 is electrically connected to a pin in a corresponding PHY in the MXG100 chip 2 .

[0061] In the present invention, firstly, according to the characteristics of the symmetrical layout of the GDDR PHY in the MXG100 chip 2, two memory pin connection areas 12 are also axially symmetrically arranged, so that the connection schemes in the two memory pin connection areas 12 can be reused. At the same time, the pin arrangement modes in each unit pin connection area 11 in each memory pin connection area 12 are the same, so that the reuse rate of the pin arrangement scheme in the connection scheme can also be improved. In addition, the number of simulation verifications can be reduced, and the development efficiency of the GPU can be improved.

[0062] In addition, since the routing schemes between each unit pin connection area 11 and the corresponding GDDRPHY in the same memory pin connection area 12 are only different in routing distance, when performing electrical performance simulation later, as long as the connection scheme with the longest routing distance meets the use requirements, the other connection schemes will also meet the use requirements. This avoids the need to extract all channels of the entire board, and can further reduce the number of simulation verifications and improve the development efficiency of the GPU.

[0063] As another embodiment of the present invention, Figure 3 and Figure 4 As shown, the unit pin connection area 11 includes data line connection pins (DQ grid area in the figure), address line connection pins (CA grid area in the figure) and digital ground connection pins (VSS grid area in the figure).

[0064] The unit pin connection area 11 is a pin area on the substrate 1 for connecting with the GDDR PHY. The pin types included therein are the same as those in the GDDR PHY, which is the prior art in the art and will not be described in detail here.

[0065] However, different types of pins have different signal transmission rates and different requirements for signal transmission quality. Specifically, the data line connection pins have the highest signal transmission quality requirements, and the address line connection pins have the second highest signal transmission quality requirements.

[0066] like Figure 3 As shown, the data line connection pins are arranged near the side of the MXG100 chip 2 placement area, and the address line connection pins are arranged near the edge of the substrate 1. Two layers of circuit routing layers are arranged inside the substrate 1, and the routing of the data line connection pins is located in the inner circuit routing layer, and the routing of the address line connection pins, the data line connection pins and the digital ground connection pins are located in the same circuit routing layer.

[0067] like Figure 3 As shown, this arrangement can bring the following two advantages:

[0068] First, since the number of circuit routing layers in the substrate 1 is small, the routing of the address line connection pins, data line connection pins and digital ground connection pins will be arranged in the same layer as much as possible, thereby reducing space occupation. In addition, since the distribution area of ​​the data line connection pins in the GDDR6 PHY is basically symmetrical with respect to the distribution area of ​​the address line connection pins, the current pin distribution method is not prone to cross-connection when routing, which facilitates routing.

[0069] Secondly, this arrangement can facilitate the routing between the connecting pins on the substrate 1 and the corresponding pins on the PCB graphics card mainboard 3 in the later stage.

[0070] Specifically, the PCB graphics card mainboard 3 includes multiple layers of circuit routing layers.

[0071] Since the data line connection pins have higher requirements for signal transmission quality, the connection traces between the data line connection pins and the GDDR6 DRAM are located in the inner circuit trace layer of the PCB graphics card motherboard 3. The address line connection pins have slightly lower requirements for signal transmission quality, so the connection traces between the address line connection pins and the GDDR6 DRAM are located in the upper circuit trace layer of the PCB graphics card motherboard 3.

[0072] At the same time, since the address line connection pin area is closer to the edge of the substrate 1, there is no need to avoid the vias on the PCB graphics card motherboard 3 when routing, and there is a more complete routing area, which facilitates the arrangement of the routing.

[0073] A corresponding digital ground connection pin is arranged adjacently on each side around each data line connection pin.

[0074] At least three corresponding digital ground connection pins are arranged adjacently around each address line connection pin.

[0075] The pin arrangement in this embodiment is as follows Figure 4 As shown, the overall arrangement is DQ:VSS=1:1, CA:VSS=1:1.

[0076] If the distance between two pins is too close during signal transmission, crosstalk is likely to affect the signal, and the higher the transmission rate, the greater the impact of crosstalk. In order to reduce the impact of crosstalk between adjacent pins, in this embodiment, a corresponding digital ground connection pin is arranged adjacent to each side of each data line connection pin to increase the spacing between any two adjacent data line connection pins, thereby reducing the impact of crosstalk. At the same time, since the number of pins in the entire unit pin connection area 11 is limited, the pins with lower signal transmission quality requirements have a higher density of arrangement. In this embodiment, the density of the arrangement of data line connection pins and address line connection pins can be prioritized. The remaining pins are arranged according to existing pin arrangement rules, as shown in the following example. Figure 4 shown.

[0077] As another embodiment of the present invention, Figure 3 and Figure 5 As shown, the unit pin connection area 11 includes a data line connection pin, an address line connection pin and a digital ground connection pin.

[0078] like Figure 3 As shown, the data line connection pin (DQ) is arranged near one side of the MXG100 chip 2 placement area, and the address line connection pin (CA) is arranged near one side of the edge of the substrate 1.

[0079] This arrangement is the same as that in the above embodiment and will not be described in detail here.

[0080] A plurality of data line connection pins belonging to the same group are sequentially and adjacently arranged in a corresponding first preset data pin area.

[0081] A plurality of address line connection pins belonging to the same group are sequentially and adjacently arranged in a corresponding second preset data pin area.

[0082] The pin arrangement in this embodiment is as follows Figure 5 As shown, the overall arrangement is DQ:VSS=2:1, CA:VSS=2:1.

[0083] The specific grouping of the above pins is based on the GDDR6 DRAM chip. The manufacturer will define the specific pin grouping in the GDDR6 DRAM chip, such as DQ0-DQ07 is a group, DQ8-DQ015 is a group. In this embodiment, the pins belonging to the same group are arranged together, thereby saving some placement space. Specifically, Figure 4 and Figure 5 As shown, Figure 5 The pin arrangement in Figure 4 The pin arrangement in saves 24 pins.

[0084] A corresponding third preset data pin region is sandwiched between any two adjacent first preset data pin regions.

[0085] A corresponding third preset data pin region is sandwiched between any two adjacent second preset data pin regions. The third preset data pin region is a straight-line pin region formed by a plurality of digital ground connection pins arranged adjacent to each other in sequence.

[0086] Since the crosstalk between different data line groups has a greater impact, a third preset data pin area is inserted between two adjacent pin groups. This can increase the distance between different adjacent pins, thereby reducing the impact of crosstalk. Figure 5 As shown, a plurality of first preset data pin regions and second preset data pin regions are arranged vertically. Thus, by setting a third preset data pin region, the wiring spacing between two adjacent groups can be increased, and the crosstalk generated by different groups at the wiring can be reduced.

[0087] In this embodiment, since the signal transmission conditions of the pins in the same group are highly consistent, the crosstalk generated is relatively small. At the same time, since the signal transmission frequencies between the data line connection pins and the address line connection pins are quite different, the crosstalk effect generated between adjacent data line connection pin groups and address line connection pin groups is also relatively small.

[0088] The pin arrangement method in this embodiment can save more pin arrangement area while minimizing the crosstalk effect, and is more suitable for chips with limited pin area on the substrate 1.

[0089] like Figure 6 The figure shows the inter-group pin crosstalk impact results of two pin arrangement connection methods of the same GDDR PHY. Specifically, it is the crosstalk value between the two pins DQ12-B and DQ15-B. Among them, the dark line indicates that the pin arrangement is Figure 5 As shown in the figure, the crosstalk result when the overall arrangement is in the form of DQ:VSS=2:1. The light-colored line indicates that the pin arrangement is as follows Figure 4 As shown, the crosstalk result when the overall arrangement is in the form of DQ:VSS=1:1.

[0090] According to the results in the figure, the crosstalk value gradually increases with the increase of the operating frequency of GDDR PHY, but the crosstalk value of the pin arrangement scheme represented by the light-colored line is generally smaller than the crosstalk value of the pin arrangement scheme represented by the dark-colored line.

[0091] As another embodiment of the present invention, Figure 7 As shown, it also includes:

[0092] The substrate 1 is electrically connected to the PCB graphics card mainboard 3. The PCB graphics card mainboard 3 is an existing standard graphics card mainboard.

[0093] 16 GDDR6 DRAMs, 8 GDDR6 DRAMs are respectively arranged on the two side surfaces of the PCB graphics card motherboard 3. The GDDR6 DRAMs on the two side surfaces of the PCB graphics card motherboard 3 are arranged in the same manner.

[0094] The eight GDDR6 DRAMs on the same side surface of the PCB graphics card mainboard 3 are divided into two groups and arranged symmetrically. The symmetry axes of the two groups of GDDR6 DRAMs are the same as the symmetry axes of the two memory pin connection areas 12.

[0095] The arrangement position of each GDDR6 DRAM in the same group has the same relative position with the corresponding rectangular unit pin connection area 11. The connection routing of each GDDR6 DRAM and the corresponding rectangular unit pin connection area 11 is the same.

[0096] In this embodiment, 16 GDDR6 DRAMs are configured, thereby increasing the size of the video memory to improve the resolution of the rendered image. At the same time, due to the large number of GDDR6 DRAMs, if each routing scheme is designed and simulated separately, it will inevitably bring a huge workload.

[0097] In this embodiment, 16 GDDR6 DRAMs are arranged on both side surfaces of the PCB graphics card motherboard 3, and the GDDR6 DRAMs on both side surfaces are arranged in the same manner, so that the routing schemes on the front and back sides can be reused.

[0098] In addition, the eight GDDR6 DRAMs on the same side surface are divided into two symmetrical groups. Although the arrangement of the GDDR6 DRAM on the PCB graphics card motherboard 3 is a rotation arrangement around one direction, the pin distribution diagram of the GDDR6 DRAM chip is a central symmetrical diagram, such as Fig. 9 As shown. Therefore, when the GDDR6 DRAM is rotated 180°, the pin arrangement pattern of the chip is exactly the same as the pin arrangement pattern of the chip after the GDDR6 DRAM is bilaterally symmetrical. Therefore, the routing scheme of the two groups of GDDR6 DRAM on the same side surface in this embodiment can also be reused.

[0099] In summary, in this embodiment, it is only necessary to design and verify the connection routing scheme of the same group of 4 GDDR6 DRAMs on a certain side surface, and the rest can be achieved through multiplexing, thereby greatly improving the design and verification efficiency, thereby improving the GPU development efficiency.

[0100] The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A FCBGA packaging structure, characterized in that: include: A substrate for mounting an MXG100 chip; two memory pin connection areas are axially symmetrically arranged on the substrate, the two memory pin connection areas are respectively arranged close to two dynamic random access memory interface areas in the MXG100 chip, and the dynamic random access memory interface area is the placement area of ​​the PHY corresponding to the dynamic random access memory in the MXG100 chip; the symmetry axes of the two memory pin connection areas coincide with the symmetry axes of the two dynamic random access memory interface areas; The memory pin connection area includes four identical rectangular unit pin connection areas, wherein three unit pin connection areas are arranged end to end in sequence along their own length direction to form a rectangular strip connection area, and the long side of the remaining unit pin connection area is arranged adjacent to the short side of the rectangular strip area to form an L-shaped pin connection area; The arrangement of various types of pins in each of the unit pin connection areas is the same, and each pin in each of the unit pin connection areas is electrically connected to a pin in a corresponding PHY in the MXG100 chip.

2. The FCBGA packaging structure according to claim 1, characterized in that: The unit pin connection area includes a data line connection pin, an address line connection pin and a digital ground connection pin; The data line connection pins are arranged near one side of the MXG100 chip placement area, and the address line connection pins are arranged near one side of the edge of the substrate; A corresponding digital ground connection pin is arranged adjacent to each side of each of the data line connection pins; At least three corresponding digital ground connection pins are arranged adjacently around each of the address line connection pins.

3. The FCBGA packaging structure according to claim 1, characterized in that: The unit pin connection area includes a data line connection pin, an address line connection pin and a digital ground connection pin; The data line connection pins are arranged near one side of the MXG100 chip placement area, and the address line connection pins are arranged near one side of the edge of the substrate; The plurality of data line connection pins belonging to the same group are sequentially and adjacently arranged in a corresponding first preset data pin area; The plurality of address line connection pins belonging to the same group are sequentially and adjacently arranged in a corresponding second preset data pin area; A corresponding third preset data pin region is sandwiched between any two adjacent first preset data pin regions; A corresponding third preset data pin region is sandwiched between any two adjacent second preset data pin regions; The third preset data pin area is a straight-line pin area formed by a plurality of the digital ground connection pins being arranged adjacent to each other in sequence.

4. The FCBGA packaging structure according to claim 1, characterized in that: The dynamic random access memory is GDDR6 DRAM.

5. A FCBGA packaging structure according to claim 2 or 3, characterized in that: At least two circuit routing layers are arranged inside the substrate, the routing of the data line connection pins is located in the inner circuit routing layer, and the routing of the data line connection pins and the digital ground connection pins are located in the same circuit routing layer.

6. The FCBGA packaging structure according to claim 1, characterized in that: The substrate is also provided with a chip power supply pin area and a plurality of other device pin areas; The chip power pin area is a pin area corresponding to the orthographic projection area below the MXG100 chip installation position in the substrate; The plurality of other device pin regions are respectively arranged in the pin connection regions above and below the chip power pin region.

7. The FCBGA packaging structure according to claim 5, characterized in that: Also includes: PCB graphics card mainboard, the substrate is electrically connected to the PCB graphics card mainboard; 16 GDDR6 DRAMs, 8 GDDR6 DRAMs are respectively arranged on the two side surfaces of the PCB graphics card motherboard; The eight GDDR6 DRAMs on the same side surface of the PCB graphics card mainboard are divided into two groups and arranged symmetrically; the symmetry axes of the two groups of GDDR6 DRAMs are the same as the symmetry axes of the two memory pin connection areas; The setting position of each GDDR6 DRAM in the same group has the same relative position with the corresponding rectangular unit pin connection area; and the connection routing between each GDDR6 DRAM and the corresponding rectangular unit pin connection area is the same.

8. The FCBGA packaging structure according to claim 7, characterized in that: The PCB graphics card mainboard includes multiple layers of circuit routing layers; The connection wiring between the address line connection pin and the GDDR6 DRAM is located on the upper surface circuit wiring layer of the PCB graphics card motherboard.

9. The FCBGA packaging structure according to claim 8, characterized in that: The connection line between the data line connection pin and the GDDR6 DRAM is located in the inner circuit wiring layer of the PCB graphics card motherboard.

10. The FCBGA packaging structure according to claim 6, characterized in that: The other device pin areas include: pin areas corresponding to the PCIe module, the Display module and the Serdes module respectively.

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