Multiple edge through silicon vias and related systems, methods, and devices

Abstract

Multiple edge through silicon vias (TSVs) and related systems, methods, and devices are disclosed. An electronic device includes a chip stack, a first TSV, and a second TSV. The chip stack includes one or more side edges at a perimeter of the chip stack. The TSV region of the chip stack is located within a predetermined distance from the one or more side edges. The first TSV is located within the TSV region of the chip stack at a first distance from the one or more side edges. The second TSV is located within the TSV region of the chip stack at a second distance from the one or more side edges. The second distance is shorter than the first distance.

Description

[0001] Information about divisional applications

[0002] This application is a divisional application. The parent application is an invention patent application with an application date of August 3, 2020, application number 202010769221.0, and invention name “Multiple edge silicon vias and related systems, methods and devices”.

[0003] Priority claim

[0004] This application claims the benefit of the filing date of U.S. patent application serial number 16 / 577,243, filed on September 20, 2019, entitled “A Plurality of Edge Through-Silicon Vias and Related Systems, Methods, and Devices.” Technical Field

[0005] The present disclosure relates generally to identifying a minimum acceptable through silicon via (TSV) distance from a side edge of a chip stack, and more particularly to identifying a minimum acceptable TSV distance in a memory device. Background Art

[0006] A three-dimensional integrated circuit can be formed by stacking semiconductor chips having electronic circuit systems formed therein or thereon. These stacked semiconductor chips can be interconnected vertically. For example, the stacked semiconductor chips can be interconnected using TSVs. Summary of the invention

[0007] In some embodiments, an electronic device includes a chip stack, a first TSV, and a second TSV. The chip stack includes one or more side edges at the perimeter of the chip stack. A through silicon via region (TSV region) of the chip stack is located within a predetermined distance from the one or more side edges. The first TSV is located within the TSV region of the chip stack at a first distance from the one or more side edges. The second TSV is located within the TSV region of the chip stack at a second distance from the one or more side edges. The second distance is shorter than the first distance.

[0008] In some embodiments, a method for determining a minimum acceptable TSV distance from one or more side edges of a chip stack includes performing a conductivity test on a first TSV positioned at a first distance from the one or more side edges of the chip stack; performing the conductivity test on a second TSV positioned at a second distance from the one or more side edges, the second distance being shorter than the first distance; and identifying the minimum acceptable TSV distance from the one or more side edges as the first distance in response to determining that: the first TSV passed the conductivity test, the second TSV failed the conductivity test, and no other TSV that is farther from the one or more side edges than the first TSV failed the conductivity test.

[0009] In some embodiments, a memory device includes a chip stack, a plurality of TSVs, and a control circuit system. The chip stack includes a logic die and a plurality of core dies stacked on the logic die. The plurality of TSVs are positioned at different distances from one or more side edges of the chip stack. An ordered sequence is associated with the plurality of TSVs from the TSV farthest from the one or more side edges to the TSV closest to the one or more side edges. The control circuit system is located on or in the logic die. The control circuit system is configured to perform a conductivity test on each of the plurality of TSVs; identify a TSV in the plurality of TSVs that is the last consecutive TSV in the ordered sequence that passes the conductivity test when no preceding TSV in the ordered sequence fails the conductivity test; and determine that the minimum acceptable TSV distance from the one or more side edges is the same as the distance from the identified TSV to the one or more side edges. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] While the present disclosure concludes with claims that particularly point out and distinctly claim specific embodiments, the various features and advantages of embodiments within the scope of the present disclosure may be more readily ascertained from the following description when read in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a top view of an electronic device according to some embodiments;

[0012] Figure 2 yes Figure 1 A cross-sectional view of a portion of an electronic device, the cross section being Figure 1 The cross section 2 is taken;

[0013] Figure 3 is a flow chart illustrating a method of determining a minimum acceptable TSV distance from one or more side edges of a chip stack according to some embodiments;

[0014] Figure 4 is a cross-sectional view of a chip stack according to some embodiments;

[0015] Figure 5 is a flow chart illustrating a method of performing a conductivity test according to some embodiments;

[0016] Figure 6 is a top view of a chip stack according to some embodiments;

[0017] Figure 7 is a diagram showing an example of signal management according to some embodiments Figure 6 A top view of a chip stack;

[0018] Figure 8 is a schematic diagram of a multiplexing circuit according to some embodiments;

[0019] Fig. 9 yes Figure 1 A block diagram of an example of a logic die of an electronic device 100;

[0020] Fig.10 is a block diagram of a high bandwidth memory HBM+ system according to some embodiments; and

[0021] Fig.11 is a block diagram of a computing system according to some embodiments. DETAILED DESCRIPTION

[0022] In the following detailed description, reference is made to the accompanying drawings, which form a part of the detailed description, and in which specific examples of embodiments in which the present disclosure may be practiced are shown by way of illustration. These embodiments are described in sufficient detail to enable one of ordinary skill in the art to practice the present disclosure. However, other embodiments implemented herein may be utilized, and structural, material and process changes may be made without departing from the scope of the present disclosure.

[0023] The illustrations presented herein are not intended to be actual views of any particular method, system, device, or structure, but are merely idealized representations for describing embodiments of the present disclosure. In some cases, similar structures or components in the various figures may retain the same or similar reference numerals for the convenience of the reader; however, the similarity of the reference numerals does not necessarily mean that the structures or components are identical in size, composition, configuration, or any other properties.

[0024] The following description may contain examples to help enable one of ordinary skill in the art to practice the disclosed embodiments. The use of the terms "exemplary," "by way of example," and "for example" means that the related description is illustrative, and although the scope of the present disclosure is intended to cover examples and legal equivalents, the use of such terms is not intended to limit the embodiments or the scope of the present disclosure to specific components, steps, features, functions, etc.

[0025] It should be readily understood that the components of the embodiments as generally described herein and illustrated in the accompanying drawings may be arranged and designed in a variety of different configurations. Therefore, the following description of the various embodiments is not intended to limit the scope of the present disclosure, but merely represents the various embodiments. Although various aspects of the embodiments may be presented in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise indicated.

[0026] In addition, the specific embodiments shown and described are merely examples and should not be construed as the only way to implement the present disclosure, unless otherwise stated herein. Components, circuits, and functions may be shown in the form of block diagrams to avoid obscuring the present disclosure in unnecessary detail. On the contrary, the specific embodiments shown and described are merely exemplary and should not be construed as the only way to implement the present disclosure, unless otherwise stated herein. In addition, the logical partitions between block definitions and various blocks are examples of specific embodiments. It will be apparent to those of ordinary skill in the art that the present disclosure can be practiced through many other partition solutions. In most cases, details about timing considerations, etc. have been omitted, where such details are unnecessary for obtaining a complete understanding of the present disclosure and such details are within the capabilities of those of ordinary skill in the relevant art.

[0027] Those of ordinary skill in the art will appreciate that information and signals may be represented using any of a variety of different techniques and technologies. To make representation and description clear, some figures may show signals as a single signal. Those of ordinary skill in the art will appreciate that a signal may represent a bus of signals, where the bus may have various bit widths and the present disclosure may be implemented on any number of data signals including a single data signal.

[0028] The various illustrative logical blocks, modules, and circuits described in conjunction with the embodiments disclosed herein may be implemented or executed using a general purpose processor, a special purpose processor, a digital signal processor (DSP), an integrated circuit (IC), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor (which may also be referred to herein as a host processor or simply a host) may be a microprocessor, but in an alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. A general purpose computer including a processor is considered a special purpose computer, while a general purpose computer is configured to execute computing instructions (e.g., software code) associated with the embodiments of the present disclosure.

[0029] Embodiments can be described according to the process depicted as a flow chart (flowchart or flow diagram) structure diagram or block diagram. Although the flow chart can describe the operational actions as a sequential process, many of these actions can be performed in another order, in parallel or substantially simultaneously. In addition, the order of the actions can be rearranged. The process can correspond to a method, a thread, a function, a process, a subroutine, a subprogram, other structures or a combination thereof. In addition, the method disclosed herein can be implemented in hardware, software or both. If implemented in software, the function can be stored or transmitted to a computer-readable medium as one or more instructions or codes. Computer-readable media includes both computer storage media and communication media, and communication media includes any medium that facilitates the transmission of a computer program from one place to another.

[0030] Unless such limitations are explicitly stated, any reference to an element using designations such as "first," "second," etc. herein does not limit the number or order of those elements. Instead, these designations may be used herein as a convenient method of distinguishing two or more elements or element instances. Thus, a reference to a first element and a second element does not mean that only two elements may be employed or that the first element must precede the second element in some manner. Additionally, unless otherwise stated, a group of elements may include one or more elements.

[0031] The term "substantially" as used herein with respect to a given parameter, property, or condition means and encompasses the extent to which one of ordinary skill in the art would understand that the given parameter, property, or condition is met with a small degree of variance (e.g., variance within an acceptable tolerance). For example, depending on a particular parameter, property, or condition being substantially met, the parameter, property, or condition may be at least 90% met, at least 95% met, or even at least 99% met.

[0032] The term "chip" as used herein refers to a semiconductor wafer (eg, a silicon wafer) having electronic circuitry formed therein or thereon. Examples of chips include memory logic chips, memory core chips, central processing unit chips, and other electronic device chips.

[0033] In some embodiments, an electronic device includes a chip stack, a first TSV, and a second TSV. The chip stack includes one or more side edges at the perimeter of the chip stack. A through silicon via region (TSV region) of the chip stack is located within a predetermined distance from the one or more side edges. The first TSV is located within the TSV region of the chip stack at a first distance from the one or more side edges. The second TSV is located within the TSV region of the chip stack at a second distance from the one or more side edges. The second distance is shorter than the first distance.

[0034] In some embodiments, a method for determining a minimum acceptable TSV distance from one or more side edges of a chip stack includes performing a conductivity test on a first TSV positioned at a first distance from the one or more side edges of the chip stack; performing the conductivity test on a second TSV positioned at a second distance from the one or more side edges, the second distance being shorter than the first distance; and identifying the minimum acceptable TSV distance from the one or more side edges as the first distance in response to determining that: the first TSV passed the conductivity test, the second TSV failed the conductivity test, and no other TSV that is farther from the one or more side edges than the first TSV failed the conductivity test.

[0035] In some embodiments, a memory device includes a chip stack, a plurality of TSVs, and a control circuit system. The chip stack includes a logic die and a plurality of core dies stacked on the logic die. The plurality of TSVs are positioned at different distances from one or more side edges of the chip stack. An ordered sequence is associated with the plurality of TSVs from the TSV farthest from the one or more side edges to the TSV closest to the one or more side edges. The control circuit system is located on or in the logic die. The control circuit system is configured to perform a conductivity test on each of the plurality of TSVs; identify a TSV in the plurality of TSVs that is the last consecutive TSV in the ordered sequence that passes the conductivity test when no preceding TSV in the ordered sequence fails the conductivity test; and determine that the minimum acceptable TSV distance from the one or more side edges is the same as the distance from the identified TSV to the one or more side edges.

[0036] Figure 1 1 is a top view of an electronic device 100 according to some embodiments. The electronic device 100 includes a chip stack 102, the chip stack including one or more side edges 108, a TSV region 106 of the chip stack 102, the one or more side edges being located at the perimeter of the chip stack 102, and the TSV region being located within a predetermined distance D (e.g., 230 micrometers (μm)) from the one or more side edges 108. The TSV region 106 is formed by Figure 1 The side edges 108 and TSV region boundaries 104 are shown to define the electronic device 100. The electronic device 100 also includes TSVs 110 positioned at various distances from the side edges 108.

[0037] Figure 2 yes Figure 1 A cross-sectional view of a portion of the electronic device 100, the cross section being Figure 1 The cross section 2 of the reference Figure 1 and Figure 2 , electronic device 100 includes a plurality of chips. For example, chip stack 102 includes chip 214, chip 216, chip 218, chip 220, and chip 222. It should be noted that chip stack 102 may include any number of chips greater than or equal to two chips.

[0038] One of the chips in chip stack 102 includes control circuitry 224 therein or thereon. A chip including control circuitry 224 may sometimes be referred to herein as a "control chip." In some embodiments, bottom chip 214 in chip stack 102 may include a control circuitry 224 as described in Figure 2Control circuitry 224 in the example shown. In some embodiments, the top chip (e.g., chip 222) may include control circuitry 224. As a specific non-limiting example, chip 214 may include a logic die of a memory device, chip 216, chip 218, chip 220, and chip 222 may include memory core chips, and control circuitry 224 may include direct access (DA) control circuits.

[0039] The chip stack 102 also includes TSVs 110 within the TSV region 106 of the chip stack 102, the TSVs including TSVs 202, TSVs 204, TSVs 206, TSVs 208, TSVs 210, and TSVs 212. Figure 1 and Figure 2 Six TSVs 110 are shown, but the electronic device 100 may include any number of TSVs greater than or equal to two TSVs. Each of the TSVs 110 is positioned at a different distance from the side edge 108 of the chip stack 102. For example, TSV 202 is positioned at a distance D1 from the side edge 108; TSV 204 is positioned at a distance D2 from the side edge 108; TSV 206 is positioned at a distance D2 from the side edge 108; TSV 208 is positioned at a distance D4 from the side edge 108; TSV 210 is positioned at a distance D5 from the side edge 108; and TSV 212 is positioned at a distance D6 from the side edge 108.

[0040] In the case where TSVs 110 are arranged at different distances from side edge 108, control circuit system 224 is configured to perform a conductivity test on each TSV in TSVs 110 and use the results of the conductivity test to identify the minimum acceptable TSV distance from side edge 108. In other words, control circuit system 224 is configured to use the results of the conductivity test to identify the limit of well-formed TSVs that can be formed. If a first conductivity test of a first TSV in TSVs 110 shows no problems, and a second conductivity test of a second TSV in TSVs 110 that is arranged adjacent to the first TSV in TSVs 110 shows an open circuit, then the limit can be determined to be the distance to the first TSV in TSVs 110. In other words, the control circuit system 224 is configured to perform a conductivity test on the TSVs 110 and identify a minimum acceptable TSV distance from the side edge 108 as a first distance corresponding to a first TSV in the TSVs 110 in response to determining that the first TSV in the TSVs 110 passed the conductivity test, a second TSV in the TSVs 110 that is adjacent to the first TSV in the TSVs 110 failed the conductivity test, and no other TSVs 110 that are farther from the side edge than the first TSV in the TSVs 110 failed the conductivity test.

[0041] Still in other words, the ordered sequence may be associated with TSVs 110 from the TSV farthest from side edge 108 (TSV 202) to the TSV closest to side edge 108 (TSV 212). Control circuitry 224 is configured to perform a conductivity test on each of TSVs 110, identifying a TSV in TSVs 110 that is the last consecutive TSV in the ordered sequence to pass the conductivity test without a preceding TSV in the ordered sequence failing the conductivity test. Control circuitry 224 is further configured to determine that the minimum acceptable TSV distance from side edge 108 is the same as the distance from the identified TSV to side edge 108.

[0042] As a specific non-limiting example, control circuitry 224 may perform a conductivity test on each of TSVs 110, resulting in no issues in TSVs 202, 204, 206, and 208 and an open circuit in TSVs 210 and 212. In this example, the minimum acceptable TSV distance, or the limit at which a well-formed TSV may be formed, may be determined to be a distance D4 of TSV 208 from side edge 108.

[0043] Compared to using a single TSV, using multiple TSVs 110 to determine the minimum acceptable TSV distance allows for evaluating multiple different distances (e.g., D1, D2, D3, D4, D5, and D6) from the side edge 108 instead of a single distance. In the case of using only a single TSV, it can only be determined whether the distance of the single TSV from the side edge 108 is acceptable or unacceptable without providing the granularity provided by multiple TSVs.

[0044] Figure 3 3 is a flow chart illustrating a method 300 for determining a minimum acceptable TSV distance from one or more side edges of a chip stack according to some embodiments. In operation 302, the method 300 performs a conductivity test on a first TSV located at a first distance from the one or more side edges of the chip stack. Figure 4 and Figure 5 Details on examples of conductivity testing are provided.

[0045] In operation 304, the method 300 performs a conductivity test on a second TSV located at a second distance from the one or more side edges. The second distance is shorter than the first distance. In operation 306, the method 300 identifies a minimum acceptable TSV distance from the one or more side edges as a first distance in response to determining that the first TSV passed the conductivity test, the second TSV failed the conductivity test, and no other TSV further from the one or more side edges than the first TSV failed the conductivity test.

[0046] Figure 4 4 is a cross-sectional view of a chip stack 400 according to some embodiments. The chip stack 400 includes a control chip 402 at the bottom of the chip stack 400, an end chip 410 at the top of the chip stack 400, and middle chips (chip 404, chip 406, and chip 408) located between the control chip 402 and the end chip 410. The chip stack 400 also includes a TSV 430 that traverses the chip stack 400. The TSV 430 includes a first end 434 close to the control chip 402 and a second end 432 close to the end chip 410.

[0047] The control chip 402 includes a Figure 2 The control chip 402 further includes a switch 418 and a detection circuit system 428. The switch 418 is operably coupled between the first test voltage potential 414 and the first end 434 of the TSV 430. The control input of the switch 418 is operably coupled to the control circuit system 412 so that the control circuit system 412 can open and close the switch 418. The switch 418 is configured to selectively operably couple the first end 434 of the TSV 430 to the first test voltage potential 414 and electrically isolate the first end from the first test voltage potential in response to the control of the control circuit system 412. The detection circuit system 428 is configured to detect the voltage potential of the first end 434 of the TSV 430. The detection circuit system 428 is operably coupled to the control circuit system 412 to provide the detected voltage potential of the first end 434 of the TSV 430 to the control circuit system 412.

[0048] The end chip 410 includes a switch 426 operably coupled between the second test voltage potential 416 and the second end 432 of the TSV 430. The control input of the switch 426 is operably coupled to the control circuit system 412 to enable the control circuit system 412 to open and close the switch 426. The switch 418 is configured to selectively operably couple the second end 432 of the TSV 430 to the second test voltage potential 416 and electrically isolate the second end from the second test voltage potential in response to control of the control circuit system 412.

[0049] The intermediate chips, namely chip 404, chip 406, and chip 408, include switches, switch 420, switch 422, and switch 424, respectively, operably coupled between the second test voltage potential 416 and the TSV 430. The control inputs of switch 420, chip 406, and chip 408 are operably coupled to the control circuit system 412 to enable the control circuit system 412 to open and close the switches 420, switch 422, and switch 424. The switches, namely switch 420, switch 422, and switch 424, are configured to selectively operably couple the TSV 430 to the second test voltage potential 416 at its respective position along the TSV 430 in response to control of the control circuit system 412 and electrically isolate the TSV 430 from the second test voltage potential.

[0050] Spiral TSVs may be used to transmit signals (eg, signals controlling switches 420 , 422 , 424 , and 426 ) between the control chip 402 and other chips (chip 404 , chip 406 , chip 408 , and end chip 410 ) of the chip stack 400 .

[0051] The control circuit system 412 is configured to perform a conductivity test on the second end 432. Figure 5 An example of conductivity testing is discussed. Figure 4 Only one TSV 430 is shown in FIG. 4 , but it should be understood that the chip stack 400 may include multiple TSVs, such as Figure 1 and Figure 2 The electronic device 100 may also be configured to perform a similar conductivity test on each of the TSVs.

[0052] Figure 5 is a flow chart illustrating a method 500 of performing a conductivity test according to some embodiments. Figure 4 and Figure 5 In operation 502, the method 500 precharges the first end 434 of the TSV 430 to the first test voltage potential 414. In some embodiments, precharging the first end 434 of the TSV 430 to the first test voltage potential 414 includes activating a switch 418 operably coupled between the first end 434 of the TSV 430 and the first test voltage potential 414 until the first end 434 of the TSV 430 is charged to the first test voltage potential 414.

[0053] In operation 504, the method 500 discharges a second end 432 of the TSV 430 opposite the first end 434 to the second test voltage potential 416. In some embodiments, pre-discharging the second end 432 of the TSV 430 to the second test voltage potential 416 includes activating a switch 426 operably coupled between the second end 432 of the TSV 430 and the second test voltage potential 416 until the second end 432 of the TSV 430 is discharged to the second test voltage potential 416.

[0054] In operation 506, the method 500 detects a voltage potential at the first end 434 of the TSV 430. In some embodiments, detecting the voltage potential at the first end 434 of the TSV 430 includes detecting the voltage potential using the detection circuitry 428. If the conductivity of the TSV 430 is good, discharging the second end 432 of the TSV 430 to the second test voltage potential 416 in operation 504 will discharge the entire TSV 430 from the second end 432 to the first end 434 to the second test voltage potential 416. Therefore, if the conductivity of the TSV 430 is good, the voltage potential detected at the first end 434 of the TSV 430 after the discharge in operation 504 will be at the second test voltage potential 416. On the other hand, if the conductivity of the TSV 430 is poor (e.g., an open circuit is not well formed at a connection point such as between dies or at a point of the TSV 430 itself), the voltage potential detected at the first end 434 of the TSV 430 after the discharge of operation 504 will not be at the second test voltage potential 416. For example, the voltage potential at the first end 434 may remain at the first test voltage potential 414 and end at some other voltage potential between the first test voltage potential 414 and the second test voltage potential 416.

[0055] In operation 508, method 500 determines that TSV 430 passes the conductivity test in response to detecting second test voltage potential 416 at first end 434 of TSV 430. In operation 510, method 500 determines that TSV 430 fails the conductivity test in response to detecting first test voltage potential 414 at first end 434 of TSV 430.

[0056] If it is determined that TSV 430 fails the conductivity test, method 500 may be repeated for each of the middle chips (chip 404, chip 406, and chip 408) in the middle chips of chip stack 400, but not end chip 410, to identify the location of the failure in TSV 430. For example, if TSV 430 fails at the connection between chip 404 and chip 406, TSV 430 will pass the conductivity test between chip 404 and control chip 402, but TSV 430 will fail the conductivity test between control chip 402 and each of chips 406, chip 408, and end chip 410.

[0057] Figure 6 is a top view of a chip stack 600 according to some embodiments. The chip stack 600 may be similar to Figure 1 and Figure 2 The electronic device 100 is similar to Figure 4 The chip stack 400 is shown in FIG. 600. The chip stack 600 includes several groups of edge TSVs (edge ​​TSV 604, edge TSV 620, edge TSV 628, edge TSV 630, edge TSV 632, edge TSV 634, edge TSV 638), VDD / VSS / VPP TSVs (VDD / VSS / VPP TSV 608, VDD / VSS / VPP TSV 610, VDD / VSS / VPP TSV 612, VDD / VSS / VPP TSV 614), and VDD / VSS TSV 640. The VDD / VSS / VPP TSVs include VDD / VSS / VPP edge TSVs (VDD / VSS / VPP edge TSV 606, VDD / VSS / VPP edge TSV 618, VDD / VSS / VPP edge TSV 624, VDD / VSS / VPP edge TSV 622). VDD / VSS TSV 640 includes VDD / VSS edge TSV 626 and VDD / VSS edge TSV 616 .

[0058] Where various groups of TSVs are arranged at the side edges 602 of the chip stack 600, it is possible (eg, using Figure 3 Method 300 and Figure 5 Method 500) determines the method for determining the edge region (e.g., Figure 1The TSV region 106 of the chip stack 600 may be a restricted area or a minimum acceptable TSV distance for placing TSVs. In some embodiments, this minimum acceptable TSV distance may be determined globally (e.g., by selecting the largest minimum acceptable TSV distance among the minimum acceptable TSV distances for each edge TSV group in the edge TSV group including edge TSVs, VDD / VSS edge TSVs, and VDD / VSS / VPP edge TSVs). However, the minimum acceptable TSV distance may be determined independently for each of the side edges 602 of the chip stack 600 by placing a test TSV along each of the side edges 602 of the chip stack 600. Therefore, in some embodiments, the minimum acceptable TSV distance may be determined independently for each of the side edges 602 of the chip stack 600. In some embodiments, the minimum acceptable TSV distance may be determined for each group of edge TSVs including edge TSVs, VDD / VSS edge TSVs, and VDD / VSS / VPP edge TSVs.

[0059] As a specific non-limiting example, the edge TSV 630 may include TSVs at each of 70 μm, 110 μm, 150 μm, and 190 μm from the side edge 602, as shown in an exploded view 642 of the edge TSV 630. In this example, it may be determined that the TSVs at 110 μm, 150 μm, and 190 μm pass the conductivity test, while the TSV at 70 μm fails the conductivity test. Therefore, 110 μm may be selected as the minimum acceptable TSV distance for the edge TSV 630, the side edge of the chip stack 600 close to the edge TSV 630, or the entire chip stack 600.

[0060] As another specific non-limiting example, the VDD / VSS edge TSV 626 may include two TSVs at each of 70 μm, 110 μm, 150 μm, and 190 μm from the side edge 602, as shown in an exploded view 644 of the VDD / VSS edge TSV 626. In this example, it may be determined that the TSVs at 110 μm, 150 μm, and 190 μm pass the conductivity test, while at least one of the TSVs at 70 μm fails the conductivity test. Therefore, 110 μm may be selected as the minimum acceptable TSV distance for the VDD / VSS edge TSV 626, the side edge of the chip stack 600 close to the VDD / VSS edge TSV 626, or the entire chip stack 600.

[0061] In some embodiments, looking at the power sources providing the power rail voltages, increasing the number of TSVs for the power rail voltages (e.g., VSS, VDD, VPP, etc.) may reduce the impedance of the chip stack 600. Using the embodiments disclosed herein, it may be determined how many additional TSVs may be placed near the side edge 602 for each set of VDD / VSS / VPP TSVs and VDD / VSS TSVs, thereby reducing impedance compared to previously known systems.

[0062] Figure 7 is a diagram showing an example of signal management according to some embodiments Figure 6 600. In the upper left quarter 706 of the chip stack 600, the top view Figure 6 , some signal management for outputting the conductivity test results is shown. For example, the chip stack 600 may include (e.g., in a control chip) a local multiplexer (e.g., local multiplexer 702, local multiplexer 704) configured to deliver the results of the conductivity test from each TSV in each TSV group in the TSV group. Figure 7 , local multiplexer 702 multiplexes results from edge TSV 604 and edge TSV 620, and local multiplexer 704 multiplexes results from VDD / VSS edge TSV 616 and the output of local multiplexer 702. Thus, local multiplexer 704 can selectively provide results from edge TSV 620, edge TSV 604, or VDD / VSS edge TSV 616 in response to control applied to these edges (e.g., provided by control circuitry). Although not shown, the chip stack 600 may include additional local multiplexers configured to multiplex results from conductivity tests of other edge TSVs (e.g., edge TSV 628, edge TSV 630, VDD / VSS / VPP edge TSV 624, VDD / VSS edge TSV 626, VDD / VSS / VPP edge TSV 622, edge TSV 632, edge TSV 634, edge TSV 636, edge TSV 638, VDD / VSS / VPP edge TSV 618, VDD / VSS / VPP edge TSV 606).

[0063] In some embodiments, the results of the conductivity test may be output sequentially (e.g., continuously, one at a time on a single bus). In some embodiments, the results of the conductivity test may be output in parallel (e.g., simultaneously on enough test buses to carry all the results at once). In some embodiments, some intermediate multiplexing may occur. For example, the number of buses that transmit the results of the conductivity test may be less than the number of results of the conductivity test, and each of the buses transmits a series of different portions of the results.

[0064] Figure 8 8 is a schematic diagram of a multiplexing circuit 800 according to some embodiments. The multiplexing circuit 800 can be used to multiplex the multiplexing circuit 800 from edge TSVs (e.g., Figure 6 and Figure 7 The multiplexing circuit 800 multiplexes the TSV conductivity test results 816 and 818 of the VDD / VSS edge TSV, VDD / VSS / VPP edge TSV to the global output 814. The multiplexing circuit 800 includes local multiplexers (e.g., local multiplexers 804, local multiplexers 806, local multiplexers 808, local multiplexers 810) configured to multiplex the TSV conductivity test results 816 and the TSV conductivity test results 818 to the local output 812, some of which may be analog (e.g., to indicate a detected voltage potential on the TSV) and some of which may be digital (e.g., to indicate whether the corresponding TSV passed or failed the conductivity test). The multiplexing circuit 800 also includes a global multiplexer 802 configured to multiplex the local outputs 812 into a global output 814 .

[0065] Each of the multiplexers (global multiplexer 802, local multiplexer 804, local multiplexer 806, local multiplexer 808, local multiplexer 810) is configured to selectively output one of the multiplexer inputs in response to a selection signal SEL. Thus, depending on the value of the selection signal SEL, any one of the TSV conductivity test results 816 or the TSV conductivity test results 818 may be provided at a global output 814. The control circuit system (e.g., control circuit system 224, control circuit system 412) may be configured to provide the selection signal SEL and receive the global output 814.

[0066] In some embodiments, local multiplexer 804, local multiplexer 806, local multiplexer 808, and / or local multiplexer 810 may be configured to receive signals not related to conductivity testing (e.g., signals related to other types of tests). Thus, multiplexing circuit 800 may be configured to selectively output any of TSV conductivity test results 816 or TSV conductivity test results 818 or other signals related to other tests to global output 814.

[0067] Fig. 9 yes Figure 1 1 is a block diagram of an example of a logic die 900 of an electronic device 100. The logic die 900 includes an AWORD / DWORD interface 904, a P1500 interface 906, and a direct access interface, DA interface 908. The logic die 900 also includes a command address data control circuit 902 operably coupled to the AWORD / DWORD interface 904, a P1500 control circuit 916 operably coupled to the P1500 interface 906 through a multiplexer 910, and a DA control circuit 914 operably coupled to the DA interface 908. The command address data control circuit 902 is configured to control the operation of the AWORD / DWORD interface 904, the P1500 control circuit 916 is configured to control the operation of the P1500 interface 906, and the DA control circuit 914 is configured to control the operation of the DA interface 908. Each of the command address data control circuit 902, the P1500 control circuit 916, and the DA control circuit 914 is configured to communicate with a DRAM die (eg, Fig.10 The P1500 control circuit 916 and the DA control circuit 914 are also configured to communicate with the DRAM die (e.g., Fig.10 In addition, the P1500 control circuit 916 and the DA control circuit 914 are configured to communicate with the DRAM die (e.g., Fig.10 1006) to perform hybrid communication, wherein the hybrid communication includes communicating with a DRAM die (e.g., Fig.10 DRAM die 1006) communicates both directly and indirectly (through BIST 912).

[0068] AWORD / DWORD interface 904 is used for high bandwidth memory ( Fig.10The AWORD / DWORD interface 904 provides an interface for address / command (AWORD) and data (DWORD) for normal operation of the HBM 1002. By way of non-limiting example, the AWORD / DWORD interface 904 is configured to be used as an interface for conducting operation signals (e.g., commands, address signals, DQ input / output data signals, etc.). The AWORD / DWORD interface 904 includes an AWORD / DWORD port 918.

[0069] The P1500 interface 906 is an interface for test operations specified by JEDEC. The P1500 interface 906 includes a P1500 port 922. The number of P1500 ports 922 specified by JEDEC is fifteen P1500 ports 922. The P1500 test interface is a test interface between an embedded core and a system chip that can be used to test core interoperability. The functions and circuits (e.g., P1500 control circuit 916) of the P1500 interface between various different HBMs can be relatively similar because JEDEC closely regulates the P1500 interface 906.

[0070] DA interface 908 is an interface for other operations (eg, mainly test operations). For other test operations, DA interface 908 is not defined (manufacturer / user specific). Some of these test operations may include Figure 3 Method 300, Figure 5 The method 500 of , other test operations discussed herein, or any combination thereof. Thus, the DA control circuit 914 can implement the control circuit system discussed herein (eg, the control circuit system 224, the control circuit system 412).

[0071] The basic function of the DA interface 908 is to verify the HBM (e.g., Figure 1 The DA interface 908 includes DA ports 920. At least some of the DA ports 920 have test pads 924. The number of DA ports 920 is sixty DA ports 920. The functions and circuits of the DA interface 908 (e.g., the DA control circuit 914) can be relatively different from one HBM to another because the functions and circuits of the DA interface 908 are not as closely regulated as the functions and circuits of the P1500 interface 906. For example, JEDEC defines the number and placement of microbumps (uBumps) of the DA port 920. However, the port allocation and use of the DA interface 908 can vary from one HBM to another.

[0072] exist Fig. 9Various arrows indicating signal directions are shown in FIG. 100. It should be noted that in one direction, from the outside of the logic die 900 to the DRAM die 1006 ( Fig.10 ) drives the address / command signals and the corresponding test signals. On the other hand, driving the data signals and the corresponding test signals in both directions (i.e., driving to Fig.10 DRAM die 1006 and driven from said DRAM die).

[0073] Fig.10 1 is a block diagram of a high bandwidth memory HBM+ system 1000 according to some embodiments. The HBM+ system 1000 includes an HBM 1002 and a processing unit 1004 (e.g., a central processing unit or CPU, a graphics processing unit or GPU, an accelerated processing unit or APU, etc.) operably coupled to the HBM 1002. The HBM 1002 includes a dynamic random access memory die, a DRAM die 1006, and a logic die 1008. The logic die 1008 includes a processor 1010 and a near memory controller NMC 1012. The processing unit 1004 includes a far memory controller FMC 1014.

[0074] The NMC 1012 and the FMC 1014 are configured to function as a memory controller master. The FMC 1014 includes a disconnected HBM memory controller, and the NMC 1012 includes an on-HBM memory controller located on a logic die 1008 of the HBM 1002. The logic die 1008 may be a control chip (e.g., Figure 4 1002). By way of non-limiting example, the logic die 1008 may correspond to the bottom layer of the 3D stacked memory as the HBM 1002, while the DRAM die 1006 may correspond to one of the upper layers of the HBM 1002. The logic die 1008 may control the DRAM die 1006 using the NMC 1012, which may be instructed by the processor 1010 to control the DRAM die 1006. It should be noted that one or both of the NMC 1012 and the FMC 1014 may be represented by a general memory controller. The logic die 1008 may include Fig. 9 Logic die 900.

[0075] Fig.111 is a block diagram of a computing system 1100 according to some embodiments. The computing system 1100 includes one or more processors 1104, one or more non-volatile data storage devices 1110, one or more input devices 1106, and one or more output devices 1108, the one or more processors being operably coupled to one or more memory devices 1102. In some embodiments, the computing system 1100 includes a personal computer (PC), such as a desktop computer, a laptop computer, a tablet computer, a mobile computer (e.g., a smart phone, a personal digital assistant (PDA)), etc., a network server, or other computer devices.

[0076] In some embodiments, the one or more processors 1104 may include a central processing unit (CPU) or other processor configured to control the computing system 1100. In some embodiments, the one or more memory devices 1102 include random access memory (RAM), such as volatile data storage (e.g., dynamic RAM (DRAM), static RAM (SRAM), etc.). In some embodiments, the one or more non-volatile data storage devices 1110 include a hard disk drive, a solid state drive, a flash memory, an erasable programmable read-only memory (EPROM), other non-volatile data storage devices, or any combination thereof. In some embodiments, the one or more input devices 1106 include a keyboard 1112, a pointing device 1114 (e.g., a mouse, a trackpad, etc.), a microphone 1116, a keypad 1118, a scanner 1120, a camera 1122, other input devices, or any combination thereof. In some embodiments, the one or more output devices 1108 include an electronic display 1124, a speaker 1126, a printer 1128, other output devices, or any combination thereof.

[0077] In some embodiments, the one or more memory devices 1102 include Fig.10 In some embodiments, the one or more memory devices 1102 include a chip stack (e.g., Figure 1 Chip stack 102, Figure 4 Chip stack 400, Figure 6 A chip stack 600), wherein the chip stack comprises Fig. 9 Logic die 900.

[0078] As used in the present disclosure, the term "module" or "component" may refer to a specific hardware implementation that is configured to perform the actions of a module or component and / or software object or to execute a software routine that may be stored on or executed by the general-purpose hardware of a computing system. In some embodiments, the different components, modules, engines, and services described in the present disclosure may be implemented as objects or processes executed on a computing system (e.g., as separate threads). Although some of the systems and methods described in the present disclosure are generally described as being implemented in software (stored on and / or executed by general-purpose hardware), specific hardware implementations or combinations of software and specific hardware implementations are also possible and contemplated.

[0079] As used in this disclosure, the term "combination" referring to a plurality of elements may include any combination of all elements or any of the various subcombinations of some of the elements. For example, the phrase "A, B, C, D, or a combination thereof" may refer to any one of A, B, C, or D; a combination of each of A, B, C, and D; and any subcombination of A, B, C, or D, such as A, B, and C; A, B, and D; A, C, and D; B, C, and D; A and B; A and C; A and D; B and C; B and D; or C and D.

[0080] The terms used in this disclosure and especially in the appended claims (e.g., the bodies of the appended claims) are generally intended to be “open” terms (e.g., the term “including” should be construed as “including, but not limited to,” the term “having” should be construed as “having at least,” the term “includes” should be construed as “including, but not limited to,” etc.).

[0081] Additionally, if a specific number of introduced claim statements is intended, such intent will be explicitly stated in the claim, and in the absence of such a statement, no such intent is present. For example, to aid understanding, the following appended claims may contain the introductory phrases "at least one" and "one or more" to introduce claim statements. However, the use of such phrases should not be interpreted as implying that a claim statement introduced by the indefinite article "a, an" will limit any particular claim containing such introduced claim statement to an embodiment containing only one such statement, even when the same claim contains the introductory phrases "one or more" or "at least one" and an indefinite article such as "a, a kind" (e.g., "a" and / or "an" should be interpreted as meaning "at least one" or "one or more"); the same is true for the use of definite articles used to introduce claim statements.

[0082] In addition, even if a specific number of an introduced claim statement is explicitly stated, one skilled in the art will recognize that such statements should be interpreted to mean at least the stated number (e.g., the unmodified statement "two statements" without other modifiers means at least two statements, or two or more statements). Moreover, in those cases where a convention similar to "at least one of A, B, and C, etc." or "one or more of A, B, and C, etc." is used, such constructions are generally intended to include only A, only B, only C, A and B, A and C, B and C, or A, B and C, etc.

[0083] Further, any separating word or phrase presenting two or more alternative terms, whether in the specification, claims or drawings, should be understood to include the possibility of including one of the terms, any of the terms, or both of the terms. For example, the phrase "A or B" should be understood to include the possibility of "A" or "B" or "A and B".

[0084] Although the present disclosure has been described herein with respect to certain illustrated embodiments, those of ordinary skill in the art will recognize and appreciate that the present invention is not limited thereto. Rather, many additions, deletions, and modifications may be made to the illustrated and described embodiments without departing from the scope of the present invention as hereinafter claimed and its legal equivalents. Additionally, features from one embodiment may be combined with features of another embodiment while still being encompassed within the scope of the present invention as contemplated by the inventor.

Claims

1. A device comprising: one or more through silicon vias (TSVs) of the chip stack, the TSVs being located at different distances from one or more side edges of the chip stack; as well as A control circuit system configured to: performing a conductivity test on the one or more TSVs; and A minimum acceptable TSV distance from the one or more side edges is identified in response to the conductivity test.

2. The apparatus of claim 1 , wherein the one or more TSVs are in the form of two or more TSVs, and wherein the control circuitry is configured to: The minimum acceptable TSV distance from the one or more side edges is identified as a first distance from the one or more side edges in response to determining that a first TSV of the two or more TSVs passes the conductivity test, a second TSV of the two or more TSVs fails the conductivity test, and no other TSV of the two or more TSVs that is farther from the one or more side edges than the first TSV fails the conductivity test.

3. The apparatus of claim 1 or 2, wherein the control circuitry is located on or in a control chip in the chip stack, the control chip comprising a logic die of a memory device.

4. The apparatus of claim 1 or 2, wherein the control circuit system is configured to: precharging a first end of at least one TSV of the one or more TSVs to a first test voltage potential; discharging a second end of the at least one TSV opposite to the first end to a second test voltage potential; and A voltage potential is detected at the first end of the at least one TSV.

5. The apparatus of claim 4, wherein the control circuitry is configured to: determining that the at least one TSV passes the conductivity test in response to detecting the second test voltage potential at the first end of the at least one TSV; and The at least one TSV is determined to have failed the conductivity test in response to detecting the first test voltage potential at the first end of the at least one TSV.

6. The device of claim 3, wherein the control chip includes a multiplexer configured to deliver a result of the conductivity test to the control circuitry.

7. The apparatus according to claim 1 or 2, wherein: The control circuitry is positioned at a first end of the first TSV; wherein the control circuitry includes a first electrically controllable switch configured to selectively operably couple the first TSV to a first test voltage potential proximate the first end of the first TSV; and The chip stack includes an end chip positioned at a second end of the first TSV opposite the first end.

8. The device according to claim 7, wherein: The end chip includes a second electrically controllable switch configured to selectively operably couple the first TSV proximate the second end to a second test voltage potential that is different from the first test voltage potential.

9. The apparatus of claim 8, wherein the control circuitry is configured to: controlling the first electrically controllable switch to operably couple the first TSV to the first test voltage potential until the first end of the first TSV is charged to the first test voltage potential; and The second electrically controllable switch of the end chip is controlled to operably couple the first TSV to the second test voltage potential until the second end of the first TSV is discharged to the second test voltage potential.

10. The apparatus of claim 9, wherein the control circuitry is configured to: determining that the first TSV passes the conductivity test in response to determining that the first end of the first TSV is at the second test voltage potential; and The first TSV is determined to have failed the conductivity test in response to determining that the first end of the first TSV is at the first test voltage potential.

11. A method of determining a minimum acceptable through silicon via distance (minimum acceptable TSV distance) from one or more side edges of a chip stack, the method comprising: performing a conductivity test on the one or more TSVs; as well as A minimum acceptable TSV distance from the one or more side edges is determined in response to the conductivity test.

12. The method of claim 11 , wherein performing the conductivity test on the one or more TSVs comprises: performing a conductivity test on a first TSV positioned at a first distance from the one or more side edges of the chip stack; as well as The conductivity test is performed on a second TSV positioned at a second distance from the one or more side edges, the second distance being shorter than the first distance.

13. The method of claim 12, wherein determining the minimum acceptable TSV distance comprises: The minimum acceptable TSV distance from the one or more side edges is determined to be the first distance in response to determining that: the first TSV passes the conductivity test, the second TSV fails the conductivity test, and no other TSV of the one or more TSVs that is farther from the one or more side edges than the first TSV fails the conductivity test.

14. The method of claim 13, wherein performing the conductivity test on the one or more TSVs comprises: precharging a first end of a TSV of the one or more TSVs to a first test voltage potential; discharging a second end of the TSV opposite to the first end to a second test voltage potential; detecting a voltage potential at the first end of the TSV; determining that the TSV passes the conductivity test in response to detecting the second test voltage potential at the first end of the TSV; as well as The TSV is determined to have failed the conductivity test in response to detecting the first test voltage potential at the first end of the TSV. 15 . The method of claim 14 , wherein precharging the first end of the TSV to the first test voltage potential comprises activating a switch operably coupled between the first end of the TSV and the first test voltage potential until the first end of the TSV is charged to the first test voltage potential.

16. The method of claim 14 or 15, wherein discharging the second end of the TSV to the second test voltage potential comprises activating a switch operably coupled between the second end of the TSV and the second test voltage potential until the second end of the TSV is discharged to the second test voltage potential.

17. A memory device comprising: A chip stack comprising a logic die and a core die stacked on the logic die; Through Silicon Vias (TSVs), the TSVs being located at different distances from one or more side edges of the chip stack; control circuitry located on or in the logic die, the control circuitry being configured to: performing a conductivity test on each of the TSVs; and A minimum acceptable TSV distance from the one or more side edges is determined to be the same as a distance from the identified TSV to the one or more side edges.

18. The memory device of claim 17, wherein an ordered sequence is associated with the TSVs from a TSV farthest from the one or more side edges to a TSV closest to the one or more side edges, and wherein the control circuitry is configured to: A TSV of the TSVs is identified that is a last consecutive TSV in the ordered sequence that passes the conductivity test without a previous TSV in the ordered sequence failing the conductivity test.

19. The memory device according to claim 17 or 18, wherein: The TSV is positioned at a first side edge of the one or more side edges; and The memory device further includes an additional TSV at a second side edge of the one or more side edges, the second side edge being different from the first side edge.

20. The memory device of claim 19, wherein the control circuitry is configured to determine another minimum acceptable TSV distance corresponding to the other TSVs independently of determining the minimum acceptable TSV distance corresponding to the TSV.

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