Power management integrated circuit and memory module including same

Abstract

Disclosed are a power management integrated circuit and a memory module including the same. The power management integrated circuit includes: an internal output transistor connected to an external voltage input line to which an external voltage is supplied and outputting an internal output voltage; the self-overvoltage protection circuit detects whether an external voltage exceeds a breakdown condition of the internal output transistor and supplies a gate voltage to a gate terminal of the internal output transistor. The clamp circuit outputs, as an internal output voltage, a first clamp voltage having a uniform level in a first overvoltage clamp mode and outputs, as the internal output voltage, a second clamp voltage that becomes lower from an external voltage level in a second overvoltage clamp mode. When the internal output transistor is turned off, the clamping circuit outputs the internal output voltage. The external voltage in the second overvoltage clamping mode may be greater than the external voltage in the first overvoltage clamping mode.

Description

[0001] This application claims the priority of Korean Patent Application No. 10-2023-0159160 filed on November 16, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure relates to a power management integrated circuit (PMIC) for a memory module. Background Art

[0003] The memory module is powered by at least two external power supplies according to standard specifications. For example, the memory module receives a high voltage power of 12V and a low voltage power of 5V or less, and converts them into internal voltages. In a memory system (e.g., a server module) including such a memory module, multiple memory modules are driven simultaneously by a single server, so the external power generated by the server is designed to drive a large current of tens of amperes (A) or more. Due to cost, power efficiency, and space limitations, it may be difficult for the power supply circuit of the server to apply a system that recognizes the state of the memory modules connected in parallel and selectively controls the supplied current.

[0004] Specifically, there may be an instance of a hot plug-short phenomenon between a high voltage pin and a low voltage pin among the input / output pins of each memory module. Hot plugging refers to the situation where a memory module is connected or disconnected while power is supplied during the operation of a server or data center. In the case of hot plugging, if the connector to the memory module is defective or not connected correctly, there is a defective cable, or there is a problem with the power supply device itself or a compatibility problem with the hardware components, a power short circuit may occur between nodes that should not be electrically connected. This is called a hot plug short circuit or a hot plug short circuit phenomenon. The hot plug short circuit phenomenon may cause overcurrent, fire, or damage to the memory module and its connected memory system (such as a server).

[0005] For example, due to damage to a low voltage device connected to a low voltage pin, burning of an integrated circuit (IC) (referred to as "IC burning") may occur, and IC burning of a memory module may be directly related to a fire hazard of a server. Therefore, a memory module is required to have a feature that can protect the memory module from unstable power supply conditions. Summary of the invention

[0006] Aspects of the present disclosure provide a memory module having improved endurance and reliability even under unstable power conditions.

[0007] Aspects of the present disclosure also provide a power management integrated circuit (PMIC) that protects a memory module from a hot-swap short circuit phenomenon.

[0008] Aspects of the present disclosure also provide a memory device including a PMIC capable of stably operating while minimizing an increase in its area with the use of a low voltage device.

[0009] However, aspects of the present disclosure are not limited to those set forth herein. The above and other aspects of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below.

[0010] According to one aspect of the present disclosure, there is provided a power management integrated circuit including an internal output transistor, a self-overvoltage protection circuit, and a clamp circuit, the internal output transistor being connected to an external voltage input line supplied with an external voltage and outputting an internal output voltage, the self-overvoltage protection circuit detecting whether the external voltage exceeds a breakdown condition of the internal output transistor and providing a gate voltage of the internal output transistor, and the clamp circuit outputting a first clamp voltage having a uniform level as the internal output voltage in a first overvoltage mode and outputting a second clamp voltage lower than the external voltage as the internal output voltage in a second overvoltage mode. When the internal output transistor is turned off, the clamp circuit may output the internal output voltage. The external voltage in the second overvoltage clamp mode may be greater than the external voltage in the first overvoltage clamp mode.

[0011] According to another aspect of the present disclosure, a power management integrated circuit (PMIC) is provided, including: an internal output transistor having a source terminal connected to an external voltage input line to which an external voltage is supplied and outputting an internal output voltage to a voltage supply terminal of an external device in a normal mode and an overvoltage sensing mode, a self-overvoltage protection circuit turning on the internal output transistor in the overvoltage sensing mode and turning off the internal output transistor in the clamping mode, a clamping circuit including a first high voltage clamping transistor and a second high voltage clamping transistor connected to each other via a current mirror, and outputting a clamping voltage generated from the second high voltage clamping transistor as an internal output voltage to the external device in the clamping mode. When the external voltage becomes higher than the first voltage, the self-overvoltage protection circuit turns on the internal output transistor. When the external voltage becomes higher than the second voltage greater than the first voltage, the self-overvoltage protection circuit turns off the internal output transistor.

[0012] According to the foregoing and other embodiments of the present disclosure, a memory module includes memory input / output pins, a plurality of memory devices, and a power management integrated circuit (PMIC). The PMIC receives an external voltage at an external voltage input line through at least one of the memory input / output pins, and outputs an internal output voltage to the plurality of memory devices. The PMIC includes an internal output transistor and a clamp circuit, the internal output transistor being turned on in a normal mode and in an overvoltage sensing mode and providing an internal output voltage, the clamp circuit including a first high voltage clamp transistor and a second high voltage clamp transistor connected to each other via a current mirror, and outputting a clamp voltage generated from the second high voltage clamp transistor as the internal output voltage. When the internal output transistor is turned off, the clamp circuit outputs a clamp voltage from the second high voltage clamp transistor.

[0013] It should be noted that the effects of the present disclosure are not limited to those described above, and other effects of the present disclosure will be clear from the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The above and other aspects and features of the present disclosure will become more apparent by describing in detail exemplary embodiments of the present disclosure with reference to the accompanying drawings, in which: Figure 1 is a diagram illustrating a memory module according to some embodiments of the present disclosure.

[0015] Figure 2 and Figure 3 is a circuit diagram illustrating a PMIC according to some embodiments of the present disclosure.

[0016] Figure 4 is a time-voltage graph illustrating an external voltage input to the PMIC 100 and an internal voltage output from the PMIC 100 according to example embodiments.

[0017] Figure 5 is a circuit diagram illustrating operation of the PMIC 100 in a normal mode according to an example embodiment.

[0018] Figure 6 is a diagram showing a method according to an example embodiment Figure 5 FIG. 1 is a table of the on / off states of transistors and Zener diodes in the PMIC 100 .

[0019] Figure 7 is a circuit diagram illustrating operation of the PMIC 100 in an overvoltage sensing mode according to an example embodiment.

[0020] Figure 8 is a diagram showing a method according to an example embodiment Figure 7 FIG. 1 is a table of the on / off states of transistors and Zener diodes in the PMIC 100 .

[0021] Fig. 9 is a table showing characteristics of transistors and resistors included in the PMIC 100 according to example embodiments.

[0022] Fig.10 is a circuit diagram illustrating operation of the PMIC 100 in a first overvoltage clamping mode according to an example embodiment.

[0023] Fig.11 is a diagram showing a method according to an example embodiment Fig.10 FIG. 1 is a table of the on / off states of transistors and Zener diodes in the PMIC 100 .

[0024] Fig.12 is a circuit diagram illustrating operation of the PMIC 100 in a second overvoltage clamping mode according to example embodiments.

[0025] Fig.13 is a diagram showing a method according to an example embodiment Fig.12 FIG. 1 is a table of the on / off states of transistors and Zener diodes in the PMIC 100 .

[0026] Fig.14 The minimum required breakdown voltage of each component of the PMIC 100 according to an example embodiment is shown.

[0027] Fig.15 A memory module including a PMIC 100 according to some embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0028] In the following we will refer to Figures 1 to 15 A memory device according to some embodiments of the present disclosure is described.

[0029] Figure 1 is a diagram illustrating a memory module according to some embodiments of the present disclosure.

[0030] Reference Figure 1 , the memory module 1 may include a memory device 10 , a controller (CON) 20 , a power management integrated circuit (PMIC) 100 , and an input / output interface 30 .

[0031] For example, the memory device 10 may be a dynamic random access memory (DRAM) device, but the present disclosure is not limited thereto. The memory device 10 may be a volatile memory device (such as a synchronous DRAM, a double data rate static DRAM (DDRSRAM), a low power double data rate static DRAM (LPDDR SDRAM), a graphic double data rate static DRAM (GDDRSDRAM), a DDR2 SDRAM, a DDR3 SDRAM, a DDR4 SDRAM, a DDR5 SDRAM, a wide I / O DRAM, a high bandwidth memory (HBM), a hybrid memory cube (HMC), etc.). In some embodiments, the memory device 10 may be a group of memory devices mounted on a memory module 1. The memory module 1 may be implemented as an unbuffered dual inline memory module (UDIMM), a registered dual inline memory module (RDIMM), a load reduced dual inline memory module (LRDIMM), a fully buffered dual inline memory module (FBDIMM), a small outline dual inline memory module (SODIMM), etc. Alternatively, in some embodiments, the memory device 10 may be a nonvolatile memory device (such as flash memory, phase change random access memory (PRAM), magnetic random access memory (MRAM), resistive random access memory (RRAM), ferroelectric random access memory (FRAM), etc.).

[0032] Although not shown, the memory module 1 may be connected to a memory controller and operate under the control of the memory controller. For example, the memory controller may control access operations (e.g., write operations or read operations) to the memory device 10 within the memory module 1. The memory controller may be implemented using one or more hardware components and / or program code of software and / or firmware for memory engagement (e.g., selecting rows and columns corresponding to memory cells, writing data to memory cells, or reading written data).

[0033] The controller 20 may convert signals received through the I / O interface 30 into signals for the memory device 10 to control a data access operation such as writing data, reading stored data, erasing data, or performing error correction.

[0034] The I / O interface 30 may include an interface circuit for communication between the memory device 10 and a memory controller, and may include, for example, a buffer circuit, a pin, a connector, a trace, and the like.

[0035] The PMIC 100 performs power management for the memory module 1. The PMIC 100 may convert an external voltage VINLV into an internal output voltage VINLVINT, and supply the internal output voltage VINLVINT to the memory device 10, the controller 20, and the I / O interface 30. For example, the PMIC 100 may be configured to scale up or scale down an external voltage VINLV provided from outside the memory module 1, and perform direct current-to-direct current (DC-DC) conversion or another similar power management operation to convert the external voltage VINLV into the internal output voltage VINLVINT. In some embodiments, the PMIC 100 may include a DC-DC converter (such as a low dropout regulator (LDO) circuit, a buck converter or a boost converter or a buck-boost converter), a power field effect transistor, a pulse frequency modulation circuit or a pulse width modulation circuit, a real-time clock circuit, or any other arbitrary circuit that can be generally implemented in a PMIC.

[0036] Figure 2 and Figure 3 is a circuit diagram illustrating a PMIC according to some embodiments of the present disclosure.

[0037] Reference Figure 2 In the normal mode, the PMIC 100 receives the external voltage VINLV through the external voltage input line for the external voltage VINLV, converts the external voltage VINLV into the internal output voltage VINLVINT, and outputs the internal output voltage VINLVINT. In the case where a high voltage is input to the external voltage input line, the PMIC 100 controls the output of the high voltage as the internal supply voltage using a series-connected transistor structure except for the normal mode, thereby preventing the external voltage VINLV from being directly input to the memory device 10.

[0038] The PMIC 100 operates in a normal mode, an overvoltage sensing mode, and an overvoltage clamping mode. The normal mode is a mode in which an external voltage VINLV within a predetermined normal power range is supplied to the PMIC 100. The overvoltage sensing mode is a mode in which an external voltage exceeds the normal power range and is still within a voltage range that does not damage a low voltage device (e.g., a transistor) included in the PMIC 100. The overvoltage clamping mode is a mode in which an external voltage exceeds the normal power range and even reaches a voltage level that may damage a low voltage device. This will be referred to later. Figures 4 to 14 The operation of the PMIC 100 in a normal mode, an overvoltage sensing mode, and an overvoltage clamping mode is described.

[0039] In some embodiments, the PMIC 100 includes an electrostatic discharge (ESD) protection circuit 110 , an overvoltage sensing circuit 120 , and a clamping circuit 130 .

[0040] In some embodiments, the ESD protection circuit 110 may include a low voltage ESD protection circuit "LV ESD", which is a circuit designed to prevent damage to the memory module 1 that may be caused by a surge voltage (such as static electricity). For example, the ESD protection circuit 110 can be implemented in a configuration of stacking and connecting a low voltage ESD protection circuit (LV ESD) between an external voltage input line and a ground voltage line for a ground voltage GND. For example, the ESD protection circuit 110 can be stacked and connected to N low voltage ESD protection circuits (LV ESD) of the same size (where N is a natural number greater than 2) to withstand a voltage that is N times higher than a single low voltage device without the assistance of a high voltage device.

[0041] In some embodiments, the overvoltage sensing circuit 120 includes a self-overvoltage protection circuit 125 and an internal output transistor LVMP2. When the external voltage VINLV is within the normal power range (i.e., in the normal mode), the overvoltage sensing circuit 120 turns on the internal output transistor LVMP2 to output the external voltage VINLV to an eighth node N8 connected to a low voltage device (LV device). In example embodiments, the low voltage device (LV device) may include at least one of a controller, a memory device, a logic device, an interface device, and a bias circuit. For example, the low voltage device (LV device) may be Figure 1 , the memory device 10, the controller 20, or the input / output interface 30 shown in . For example, the low voltage device (LV device) may include a transistor or component included in the memory device 10, the controller 20, and / or the input / output interface 30. The logic device or controller may include a microprocessor, a graphic processor, a signal processor, a network processor, a codec, etc. When an external voltage VINLV exceeding the normal power range is input, the overvoltage sensing circuit 120 operates in an overvoltage sensing mode for the external voltage VINLV within a predetermined range, and if the external voltage VINLV further increases, operates in an overvoltage clamping mode.

[0042] Reference Figure 3 , the self-overvoltage protection circuit 125 may include a plurality of low voltage transistors, a high voltage transistor, a plurality of Zener diodes, a plurality of resistors and two inverters. The difference between the low voltage transistor and the high voltage transistor may be at least one of their source / drain concentrations, the distance between their source and drain, the breakdown voltage of their pn junctions and the thickness of their gate oxides.

[0043] For example, the self-overvoltage protection circuit 125 includes a first Zener diode DZ1 and first, second, and third resistors R0, R1, R2 connected in series between the external voltage input line and the ground voltage line. For ease of explanation, the common node of the first and second resistors R0 and R1 is referred to as a first sensing node (or first node) N1 hereinafter.

[0044] The self-overvoltage protection circuit 125 also includes a fourth resistor R3 and a second Zener diode DZ2 between the external voltage input line and the ground voltage line. The fourth resistor R3 and the second Zener diode DZ2 generate a sensed external voltage VINLVOVP from the external voltage input line. Hereinafter, the common node of the fourth resistor R3 and the second Zener diode DZ2 is referred to as a second node or a sensed external voltage node N2.

[0045] The self-overvoltage protection circuit 125 further includes a third Zener diode DZ3 connected between the first node N1 and the ground voltage line.

[0046] The self-overvoltage protection circuit 125 also includes a fifth resistor R4 and a first low voltage transistor LVMN1 connected in series between the sensed external voltage node N2 and the ground voltage line. The gate terminal of the first low voltage transistor LVMN1 is connected to the first sensing node N1. For ease of explanation, the common node of the first low voltage transistor LVMN1 and the fifth resistor R4 is referred to as a buffer input node or a third node N3 hereinafter.

[0047] The self-overvoltage protection circuit 125 also includes two inverters, namely, a first inverter INV1 and a second inverter INV2 connected in series to the third node N3. The first inverter INV1 inverts a signal from the third node N3 and outputs the inverted signal to the fourth node N4, and the second inverter INV2 inverts a signal from the fourth node N4 and outputs the inverted signal to the fifth node N5. The first inverter INV1 and the second inverter INV2 are applied with the sensed external voltage VINLVOVP from the second node N2.

[0048] The self-overvoltage protection circuit 125 further includes a seventh resistor R6, a second low voltage transistor LVMN2, and a sixth resistor R5 connected in series between the external voltage input line and the ground voltage line. The gate terminal of the second low voltage transistor LVMN2 is connected to the fourth node N4. The common node of the seventh resistor R6 and the second low voltage transistor LVMN2 is hereinafter referred to as the sixth node N6.

[0049] The self-overvoltage protection circuit 125 further includes a third low voltage transistor LVMN3 connected between the ground line and a common node of the second resistor R1 and the third resistor R2. A gate terminal of the third low voltage transistor LVMN3 is connected to a fifth node N5.

[0050] The self-overvoltage protection circuit 125 may further include an eighth resistor R7 and a high voltage sensing transistor HVMN1 connected in series between the external voltage input line and the ground voltage line. The gate terminal of the high voltage sensing transistor HVMN1 is connected to the fifth node N5. The common node of the eighth resistor R7 and the high voltage sensing transistor HVMN1 is hereinafter referred to as a seventh node N7.

[0051] The self overvoltage protection circuit 125 may further include a fourth low voltage transistor LVMP1 connected between the external voltage input line and the seventh node N7 and having a gate terminal connected to the sixth node N6 .

[0052] The internal output transistor LVMP2 is connected between the external voltage input line and the low voltage device (LV device), and has a gate terminal connected to the seventh node N7 to provide the internal output voltage VINLVINT to the low voltage device (LV device) through a drain terminal thereof.

[0053] In some embodiments, the fourth low voltage transistor LVMP1 may be a P-type power transistor having the same breakdown characteristics as the internal output transistor LVMP2. In some embodiments, the first low voltage transistor LVMN1, the second low voltage transistor LVMN2, and the third low voltage transistor LVMN3 may be N-type power transistors having the same breakdown characteristics.

[0054] The term "breakdown characteristic" means that the internal output transistor LVMP2 has the same rated voltage as the first low voltage transistor LVMN1, the second low voltage transistor LVMN2, and the third low voltage transistor LVMN3, and has a higher rated current than the first low voltage transistor LVMN1, the second low voltage transistor LVMN2, and the third low voltage transistor LVMN3. To this end, the internal output transistor LVMP2 can be implemented in the form of a plurality of unit transistors connected. For example, the internal output transistor LVMP2 may include a plurality of unit transistors connected in parallel to each other.

[0055] In some embodiments, the clamp circuit 130 may include a first high voltage clamp transistor HVMN21 , a second high voltage clamp transistor HVMN22 , a ninth resistor R8 , a tenth resistor R9 , a fourth Zener diode DZ4 , and a fifth Zener diode DZ5 .

[0056] For example, the clamp circuit 130 may include a second high voltage clamp transistor HVMN22 connected to a low voltage device (LV device), and the second high voltage clamp transistor HVMN22 and the low voltage device (LV device) are connected in series between an external voltage input line and a ground voltage line. The low voltage device (LV device) receives the internal output voltage VINLVINT through a drain terminal of the second high voltage clamp transistor HVMN22. For ease of explanation, the common node of the second high voltage clamp transistor HVMN22 and the low voltage device (LV device) to which the internal output voltage VINLVINT is applied is referred to as an eighth node N8 hereinafter.

[0057] The clamp circuit 130 may further include a fifth Zener diode DZ5, a tenth resistor R9, a first high voltage clamp transistor HVMN21, a ninth resistor R8, and a fourth Zener diode DZ4 connected in series between the external voltage input line and the ground voltage line. The gate terminal and the drain terminal of the first high voltage clamp transistor HVMN21 are connected to a ninth node N9, and the ninth node N9 is connected to the gate terminal of the second high voltage clamp transistor HVMN22.

[0058] The clamp circuit 130 may further include an eleventh resistor R10 connected between the external voltage input line and the ninth node N9.

[0059] In some embodiments, the first high voltage clamp transistor HVMN21 and the second high voltage clamp transistor HVMN22 may be N-type high voltage power transistors having the same breakdown voltage as the internal output transistor LVMP2, and the rated voltages of the first high voltage clamp transistor HVMN21 and the second high voltage clamp transistor HVMN22 may be the same as the rated voltage of the internal output transistor LVMP2. Similar to the internal output transistor LVMP2, the first high voltage clamp transistor HVMN21 and the second high voltage clamp transistor HVMN22 may be implemented in the form of a plurality of unit transistors connected. For example, each of the first high voltage clamp transistor HVMN21 and the second high voltage clamp transistor HVMN22 may include a plurality of unit transistors connected in parallel to each other.

[0060] When the external voltage VINLV exceeds the normal power range and is high enough to damage the low voltage device (e.g., transistor), the first high voltage clamp transistor HVMN21 and the second high voltage clamp transistor HVMN22 are turned on through the ninth node N9 and act as switches in a source follower structure. Since the first high voltage clamp transistor HVMN21 and the second high voltage clamp transistor HVMN22 have a breakdown characteristic for high voltage, the first high voltage clamp transistor HVMN21 and the second high voltage clamp transistor HVMN22 can prevent the circuits and low voltage devices (LV devices) within the PMIC 100 from being damaged.

[0061] Figure 4 is a time-voltage graph illustrating an external voltage input to the PMIC 100 and an internal voltage output from the PMIC 100 according to example embodiments.

[0062] Reference Figure 4 , the PMIC 100 operates in a normal mode (Normal mode), an overvoltage sensing mode (OVP sensing mode) and an overvoltage clamping mode. The overvoltage clamping mode may include a first overvoltage clamping mode (OVP clamping mode 1) and a second overvoltage clamping mode (OVP clamping mode 2).

[0063] In the normal mode, the PMIC 100 is supplied with an external voltage VINLV within a normal power range defined based on characteristics of low voltage devices (LV devices) and other devices included in the PMIC 100. In the normal mode, the PMIC 100 generates and outputs an internal output voltage VINLVINT proportional to the external voltage VINLV. Figure 4 As shown in , when the external voltage VINLV is within the range of 0 to the Zener voltage VDZ, the PMIC 100 operates in the normal mode (Normal mode). The Zener voltage VDZ may be a turn-on threshold voltage of each of the first Zener diode DZ1 to the fifth Zener diode DZ5. For example, each of the first Zener voltage VDZ1 of the first Zener diode DZ1 to the fifth Zener voltage VDZ5 of the fifth Zener diode DZ5 may have the same voltage level. Here, each of the first Zener voltage VDZ1 to the fifth Zener voltage VDZ5 may be collectively referred to as the Zener voltage VDZ.

[0064] When the external voltage VINLV exceeds the normal power range and still remains within the voltage range without damaging the low voltage devices (e.g., transistors) included in the PMIC 100, the PMIC 100 operates in an overvoltage sensing mode (OVP sensing mode). In the overvoltage sensing mode (OVP sensing mode), the PMIC 100 generates and outputs an internal output voltage VINLVINT proportional to the external voltage VINLV. Figure 4 As shown in , when the external voltage VINLV exceeds the voltage VDZ but is lower than the level of (VDZ+VTH+VHYS), the PMIC 100 operates in an overvoltage sensing mode (OVP sensing mode). Hereinafter, the voltage VTH may be a threshold voltage corresponding to each of the first to third low voltage transistors LVMN1 to LVMN3, the high voltage sensing transistor HVMN1, and the high voltage clamping transistors HVMN21 and HVMN22.

[0065] When the external voltage VINLV exceeds the normal power range and reaches the level that can damage the low-voltage transistors in the device, the PMIC 100 operates in the overvoltage clamping mode. For example, when the external voltage VINLV is between (VDZ + VTH + VHYS) and (2VDZ + VTH), the PMIC 100 operates in the first overvoltage clamping mode (OVP clamping mode 1), and when the external voltage VINLV exceeds (2VDZ + VTH), the PMIC 100 operates in the second overvoltage clamping mode (OVP clamping mode 2). In the first overvoltage clamping mode (OVP clamping mode 1), the PMIC 100 controls the internal output voltage VINLVINT to maintain a constant level (e.g., the level of voltage VDZ), regardless of the continuous rise of the external voltage VINLV. For example, the PMIC 100 outputs a first clamping voltage with a uniform level as the internal output voltage VINLVINT in the first overvoltage clamping mode (OVP clamping mode 1). If the external voltage VINLV continues to rise in the second overvoltage clamping mode (OVP clamping mode 2), the PMIC 100 generates and outputs an internal output voltage VINLVINT that is proportional to but less than the external voltage VINLV. For example, the PMIC 100 outputs a second clamping voltage that becomes lower from the external voltage VINLV level as the internal output voltage VINLVINT in the second overvoltage clamping mode (OVP clamping mode 2).

[0066] In the following, reference will be made to Figures 5 to 14 Describe the operations of the PMIC 100 in the normal mode, overvoltage sensing mode, and the first and second overvoltage clamping modes.

[0067] Figure 5 and Figure 6 Show the PMIC 100 in the normal mode according to some embodiments of the present disclosure. Figure 5 is a circuit diagram showing the operation of the PMIC 100 in the normal mode, Figure 6 is to show Figure 5 A table of the on / off states of the transistors and Zener diodes in the PMIC 100 of

[0068] Referring to Figure 5 and Figure 6 If the external voltage VINLV input to the PMIC 100 is lower than the first Zener voltage VDZ1 of the first Zener diode DZ1 (i.e., VINLV < VDZ1), the PMIC 100 operates in the normal mode, and the overvoltage protection circuit 125 is deactivated.

[0069] For example, the first Zener diode DZ1 connected to the external voltage input line and the second Zener diode DZ2 connected to the external voltage input line through the fourth resistor R3 are turned off, so that the self-overvoltage protection circuit 125 is inactivated. Therefore, the first node N1 becomes a logic low, maintaining the first low voltage transistor LVMN1 turned off. The external voltage VINLV is applied to the second node N2 as the sensed external voltage VINLVOVP through the fourth resistor R3, and as a result, the second node N2 operates as an internal logic power supply. The second node N2 is defined as a logic high as an internal logic power supply. Since the sensed external voltage VINLVVOVP of the second node N2 is applied to the third node N3 through the fifth resistor R4 when the first low voltage transistor LVMN1 is turned off, the third node N3 also becomes a logic high. When the logic high of the third node N3 is inverted, the fourth node N4 becomes a logic low, turning off the second low voltage transistor LVMN2, and when the logic low of the fourth node N4 is inverted, the fifth node N5 becomes a logic high, turning on the third low voltage transistor LVMN3 and the high voltage sensing transistor HVMN1.

[0070] Since the external voltage VINLV is applied, the sixth node N6 becomes logic high, turning off the fourth low voltage transistor LVMP1, and the seventh node N7 becomes logic low, turning on the internal output transistor LVMP2.

[0071] Since the ground voltage GND is applied in the forward direction, the fourth Zener diode DZ4 is turned off, and since the external voltage VINLV within the normal power range less than the fifth Zener voltage VDZ5 is applied, the fifth Zener diode DZ5 is also turned off. The ninth node N9 is supplied with the external voltage VINLV through the eleventh resistor R10. The gate terminal and the drain terminal of the first high voltage clamp transistor HVMN21 are both connected to the ninth node N9, and since the fourth Zener diode DZ4 is turned off, the first high voltage clamp transistor HVMN21 is turned off. Since in the normal mode, the external voltage VINLV is applied to the ninth node N9, and a voltage of the same level as the external voltage VINLV is applied to the eighth node N8, the second high voltage clamp transistor HVMN22 is also turned off.

[0072] Since the normal mode is not an environment that affects the breakdown of the device or component, the operations related to the breakdown of the component of the overvoltage sensing circuit 120 and the clamping circuit 130 are not performed, and the internal output transistor LVMP2 is turned on and operates. For example, the first Zener diode DZ1, the second Zener diode DZ2, the third Zener diode DZ3, the fourth Zener diode DZ4, and the fifth Zener diode DZ5, the first low voltage transistor LVMN1, the second low voltage transistor LVMN2, and the fourth low voltage transistor LVMP1, and the first high voltage clamping transistor HVMN21 and the second high voltage clamping transistor HVMN22 are turned off, and the high voltage sensing transistor HVMN1, the third low voltage transistor LVMN3, and the internal output transistor LVMP2 are turned on. Due to the turned-on or turned-off Zener diodes and transistors, the current in the PMIC is as follows Figure 5 As shown by the arrow in FIG, , the voltage flows from the external voltage input line to the low voltage device (LV device) through the internal output transistor LVMP2. Figure 4 , in the normal mode, an internal output voltage VINLVINT for a low voltage device (LV device) in the PMIC 100 rises together with the external voltage VINLV.

[0073] Figure 7 and Figure 8 The PMIC 100 in an overvoltage sensing mode according to some embodiments of the present disclosure is illustrated. Figure 7 is a circuit diagram illustrating the operation of the PMIC 100 in an overvoltage sensing mode, and Figure 8 It is shown Figure 7 FIG. 1 is a table of the on / off states of transistors and Zener diodes in the PMIC 100 . Fig. 9 is a table showing characteristics of transistors and resistors included in the PMIC 100 according to example embodiments.

[0074] Reference Figures 7 to 9 If the external voltage VINLV input to the PMIC 100 increases and becomes higher than the first Zener voltage VDZ1 of the first Zener diode DZ1 (ie, VINLV>VDZ1), the PMIC 100 operates in the overvoltage sensing mode and the overvoltage sensing circuit 120 is activated. However, if the external voltage VINLV is lower than a critical level that may damage a low voltage transistor included in the device, the first high voltage clamp transistor HVMN21 and the second high voltage clamp transistor HVMN22 in the clamp circuit 130 are turned off.

[0075] For example, the first Zener diode DZ1 connected to the external voltage input line and the second Zener diode DZ2 connected to the external voltage input line through the fourth resistor R3 are turned on, so that the self-overvoltage protection circuit 125 is activated.

[0076] The switching voltage (or hysteresis voltage) VHYS of the first low-voltage transistor LVMN1 is based on the second resistor R1 and the third resistor R2. For example, referring to Fig. 9 the voltage-current curve graph (VDZ-ID curve), when the external voltage VINLV increases and reaches the reverse first Zener voltage VDZ1 of the first Zener diode DZ1 (i.e., VINLV = VDZ1), the first Zener diode DZ1 conducts, and the current I1 flows through the first resistor R0, the second resistor R1, and the third resistor R2. Therefore, the current I1 is applied to the first node N1, but the voltage VN1 of the first node N1 does not reach the threshold voltage of the first low-voltage transistor LVMN1 (i.e., VDZ1 + VTH), that is, VN1 < VDZ1 + VTH. Therefore, the first low-voltage transistor LVMN1 remains in the cut-off state. Conversely, if the external voltage VINLV continues to increase and exceeds the reverse first Zener voltage VDZ1 of the first Zener diode DZ1 (i.e., VINLV = VDZ1’), the first Zener diode DZ1 conducts, and the third low-voltage transistor LVMN3 also conducts, such that the current I2 flows through the first resistor R0, the second resistor R1, and the third low-voltage transistor LVMN3. The resistance of the third low-voltage transistor LVMN3 is much smaller than the resistance of the third resistor R2. Due to the difference between the combined resistance (R0 + R1 + R2) and the combined resistance (R0 + R1), the current I2 is greater than the current I1 (I2 > I1). The voltage of the first node N1 is lower in the case where the current I2 flows through the first resistor R0 and the second resistor R1 (rising) than in the case where the current I1 flows through the first resistor R0, the second resistor R1, and the third resistor R2 (falling).

[0077] Since the external voltage VINLV is applied to the second node N2 as the sensed external voltage VINLVOVP through a clamping circuit composed of the fourth resistor R3 and the second Zener diode DZ2, the operating power of the overvoltage protection circuit is limited to the reverse conduction voltage of the second Zener diode DZ2. Since the sensed external voltage VINLVOVP from the second node N2 is applied to the third node N3, the third node N3 also becomes logic high. Since the logic level of the fourth node N4 is inverted to logic low through the first inverter INV1, the second low-voltage transistor LVMN2 is cut off. Since the inversion of the fourth node N4 through the second inverter INV2, the fifth node N5 becomes logic high, turning on the third low-voltage transistor LVMN3 and the high-voltage sensing transistor HVMN1. However, since the operating voltage of the third Zener diode DZ3 is lower than the third Zener voltage VDZ3, the third Zener diode DZ3 connected to the first node N1 is cut off even when the current I1 is applied.

[0078] Due to the application of the external voltage VINLV, the sixth node N6 becomes logic high, turning off the fourth low voltage transistor LVMP1, and the seventh node N7 becomes logic low, turning on the internal output transistor LVMP2.

[0079] For example, the third Zener diode DZ3, the fourth Zener diode DZ4, and the fifth Zener diode DZ5, the first low voltage transistor LVMN1, the second low voltage transistor LVMN2, and the fourth low voltage transistor LVMP1, and the first high voltage clamp transistor HVMN21 and the second high voltage clamp transistor HVMN22 are turned off, and the first Zener diode DZ1 and the second Zener diode DZ2, the high voltage sensing transistor HVMN1, the third low voltage transistor LVMN3, and the internal output transistor LVMP2 are turned on. Due to these turned-on or turned-off Zener diodes and transistors, the current of the PMIC 100 is as follows: Figure 7 As shown by the arrow in , current flows from the external voltage input line to the low voltage device (LV device) through the internal output transistor LVMP2.

[0080] For example, in the overvoltage sensing mode, since the first Zener diode DZ1 and the second Zener diode DZ2 are turned on, the PMIC 100 starts to apply current to the first node N1 and the second node N2. However, since the first node N1 does not reach the threshold voltage (VDZ1+VTH+VHYS), the logic signal based on the third node N3 and the fourth node N4 satisfies the same condition as the normal mode, so that the first low voltage transistor LVMN1 and the second low voltage transistor LVMN2 in the self-overvoltage protection circuit 125 are turned off.

[0081] exist Figure 4In the overvoltage sensing mode, the internal output voltage VINLVINT of the PMIC 100 continues to increase even after the external voltage VINLV exceeds the voltage VDZ. Then, when the internal output voltage VINLVINT reaches the turn-on voltage of the first low voltage transistor LVMN1 (i.e., VDZ1+VTH+VHYS), the first low voltage transistor LVMN1 is turned on, so that the third node N3 becomes a logic low, which in turn makes the fourth node N4 a logic high and the fifth node N5 a logic low. Therefore, when the external voltage VINLV reaches the turn-on voltage level of the first low voltage transistor LVMN1, the second low voltage transistor LVMN2 and the fourth low voltage transistor LVMP1 are turned on, and the third low voltage transistor LVMN3 and the high voltage sensing transistor HVMN1 are turned off. Since the high voltage sensing transistor HVMN1 is turned off, the seventh node N7 is supplied with the external voltage VINLV through the eighth resistor R7, and as a result, the internal output transistor LVMP2 is turned off, so that the power supplied by the external voltage VINLV is cut off. By adjusting the voltage variation ΔVDZ (= VDZ1 − VDZ2 ) across the first Zener diode DZ1 using the on / off state of the third low voltage transistor LVMN3 and the second and third resistors R1 and R2 , a rising / falling hysteresis voltage (rising / falling VHYS) supplied to the gate terminal of the first low voltage transistor LVMN1 may be adjusted.

[0082] Fig.10 and Fig.11 The PMIC 100 in a first overvoltage clamping mode according to some embodiments of the present disclosure is described. Fig.10 is a circuit diagram illustrating the operation of the PMIC 100 in a first overvoltage clamping mode. Fig.11 It is shown Fig.10 A table of the on / off states of transistors and Zener diodes in the PMIC 100.

[0083] Reference Fig.10 and Fig.11 And further refer to Figure 4, as the external voltage VINLV continuously increases, exceeding the normal power range and reaching a level that can damage the low-voltage transistors included in the device, the PMIC 100 operates in overvoltage clamping modes ((OVP clamping mode 1) and (OVP clamping mode 2)). For example, when the external voltage VINLV exceeds the first clamping range that turns on the first low-voltage transistor LVMN1 (e.g., the voltage range from (VDZ1 + VTH + VHYS) to (2VDZ + VTH)), the PMIC 100 operates in the first overvoltage clamping mode (OVP clamping mode 1). In the overvoltage clamping modes ((OVP clamping mode 1) and (OVP clamping mode 2)), the external voltage VINLV is cut off, and power is supplied to the low-voltage device (LV device) based on the clamped power.

[0084] Refer to Fig.10 and Fig.11 , when the external voltage VINLV is within the first clamping range, that is, when (VDZ1 + VTH + VHYS) < VINLV ≤ (2VDZ4 + VTH), both the overvoltage sensing circuit 120 and the clamping circuit 130 are activated and operable.

[0085] For example, when the external voltage VINLV input to the PMIC 100 increases and exceeds the first Zener voltage VDZ1 of the first Zener diode DZ1 connected to the external voltage input line (i.e., VINLV > VDZ1), the first Zener diode DZ1 and the second Zener diode DZ2 conduct. The first low-voltage transistor LVMN1 receives, via the first node N1, a voltage signal obtained by dividing the voltage obtained by subtracting the first Zener voltage VDZ1 from the external voltage VINLV by the first resistor R0, the second resistor R1, and the third resistor R2. The resistances of the first resistor R0, the second resistor R1, and the third resistor R2 satisfy the following mathematical formula: R0 << R1 + R2, which ensures that most of the change in the external voltage VINLV is applied to the first node N1. The overvoltage protection circuit 125 further includes a third Zener diode DZ3, which is connected between the first node N1 and the ground voltage line. The third Zener diode DZ3 is cut off within the first clamping range, allowing the first low-voltage transistor LVMN1 to operate stably within its breakdown condition.

[0086] When the second Zener diode DZ2 conducts, the sensed external voltage VINLVOVP of the second node N2 is continuously clamped to the voltage VDZ2 of the second Zener diode DZ2. As a result, even if a high voltage is applied to the external voltage input line, the low-voltage device (LV device) operates stably at the clamping voltage of the second Zener diode DZ2. If the condition of the first clamping range is satisfied, i.e., VDZ1 + VTH + VHYS < VINLV, the first node N1 ensures the threshold voltage VTH of the first low-voltage transistor LVMN1, and the first low-voltage transistor LVMN1 conducts, causing the third node N3 to become logic low. Therefore, the fourth node N4 becomes logic high due to the inversion of the level of the third node N3 by the first inverter INV1, and the fifth node N5 becomes logic low due to the inversion of the level of the fourth node N4 by the second inverter INV2. Accordingly, the second low-voltage transistor LVMN2 conducts, and the third low-voltage transistor LVMN3 and the high-voltage sensing transistor HVMN1 are cut off. Since the external voltage VINLV within the first clamping range is applied to the sixth node N6, the fourth low-voltage transistor LVMP1 conducts, and since the seventh node N7 becomes logic high due to the conduction of the fourth low-voltage transistor LVMP1, the internal output transistor LVMP2 is cut off.

[0087] The first high-voltage clamping transistor HVMN21 and the second high-voltage clamping transistor HVMN22 operate as switches to supply the internal output voltage VINLVINT within the first clamping range. For example, since the internal output transistor LVMP2 is cut off, the supply of the external voltage VINLV is cut off, the level of the internal output voltage VINLVINT decreases, and when the gate-source voltage VGS of the second high-voltage clamping transistor HVMN22 is ensured, the second high-voltage clamping transistor HVMN22 conducts. Accordingly, the second high-voltage clamping transistor HVMN22 operates as a source-follower regulator that generates the internal output voltage VINLVINT. If the resistance of the eleventh resistor R10 is set to be much larger than the resistance of the ninth resistor R8 (i.e., R10 >> R8), most of the voltage is applied to the eleventh resistor R10. Therefore, as Figure 4 shown, the voltage of the ninth node N9 is maintained at a constant level (e.g., (VDZ4 + VTH)). The source voltage of the second high-voltage clamping transistor HVMN22 is close to the clamping voltage VDZ4 obtained by subtracting the threshold voltage VTH. Therefore, through the operation of the second high-voltage clamping transistor HVMN22, Figure 4 the internal output voltage VINLVINT is uniformly maintained at the level of the clamping voltage VDZ4 of the fourth Zener diode DZ4.

[0088] For example, in the PMIC 100, as the external voltage VINLV increases, the second low voltage transistor LVMN2 is turned on or off, which in turn causes the fourth low voltage transistor LVMP1 to be turned on or off. Subsequently, the internal output transistor LVMP2 is turned off or on according to the turning off or on of the high voltage sensing transistor HVMN1. As a result, the low voltage device (LV device) can receive the external voltage VINLV through the internal output transistor LVMP2, or receive a clamp voltage with a uniform level through the high voltage clamp transistor HVMN22.

[0089] Fig.12 and Fig.13 The PMIC 100 is shown in a second overvoltage clamping mode according to some embodiments of the present disclosure. Fig.12 is a circuit diagram illustrating the operation of the PMIC 100 in the second overvoltage clamping mode, and Fig.13 It is shown Fig.12 FIG. 1 is a table of the on / off states of transistors and Zener diodes in the PMIC 100 .

[0090] Reference Figure 4 , since the external voltage VINLV continues to increase beyond the normal power range and reaches a level (2VDZ+VTH) exceeding the breakdown voltage of the Zener diode, that is, VINLV>(2VDZ+VTH), the PMIC 100 operates in the second overvoltage clamping mode (OVP clamping mode 2). Even in the second overvoltage clamping mode (OVP clamping mode 2), the supply of the external voltage VINLV is cut off, and power is supplied to the low voltage device (LV device) based on the clamping power, as in the first overvoltage clamping mode (OVP clamping mode 1). However, in the second overvoltage clamping mode (OVP clamping mode 2), unlike in the first overvoltage clamping mode (OVP clamping mode 1), the clamping power increases based on the change of the external voltage VINLV.

[0091] For example, refer to Fig.12 and Fig.13 When the external voltage VINLV is within the second clamping range, that is, VINLV>(2VDZ+VTH), the first Zener diode DZ1, the second Zener diode DZ2, the third Zener diode DZ3, the fourth Zener diode DZ4 and the fifth Zener diode DZ5 are turned on.

[0092] Since the external voltage VINLV increases and exceeds the reverse first Zener voltage VDZ1 of the first Zener diode DZ1, the first Zener diode DZ1 is turned on, and the first Zener voltage VDZ1 is applied to the first node N1, so that the first low voltage transistor LVMN1 is turned on. However, if the voltage of the first node N1 increases excessively and exceeds the breakdown voltage of the first low voltage transistor LVMN1, the first low voltage transistor LVMN1 may be damaged. In order to prevent this, if the voltage of the first node N1 exceeds the third Zener voltage VDZ3, the third Zener diode DZ3 is turned on, causing a current to flow through the external voltage input line, the first Zener diode DZ1, the first resistor R0 and the third Zener diode DZ3. Therefore, the first low voltage transistor LVMN1 operates stably within its breakdown condition.

[0093] When the second Zener diode DZ2 is turned on, the sensed external voltage VINLVOVP of the second node N2 is continuously clamped to the second Zener voltage VDZ2 by the operation of the clamping circuit composed of the fourth resistor R3 and the second Zener diode DZ2. Therefore, even if a high voltage is applied to the external voltage input line, the low voltage device (e.g., transistor or component) included in the PMIC 100 is stably operated with the second Zener voltage VDZ2. Since a voltage exceeding the threshold voltage VTH of the first low voltage transistor LVMN1 is applied to the first node N1, the first low voltage transistor LVMN1 is turned on, so that the third node N3 becomes a logic low. Therefore, the fourth node N4 becomes a logic high due to the inversion of the level of the third node N3, and the fifth node N5 becomes a logic low due to the inversion of the level of the fourth node N4. Therefore, the second low voltage transistor LVMN2 is turned on, and the third low voltage transistor LVMN3 and the high voltage sensing transistor HVMN1 are turned off. Since the external voltage VINLV within the second clamping range is applied to the sixth node N6, the fourth low voltage transistor LVMP1 is turned on, and since the seventh node N7 becomes logic high due to the fourth low voltage transistor LVMP1 being turned on, the internal output transistor LVMP2 is turned off.

[0094] The first high voltage clamp transistor HVMN21 and the second high voltage clamp transistor HVMN22 operate as switches to supply an internal output voltage VINLVINT within a second clamp range. For example, at an external voltage VINLV within the second clamp range, the fifth Zener diode DZ5 is additionally turned on in a second overvoltage clamp mode (overvoltage clamp mode 2). Even if the second high voltage clamp transistor HVMN22 is turned on, if an external voltage VINLV within the second clamp range is applied, the breakdown voltage of the internal output transistor LVMP2 or the low voltage device (LV device) may be reached first. Therefore, by turning on both the fourth Zener diode DZ4 and the fifth Zener diode DZ5, the external voltage VINLV is used to generate an internal output voltage VINLVINT based on the resistance of the ninth resistor R8. The ninth resistor R8 may have almost the same resistance as the tenth resistor R9. Therefore, the second high voltage clamp transistor HVMN22 may mirror the voltage divided between the ninth resistor R8 and the tenth resistor R9 and output the voltage as the internal output voltage VINLVINT. As a result of voltage division between the ninth resistor R8 and the tenth resistor R9 , the level of the internal output voltage VINLVINT may be half the level of the external voltage VINLV.

[0095] For example, in the PMIC 100, even if the internal output transistor LVMP2 is turned off, the fourth Zener diode DZ4 and the fifth Zener diode DZ5 are turned on or off based on the level of the external voltage VINLV, and the first high voltage clamp transistor HVMN21 and the second high voltage clamp transistor HVMN22 are turned on. As a result, the external voltage VINLV is divided by the ninth resistor R8 and the tenth resistor R9, so that a clamp voltage proportional to the change in the external voltage VINLV can be output as the internal output voltage VINLVINT.

[0096] Fig.14 is a table illustrating breakdown conditions of components included in the PMIC 100 according to some embodiments of the present disclosure.

[0097] The first, second, third, fourth, and fifth Zener diodes DZ1, DZ2, DZ3, DZ4, and DZ5 included in the PMIC 100 may have the same Zener voltage.

[0098] The first low voltage transistor LVMN1, the second low voltage transistor LVMN2, the third low voltage transistor LVMN3, and the fourth low voltage transistor LVMP1 and the internal output transistor LVMP2 may be low voltage devices, and hereinafter, the following will describe the Figure 3The breakdown conditions of the first low-voltage transistor LVMN1, the second low-voltage transistor LVMN2, the third low-voltage transistor LVMN3, and the fourth low-voltage transistor LVMP1, which are connected to each other as shown, and the internal output transistor LVMP2.

[0099] Fig.14 Shows the required minimum breakdown voltage of each component in the PMIC 100. In some embodiments, a negative voltage can be mathematically obtained based on the condition of the external voltage VINLV, and such a negative voltage is considered to be 0V. Refer to Fig.14 , for the first low-voltage transistor LVMN1, the maximum gate-source voltage (Max VGS) is the third Zener voltage VDZ3 of the third Zener diode DZ3, and the maximum drain-source voltage (Max VDS) is the second Zener voltage VDZ2 of the second Zener diode DZ2. The breakdown condition of the first low-voltage transistor LVMN1 is that the breakdown voltage LVBV of the first low-voltage transistor LVMN1 is higher than the first Zener voltage VDZ1 of the first Zener diode DZ1.

[0100] For the second low-voltage transistor LVMN2, the maximum gate-source voltage (Max VGS) is the threshold voltage VTH of the low-voltage transistor, and the maximum drain-source voltage (Max VDS) is the voltage obtained by subtracting twice the second Zener voltage VDZ2 from the external voltage VINLV, i.e., (VINLV – 2×VDZ2). The breakdown condition of the second low-voltage transistor LVMN2 is that the breakdown voltage LVBV of the second low-voltage transistor LVMN2 is lower than (VINLV - 2×VDZ2). For example, if the drain-source breakdown voltage VDS_BV2 of the second low-voltage transistor LVMN2 is lower than (VINLV - 2×VDZ2), (i.e., VDS_BV2 < VINLV - 2×VDZ2), then the breakdown condition of the second low-voltage transistor LVMN2 can be satisfied. In other words, the maximum level of the external voltage VINLV can be defined when using a specific component.

[0101] For the third low-voltage transistor LVMN3 in the PMIC 100, the maximum gate-source voltage (Max VGS) is the second Zener voltage VDZ2, and the maximum drain-source voltage (Max VDS) is the third Zener voltage VDZ3. The breakdown condition of the third low-voltage transistor LVMN3 is that the breakdown voltage LVBV of the third low-voltage transistor LVMN3 is higher than the third Zener voltage VDZ3.

[0102] For the fourth low voltage transistor LVMP1, the maximum gate-source voltage (Max VGS) is a voltage obtained by subtracting the threshold voltage VTH from the second Zener voltage VDZ2, that is, (VDZ2-VTH), and the maximum drain-source voltage (MaxVDS) is the sum of the first Zener voltage VDZ1 and the threshold voltage VTH. The breakdown condition of the fourth low voltage transistor LVMP1 is that the breakdown voltage LVBV of the fourth low voltage transistor LVMP1 is higher than the sum of the first Zener voltage VDZ1 and the threshold voltage VTH.

[0103] For the internal output transistor LVMP2, the maximum gate-source voltage (Max VGS) is the sum of the first Zener voltage VDZ1 of the first Zener diode DZ1 and the threshold voltage VTH, and the maximum drain-source voltage (Max VDS) is also the sum of the first Zener voltage VDZ1 and the threshold voltage VTH. The breakdown condition of the internal output transistor LVMP2 is that the breakdown voltage LVBV of the internal output transistor LVMP2 is higher than the sum of the Zener voltage VDZ and the threshold voltage VTH.

[0104] The high voltage sensing transistor HVMN1 and the first and second high voltage clamping transistors HVMN21 and HVMN22 (hereinafter collectively referred to as “high voltage clamping transistors HVMN2”) have a breakdown condition that allows them to withstand a higher voltage than the first, second, third, and fourth low voltage transistors LVMN1, LVMN2, LVMN3, and LVMP1.

[0105] For example, for the high voltage sensing transistor HVMN1, the maximum gate-source voltage (Max VGS) is the second Zener voltage VDZ2, and the maximum drain-source voltage (Max VDS) is the external voltage VINLV. The breakdown condition of the high voltage sensing transistor HVMN1 is that the breakdown voltage HVBV of the high voltage sensing transistor HVMN1 is higher than the protected target external voltage VINLV.

[0106] For the high voltage clamp transistor HVMN2, the maximum gate-source voltage (Max VGS) is the threshold voltage VTH of the high voltage transistor HVMN2, and the maximum drain-source voltage (Max VDS) is a voltage (VINLV-VDZ5) obtained by subtracting the fifth Zener voltage VDZ5 from the external voltage VINLV. The breakdown condition of the high voltage clamp transistor HVMN2 is that the breakdown voltage HVBV of the high voltage clamp transistor HVMN2 is higher than the voltage obtained by subtracting the fourth Zener voltage VDZ4 or the fifth Zener voltage VDZ5 from the external voltage VINLV.

[0107] The resistance of the first resistor R0 can be much smaller than the combined resistance of the second resistor R1 and the third resistor R2 (i.e., R0 << R1 + R2), and the resistance of the sixth resistor R5 can be almost equal to the resistance of the seventh resistor R6 (i.e., R5 ≈ R6). The resistance of the eleventh resistor R10 can be much greater than the resistance of the ninth resistor R8 and the tenth resistor R9 (i.e., R10 >> R9 ≈ R8), where the resistance of the ninth resistor R8 and the tenth resistor R9 are almost equal. If the resistance of the sixth resistor R5 and the seventh resistor R6 are almost equal (i.e., R5 ≈ R6), then breakdown voltage protection can be provided for the fourth low-voltage transistor LVMP1 through the operation of an inverting amplifier composed of the second low-voltage transistor LVMN2 and the sixth resistor R5 without the need for an additional gate breakdown voltage protection circuit.

[0108] Fig.15 A memory module including a PMIC 100 is shown in accordance with some embodiments of the present disclosure.

[0109] Referring Fig.15 , the PMIC 100 can be included in a memory module 200 that can be installed in an electronic device. At least one memory module 200 can be installed in the electronic device.

[0110] The memory module 200 can include a plurality of volatile memory devices 211 to 218, a driver circuit, a PMIC 100, and memory input / output pins 220, all of which are arranged on a substrate 201. The driver circuit can include, for example, a serial presence detect (SPD) chip 250 and a register clock driver (RCD) 280.

[0111] In some embodiments, the volatile memory devices 211 to 218 can be dynamic random access memory (DRAM) devices, static random access memory (SRAM) devices, and / or synchronous DRAM (SDRAM) devices. In some embodiments, the memory module 200 can further include a data buffer (not shown) for data communication, and the data buffer is synchronized with a data strobe signal to exchange data with a memory controller (not shown).

[0112] In some embodiments, the memory controller can communicate with the volatile memory devices 211 to 218 using the following memory module standards: dual in-line memory module (DIMM), registered DIMM (RDIMM), load-reduced LR-DIMM (LRDIMM), or unbuffered DIMM (UDIMM).

[0113] The RCD 280 may control the volatile memory devices 211 to 218 and the PMIC 100 under the control of the memory controller. For example, the RCD 280 may receive addresses, commands, reset signals, and clock signals from the memory controller. The RCD 280 may control the volatile memory devices 211 to 218 using a first control signal and control the PMIC 100 using a second control signal.

[0114] In response to the received signals, the RCD 280 may control the volatile memory devices 211 to 218 to ensure that data received through the data signal DATA and the data strobe signal is written to the volatile memory devices 211 to 218 or data is retrieved from the volatile memory devices 211 to 218 .

[0115] The SPD chip 250 may be an electrically erasable programmable read-only memory (EEPROM). The SPD chip 250 may include initial information or device information of the memory module 200. For example, the SPD chip 250 may include initial information or device information (such as the form, configuration, storage capacity, type, and operating environment of the memory module 200).

[0116] When a memory system including the memory module 200 is booted, a host device (not shown) may read device information from the SPD chip 250 , and may recognize the memory module 200 based on the read information.

[0117] The PMIC 100 may generate an internal output voltage VINLVINT based on the external voltage VINLV, and provide the internal output voltage VINLVINT to the driver circuit and / or each of the plurality of volatile memory devices 211 to 218. The driver circuit and each of the plurality of volatile memory devices 211 to 218 may operate protectively based on the internal output voltage VINLVINT. The external voltage VINLV may be provided to an external voltage input line of the PMIC 100 through a host device. For example, the host device may provide the external voltage VINLV to the external voltage input line of the PMIC 100 through at least one of the memory input / output pins 220. As previously described with reference to Figures 1 to 14 As described, the PMIC 100 may operate in various modes (such as a normal mode, an overvoltage sensing mode, a first overvoltage clamping mode, and a second overvoltage clamping mode) according to a level of the external voltage VINLV.

[0118] The embodiments of the present disclosure have been described above with reference to the accompanying drawings, but the present disclosure is not limited thereto and can be implemented in various different forms. It will be understood that the present disclosure can be implemented in other specific forms without changing the technical spirit or gist of the present disclosure set forth in the appended claims. Therefore, it should be understood that the embodiments set forth herein are illustrative in all aspects and not restrictive.

Claims

1. A power management integrated circuit, comprising: an internal output transistor connected to an external voltage input line to which an external voltage is supplied and configured to output an internal output voltage; a self overvoltage protection circuit configured to detect whether an external voltage exceeds a breakdown condition of an internal output transistor and to provide a gate voltage to a gate terminal of the internal output transistor; as well as a clamp circuit configured to output a first clamp voltage having a uniform level as an internal output voltage in a first overvoltage clamp mode and to output a second clamp voltage lowered from an external voltage level as an internal output voltage in a second overvoltage clamp mode, Wherein, the clamp circuit is configured to output the internal output voltage when the internal output transistor is turned off, The external voltage in the second overvoltage clamping mode is greater than the external voltage in the first overvoltage clamping mode.

2. The power management integrated circuit of claim 1, wherein: The self-overvoltage protection circuit includes: A first Zener diode and a first resistor are connected in series between an external voltage input line and a first node; A second resistor and a third resistor are connected in series between the first node and a ground voltage line; a fourth resistor connected between the external voltage input line and the second node and configured to convert the external voltage into a sensed external voltage; and A second Zener diode is connected between the second node and the ground voltage line. The sum of the resistances of the second resistor and the third resistor is greater than the resistance of the first resistor.

3. The power management integrated circuit of claim 2, wherein: The self-overvoltage protection circuit also includes: a fifth resistor connected between the second node and the third node, a first low voltage transistor connected between the third node and the ground voltage line, a first inverter configured to invert a signal from the third node and output the inverted signal to a fourth node, and The second inverter is configured to invert the signal from the fourth node and output the inverted signal to the fifth node.

4. The power management integrated circuit of claim 3, wherein: The self-overvoltage protection circuit also includes: a sixth resistor having a first end and a second end connected to a ground voltage line; a seventh resistor connected between the external voltage input line and the sixth node; a second low voltage transistor connected between the sixth node and the first end of the sixth resistor and including a gate terminal connected to the fourth node; and A third low voltage transistor is connected between the ground voltage line and a common node of the second resistor and the third resistor and includes a gate terminal connected to a fifth node.

5. The power management integrated circuit of claim 4, wherein: The self-overvoltage protection circuit also includes: a fourth low voltage transistor connected between the external voltage input line and the seventh node and including a gate terminal connected to the sixth node, an eighth resistor connected between the external voltage input line and the seventh node, and a high voltage sensing transistor connected between the seventh node and the ground voltage line and including a gate terminal connected to the fifth node, Here, the gate terminal of the internal output transistor is connected to the seventh node.

6. The power management integrated circuit of claim 1, wherein: The clamping circuit includes: A fifth Zener diode, a tenth resistor, a first high voltage clamp transistor, a ninth resistor and a fourth Zener diode are connected in series between the external voltage input line and the ground voltage line; an eleventh resistor connected between the external voltage input line and the drain terminal of the first high voltage clamp transistor; and a second high voltage clamp transistor connected between the external voltage input line and an eighth node configured to output the internal output voltage, The gate terminal and the drain terminal of the first high voltage clamp transistor and the gate terminal of the second high voltage clamp transistor are connected to a ninth node.

7. A power management integrated circuit, comprising: an internal output transistor including a source terminal connected to an external voltage input line to which an external voltage is supplied, and configured to output the internal output voltage to a voltage supply terminal of an external device in a normal mode and an overvoltage sensing mode; a self-overvoltage protection circuit configured to turn on an internal output transistor in an overvoltage sensing mode and to turn off the internal output transistor in a clamping mode; as well as a clamp circuit including a first high voltage clamp transistor and a second high voltage clamp transistor connected to each other in a current mirror, and configured to output a clamp voltage generated from the second high voltage clamp transistor as an internal output voltage to an external device in a clamp mode, wherein the self-overvoltage protection circuit is configured to turn on the internal output transistor when the external voltage becomes higher than the first voltage, The self-overvoltage protection circuit is configured to turn off the internal output transistor when the external voltage becomes higher than a second voltage greater than the first voltage.

8. The power management integrated circuit of claim 7, wherein: The self-overvoltage protection circuit includes: A first Zener diode, a first resistor, a second resistor and a third resistor are connected in series between an external voltage input line and a ground voltage line; A fourth resistor and a second Zener diode are connected in series between the external voltage input line and the ground voltage line; a third Zener diode connected between the ground voltage line and a first node, the first node being a common node of the first resistor and the second resistor; and The first low voltage transistor includes a gate terminal connected to the first node.

9. The power management integrated circuit of claim 8, wherein: The self-overvoltage protection circuit also includes: a fifth resistor connected between the second node and a third node, wherein the second node is a common node of the fourth resistor and the second Zener diode, and a drain terminal of the first low voltage transistor is connected to the third node; a first inverter supplied with power from the second node, the first inverter being configured to invert a signal from the third node and output the inverted signal to a fourth node; a second inverter supplied with power from the second node, the second inverter being configured to invert a signal from the fourth node and output the inverted signal to a fifth node; and The seventh resistor, the second low voltage transistor and the sixth resistor are connected in series between the external voltage input line and the ground voltage line, Wherein, a gate terminal of the second low voltage transistor is connected to the fourth node.

10. The power management integrated circuit of claim 9, wherein: The self-overvoltage protection circuit also includes: a third low voltage transistor connected between the ground voltage line and a common node of the second resistor and the third resistor and including a gate terminal connected to a fifth node; a fourth low voltage transistor connected between the external voltage input line and a seventh node, the fourth low voltage transistor including a gate terminal connected to a sixth node, the sixth node being a common node of the seventh resistor and the second low voltage transistor; and A high voltage sensing transistor is connected between the seventh node and the ground voltage line and includes a gate terminal connected to the fifth node.

11. The power management integrated circuit of claim 10, wherein the self-overvoltage protection circuit further comprises: an eighth resistor connected between the external voltage input line and the seventh node, wherein the gate terminal of the internal output transistor is connected to the seventh node, The internal output transistor is configured to be turned on or off based on the level of the external voltage.

12. The power management integrated circuit of claim 10, wherein: The first to third Zener diodes are configured to be turned on in response to the first to third Zener voltages, respectively. Wherein, in the clamp mode, when the external voltage becomes higher than the second voltage, the high voltage sensing transistor and the internal output transistor are turned off and the first low voltage transistor and the fourth low voltage transistor are turned on.

13. The power management integrated circuit of claim 8, wherein: The first to third Zener diodes are configured to be turned on in response to the first to third Zener voltages, respectively. The first voltage is the same as each of the first to third Zener voltages.

14. The power management integrated circuit of claim 8, wherein: The resistance of the first resistor is smaller than the resistance of the sum of the resistance of the second resistor and the resistance of the third resistor.

15. The power management integrated circuit of claim 8, wherein: The first to third Zener diodes are configured to be turned on in response to the first to third Zener voltages, respectively. In which, in the overvoltage sensing mode, when the external voltage is higher than the first Zener voltage of the first Zener diode and the sensed external voltage from the fourth resistor is higher than the second Zener voltage of the second Zener diode, the self-overvoltage protection circuit outputs an internal output voltage according to the external voltage by turning on the first Zener diode and the second Zener diode and the internal output transistor and turning off the third Zener diode.

16. The power management integrated circuit of claim 15, wherein: In the overvoltage sensing mode, the first high voltage clamp transistor and the second high voltage clamp transistor are configured to be turned off.

17. The power management integrated circuit of claim 8, wherein: The clamping circuit also includes: a fourth Zener diode and a ninth resistor connected in series between the ground voltage line and the source terminal of the first high voltage clamp transistor; a fifth Zener diode and a tenth resistor connected in series between the external voltage input line and the drain terminal of the first high voltage clamp transistor; and an eleventh resistor connected between the external voltage input line and the drain terminal of the first high voltage clamp transistor, The clamp circuit is configured to output a clamp voltage to an external device based on a state of the first high voltage clamp transistor.

18. The power management integrated circuit of claim 17, wherein: The resistance of the ninth resistor is the same as the resistance of the tenth resistor, The resistance of the eleventh resistor is greater than the resistance of the ninth resistor and the resistance of the tenth resistor.

19. The power management integrated circuit of claim 17, wherein: The clamping mode includes a first overvoltage clamping mode and a second overvoltage clamping mode. wherein, in the first overvoltage clamping mode, the fourth Zener diode is configured to be turned on and the fifth Zener diode is configured to be turned off, In the second overvoltage clamping mode, the fourth Zener diode and the fifth Zener diode are configured to be turned on.

20. A memory module, comprising: Memory input / output pins; a plurality of memory devices; as well as A power management integrated circuit configured to: receiving an external voltage at an external voltage input line through at least one of the memory input / output pins, and outputting an internal output voltage to the plurality of memory devices, Wherein, the power management integrated circuit comprises: an internal output transistor configured to conduct and provide an internal output voltage in a normal mode and an overvoltage sensing mode, and a clamp circuit including a first high voltage clamp transistor and a second high voltage clamp transistor connected to each other in a current mirror and configured to output a clamp voltage generated from the second high voltage clamp transistor as an internal output voltage, Wherein, when the internal output transistor is turned off, the clamp circuit is configured to output a clamp voltage from the second high voltage clamp transistor.

Images