Crystal oscillator driving circuit

By using switching capacitors and DET control signals in the crystal oscillator driving circuit, it is possible to increase the bias current before the crystal oscillator starts to accelerate the start-up, and reduce the bias current after the start-up to reduce power consumption, solving the problem of difficult to balance the start-up speed and power consumption in the prior art.

CN120016968APending Publication Date: 2025-05-16SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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Patent Information

Application Number
CN202510125632.9
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2025-01-26
Publication Date
2025-05-16

AI Technical Summary

Technical Problem

The prior art crystal oscillator driving circuit requires a large bias current to increase the starting speed when starting up, but after the crystal oscillator starts up, the current is wasted, making it difficult to balance the starting speed and power consumption.

Method used

A crystal oscillator driving circuit is designed to reduce the bias current after the crystal oscillator starts, and power consumption is reduced by using switching capacitors and DET control signals after the start of the crystal oscillator.

Benefits of technology

It realizes the startup speed before the crystal oscillator starts, and reduces power consumption after the start of the crystal oscillator, which balances the startup performance and energy efficiency of the circuit.

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Abstract

The invention provides a crystal oscillator driving circuit, which is characterized in that a drain electrode of a third PMOS (P-channel Metal Oxide Semiconductor) tube is connected with a third NMOS (N-channel Metal Oxide Semiconductor) tube, a drain electrode of a fifth PMOS tube and a first end of a second resistor, and is also connected to a first end of a crystal oscillator; the second end of the second resistor is connected with the grid electrode of the third NMOS tube and is also connected to the second end of the crystal oscillator; the drain electrode of the fourth PMOS tube is connected with the source electrode of the fifth PMOS tube, the grid electrode of the fifth PMOS tube is connected with a DET control signal, and the drain electrode of the fifth PMOS tube is connected with the drain electrode of the third PMOS tube; the grid electrode of the first NMOS tube is connected with the drain electrode of the first PMOS tube, and the drain electrode of the first NMOS tube is connected with the grid electrode of the second NMOS tube; the first end of the first switch is connected with a power supply, the second end is connected with the first end of the second switch, and the second end of the second switch outputs a DET control signal; the first end of the capacitor is connected with the first end of the first switch.
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Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor integrated circuit manufacturing, and in particular to a crystal oscillator driving circuit. Background Art

[0002] In timing circuits, crystal oscillators, or crystal oscillators for short, are the most basic electronic components and are widely used in integrated circuits.

[0003] The crystal oscillator driving circuit of the prior art is as follows Figure 1 As shown, it includes 3 PMOS tubes (MP1-MP3) and 3 NMOS tubes (MN1-MN3), the PMOS tube MP2 is connected in series with the NMOS tube MN2, the PMOS tube MP3 is connected in series with the NMOS tube MN3, the gates of the PMOS tubes MP1, MP2 and MP3 are connected together and short-circuited with the drain of the PMOS tube MP2, the PMOS tube MP1 and the NMOS tube MN1 are connected in series through a resistor R1, and the gate of the NMOS tube MN1 is connected to the drain of the PMOS tube MP1, the gate of the NMOS tube MN2 is connected to the drain of the NMOS tube MN1, the gate of the NMOS tube MN3 is connected to one end of the crystal oscillator and then connected to the drain of the PMOS tube MP3 through a resistor Rf, and the other end of the crystal oscillator is connected to the drain of the PMOS tube MP3. The crystal oscillator oscillation signals X1 and X2 are output as positive clock signals CKP and reverse clock signals CKN through the operational amplifier AMP. The width-to-length ratio of the NMOS tube MN2 is N times that of the NMOS tube MN1, generating a current on the resistor R1: IB = (kT / q)*lnN / R1; where K is the Boltzmann constant, T is the temperature, and q is the charge constant. The operational amplifier AMP amplifies the signals of X1 and X2 to the power supply to ground.

[0004] However, the crystal oscillator driving circuit in the prior art has the following disadvantages: since the current required to maintain the oscillation after the crystal oscillator is started is relatively small, but a relatively large bias current is required to increase the startup speed during startup. Therefore, when a fixed bias current is used for driving, if the current is relatively small, the crystal oscillator circuit starts relatively slowly, and if a relatively large bias current is used, current will be wasted after the crystal oscillator is started. Summary of the invention

[0005] The object of the present invention is to provide a crystal oscillator driving circuit, which can increase the bias current before the crystal oscillator is started, thereby improving the startup speed of the circuit, and reduce the bias current and power consumption after the crystal oscillator is started.

[0006] In order to achieve the above object, the present invention provides a crystal oscillator driving circuit, comprising:

[0007] The first to fifth PMOS transistors, the first to third NMOS transistors, the first to third resistors, the first switch, the second switch and the capacitor;

[0008] The source of the first PMOS tube, the source of the second PMOS tube, the source of the third PMOS tube and the source of the fourth PMOS tube are all connected to a power supply, the gate of the first PMOS tube is connected to the gate of the second PMOS tube, the gate of the third PMOS tube and the gate of the fourth PMOS tube, and the drain of the first PMOS tube is connected to the drain of the first NMOS tube through the first resistor;

[0009] The source of the first NMOS tube, the source of the second NMOS tube and the source of the third NMOS tube are all grounded;

[0010] The drain of the second PMOS tube is connected to the drain of the second NMOS tube;

[0011] The drain of the third PMOS tube is connected to the drain of the third NMOS tube, the drain of the fifth PMOS tube, and the first end of the second resistor, and is also connected to the first end of the crystal oscillator;

[0012] The second end of the second resistor is connected to the gate of the third NMOS tube, and is also connected to the second end of the crystal oscillator;

[0013] The drain of the fourth PMOS tube is connected to the source of the fifth PMOS tube, the gate of the fifth PMOS tube is connected to the DET control signal, and the drain of the fifth PMOS tube is connected to the drain of the third PMOS tube;

[0014] The gate of the first NMOS tube is connected to the drain of the first PMOS tube, and the drain of the first NMOS tube is connected to the gate of the second NMOS tube;

[0015] The first end of the first switch is connected to a power supply, the second end of the first switch is connected to the first end of the second switch, the second end of the second switch is grounded through the third resistor, and the second end of the second switch outputs a DET control signal;

[0016] A first end of the capacitor is connected to a first end of the first switch, and a second end of the capacitor is grounded.

[0017] Optionally, in the crystal oscillator driving circuit, the width-to-length ratio of the second NMOS tube is N times the width-to-length ratio of the first NMOS tube, where N is a positive integer.

[0018] Optionally, the crystal oscillator driving circuit also includes an operational amplifier, wherein the first input terminal of the operational amplifier is connected to the first end of the crystal oscillator, the second input terminal is connected to the second end of the crystal oscillator, the first output terminal outputs a forward clock signal, and the second output terminal outputs a reverse clock signal.

[0019] Optionally, in the crystal oscillator driving circuit, the first switch is controlled by the forward clock signal, and the second switch is controlled by the reverse clock signal.

[0020] Optionally, in the crystal oscillator driving circuit, the first switch, the second switch and the capacitor constitute a switched capacitor, and the switched capacitor equivalent resistance is: Req=1 / (C*F), where C is the capacitance, F is the crystal oscillator frequency, and Req is the equivalent resistance.

[0021] Optionally, in the crystal oscillator driving circuit, the resistance of the third resistor is 9 to 11 times the equivalent resistance of the switching capacitor.

[0022] Optionally, in the crystal oscillator driving circuit, before the crystal oscillator starts oscillating, the switching capacitor does not work.

[0023] Optionally, in the crystal oscillator driving circuit, before the crystal oscillator starts oscillating, the DET control signal is at a low level, the fifth PMOS tube is turned on, and the current flowing through the third NMOS tube is the sum of the currents flowing through the third PMOS tube and the fourth PMOS tube.

[0024] Optionally, in the crystal oscillator driving circuit, after the crystal oscillator starts oscillating, the switching capacitor works.

[0025] Optionally, in the crystal oscillator driving circuit, after the switch capacitor works, the DET control signal is at a high level, the fifth PMOS tube is turned off, and the current flowing through the third NMOS tube is the current flowing through the third PMOS tube.

[0026] The crystal oscillator driving circuit provided by the present invention comprises: a first PMOS tube to a fifth PMOS tube, a first NMOS tube to a third NMOS tube, a first resistor to a third resistor, a first switch, a second switch and a capacitor; the source of the first PMOS tube, the source of the second PMOS tube, the source of the third PMOS tube and the source of the fourth PMOS tube are all connected to a power supply, the gate of the first PMOS tube is connected to the gate of the second PMOS tube, the gate of the third PMOS tube and the gate of the fourth PMOS tube, the drain of the first PMOS tube is connected to the drain of the first NMOS tube through the first resistor; the source of the first NMOS tube, the source of the second NMOS tube and the source of the third NMOS tube are all grounded; the drain of the second PMOS tube is connected to the drain of the second NMOS tube; the drain of the third PMOS tube is connected to the drain of the third NMOS tube; The gate of the fourth PMOS tube is connected to the source of the fifth PMOS tube, the gate of the fifth PMOS tube is connected to the DET control signal, and the drain of the fifth PMOS tube is connected to the drain of the third PMOS tube; the gate of the first NMOS tube is connected to the drain of the first PMOS tube, and the drain of the first NMOS tube is connected to the gate of the second NMOS tube; the first end of the first switch is connected to the power supply, the second end of the first switch is connected to the first end of the second switch, the second end of the second switch is grounded through the third resistor, and the second end of the second switch outputs the DET control signal; the first end of the capacitor is connected to the first end of the first switch, and the second end of the capacitor is grounded. Before the crystal oscillator starts oscillating, the switch capacitor composed of the first switch, the second switch and the capacitor does not work, the DET control signal is low, and the fifth PMOS tube is turned on. The current flowing through the third NMOS tube is the sum of the currents flowing through the third PMOS tube and the fourth PMOS tube. Therefore, compared with only the current of the third PMOS tube flowing through the third NMOS tube, the bias current is increased, and the start-up time of the crystal oscillator is increased. After the crystal oscillator starts, the switch capacitor composed of the first switch, the second switch and the capacitor works. The DET control signal is at a high level, the fifth PMOS tube is turned off, the branch of the fourth PMOS tube is closed, and only the branch of the third PMOS tube remains. The current flowing through the third NMOS tube is the current flowing through the third PMOS tube. Therefore, after the crystal oscillator starts, the power consumption is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a schematic diagram of a crystal oscillator driving circuit of the prior art;

[0028] Figure 2 Schematic diagram of a crystal oscillator driving circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0029] The specific implementation of the present invention will be described in more detail below in conjunction with the schematic diagram. The advantages and features of the present invention will become clearer based on the following description. It should be noted that the drawings are all in a very simplified form and are not in exact proportions, and are only used to facilitate and clearly assist in explaining the purpose of the embodiments of the present invention.

[0030] Hereinafter, the terms "first", "second", etc. are used to distinguish between similar elements and are not necessarily used to describe a particular order or chronological sequence. It is to be understood that these terms used in this manner are interchangeable where appropriate. Similarly, if the method described herein includes a series of steps, the order of these steps presented herein is not necessarily the only order in which these steps can be performed, and some of the steps described may be omitted and / or some other steps not described herein may be added to the method.

[0031] Furthermore, it should be understood that when a layer (or film), region, pattern or structure is referred to as being "on" a substrate, layer (or film), region and / or pattern, it can be directly on another layer or substrate, and / or there can be intervening layers. In addition, it should be understood that when a layer is referred to as being "under" another layer, it can be directly under another layer, and / or there can be one or more intervening layers. In addition, references to being "on" and "under" each layer can be made based on the accompanying drawings.

[0032] Please refer to Figure 2The present invention provides a crystal oscillator driving circuit, comprising: a first PMOS tube MP1, a second PMOS tube MP2, a third PMOS tube MP3, a fourth PMOS tube MP4, a fifth PMOS tube MP5, a first NMOS tube MN1, a second NMOS tube MN2, a third NMOS tube MN3, a first resistor R1, a second resistor Rf, a third resistor R, a first switch SW1, a second switch SW2 and a capacitor Ca; the source of the first PMOS tube MP1 is connected to a power supply VDDA, the gate of the first PMOS tube MP1 is connected to the gate of the second PMOS tube MP2, the third PMOS tube MP3 is connected to the gate of the third PMOS tube MP4, and the gate of the second PMOS tube MP3 is connected to the gate of the third PMOS tube MP5. The gate of the OS transistor MP3 and the gate of the fourth PMOS transistor MP4 are both connected, the drain of the first PMOS transistor MP1 is connected to the drain of the first NMOS transistor MN1 through the first resistor R1, and the source of the first NMOS transistor MN1 is grounded to GNDA; the source of the second PMOS transistor MP2 is connected to the power supply VDDA, the drain of the second PMOS transistor MP2 is connected in series with the drain of the second NMOS transistor MN2, and the source of the second NMOS transistor MN2 is grounded to GNDA; the source of the third PMOS transistor MP3 is connected to the power supply VDDA, the drain of the third PMOS transistor MP3 is connected in series with the drain of the third NMOS transistor MN3 The drain of the third NMOS tube MN3 is connected to the ground GNDA; the second end of the second resistor is connected to the gate of the third NMOS tube, and is also connected to the second end of the crystal oscillator; the source of the fourth PMOS tube MP4 is connected to the power supply VDDA, and the drain of the fourth PMOS tube MP4 is connected to the source of the fifth PMOS tube MP5; the gate of the fifth PMOS tube MP5 is connected to the DET control signal, and the drain of the fifth PMOS tube MP5 is connected to the drain of the third PMOS tube MP3; the gate of the first NMOS tube MN1 is connected to the gate of the first PMOS tube MP1 The drain of the first NMOS tube MN1 is connected to the ground GNDA; the gate of the second NMOS tube MN2 is connected to the drain of the first NMOS tube MN1, and the drain of the second NMOS tube MN2 is connected to the ground GNDA; the first end of the first switch SW1 is connected to the power supply VDDA, the second end of the first switch SW1 is connected to the first end of the second switch SW2, the second end of the second switch SW2 is connected to the ground GNDA through the third resistor Ra, and the second end of the second switch SW2 outputs the DET control signal; the first end of the capacitor Ca is connected to the first end of the first switch SW1, and the second end of the capacitor Ca is grounded. The width-to-length ratio of the second NMOS tube is N times the width-to-length ratio of the first NMOS tube, where N is a positive integer.

[0033] Preferably, the crystal oscillator driving circuit of the present invention may also include: an operational amplifier AMP, the first input terminal of the operational amplifier AMP is connected to the first terminal X1 of the crystal oscillator, the second input terminal is connected to the second terminal X1 of the crystal oscillator, the first output terminal outputs a positive clock signal CKP, and the second output terminal outputs a reverse clock signal CKN.

[0034] The first switch SW1, the second switch SW2 and the capacitor Ca of the embodiment of the present invention form a switch capacitor, and the equivalent resistance is: Req=1 / (C*F), where C is the capacitance of the capacitor Ca, F is the crystal frequency, and Req is the equivalent resistance. The first switch SW1 is controlled by the positive clock signal CKP output by the operational amplifier, and the second switch SW2 is controlled by the reverse clock signal CKN output by the operational amplifier. The resistance value of the equivalent resistance of the switch capacitor of the embodiment of the present invention is much smaller than the resistance value of the third resistor, and the preferred resistance value of the third resistor is 9 to 11 times that of the equivalent resistance. For example, the equivalent resistance can be 1Mohm, and the third resistor can be 10Mohm.

[0035] Before the crystal oscillator starts, the switch capacitor does not work. The DET control signal is at a low level, and the fifth PMOS tube MP5 is turned on. The current flowing through the third NMOS tube MN3 is the sum of the current flowing through the third PMOS tube MP3 and the fourth PMOS tube MP4. Therefore, compared with only the current of the third PMOS tube flowing through the third NMOS tube MN3, the bias current is increased, and the start-up time of the crystal oscillator is increased. Compared with the prior art, the embodiment of the present invention is increased from 19ms to 36ms. After the crystal oscillator starts, the switch capacitor works. The DET control signal is at a high level, the fifth PMOS tube MP5 is turned off, the branch of the fourth PMOS tube MP4 is closed, and only the branch of the third PMOS tube MP3 remains. The current flowing through the third NMOS tube MN3 is the current flowing through the third PMOS tube MP3. The bias current after startup is smaller than the bias current before startup, so after the crystal oscillator starts, the power consumption is reduced.

[0036] In summary, the crystal oscillator driving circuit provided in the embodiment of the present invention includes: a first PMOS tube to a fifth PMOS tube, a first NMOS tube to a third NMOS tube, a first resistor to a third resistor, a first switch, a second switch and a capacitor; the source of the first PMOS tube, the source of the second PMOS tube, the source of the third PMOS tube and the source of the fourth PMOS tube are all connected to the power supply, the gate of the first PMOS tube is connected to the gate of the second PMOS tube, the gate of the third PMOS tube and the gate of the fourth PMOS tube, the drain of the first PMOS tube is connected to the drain of the first NMOS tube through the first resistor; the source of the first NMOS tube, the source of the second NMOS tube and the source of the third NMOS tube are all grounded; the drain of the second PMOS tube is connected to the drain of the second NMOS tube; the drain of the third PMOS tube is connected to the drain of the third NMOS tube The drain of the tube, the drain of the fifth PMOS tube, and the first end of the second resistor are all connected, and are also connected to the first end of the crystal oscillator; the second end of the second resistor is connected to the gate of the third NMOS tube, and is also connected to the second end of the crystal oscillator; the drain of the fourth PMOS tube is connected to the source of the fifth PMOS tube, the gate of the fifth PMOS tube is connected to the DET control signal, and the drain of the fifth PMOS tube is connected to the drain of the third PMOS tube; the gate of the first NMOS tube is connected to the drain of the first PMOS tube, and the drain of the first NMOS tube is connected to the gate of the second NMOS tube; the first end of the first switch is connected to the power supply, the second end of the first switch is connected to the first end of the second switch, the second end of the second switch is grounded through the third resistor, and the second end of the second switch outputs the DET control signal; the first end of the capacitor is connected to the first end of the first switch, and the second end of the capacitor is grounded. Before the crystal oscillator starts oscillating, the switch capacitor composed of the first switch, the second switch and the capacitor does not work, the DET control signal is low, and the fifth PMOS tube is turned on. The current flowing through the third NMOS tube is the sum of the currents flowing through the third PMOS tube and the fourth PMOS tube. Therefore, compared with only the current of the third PMOS tube flowing through the third NMOS tube, the bias current is increased, and the start-up time of the crystal oscillator is increased. After the crystal oscillator starts, the switch capacitor composed of the first switch, the second switch and the capacitor works. The DET control signal is at a high level, the fifth PMOS tube is turned off, the branch of the fourth PMOS tube is closed, and only the branch of the third PMOS tube remains. The current flowing through the third NMOS tube is the current flowing through the third PMOS tube. Therefore, after the crystal oscillator starts, the power consumption is reduced.

[0037] The above is only a preferred embodiment of the present invention and does not limit the present invention in any way. Any technician in the relevant technical field, without departing from the scope of the technical solution of the present invention, makes any form of equivalent replacement or modification to the technical solution and technical content disclosed in the present invention, which does not depart from the content of the technical solution of the present invention and still falls within the protection scope of the present invention.

Claims

1. A crystal oscillator driving circuit, characterized in that: include: The first to fifth PMOS transistors, the first to third NMOS transistors, the first to third resistors, the first switch, the second switch and the capacitor; The source of the first PMOS tube, the source of the second PMOS tube, the source of the third PMOS tube and the source of the fourth PMOS tube are all connected to a power supply, the gate of the first PMOS tube is connected to the gate of the second PMOS tube, the gate of the third PMOS tube and the gate of the fourth PMOS tube, and the drain of the first PMOS tube is connected to the drain of the first NMOS tube through the first resistor; The source of the first NMOS tube, the source of the second NMOS tube and the source of the third NMOS tube are all grounded; The drain of the second PMOS tube is connected to the drain of the second NMOS tube; The drain of the third PMOS tube is connected to the drain of the third NMOS tube, the drain of the fifth PMOS tube, and the first end of the second resistor, and is also connected to the first end of the crystal oscillator; The second end of the second resistor is connected to the gate of the third NMOS tube, and is also connected to the second end of the crystal oscillator; The drain of the fourth PMOS tube is connected to the source of the fifth PMOS tube, the gate of the fifth PMOS tube is connected to the DET control signal, and the drain of the fifth PMOS tube is connected to the drain of the third PMOS tube; The gate of the first NMOS tube is connected to the drain of the first PMOS tube, and the drain of the first NMOS tube is connected to the gate of the second NMOS tube; The first end of the first switch is connected to a power supply, the second end of the first switch is connected to the first end of the second switch, the second end of the second switch is grounded through the third resistor, and the second end of the second switch outputs a DET control signal; A first end of the capacitor is connected to a first end of the first switch, and a second end of the capacitor is grounded.

2. The crystal oscillator driving circuit according to claim 1, characterized in that: The width-to-length ratio of the second NMOS transistor is N times the width-to-length ratio of the first NMOS transistor, where N is a positive integer.

3. The crystal oscillator driving circuit according to claim 1, characterized in that: It also includes an operational amplifier, wherein the first input terminal of the operational amplifier is connected to the first terminal of the crystal oscillator, the second input terminal is connected to the second terminal of the crystal oscillator, the first output terminal outputs a positive clock signal, and the second output terminal outputs a reverse clock signal.

4. The crystal oscillator driving circuit according to claim 3, characterized in that: The first switch is controlled by the positive clock signal, and the second switch is controlled by the negative clock signal.

5. The crystal oscillator driving circuit according to claim 1, characterized in that: The first switch, the second switch and the capacitor form a switched capacitor, and the equivalent resistance of the switched capacitor is: Req=1 / (C*F), where C is the capacitance, F is the crystal oscillator frequency, and Req is the equivalent resistance.

6. The crystal oscillator driving circuit according to claim 5, characterized in that: The resistance of the third resistor is 9 to 11 times the equivalent resistance of the switch capacitor.

7. The crystal oscillator driving circuit according to claim 5, characterized in that: Before the crystal oscillator starts oscillating, the switch capacitor does not work.

8. The crystal oscillator driving circuit according to claim 1, characterized in that: Before the crystal oscillator starts oscillating, the DET control signal is at a low level, the fifth PMOS tube is turned on, and the current flowing through the third NMOS tube is the sum of the currents flowing through the third PMOS tube and the fourth PMOS tube.

9. The crystal oscillator driving circuit according to claim 5, characterized in that: After the crystal oscillator starts oscillating, the switch capacitor operates.

10. The crystal oscillator driving circuit according to claim 9, characterized in that: After the switch capacitor works, the DET control signal is at a high level, the fifth PMOS tube is turned off, and the current flowing through the third NMOS tube is the current flowing through the third PMOS tube.