High-frequency data transmission method and device and semiconductor test equipment

Abstract

The invention discloses a high-frequency data transmission method and device and semiconductor testing equipment, and relates to the technical field of semiconductor testing, and the high-frequency data transmission method comprises the steps: obtaining a to-be-switched target transmission rate; therefore, on the basis of the target transmission rate, a frequency division number used for indicating the number of repetitions of each bit in the initial parallel data to be sent is determined; according to the embodiment of the invention, the frequency division number is determined according to the target transmission rate to be switched, the frequency division number is determined according to the target transmission rate to be switched, and then the initial parallel data is processed based on the frequency division number to obtain frequency division parallel data, and the frequency division parallel data is new parallel data obtained after each bit in the initial parallel data is repeated according to the frequency division number. And the initial parallel data is recoded through the frequency division number, so that the data transmission rate is influenced, the purpose of switching the transmission rate is achieved, and the non-delay switching of the target transmission rate is realized.

Description

Technical Field

[0001] The present application relates to the field of semiconductor testing technology, and in particular to a high-frequency data transmission method, device and semiconductor testing equipment. Background Art

[0002] In the field of semiconductor testing, as the functions of electronic components, circuit boards, integrated circuits, etc. become more and more complex and the data transmission rate requirements become higher and higher, equipment that can process high-speed signals is needed to conduct effective testing. Semiconductor testing equipment meets this demand with the help of high-speed transceivers. High-speed transceivers are the key factor for semiconductor testing equipment to meet high-speed testing requirements. They can provide faster transmission speeds for high-speed processing and exchange of large amounts of data to meet the needs of various scenarios.

[0003] In the related art, high-speed transceivers usually adjust the transmission data clock frequency to switch the transmission data transmission rate; in the above-mentioned process of adjusting the clock frequency, when adjusting from the first clock frequency to the second clock frequency, it takes a period of time to reach a stable clock state. However, during the period of waiting for the clock to stabilize, the transmission data sent by the high-speed transceiver will be erroneous or lost. Summary of the invention

[0004] The present application provides a high-frequency data transmission method, device and semiconductor testing equipment, which can solve the technical problem of data error or loss in the process of switching the transmission rate of the transmission data by adjusting the transmission data clock frequency.

[0005] In a first aspect, a high-frequency data transmission method is provided, comprising: obtaining a target transmission rate to be switched; determining a frequency division number based on the target transmission rate, the frequency division number being used to indicate the number of repetitions of each bit in initial parallel data to be sent; processing the initial parallel data based on the frequency division number to obtain frequency-divided parallel data, the frequency-divided parallel data being new parallel data obtained by repeating each bit in the initial parallel data according to the frequency division number; and sending the frequency-divided parallel data.

[0006] The method determines the frequency division number used to indicate the number of repetitions of each bit in the initial parallel data to be sent through the target transmission rate to be switched, and then obtains the frequency division parallel data for transmission after repeating each bit in the initial parallel data through the frequency division number, thereby achieving the switching of the transmission data to the target transmission rate without delay.

[0007] In a possible implementation, processing the initial parallel data based on the frequency division number to obtain the frequency division parallel data includes:

[0008] Based on a preset processing strategy, the frequency-divided parallel data corresponding to the initial parallel data is determined, and the preset processing strategy is used to repeatedly process each bit in the initial parallel data according to the frequency-divided number.

[0009] In a possible implementation, processing the initial parallel data based on the frequency division number to obtain the frequency division parallel data includes:

[0010] If the frequency division number is smaller than the data bit width of the initial parallel data, determining the frequency division parallel data corresponding to the initial parallel data based on a preset lookup table group, wherein the lookup table in the preset lookup table group is determined by the data bit width and the frequency division number of the initial parallel data;

[0011] If the frequency division number is greater than or equal to the data bit width of the initial parallel data, the initial parallel data is processed based on a preset frequency division strategy to obtain frequency division parallel data. The preset frequency division strategy is used to repeatedly process each bit in the initial parallel data by the frequency division number.

[0012] The frequency division number is compared with the data bit width. If the frequency division number is less than the data bit width, the corresponding frequency division parallel data is determined by a table lookup method. If the frequency division number is greater than or equal to the data bit width, each bit in the initial parallel data is repeatedly processed by a preset frequency division strategy to obtain the frequency division parallel data. Among them, the frequency division number is compared with the data bit width to perform classification processing, thereby reducing the redundancy of data processing when the frequency division number is less than the data bit width and improving the efficiency of processing the initial parallel data.

[0013] In a possible implementation, based on a preset frequency division strategy, initial parallel data is processed to obtain frequency division parallel data, including:

[0014] Obtain the number of clocks, which is used to indicate the number of clocks required to transmit the divided parallel data; in each processing cycle corresponding to the number of clocks, determine the data segment corresponding to the processing cycle according to the number of operations required to send the corresponding bit in the initial parallel data, wherein the number of operations is determined by the division number and the operation factor required for each bit to be repeated; determine the divided parallel data based on the data segment corresponding to each processing cycle.

[0015] By using the number of clocks required to transmit the divided-frequency parallel data, each bit in the initial parallel data is processed in turn to obtain each data segment, which is then integrated into the divided-frequency parallel data. The processing cycles corresponding to each clock number are processed in turn, so that the initial parallel data can be processed and sent at the same time. There is no need to wait for the entire initial parallel data to be processed before sending, which improves the real-time and efficiency of data transmission.

[0016] In a possible implementation, the operation factor is calculated using the following formula:

[0017] A i=(N%X)×(i-1))%X, i∈[1,N]

[0018] In the formula, A i is the operation factor of the i-th cycle, N is the frequency division number, X is the data bit width of the initial parallel data, and % is the modulo operator.

[0019] In a possible implementation, the method further includes: acquiring a status signal, the status signal effectively indicating whether the next group of first parallel data is ready to be processed, the initial parallel data including the first parallel data; and re-assigning the clock quantity if the status signal is valid.

[0020] By introducing status signals, the processing and transmission processes of different initial parallel data can be carried out in an orderly and efficient manner, reducing errors, conflicts or inefficiencies that may be caused by blindly starting to process new data without preparation. The status signals provide coordination and synchronization, so that each link can work closely together and smoothly advance the processing of parallel data according to the predetermined process and rhythm.

[0021] In a possible implementation, the method further includes: performing serial conversion processing on the divided parallel data to obtain target serial data, wherein a transmission rate of the target serial data is the same as a transmission rate of the divided parallel data; sending the target serial data so that a receiving end receives the target serial data at a target transmission rate to obtain initial serial data, wherein the initial serial data is serial data corresponding to the initial parallel data.

[0022] In a possible implementation, determining the frequency division number based on the target transmission rate includes: acquiring an initial transmission rate, which is the transmission rate of the frequency-divided parallel data; and determining the frequency division number based on a ratio of the initial transmission rate to the target transmission rate.

[0023] The frequency division number is determined by the ratio of the initial transmission rate to the target transmission rate, so that the frequency-divided parallel data determined by the frequency division number can be switched to the target transmission rate without delay during the transmission process.

[0024] In a second aspect, a data transmission device is provided, comprising a processor and a memory, wherein the memory is used to store a computer program, and the processor is used to call and run the computer program from the memory, so that the data transmission device executes any one of the high-frequency data transmission methods in the first aspect; the device can be a semiconductor test board or a chip in a semiconductor test board.

[0025] According to a third aspect, a semiconductor testing device is provided, comprising a processor. When the processor executes an instruction, the processor executes any one of the high-frequency data transmission methods according to the first aspect.

[0026] In a fourth aspect, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores a computer program code, and when the computer program code is executed by a data transmission device, the data transmission device executes any one of the high-frequency data transmission methods in the first aspect.

[0027] In a fifth aspect, a computer program product is provided, the computer program product comprising: a computer program code, when the computer program code is executed by a data transmission device, the data transmission device executes any one of the high-frequency data transmission methods in the first aspect.

[0028] It can be understood that the beneficial effects of the above-mentioned second to fifty-four aspects can be found in the relevant description of the above-mentioned first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is a flow chart of a high-frequency data transmission method provided by an embodiment of the present application;

[0030] Figure 2 is a flowchart of another high-frequency data transmission method provided in an embodiment of the present application;

[0031] Figure 3 is a flowchart of initial parallel data processing in the high-frequency data transmission method provided in an embodiment of the present application;

[0032] Figure 4 It is a preset lookup table group in the embodiment of the present application;

[0033] Figure 5 is another flowchart of initial parallel data processing in the high-frequency data transmission method provided in an embodiment of the present application;

[0034] Figure 6 is a schematic diagram of the structure of a high-speed transceiver provided in an embodiment of the present application;

[0035] Figure 7 is a flow chart of frequency division processing in a high-frequency data transmission method provided in an embodiment of the present application;

[0036] Figure 8 To pass Figure 7 Schematic diagram of the frequency division parallel number obtained by the process;

[0037] Fig. 9 is a schematic diagram of frequency-divided parallel data obtained by the high-frequency data transmission method provided by an embodiment of the present application;

[0038] Fig.10 A schematic structural diagram of a semiconductor testing device provided by the present application is shown. DETAILED DESCRIPTION

[0039] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. In the description of the embodiments of the present application, unless otherwise specified, " / " means or, for example, A / B can mean A or B; "and / or" in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships, for example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, in the description of the embodiments of the present application, "multiple" means two or more than two.

[0040] In the following, the terms "first", "second", and "third" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first", "second", and "third" may explicitly or implicitly include one or more of the features.

[0041] For the purpose of illustration rather than limitation, specific details such as specific system structures, technologies, etc. are provided to provide a thorough understanding of the embodiments of the present application. However, it should be clear to those skilled in the art that the present application may also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present application.

[0042] For ease of understanding, some concepts involved in the embodiments of the present application are introduced and explained below:

[0043] High-speed transceiver: refers to an electronic device used for high-speed data transmission in semiconductor test equipment or semiconductor test boards. High-speed transceiver is a key component for achieving high-speed data transmission. It can provide faster transmission speeds for high-speed processing and exchange of large amounts of data to meet the needs of various scenarios. Its main function is to convert parallel data into serial data and transmit it in a high-speed serial link.

[0044] Bit: Also known as "bit", it is the smallest unit of computer information, abbreviated as bit, which is the abbreviation of binary digit, referring to one bit in binary.

[0045] Data bit width: It is a characteristic of the transmission interface and an important parameter for data transmission.

[0046] In parallel data transmission, the data bit width refers to the number of data bits transmitted in parallel at one time, that is, multiple data are transmitted at the same time. For example, common data bit widths are 8 bits, 16 bits, and 32 bits; this allows a large amount of data to be transmitted at the same time, and the data transmission rate is high. In serial data transmission, the data bit width is usually 1 bit, and the data is usually transmitted one bit at a time in sequence.

[0047] Number of clocks: refers to the number of clocks used to send parallel data.

[0048] In the field of semiconductor testing, as the functions of electronic components, circuit boards, integrated circuits, etc. become more and more complex and the data transmission rate requirements become higher and higher, equipment that can process high-speed signals is needed to conduct effective testing. Semiconductor testing equipment meets this demand with the help of high-speed transceivers. High-speed transceivers are the key factor for semiconductor testing equipment to meet high-speed testing requirements. They can provide faster transmission speeds for high-speed processing and exchange of large amounts of data to meet the needs of various scenarios.

[0049] In the related art, high-speed transceivers usually adjust the transmission data clock frequency to switch the transmission data transmission rate; in the above-mentioned process of adjusting the clock frequency, when adjusting from the first clock frequency to the second clock frequency, it takes a period of time to reach a stable clock state. However, during the period of waiting for the clock to stabilize, the transmission data sent by the high-speed transceiver will be erroneous or lost.

[0050] In order to solve the above problems, the embodiments of the present application provide a high-frequency data transmission method, device and semiconductor testing equipment. The high-frequency data transmission method first obtains the target transmission rate to be switched; based on the target transmission rate, determines the division number used to indicate the number of repetitions of each bit in the initial parallel data to be sent; then, based on the division number, processes the initial parallel data to obtain divided parallel data, which is new parallel data obtained by repeating each bit in the initial parallel data according to the division number. By adjusting the number of repetitions of each bit in the initial parallel data, the divided parallel data for transmission is obtained, thereby realizing the switching of the transmission data to the target transmission rate without delay.

[0051] Combine the following Figures 1 to 5 The high-frequency data transmission method provided in an embodiment of the present application is described in detail.

[0052] Figure 1 : is a flow chart of a high-frequency data transmission method provided by an embodiment of the present application. Figure 1 As shown, the embodiment of the present application proposes a high-frequency data transmission method, comprising the following steps:

[0053] S110: Obtain a target transmission rate to be switched.

[0054] During the data transmission process, the transmission rate requirement for the transmitted data is dynamic. In actual application scenarios, it is necessary to convert or adjust to a specific transmission rate to achieve a change in the transmission rate.

[0055] It should be understood that the transmission data is the data transmitted between the sending end and the receiving end, wherein the sending end is the source of data transmission, which can encode, process, etc. the information to be transmitted, and send the data through a specific transmission channel or line, wherein the transmission mode of the transmission channel or line includes parallel transmission, serial transmission, simplex transmission, duplex transmission, etc.

[0056] The target transmission rate to be switched is a transmission rate determined by adjusting according to the needs of the receiving end, that is, the target transmission rate is the transmission rate expected by the receiving end, and the receiving end switches the target transmission rate according to the needs of the actual application.

[0057] For example, for the transmission data {p0, p1, p2, p3, p4, p5, p6, p7, p8, p9, p10, p11, p12, p13, p14, p15}, the receiving end expects to receive {p0~p7} at a transmission rate of R1 and {p8~P15} at a transmission rate of R2; that is, for {p0~p7} in the transmission data, the corresponding target transmission data is R1, and for {p8~P15} in the transmission data, the corresponding target transmission rate is R2.

[0058] The target transmission rate may be a rate preset in advance at the sending end according to the needs of the receiving end, or may be a rate obtained by the sending end from the receiving end during data transmission between the sending end and the receiving end.

[0059] S120: Determine the frequency division number based on the target transmission rate.

[0060] Among them, the frequency division number is used to indicate the number of repetitions of each bit in the initial parallel data to be sent; that is, the frequency division number determines the number of times each bit in the initial parallel data will be repeated when it is actually sent, and then, the demand for transmission rate switching is met by repeatedly encoding the initial parallel data.

[0061] It should be understood that the frequency division number is a positive integer.

[0062] For example, if the frequency division number is 2, it indicates that each bit in the initial parallel data needs to be repeated twice when actually sent; if the frequency division number is 11, it indicates that each bit in the initial parallel data needs to be repeated eleven times when actually sent.

[0063] It should be understood that each bit in the initial parallel data to be sent is the data actually needed to be transmitted during the data transmission process. Even if each bit in the initial parallel data to be sent is repeated through the frequency division number indication, for the data transmission link, the data actually needed to be transmitted is still the initial parallel data.

[0064] In some embodiments, for step 120, based on the target transmission rate, the frequency division number is determined, including: first, obtaining the initial transmission rate, the initial transmission rate is the transmission rate of the divided parallel data; second, based on the ratio of the initial transmission rate and the target transmission rate, the frequency division number is determined, that is, the frequency division number = initial transmission rate / target transmission rate.

[0065] In some embodiments, if the ratio of the initial transmission rate to the target transmission rate is a positive integer, then the ratio is the frequency division number; if the ratio of the initial transmission rate to the target transmission rate is not a positive integer, the comparison value can be rounded up, i.e., down-converted, to obtain the frequency division data.

[0066] It should be understood that the high-frequency data transmission method provided in the embodiment of the present application is applied to semiconductor testing equipment. With the development of semiconductor testing technology, the amount of data generated in the testing process continues to increase. Therefore, semiconductor testing equipment, or semiconductor testing boards in semiconductor testing equipment, can be used to achieve high-speed data transmission.

[0067] It should be understood that the semiconductor testing equipment includes one or more semiconductor testing boards, so that the testing equipment can be functionally expanded according to different testing requirements.

[0068] Semiconductor test equipment is a key device used to detect the performance, function and quality of semiconductor chips or wafers in the semiconductor manufacturing process, which mainly includes automated test equipment (ATE). ATE test equipment is used to perform automated testing on electronic components, circuit boards, integrated circuits, etc. It can automatically apply test signals, collect response signals, and analyze and judge test results through pre-programmed test programs.

[0069] It should be understood that high-speed transceivers are key components for achieving high-speed data transmission in interfaces such as high-speed interfaces and Mobile Industry Processor Interface (MIPI) in semiconductor test equipment.

[0070] Taking a high-speed transceiver as an example, the high-speed transceiver converts parallel data into serial data and transmits the serial data in a high-speed serial link. To meet application requirements, in an embodiment of the present application, the transmission rate of parallel data and the transmission rate of serial data in the high-speed transceiver are the same and high-speed.

[0071] The initial transmission rate may be the transmission rate of the frequency-divided parallel data, or the transmission rate of the serial data after the frequency-divided parallel data is serially converted.

[0072] That is, the frequency division number = the transmission rate of the divided parallel data / the target transmission rate, or the frequency division number = the transmission rate of the serial data after the divided parallel data is serially converted / the target transmission rate.

[0073] The frequency division number is determined by the ratio of the initial transmission rate to the target transmission rate, so that the frequency-divided parallel data determined by the frequency division number can be switched to the target transmission rate without delay during the transmission process.

[0074] S130 . Process the initial parallel data based on the frequency division number to obtain frequency division parallel data.

[0075] The frequency-divided parallel data is new parallel data obtained by repeating each bit in the initial parallel data according to the frequency-division number.

[0076] It should be understood that the divided parallel data is determined by processing the initial parallel data based on the division number. For example, the initial parallel data is 1101001001101110, and its data bit width is 8 bits. If the division number is 2, each bit in the initial parallel data needs to be repeated twice when it is actually sent, and the resulting divided parallel data is 11110011000011000011110011111100.

[0077] In some embodiments, for step 130, the frequency-divided parallel data corresponding to the initial parallel data may be determined according to a preset processing strategy, wherein the preset processing strategy is used to indicate to repeatedly process each bit in the initial parallel data according to the frequency-divided number.

[0078] The preset processing strategy may include data sharding, data processing, data merging, etc. For example, the initial parallel data is divided into multiple subsets, different subsets are assigned to different computing nodes for data processing, and then the processed results are merged or integrated to obtain distributed parallel data.

[0079] S140, sending frequency-divided parallel data.

[0080] It should be understood that the frequency-divided parallel data is a type of data used for transmission. By transmitting the frequency-divided parallel data, the transmission rate of the initial parallel data can be switched to the target transmission rate without delay.

[0081] The high-frequency data transmission method provided in the embodiment of the present application includes: obtaining a target transmission rate to be switched; thereby, based on the target transmission rate, determining a frequency division number for indicating the number of repetitions of each bit in the initial parallel data to be sent; and then, based on the frequency division number, processing the initial parallel data to obtain frequency division parallel data, the frequency division parallel data is new parallel data obtained by repeating each bit in the initial parallel data according to the frequency division number, and by adjusting the number of repetitions of each bit in the initial parallel data, the frequency division parallel data for sending is obtained, thereby achieving the goal of switching the transmission data to the target transmission rate without delay.

[0082] The above embodiment focuses on how to perform data processing according to the target transmission rate to be switched in the high-frequency data transmission method. Figure 2 The illustrated embodiment describes in detail how to transmit frequency-divided parallel data, thereby achieving delay-free switching between different transmission rates.

[0083] Figure 2 FIG. 1 is a flowchart of another high-frequency data transmission method provided in an embodiment of the present application. Figure 2 As shown, in Figure 1 After step 140, the high-frequency data transmission method further includes the following steps:

[0084] S150, performing serial conversion processing on the frequency-divided parallel data to obtain target serial data.

[0085] It should be understood that the target serial data is serial data corresponding to the frequency-divided parallel data, wherein the serial conversion process refers to converting the parallel data into serial data, and the serial conversion process can be implemented by using a serial-to-parallel converter, a shift register, a single-chip microcomputer, etc. For example, the shift register can shift the parallel data into the register one by one, and output the data serially under the control of the clock signal. Multiple shift registers can be cascaded to achieve parallel data conversion of more bits. For many single-chip microcomputers or microcontrollers with built-in serial communication interfaces, parallel data can be converted into serial data by programming and sent out through the serial interface. The embodiment of the present application does not limit the serial conversion process.

[0086] The transmission rate of the target serial data and the transmission rate of the frequency-divided parallel data are the same, and both are initial transmission rates.

[0087] For example, the initial parallel data is 1101001001101110, the division number is 2, the divided parallel data is 11110011000011000011110011111100, and the transmission rate is r. After serial conversion processing, the target serial data is 11110011000011000011110011111100, and the transmission rate is still r.

[0088] S160, sending target serial data.

[0089] Through the above steps, the receiving end receives the target serial data at the target transmission rate to obtain the initial serial data, wherein the initial serial data is the serial data corresponding to the initial parallel data.

[0090] Wherein, target transmission rate = initial transmission rate / frequency division number.

[0091] That is, the target transmission rate = the target transmission rate of serial data / the frequency division number, or the target transmission rate = the transmission rate of divided parallel data / the frequency division number.

[0092] Therefore, the actually received data is the initial serial data, which is the serial data corresponding to the initial parallel data.

[0093] For example, the new target transmission rate to be switched is r / 3, the initial parallel data is 1101001001101110, the division number is 2, and the divided parallel data is 11110011000011000011110011111100. After serial conversion processing, the target serial data is obtained, that is, 1111001100001100001111001111100, and the transmission rate sent is r. The receiving end can receive the initial serial data 1101001001101110 at the target transmission rate r / 2.

[0094] Furthermore, the target transmission rate to be switched is obtained again as r / 3, and the corresponding frequency division number is 3. For the initial parallel data 0110111011010010 used for further data transmission, the frequency division number is 3, and the divided parallel data obtained is 000111111000111111111110001111110001110000000111000. Further, the target serial data is obtained, that is, 000111111000111111111110001111110001110000000111000, and the transmission rate sent is still r. The receiving end can receive the initial serial data 0110111011010010 at the target transmission rate r / 3.

[0095] In an embodiment of the present application, the transmission rate of the divided parallel data before and after the serial conversion process and the transmission rate of the target serial data are the same and high-speed, wherein the transmission rate of the divided parallel data is determined by multiplying the parallel transmission clock frequency and the data bit width of the divided parallel data; the transmission rate of the target serial data is determined by multiplying the serial transmission clock frequency, the first coefficient and the data bit width of the target serial data.

[0096] It should be understood that for the parallel interface that transmits divided parallel data and the serial interface that transmits the target serial data, there is also a correlation between the actual transmission rates of each transmission interface, and the actual transmission rate of the serial interface is determined by multiplying the actual transmission rate of the parallel interface, the first coefficient and the data bit width of the parallel interface.

[0097] The first coefficient is determined by the triggering mode of the clock in serial transmission. If the triggering mode of the clock is double-edge driving, the first coefficient is 2; if the triggering mode of the clock is single-edge driving, the first coefficient is 1.

[0098] It should be understood that the actual transmission rate of the serial interface and the transmission rate of the serial data are the same.

[0099] It should also be understood that the data bit width of the parallel interface and the data bit width of the parallel data are the same. For the parallel interface, the data bit width is an interface characteristic, and for the parallel data, the data bit width is an important parameter for parallel data transmission.

[0100] Taking the case where the data bit width of parallel transmission is 8 bits and the data bit width of serial transmission is 1 bit as an example, the transmission rate of the divided parallel data = parallel transmission clock frequency × 8.

[0101] If the trigger mode of serial transmission is double-edge drive, the transmission rate of the target serial data = serial transmission clock frequency × 2 × 1. At this time, in order to achieve the same transmission rate of the divided parallel data and the target serial data, the serial transmission clock frequency is 4 times the parallel transmission clock frequency.

[0102] Since the transmission rate of the target serial data is the same as the actual transmission rate of the serial interface, the actual transmission rate of the parallel interface=actual transmission rate of the serial interface / 8 / 2.

[0103] If the trigger mode of serial transmission is single-edge drive, the transmission rate of the target serial data = serial transmission clock frequency × 1 × 1. At this time, in order to achieve the same transmission rate of the divided parallel data and the target serial data, the serial transmission clock frequency is 8 times the parallel transmission clock frequency.

[0104] Since the transmission rate of the target serial data is the same as the actual transmission rate of the serial interface, the actual transmission rate of the parallel interface=actual transmission rate of the serial interface / 8 / 1.

[0105] Through the above steps, the receiving end can receive the target serial data at the target transmission rate, and the data actually received is the initial serial data that is the same as the initial parallel data; that is, by re-encoding the initial parallel data in the above high-frequency data transmission method, the data transmission rate is affected, thereby achieving the purpose of switching the transmission rate; the target transmission rate is switched without delay, and there will be no data loss or error during the switching of the target transmission rate.

[0106] The above embodiment focuses on how to affect the data transmission rate by re-encoding the initial parallel data in the high-frequency data transmission method to achieve the non-delay switching transmission rate. Figure 3 The illustrated embodiment describes in detail how to process the initial parallel data based on the frequency division number.

[0107] Figure 3 FIG. 1 is a flowchart of initial parallel data processing in the high-frequency data transmission method provided in an embodiment of the present application. Figure 3 As shown, the initial parallel data processing includes the following steps:

[0108] S210 , comparing the frequency division number and the data bit width of the initial parallel data.

[0109] If the frequency division number is smaller than the data bit width of the initial parallel data, S220 , based on a preset lookup table group, determine the frequency division parallel data corresponding to the initial parallel data.

[0110] Among them, the lookup table in the preset lookup table group is determined by the data bit width and the frequency division number of the initial parallel data, and the number of lookup tables is determined by the data bit width of the initial parallel data. It should be understood that the data bit width of the frequency division parallel data is the same as the data bit width of the initial parallel data.

[0111] For example, if the data bit width of the initial parallel data is 8 bits, the preset lookup table group has 7 lookup tables, corresponding to the frequency-divided parallel data with any frequency-division number from 1 to 7; if the data bit width of the initial parallel data is 32 bits, the preset lookup table group has 31 lookup tables, corresponding to the frequency-divided parallel data with any frequency-division number from 1 to 31.

[0112] Figure 4 is a preset lookup table group in the embodiment of the present application, such as Figure 4 As shown, the preset lookup table group is a table group corresponding to the data bit width of the initial parallel data being 8 bits, including the frequency-divided parallel data obtained by the corresponding frequency-division processing process when the frequency-division number is 1, 2, 3, 4, 5, 6, and 7.

[0113] It should be understood that when the frequency division number is smaller than the data bit width of the initial parallel data within a limited range, the table lookup is simple, fast, and occupies less resources. If the frequency division number is smaller than the data bit width of the initial parallel data, the above-mentioned preset processing strategy is also used. When each bit in the initial parallel data is repeatedly processed by the frequency division number, the corresponding algorithm is too redundant, resulting in low data processing efficiency. Therefore, for this part, the table lookup method is used to improve the efficiency of data processing and reduce resource usage.

[0114] If the frequency division number is greater than or equal to the data bit width of the initial parallel data, S230 , based on a preset frequency division strategy, the initial parallel data is processed to obtain frequency divided parallel data.

[0115] Among them, the preset frequency division strategy is used to repeatedly process each bit in the initial parallel data through the frequency division number. It should be understood that the preset frequency division strategy is a strategy for processing data with a frequency division number greater than or equal to the data bit width of the initial parallel data. That is to say, in the preset frequency division strategy, the frequency division number is greater than or equal to the data bit width of the initial parallel data.

[0116] For example, if the data bit width of the initial parallel data is 8 bits and the frequency division number is 8, 9, or 11, the above step 230 is executed.

[0117] In some embodiments, step 230 may also be performed by the following steps:

[0118] First, get the number of clocks.

[0119] The number of clocks is used to indicate the number of clocks required to transmit the divided parallel data.

[0120] It should be understood that the number of clocks is determined by the frequency division number. For example, if the data bit width of the initial parallel data is 8 bits and the frequency division number is 9, the number of clocks is 9.

[0121] Secondly, in each processing cycle corresponding to the number of clocks, the data segment corresponding to the processing cycle is determined according to the number of operations that need to be sent for the corresponding bit in the initial parallel data.

[0122] The data segment is a group of data corresponding to the data bit width; that is, corresponding to each processing cycle, a group of data corresponding to the data bit width, namely, the data segment, can be processed.

[0123] It should be understood that each processing cycle is determined according to the number of clocks. For example, if the number of clocks is 9, the corresponding processing cycles include the first processing cycle to the ninth processing cycle.

[0124] The number of operations is determined by the frequency division number and the operation factor required for each bit repetition; the operation factor is calculated by the following formula:

[0125] Ai =(N%X)×(i-1))%X, i∈[1,N]

[0126] In the formula, A i is the operation factor of the i-th processing cycle, N is the frequency division number, X is the data bit width of the initial parallel data, and % is the modulo operator.

[0127] The number of operations is calculated using the following formula:

[0128] C i =N+A i , i∈[1,N]

[0129] In the formula, C i is the number of operations in the i-th processing cycle, A i is the operation factor of the i-th processing cycle, and N is the frequency division number.

[0130] It should be understood that after each processing cycle ends, the value corresponding to the number of clocks decreases by 1. By determining the value corresponding to the number of clocks, it can be confirmed whether the processing of the initial parallel data has been completed.

[0131] Furthermore, based on the number of operations corresponding to each processing cycle, a data segment corresponding to the processing cycle is determined, and the data segment is a part of the frequency-divided parallel data.

[0132] In some embodiments, the following process needs to be performed:

[0133] First, a state signal is obtained, the state signal effectively represents whether the next group of first parallel data is ready to be processed, and the initial parallel data includes the first parallel data. It should be understood that the state signal has two states, the first state represents that the state is valid, and the second state represents that the state is invalid.

[0134] For example, a status signal pulled high (ie, the status signal is at a high level) indicates that the status is valid; a status signal pulled low (ie, the status signal is at a low level) indicates that the status is invalid.

[0135] Secondly, if the status signal is valid, the clock quantity is reassigned.

[0136] By introducing status signals, the processing and transmission processes of different initial parallel data can be carried out in an orderly and efficient manner, reducing errors, conflicts or inefficiencies that may be caused by blindly starting to process new data without preparation. The status signals provide coordination and synchronization, so that each link can work closely together and smoothly advance the processing of parallel data according to the predetermined process and rhythm.

[0137] In some embodiments, the following process needs to be performed:

[0138] First, obtain a data valid signal, which is used to indicate whether the initial parallel data is valid data.

[0139] If the data valid signal indicates that the first parallel data is valid and the status signal indicates readiness to process the first parallel data, then perform frequency division processing on the initial parallel data, that is, execute step 230 to process the initial parallel data based on a preset frequency division strategy to obtain frequency-divided parallel data.

[0140] By introducing the data valid signal, the accuracy of the data processing process is improved.

[0141] Finally, determine the frequency-divided parallel data based on the data segments corresponding to each processing cycle.

[0142] That is to say, the frequency-divided parallel data is composed of the data segments corresponding to each processing cycle.

[0143] Through the above algorithm, when the frequency division number is greater than or equal to the data bit width of the initial parallel data, the initial parallel data can be processed based on a preset frequency division strategy to obtain frequency-divided parallel data.

[0144] By comparing the frequency division number with the data bit width, the initial parallel data is classified and processed, and through the above method, the initial parallel data can be processed and sent simultaneously, without waiting for the entire initial parallel data to be processed before performing the sending operation, improving the real-time performance and efficiency of data transmission.

[0145] Figure 5 It is another flowchart for processing initial parallel data in the high-frequency data transmission method provided by the embodiments of the present application. As Figure 5 shown, the frequency division number is N, which is a positive integer, and the data bit width of the initial parallel data is X.

[0146] S310. Determine whether N < X is satisfied.

[0147] If N < X is satisfied, in S320, perform frequency division processing on the initial parallel data by looking up a table to obtain frequency-divided parallel data. Among them, the preset lookup table group includes X - 1 lookup tables, and look up the table with N as the index.

[0148] For example, if the data bit width X of the parallel data is 8, then 7 lookup tables are constructed, namely Table 1-1 corresponding to the frequency division number of 1, Table 1-2 corresponding to the frequency division number of 2, Table 1-3 corresponding to the frequency division number of 3, Table 1-4 corresponding to the frequency division number of 4, Table 1-5 corresponding to the frequency division number of 5, Table 1-6 corresponding to the frequency division number of 6, and Table 1-7 corresponding to the frequency division number of 7.

[0149] If the frequency division number N = 5, perform table index lookup of the lookup table through the frequency division number 5 to obtain the following Table 1-5, and obtain the frequency-divided parallel data corresponding to the frequency division number of 5.

[0150] Table 1-5 Frequency Division Parallel Data Corresponding to a Frequency Division of 5

[0151]

[0152]

[0153] If N < X is not satisfied, that is, N ≥ X, the following process is executed:

[0154] S330. Determine whether data frequency division processing is ready.

[0155] It should be understood that determining whether data frequency division processing is ready includes determining through a status signal and a data valid signal. If the status signal is pulled high and the data valid signal is pulled high, the initial parallel data is transmitted, and then the initial parallel data can be frequency divided. If the status signal is pulled low or the data valid signal is pulled low, the initial parallel data is not transmitted, and thus frequency division processing cannot be performed.

[0156] During the transmission of a set of initial parallel data, the number of clocks decreases from the initial value N to 1, and the frequency division processing of this set of initial parallel data ends.

[0157] Determining whether data frequency division processing is ready also includes determining whether the number of clocks is less than or equal to 1. If the number of clocks is less than or equal to 1, the number of clocks is re-assigned through a sub-commentary, and the status signal is pulled low to prepare for processing the first parallel data of the next group.

[0158] S340. Determine the corresponding data segment according to the number of operations to be performed on the corresponding bits in the initial parallel data, and the number of clocks decreases to 1.

[0159] S350. Determine whether the number of operations is less than or equal to the data bit width. If the number of operations is less than or equal to the data bit width, execute step 340.

[0160] S360. Determine whether the number of clocks is less than or equal to 1. If the number of clocks is less than or equal to 1, execute step 330.

[0161] The application scenario of the embodiment of the present application is briefly described below.

[0162] The above high-frequency data transmission method is applied to semiconductor test equipment and can be applied to semiconductor test boards in semiconductor test equipment. Among them, the high-speed transceiver includes a frequency division processing module and a transmission module. The frequency division processing module is used to perform frequency division processing on the initial parallel data to obtain frequency division parallel data, and the transmission module is used to perform serial conversion processing on the frequency division parallel data.

[0163] The frequency division processing module and the transmission module may be implemented by a Field Programmable Gate Array (FPGA), or may be implemented by a chip with parallel data processing capability, such as an Application Specific Integrated Circuit (ASIC).

[0164] Taking high-speed transceivers as an example, Figure 6 is a schematic diagram of the structure of a high-speed transceiver provided in an embodiment of the present application, such as Figure 6 As shown, the high-speed transceiver 400 includes an acquisition module 410 , a frequency division processing module 420 and a transmission module 430 .

[0165] The acquisition module 410 is used to acquire the target transmission rate to be switched; and to determine the frequency division number based on the target transmission rate, where the frequency division number is used to indicate the number of repetitions of each bit in the initial parallel data to be sent.

[0166] The frequency division processing module 420 is used to process the initial parallel data based on the frequency division number to obtain the frequency division parallel data, which is the new parallel data obtained by repeating each bit in the initial parallel data according to the frequency division number; and send the frequency division parallel data.

[0167] The transmission module 430 is used to perform serial conversion processing on the divided parallel data to obtain target serial data, wherein the transmission rate of the target serial data is the same as the transmission rate of the divided parallel data; it is also used to send the target serial data so that the receiving end receives the target serial data at the target transmission rate to obtain initial serial data, which is serial data corresponding to the initial parallel data.

[0168] In the application scenario where the data width of the initial parallel data is 8 bits, Figure 7 is a flowchart of frequency division processing in the high-frequency data transmission method provided in an embodiment of the present application, Figure 7 As shown, when N ≥ 8, it can be divided into 9 processes, READY, STEP1, STEP2, STEP3, STEP4, STEP5, STEP6, STEP7, STEP8.

[0169] READY, when the number of clocks is less than or equal to 1, the number of clocks is reassigned to N, the module is ready to work signal (ie, status signal) is pulled high, and the frequency division processing is ready to receive the next set of data.

[0170] STEP1, when C1=N+A1 is less than or equal to 8, jump to the next process STEP2, where A1=(N%8)×0)%8, otherwise C1 decreases by 8 in each processing cycle.

[0171] STEP2, when C2=N+A2 is less than or equal to 8, jump to the next process STEP3, where A2=(N%8)×1)%8, otherwise C2 decreases by 8 in each processing cycle.

[0172] STEP3, when C3=N+A3 is less than or equal to 8, jump to the next process STEP4, where A3=(N%8)×2)%8, otherwise C3 decreases by 8 in each processing cycle.

[0173] STEP4, when C4=N+A4 is less than or equal to 8, jump to the next process STEP5, where A4=(N%8)×3)%8, otherwise C4 decreases by 8 in each processing cycle.

[0174] STEP5, when C5=N+A5 is less than or equal to 8, jump to the next process STEP6, where A5=(N%8)×4)%8, otherwise C5 decreases by 8 in each processing cycle.

[0175] STEP6, when C6=N+A6 is less than or equal to 8, jump to the next process STEP7, where A6=(N%8)×5)%8, otherwise C6 decreases by 8 in each processing cycle.

[0176] STEP7, when C7=N+A7 is less than or equal to 8, jump to the next process STEP8, where A7=(N%8)×6)%8, otherwise C7 decreases by 8 in each processing cycle.

[0177] STEP8, when C8=N+A8 is equal to 8, jump to the next process READY, where A8=(N%8)×7)%8, otherwise C8 decreases by 8 in each processing cycle.

[0178] Figure 8 To pass Figure 7 The schematic diagram of the frequency division parallel number obtained by the process is as follows: Figure 8 As shown, C1 to C8 can be determined in the READY flow of the frequency division process, which is convenient for direct reference in subsequent processes.

[0179] Taking the initial parallel data {p0, p1, p2, p3, p4, p5, p6, p7, p8, p9, p10, p11, p12, p13, p14, p15} as an example, the frequency division number is 9 obtained by the target transmission rate R1 that the receiving end expects to receive {p0-p7}, and the frequency division number is 11 obtained by the target transmission rate R2 of {p8-P15}. Fig. 9 is a schematic diagram of frequency-divided parallel data obtained by the high-frequency data transmission method provided by an embodiment of the present application, such as Fig. 9As shown, the data bit width of the initial parallel data is 8 bits, and the target transmission rate to be switched for the first time is R1, and the target transmission rate to be switched for the second time is R2. For the target transmission rate to be switched for the second time, the frequency division number is 11, and the corresponding frequency division processing process is as follows:

[0180] In the first processing cycle, the number of clocks = 11, C1 = 11 + 0 = 11;

[0181] In the second processing cycle, the number of clocks = 10, C1 = 11-8 = 3 (less than or equal to 8), C2 = 11+3 = 14;

[0182] In the third processing cycle, the number of clocks = 9, C2 = 14-8 = 6 (less than or equal to 8), C3 = 11 + 6 = 17;

[0183] 4th processing cycle, number of clocks = 8, C3 = 17-8 = 9;

[0184] In the fifth processing cycle, the number of clocks = 7, C3 = 9-8 = 1 (less than or equal to 8), C4 = 11+1 = 12;

[0185] In the sixth processing cycle, the number of clocks = 6, C4 = 12-8 = 4 (less than or equal to 8), C5 = 11+4 = 15;

[0186] In the 7th processing cycle, the number of clocks = 5, C5 = 15-8 = 7 (less than or equal to 8), C6 = 11+7 = 18;

[0187] In the 8th processing cycle, the number of clocks = 4, C6 = 18-8 = 10;

[0188] In the 9th processing cycle, the number of clocks = 3, C6 = 10-8 = 2 (less than or equal to 8), C7 = 11 + 2 = 13;

[0189] In the 10th processing cycle, the number of clocks = 2, C7 = 13-8 = 5 (less than or equal to 8), C8 = 11+5 = 16;

[0190] In the 11th processing cycle, the number of clocks = 1, C8 = 16-8 = 8 (less than or equal to 8), and the status signal is pulled high.

[0191] It should be understood that the above is an example of an application scenario and does not limit the application scenario of the present application.

[0192] It should be understood that the above examples are intended to help those skilled in the art understand the embodiments of the present application, rather than to limit the embodiments of the present application to the specific numerical values ​​or specific scenarios illustrated. Those skilled in the art can obviously make various equivalent modifications or changes based on the above examples, and such modifications or changes also fall within the scope of the embodiments of the present application.

[0193] The embodiment of the present application realizes the switching of different rates of high-speed interface by repeating data, which solves the problem that the traditional switching of different interface rates requires delay time because of clock stabilization, and realizes the delay-free switching of different interface rates.

[0194] Combination of the above Figures 1 to 5 , describes in detail the high-frequency data transmission method of the embodiment of the present application, and describes in detail the device embodiment of the present application below. It should be understood that the data transmission device in the embodiment of the present application can execute the various high-frequency data transmission methods of the aforementioned embodiment of the present application, that is, the specific working process of the following various products can refer to the corresponding process in the aforementioned method embodiment.

[0195] It should be understood that the data transmission device may perform Figures 1 to 5 The high-frequency data transmission method shown; the data transmission device includes a processor and a memory, the memory is used to store computer programs, and the processor is used to call and run the computer program from the memory, so that the data transmission device executes any one of the high-frequency data transmission methods in the aforementioned method embodiments; the device can be a semiconductor test board or a chip in a semiconductor test board.

[0196] It should be noted that the above data transmission device can be embodied in the form of a functional unit. The term "unit" here can be implemented in the form of software and / or hardware, and is not specifically limited to this.

[0197] For example, a "unit" may be a software program, a hardware circuit, or a combination of the two that implements the above functions. The hardware circuit may include an application specific integrated circuit (ASIC), an electronic circuit, a processor (such as a shared processor, a dedicated processor, or a group processor, etc.) and a memory for executing one or more software or firmware programs, a combined logic circuit, and / or other suitable components that support the described functions.

[0198] Therefore, the units of each example described in the embodiments of the present application can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present application.

[0199] Fig.10 A schematic structural diagram of a semiconductor testing device provided by the present application is shown. Fig.10The dotted line in indicates that the unit or the module is optional. The semiconductor testing device 500 can be used to implement the high-frequency data transmission method described in the above method embodiment.

[0200] The semiconductor test device 500 includes one or more processors 501, which can support the high-frequency data transmission method in the semiconductor test device 500 implementation method embodiment. The processor 501 can be a general-purpose processor or a special-purpose processor. For example, the processor 501 can be a central processing unit (CPU), a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, such as discrete gates, transistor logic devices or discrete hardware components.

[0201] The processor 501 can be used to control the semiconductor testing device 500, execute the software program, and process the data of the software program. The semiconductor testing device 500 can also include a communication unit 505 to realize the transmission of the initial parallel data.

[0202] For example, the semiconductor testing device 500 may be a chip having parallel data processing capability, the communication unit 505 may be an output circuit of the chip, and the chip may be used as a component of a terminal device or other semiconductor testing devices.

[0203] For another example, the semiconductor testing device 500 may be a terminal device, and the communication unit 505 may be a transceiver of the terminal device, such as a high-speed transceiver, or the communication unit 505 may be a transceiver circuit of the terminal device.

[0204] The semiconductor testing device 500 may include one or more memories 502 on which a program 504 is stored. The program 504 can be executed by the processor 501 to generate instructions 503, so that the processor 501 executes the high-frequency data transmission method described in the above method embodiment according to the instructions 503.

[0205] Optionally, data may be stored in the memory 502. Optionally, the processor 501 may read data stored in the memory 502. The data may be stored at the same storage address as the program 504, or may be stored at a different storage address than the program 504.

[0206] The processor 501 and the memory 502 may be provided separately or integrated together; for example, integrated on a system on chip (SOC) of the terminal device.

[0207] Exemplarily, the memory 502 can be used to store the related program 504 of the high-frequency data transmission method provided in the embodiment of the present application, and the processor 501 can be used to call the related program 504 of the high-frequency data transmission method stored in the memory 502 when performing image repair on the terminal device, and execute the high-frequency data transmission method of the embodiment of the present application.

[0208] The present application also provides a computer program product, which, when executed by the processor 501, implements the high-frequency data transmission method of any method embodiment of the present application.

[0209] The computer program product may be stored in the memory 502 , for example, a program 504 , which is finally converted into an executable target file that can be executed by the processor 501 after preprocessing, compiling, assembling, and linking.

[0210] The present application also provides a computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a computer, the high-frequency data transmission method of any method embodiment of the present application is implemented. The computer program can be a high-level language program or an executable target program.

[0211] The computer-readable storage medium is, for example, a memory 502. The memory 502 may be a volatile memory or a nonvolatile memory, or the memory 502 may include both a volatile memory and a nonvolatile memory. Among them, the nonvolatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM).

[0212] In this application, "at least one" means one or more, and "more" means two or more. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can be represented by: a, b, c, ab, ac, bc, or abc, where a, b, c can be single or multiple.

[0213] It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0214] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0215] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0216] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic; for example, the division of units is only a logical function division, and there may be other division methods in actual implementation; for example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0217] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0218] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0219] The above are only specific implementations of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A high-frequency data transmission method, characterized in that: Applied to semiconductor testing equipment, the method comprises: Obtain the target transmission rate to be switched; Based on the target transmission rate, determining a frequency division number, the frequency division number being used to indicate the number of repetitions of each bit in the initial parallel data to be sent; Based on the frequency division number, the initial parallel data is processed to obtain frequency division parallel data, where the frequency division parallel data is new parallel data obtained by repeating each bit in the initial parallel data according to the frequency division number; The frequency-divided parallel data is transmitted.

2. The high-frequency data transmission method according to claim 1, characterized in that: The processing of the initial parallel data based on the frequency division number to obtain the frequency division parallel data includes: The frequency-divided parallel data corresponding to the initial parallel data is determined based on a preset processing strategy, wherein the preset processing strategy is used to repeatedly process each bit in the initial parallel data according to the frequency-divided number.

3. The high-frequency data transmission method according to claim 1, characterized in that: The processing of the initial parallel data based on the frequency division number to obtain the frequency division parallel data includes: If the frequency division number is smaller than the data bit width of the initial parallel data, determining the frequency division parallel data corresponding to the initial parallel data based on a preset lookup table group, wherein the lookup table in the preset lookup table group is determined by the data bit width of the initial parallel data and the frequency division number; If the frequency division number is greater than or equal to the data bit width of the initial parallel data, the initial parallel data is processed based on a preset frequency division strategy to obtain the frequency division parallel data, and the preset frequency division strategy is used to repeatedly process each bit in the initial parallel data by the frequency division number.

4. The high-frequency data transmission method according to claim 3, characterized in that: The processing of the initial parallel data based on a preset frequency division strategy to obtain the frequency division parallel data includes: Acquire a clock quantity, where the clock quantity is used to indicate the number of clocks required to transmit the divided parallel data; In each processing cycle corresponding to the number of clocks, the data segment corresponding to the processing cycle is determined according to the number of operations required to send the corresponding bit in the initial parallel data, wherein the number of operations is determined by the frequency division number and the operation factor required for each bit repetition; The frequency-divided parallel data is determined based on the data segments corresponding to each of the processing cycles.

5. The high frequency data transmission method according to claim 4, characterized in that: The operation factor is calculated by the following formula: A i =((N%X)×(i-1))%X,i∈[1,N] In the formula, A i is the operation factor of the i-th cycle, N is the frequency division number, X is the data bit width of the initial parallel data, and % is the modulo operator.

6. The high-frequency data transmission method according to claim 4, characterized in that: The method further comprises: Acquire a status signal, where the status signal is used to indicate whether a next group of first parallel data is ready to be processed, where the initial parallel data includes the first parallel data; If the status signal is valid, the clock quantity is reassigned.

7. The high-frequency data transmission method according to claim 1, characterized in that: The method further comprises: Performing serial conversion processing on the frequency-divided parallel data to obtain target serial data, wherein a transmission rate of the target serial data is the same as a transmission rate of the frequency-divided parallel data; The target serial data is sent so that a receiving end receives the target serial data at a target transmission rate to obtain initial serial data, which is serial data corresponding to the initial parallel data.

8. The high-frequency data transmission method according to claim 1, characterized in that: The step of determining the frequency division number based on the target transmission rate includes: Acquire an initial transmission rate, where the initial transmission rate is a transmission rate of the frequency-divided parallel data; The frequency division number is determined based on a ratio of the initial transmission rate to the target transmission rate.

9. A data transmission device, characterized in that: The data transmission device includes a processor and a memory, wherein the memory is used to store a computer program, and the processor is used to call and run the computer program from the memory, so that the data transmission device executes the high-frequency data transmission method according to any one of claims 1 to 8.

10. A semiconductor testing device, characterized in that: The method comprises a processor, and when the processor executes instructions, the processor executes the high-frequency data transmission method according to any one of claims 1 to 8.

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