Trans-impedance amplifier and optical module

Abstract

The invention discloses a transimpedance amplifier and an optical module, and relates to the technical field of transimpedance amplifiers, the transimpedance amplifier comprises a front-end circuit, a multi-order filtering and voltage stabilizing circuit, a differential amplification buffer circuit and a feedback control circuit; the front-end circuit is connected with the optical detector, the multi-order filtering and voltage stabilizing circuit is connected with the differential amplification buffer circuit, and the multi-order filtering and voltage stabilizing circuit is connected with the feedback control circuit and the differential amplification buffer circuit; and the feedback control circuit is connected with the front-end circuit and is used for controlling the front-end circuit according to an external reset signal and an output signal of the multi-order filtering and voltage stabilizing circuit, so that the output signal of the front-end circuit changes along with the mutation of an input optical signal of the optical detector. According to the invention, the differential output voltage of the trans-impedance amplifier can be ensured to change along with the change of the input optical signal of the optical detector in real time, high-quality ultra-high-speed and large-dynamic-range burst signal transmission is realized, and the technical problem of quick response of a 50G PON OLT to an uplink burst optical signal is effectively solved.

Description

Technical Field

[0001] The present invention relates to the technical field of transimpedance amplifiers, and in particular to a transimpedance amplifier and an optical module. Background Art

[0002] At present, domestic operators are actively promoting the standard formulation and prototype development process of the next generation optical access network 50G PON (optical access network), and also require relevant optical module manufacturers to develop 50G PON optical modules and relevant optical / electrical chip manufacturers to develop and provide 50Gbps / 25Gbps optical chips and electrical chips that meet the requirements of the 50G PON standard. In the PON system architecture network, OLT represents the central office optical module; ONU represents the terminal optical module; Splitter represents the optical splitter; the downstream service data sent by OLT to ONU is sent in a broadcast continuous form. After each ONU receives the downstream signal through a continuous optical receiver, it determines whether the service data belongs to itself based on the paired ID; the upstream service data sent by ONU to OLT is sent in a time division multiplexing mode. During the ONU registration process, OLT will allocate a time period for sending upstream signals to each online ONU.

[0003] For the optical receiver on the 50G PON OLT side, since the uplink optical signals sent by each ONU are distinguished by different time periods, the optical signals received by the OLT are bursty in the time domain, that is, burst optical signal packets are segmented one by one, and there is a short protection period (guardtime, no data signal during this period) between adjacent burst optical signal packets. This requires that the optical signal receiver on the OLT side must have the ability to receive burst optical signal packets.

[0004] At the front end of the optical signal receiver, the detector PD (photodiode) and the transimpedance amplifier TIA (Transimpedance Amplifier) ​​are usually required to convert the input optical signal into a voltage signal. For the optical signal receiver of the OLT, a burst mode transimpedance amplifier must be used to receive the burst optical signal. However, the existing burst mode transimpedance amplifier mainly adopts an analog circuit closed-loop feedback solution, which has the following main problems: First, it does not support the transmission of burst signals with a sharp change in input current (such as from a minimum of nearly 10uA to a maximum of several mA). In this case, the burst response time is relatively long, about hundreds of ns; second, the output analog control signal changes gradually from the initial state to the stable state, which takes a long time, and in the stable state, there will be a certain range of fluctuations with the change of the input current signal. As a result, the use of existing burst mode transimpedance amplifiers in 50G PON will not only lead to a longer burst response time, which will significantly increase the PON system overhead and reduce the burst throughput of the PON system, but also it is difficult to output signals of good quality when receiving burst signals of 25Gbps and higher, and it is difficult to meet the 50G PON OLT's demand for rapid response to upstream burst optical signals. Summary of the invention

[0005] The embodiments of the present invention provide a transimpedance amplifier and an optical module to solve the following technical problems: when the existing transimpedance amplifier copes with burst optical signals with a large dynamic range at a rate of 25 Gbps or higher, the burst response time is long, the output signal fluctuates and the quality is poor, and it is difficult to meet the fast burst response requirements of the 50G PON OLT when receiving uplink burst optical signals.

[0006] In a first aspect, a transimpedance amplifier is provided, comprising: a front-end circuit, a multi-order filtering and voltage stabilization circuit, a differential amplifier buffer circuit, and a feedback control circuit;

[0007] The front-end circuit is connected to the photodetector, the multi-order filtering and voltage stabilizing circuit and the differential amplifier buffer circuit, and is used to convert the output photocurrent signal of the photodetector into an analog voltage signal;

[0008] The multi-order filtering and voltage stabilizing circuit is connected to the feedback control circuit and the differential amplifier buffer circuit, and is used to process the output signal of the front-end circuit and output a mean value signal to the feedback control circuit and the differential amplifier buffer circuit;

[0009] The feedback control circuit is connected to the front-end circuit and is used to control the front-end circuit according to an external reset signal and an output signal of the multi-order filtering and voltage stabilizing circuit, so that the output signal of the front-end circuit changes with the sudden change of the input light signal of the light detector.

[0010] In some embodiments, the front-end circuit includes a current extraction unit, a single-ended inverting amplifier, and a variable feedback resistor. The input ends of the current extraction unit and the single-ended inverting amplifier are connected to the photodetector, the output end of the single-ended inverting amplifier is connected to the multi-order filtering and voltage stabilizing circuit and the differential amplifier buffer circuit, the input end and the output end of the variable feedback resistor are connected to the output end and the input end of the single-ended inverting amplifier correspondingly, and the control end of the current extraction unit and the control end of the variable feedback resistor are connected to the feedback control circuit;

[0011] The feedback control circuit is used to control the control end of the current extraction unit and the control end of the variable feedback resistor according to the external reset signal and the output signal of the multi-order filtering and voltage stabilizing circuit, so that the output signal of the output end of the single-ended inverting amplifier changes with the sudden change of the input light signal of the light detector.

[0012] In some embodiments, the multi-order filtering and voltage stabilization circuit includes a multi-order filter and a stabilizer, the input end of the multi-order filter is connected to the output end of the single-ended inverting amplifier, the first output end of the multi-order filter is connected to the input end of the stabilizer, the second output end of the multi-order filter is connected to the input end of the feedback control circuit, and the output end of the stabilizer is connected to the differential amplifier buffer circuit.

[0013] In some embodiments, the feedback control circuit includes an analog-to-digital converter, a digital logic control circuit, a digital-to-analog converter, a load circuit, and a transimpedance gain control signal generating circuit connected in sequence;

[0014] The analog-to-digital converter is used to monitor the output signal of the multi-order filter in real time according to the external reset signal, and perform analog-to-digital conversion to obtain a multi-bit digital signal and output it to the digital logic control circuit;

[0015] The digital logic control circuit is used to process the multi-bit digital signal according to a preset logic algorithm and then output it to the digital-to-analog converter;

[0016] The digital-to-analog converter is used to perform digital-to-analog conversion on the multi-bit digital signal processed by the digital logic control circuit to obtain a corresponding analog current signal, and output it to the load circuit;

[0017] The load circuit is used to convert the analog current signal output by the digital-to-analog converter into an analog voltage signal, and output it to the control end of the current extraction unit and the transimpedance gain control signal generating circuit;

[0018] The transimpedance gain control signal generating circuit is used for processing the analog voltage signal and outputting it to the control end of the variable feedback resistor.

[0019] In some embodiments, the digital logic control circuit includes a comparison reference value setting unit, a digital comparison logic unit and a control processing unit, the comparison reference value setting unit is connected to the digital comparison logic unit, the digital comparison logic unit is connected to the control processing unit, and the control processing unit is connected to the digital-to-analog converter;

[0020] The output terminal of the comparison reference value setting unit is used to output the reference reference value to the reference reference value input terminal of the digital comparison logic unit;

[0021] The digital comparison logic unit is used to compare the multi-bit digital signal input by the analog-to-digital converter with the reference base value input by the digital comparison logic unit, and output the comparison result to the control processing unit;

[0022] The control processing unit is used for processing the comparison result according to a preset logic algorithm and then outputting it to the digital-to-analog converter.

[0023] In some embodiments, the multi-order filter is a second-order low-pass filter or an N-order low-pass filter, where N is an integer greater than 2.

[0024] In some embodiments, the current extraction unit uses a MOS tube.

[0025] In some embodiments, the differential amplifier buffer circuit includes a first differential amplifier, a second differential amplifier, and an output buffer connected in sequence;

[0026] The first differential amplifier is used to amplify the output signal of the front-end circuit and the output signal of the multi-order filtering and voltage stabilizing circuit, convert them into a pair of differential signals, and then output them to the second differential amplifier;

[0027] The second differential amplifier is used to amplify the differential signal output by the first differential amplifier again and then output it to the output buffer;

[0028] The output buffer is used to transmit the differential signal output by the second differential amplifier to the differential output terminal of the transimpedance amplifier and provide impedance matching.

[0029] In some embodiments, the transimpedance amplifier further comprises:

[0030] A correction circuit, wherein the input end of the correction circuit is connected to the differential output end of the output buffer, the output end of the correction circuit is connected to the differential control end of the first differential amplifier, and the correction circuit is used to correct the differential output signal of the output buffer according to an external reset signal.

[0031] In a second aspect, an optical module is provided, comprising the aforementioned transimpedance amplifier.

[0032] The embodiment of the present invention provides a transimpedance amplifier and an optical module. The transimpedance amplifier is provided with a multi-order filtering and voltage stabilizing circuit and a feedback control circuit. When the input optical signal of the optical detector undergoes a large-scale mutation, the output photocurrent signal of the optical detector will also undergo a mutation. The feedback control circuit controls the front-end circuit according to the external reset signal and the output signal of the multi-order filtering and voltage stabilizing circuit. Through closed-loop feedback control, the output signal of the front-end circuit follows the mutation of the input optical signal of the optical detector and responds quickly and stabilizes quickly, thereby ensuring that the differential output voltage of the differential amplifier buffer circuit of the transimpedance amplifier changes in real time and quickly follows the change of the input optical signal of the optical detector, realizing high-quality ultra-high-speed and large dynamic range burst signal transmission, reducing the system overhead of 50G PON, improving the burst throughput of the 50G PON system, and effectively solving the technical problem of fast burst response of 50G PON OLT when receiving uplink burst optical signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0034] Figure 1 A schematic diagram of the structure of a transimpedance amplifier provided by an embodiment of the present invention;

[0035] Figure 2 The embodiment of the present invention provides Figure 1 A schematic diagram of a transient simulation result of a signal before a differential amplifier buffer circuit in burst mode obtained by simulating a transimpedance amplifier;

[0036] Figure 3A A schematic diagram of a second-order low-pass filter provided by an embodiment of the present invention;

[0037] Figure 3B A schematic diagram of an N-th order low-pass filter provided by an embodiment of the present invention;

[0038] Figure 4 A schematic diagram of the structure of a feedback control circuit provided by an embodiment of the present invention;

[0039] Figure 5 A schematic diagram of the structure of a transimpedance gain control signal generating circuit provided by an embodiment of the present invention;

[0040] Figure 6 A schematic diagram of a digital logic control circuit provided by an embodiment of the present invention;

[0041] Figure 7 A schematic diagram of the structure of a comparison reference value setting unit and a digital comparison logic unit provided by an embodiment of the present invention;

[0042] Figure 8 A schematic diagram of the structure of a 9-bit iDAC provided by an embodiment of the present invention;

[0043] Fig. 9A A schematic diagram of a correction circuit provided by an embodiment of the present invention;

[0044] Fig. 9B Another schematic diagram of a correction circuit provided by an embodiment of the present invention;

[0045] Figures 10A to 10J The embodiment of the present invention provides Figure 2 A local enlarged diagram of each burst packet data period in the signal transient simulation result;

[0046] Fig.11 The embodiment of the present invention provides Figure 1 A schematic diagram of transient simulation results of signals of input and output of each level under burst mode obtained by simulating a transimpedance amplifier;

[0047] Figures 12A to 12J The embodiment of the present invention provides Fig.11 The eye diagram of the transimpedance amplifier output signal during each burst packet data period in the signal transient simulation results. DETAILED DESCRIPTION

[0048] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0049] The embodiment of the present invention provides a transimpedance amplifier, which can solve the problems of long burst response time and poor output signal quality of existing transimpedance amplifiers at 25Gbps and higher speeds, thereby reducing the overhead of the 50G PON system and improving the burst throughput of the 50G PON system, thereby meeting the technical requirements of the 50G PON OLT for fast burst response when receiving uplink bursts and large dynamic range optical signals.

[0050] See also Figure 1 As shown, an embodiment of the present invention provides a transimpedance amplifier, including: a front-end circuit, a multi-order filtering and voltage stabilization circuit, a differential amplifier buffer circuit and a feedback control circuit.

[0051] The front-end circuit is connected with the photodetector, the multi-order filtering and voltage stabilizing circuit and the differential amplifier buffer circuit.

[0052] The multi-order filtering and voltage stabilizing circuit is connected to the feedback control circuit and the differential amplifier buffer circuit. The multi-order filtering and voltage stabilizing circuit is used to perform high-order low-pass filtering on the output signal of the front-end circuit and output the mean signal to the feedback control circuit. The multi-order filtering and voltage stabilizing circuit also provides the mean signal with output current driving capability to the differential amplifier buffer circuit.

[0053] The feedback control circuit is connected to the front-end circuit and is used to control the front-end circuit according to the external reset signal and the output signal of the multi-order filtering and voltage stabilizing circuit, so that the output signal of the front-end circuit changes rapidly following the sudden change of the input light signal of the light detector.

[0054] Specifically, see Figure 1 As shown in the figure, the output signal of the photodetector refers to the output photocurrent signal (I IN Or / R1 / PLUS), the input end (IN) of the front-end circuit of the transimpedance amplifier is connected to the output end of the detector PD as the input end of the entire transimpedance amplifier, and the output end of the front-end circuit is connected to the input end of the multi-order filtering and voltage stabilization circuit. The main function of the multi-order filtering and voltage stabilization circuit is to perform high-order low-pass filtering on the output signal of the front-end circuit, output the mean signal to the feedback control circuit, and provide the mean signal with output current driving capability to the differential amplifier buffer circuit. The function of the feedback control circuit is to control the front-end circuit according to the external reset signal and the output mean signal of the multi-order filtering and voltage stabilization circuit, so that the output signal of the front-end circuit changes quickly following the sudden change of the input light signal of the light detector.

[0055] The transimpedance amplifier in the embodiment of the present invention is provided with a multi-order filtering and voltage stabilizing circuit and a feedback control circuit. When the input optical signal of the photodetector undergoes a large-scale mutation, the output photocurrent signal of the photodetector (that is, the input current signal of the transimpedance amplifier) ​​will also undergo a mutation. The feedback control circuit controls the front-end circuit according to the external reset signal and the output signal of the multi-order filtering and voltage stabilizing circuit. Through closed-loop feedback control, the output signal of the front-end circuit follows the mutation of the input optical signal of the photodetector and responds quickly and stabilizes quickly, thereby ensuring that the differential output voltage of the differential amplifier buffer circuit of the transimpedance amplifier changes in real time and quickly follows the change of the input optical signal of the photodetector, thereby achieving high-quality ultra-high-speed and large dynamic range burst signal transmission, reducing the system overhead of the 50G PON system, improving the burst throughput of the 50G PON system, and effectively solving the technical problem of the fast burst response of the 50G PON OLT to the received uplink burst optical signal.

[0056] As an optional implementation, in an embodiment of the invention, see Figure 1 As shown, the main function of the front-end circuit is to convert the output photocurrent signal of the photodetector into an analog voltage signal, which includes a current extraction unit, a single-ended inverting amplifier, and a variable feedback resistor. The input end of the current extraction unit and the single-ended inverting amplifier are connected to the photodetector, the output end of the single-ended inverting amplifier is connected to the multi-order filtering and voltage stabilizing circuit and the differential amplifier buffer circuit, the input end and the output end of the variable feedback resistor are connected to the output end and the input end of the single-ended inverting amplifier, and the control end of the current extraction unit and the control end of the variable feedback resistor are connected to the feedback control circuit. Among them, the current extraction unit adopts NMOS tube MN11, which has a simple structure; the current extraction unit can also adopt MOS tubes or circuits with similar functions to NMOS tube MN11 (inverting amplification, large input current range circuit), for example, a large input current range circuit using a first-stage inverting amplifier cascaded with a first-stage source follower.

[0057] The feedback control circuit is used to control the control end of the current extraction unit and the control end of the variable feedback resistor according to the external reset signal and the output signal of the multi-order filtering and voltage stabilizing circuit, so that the output signal of the output end of the single-ended inverting amplifier changes quickly following the sudden change of the input light signal of the light detector.

[0058] See also Figure 1 As shown, the input end (IN) of the front-end circuit of the transimpedance amplifier serves as the input end of the entire transimpedance amplifier, and is connected to the output end of the photodetector PD, the output end of the variable feedback resistor Rf, the drain of the NMOS tube MN11, and the input end of the single-ended inverting amplifier. The output end of the single-ended inverting amplifier serves as the output end of the front-end circuit of the transimpedance amplifier and is connected to the input end of the variable feedback resistor Rf. The gate of the NMOS tube MN11 is connected to the first output end of the feedback control circuit, and the control end of the variable feedback resistor Rf is connected to the second output end of the feedback control circuit.

[0059] Further, see Figure 1 As shown, the multi-order filtering and voltage stabilization circuit includes a multi-order filter and a stabilizer, the input end of the multi-order filter is connected to the output end of the single-ended inverting amplifier, the first output end of the multi-order filter is connected to the input end of the voltage stabilizer, the second output end of the multi-order filter is connected to the input end of the feedback control circuit, and the output end of the voltage stabilizer is connected to the differential amplifier buffer circuit.

[0060] See also Figure 1As shown, the main function of the multi-order filter is to perform high-order low-pass filtering on the output signal mTIAout of the front-end circuit, and output the mean signal mTIAoutAvg1 through the output terminal O1 and the mean signal mTIAoutAvg2 through the output terminal O2 according to the working bandwidth of the regulator and the working bandwidth requirements of the feedback control circuit.

[0061] The main functions of the voltage regulator include two aspects: one is to restore the voltage signal at the input end in a 1:1 form at the output end based on the working principle of the source follower and output it to the differential amplifier buffer circuit; the other is to provide output current driving capability at the output end.

[0062] Figure 2 For Figure 1 The transient simulation result of the signal before the differential amplifier buffer circuit in burst mode is obtained by simulating the transimpedance amplifier shown in FIG. Figure 2 As shown, the output photocurrent signal / R1 / PLUS of the photodetector PD passes through the single-ended inverting amplifier output signal mTIAout, and then passes through the multi-stage filtering and voltage stabilization circuit output signal to the feedback control circuit. The feedback control circuit generates output control signals / I0 / I0 / I200 / lbl_14_G and / I0 / I0 / I200 / Vgain under the cooperation of the external reset signal RESET. The output control signals / I0 / I0 / I200 / lbl_14_G and / I0 / I0 / I200 / Vgain both follow the output photocurrent signal / R1 / PLUS of the photodetector PD. 1 / PLUS responds quickly to the mutation in each burst data packet and stabilizes quickly, thereby controlling the output signal mTIAout of the front-end circuit to respond quickly and stabilize quickly with the mutation of the photocurrent signal / R1 / PLUS, and the regulator output signal mTIAoutDum also changes quickly with the mutation of mTIAout and stabilizes quickly to the average state of mTIAout, thereby ensuring that the differential output voltage of the differential amplifier buffer circuit of the transimpedance amplifier quickly follows the large dynamic range mutation of the input optical signal of the photodetector in real time, realizing high-quality ultra-high-speed burst signal transmission.

[0063] Further, see Figure 3A As shown, the multi-order filter can be a second-order low-pass filter, including a resistor R31, a capacitor C31, a resistor R32, and a capacitor C32. The first end of the resistor R31 is the multi-order filter input terminal IN; the second end of the resistor R31 is connected to the first end of the resistor R32 and the first end of the capacitor C31 as the multi-order filter output terminal O1; the second end of the capacitor C31 is grounded; the second end of the resistor R32 is connected to the first end of the capacitor C32 as the multi-order filter output terminal O2; the second end of the capacitor C32 is grounded.

[0064] See also Figure 3BAs shown, the multi-order filter can be an N-order low-pass filter, including a resistor R31, a capacitor C31, ..., a resistor R3N, and a capacitor C3N. The second end of the resistor R3N is connected to the first end of the capacitor C3N as the multi-order filter output end O2; the second end of the capacitor C3N is grounded.

[0065] As an optional implementation, in an embodiment of the invention, see Figure 4 As shown, the feedback control circuit includes an analog-to-digital converter, a digital logic control circuit, a digital-to-analog converter, a load circuit, and a transimpedance gain control signal generating circuit which are connected in sequence.

[0066] The analog-to-digital converter is used to monitor the output signal of the multi-order filtering and voltage stabilization circuit in real time according to the external reset signal, and synchronously perform analog-to-digital conversion to obtain a multi-bit digital signal and output it to the digital logic control circuit.

[0067] The digital logic control circuit is used to process the multi-bit digital signal according to a preset logic algorithm and then output it to the digital-to-analog converter.

[0068] The digital-to-analog converter is used to perform digital-to-analog conversion on the multi-bit digital signal processed by the digital logic control circuit to obtain an analog current signal (iDACout) corresponding to the DC value of the input current of the transimpedance amplifier and output it to the load circuit.

[0069] The load circuit is used to convert the analog current signal output by the digital-to-analog converter into an analog voltage signal, and output it to the control end of the current extraction unit and the transimpedance gain control signal generating circuit. Specifically, the load circuit uses an NMOS tube MN41, and the NMOS tube MN41 is used to convert the analog current signal (iDACout) fed back by the digital-to-analog converter into an analog voltage signal (lbl_14_G) and output it. The source of the NMOS tube MN41 is grounded, and the gate and drain of the NMOS tube MN41 are short-circuited and connected to the output end of the digital-to-analog converter and the input end of the transimpedance gain control signal generating circuit.

[0070] The transimpedance gain control signal generating circuit is used to process the analog voltage signal (lbl_14_G) in accordance with the requirement that the transimpedance gain changes with the input current and then output it to the control end of the variable feedback resistor.

[0071] The above-mentioned feedback control circuit adopts a high-speed mixed digital-analog circuit to realize signal monitoring and generate feedback control signals, and utilizes the fast response speed of the high-speed digital circuit to realize timely monitoring and feedback of burst signals, thus solving the problems such as long burst response time faced by existing transimpedance amplifiers.

[0072] See also Figure 4 As shown, the specific description is as follows using 9-bit ADC (analog-to-digital converter) and 9-bit iDAC (current-type digital-to-analog converter):

[0073] The signal input end of the 9-bit ADC is connected to the output end O2 of the multi-order filter, and the control input end of the 9-bit ADC is connected to the external reset signal RESET. Under the cooperation of the external reset signal RESET, the output end of the 9-bit ADC outputs 9-bit digital signals Vbit1, Vbit2, Vbit3, Vbit4, Vbit5, Vbit6, Vbit7, Vbit8, and Vbit9, which are connected to the 9-bit digital signal input end of the digital logic control circuit. The output end of the digital logic control circuit is the 9-bit digital signals Ibit1, Ibit2, Ibit3, Ibit4, Ibit5, Ibit6, Ibit7, Ibit8, and Ibit9, which are connected to the 9-bit digital control signal input end of the 9-bit iDAC. The output end iDACout of the 9-bit iDAC is connected to the drain and gate of the NMOS tube MN41 (the gate and drain of the NMOS tube MN41 are short-circuited), and serves as the second output end of the feedback control circuit, outputting the control signal lbl_14_G to the control end of the current extraction unit. At the same time, the output end iDACout of the 9-bit iDAC is also connected to a transimpedance gain control signal generating circuit. The output end of the transimpedance gain control signal generating circuit serves as the first output end of the feedback control circuit. The transimpedance gain control signal generating circuit processes the output control signal lbl_14_G in accordance with the requirement that the transimpedance gain changes with the input current to obtain the output control signal Vgain and output it to the control end of the variable feedback resistor Rf.

[0074] The above-mentioned digital-to-analog converter and digital-to-analog converter are both high-speed digital-to-analog mixed circuits. The high-speed digital-to-analog converter is used to realize fast real-time monitoring of the input signal, and the high-speed digital-to-analog converter is used to realize the rapid generation of feedback control signals. The closed-loop response speed is fast and the stability is good.

[0075] The bit number of 9 bits used by the ADC and iDAC here can be used as an implementation method. In actual applications, the bit number of ADC and iDAC will be adjusted according to the application scenario and actual needs. When the range of the photogenerated current output by the PD is small, the bit number of ADC and iDAC can be appropriately reduced. For example, if the range of the photogenerated current output by the PD is 0-2.5mA, the bit number of ADC and iDAC can be selected as 9bit; if the range of the photogenerated current output by the PD is 0-1mA, the bit number of ADC and iDAC can be selected as 8bit. If higher control accuracy is required, the bit number of ADC and iDAC can be appropriately increased. For example, when the range of the photogenerated current output by the PD is 0-2.5mA, the bit number of ADC and iDAC can be selected as 10bit or higher.

[0076] Further, see Figure 5 As shown, the transimpedance gain control signal generating circuit includes an NMOS transistor MN51, PMOS transistors MP51 and MP52, resistors R51 and R52, and a capacitor C51. Among them, the gate of the NMOS transistor MN51 is connected to the output end of the digital-to-analog converter (9-bit iDAC) as the input end of the transimpedance gain control signal generating circuit, the source of the NMOS transistor MN51 is grounded, the drain of the NMOS transistor MN51 is connected to the drain and gate of the PMOS transistor MP51 and the gate of the PMOS transistor MP52, the source of the PMOS transistor MP51 is connected to the power supply VCC, the source of the PMOS transistor MP52 is connected to the power supply VCC, the drain of the PMOS transistor MP52 is connected to the first end of the resistor R51, the second end of the resistor R51 is connected to the first end of the resistor R52 and the first end of the capacitor C51 and serves as the second output end of the feedback control circuit to generate the output control signal Vgain, the second end of the resistor R52 is grounded, and the second port of the capacitor C52 is grounded.

[0077] The above transimpedance gain control signal generating circuit first performs proportional mirroring on the analog current signal (iDACout) fed back by the digital-to-analog converter through the NMOS tube MN51, the PMOS tube MP51 and the MP52, and then performs proportional voltage division through the resistors R51 and R52 to obtain the output control signal Vgain. Among them, the proportional mirroring parameters and the proportional voltage division parameters of the resistors R51 and R52 are set according to the requirements that the transimpedance gain changes with the input current. The above transimpedance gain control signal generating circuit is characterized by a simple structure, a fast burst response speed, and the output signal changes quickly following the changes in the input signal.

[0078] See also Figure 6 As shown, the digital logic control circuit includes a comparison reference value setting unit, a digital comparison logic unit and a control processing unit. The comparison reference value setting unit is connected to the digital comparison logic unit, the digital comparison logic unit is connected to the control processing unit, and the control processing unit is connected to the digital-to-analog converter.

[0079] The output terminal of the comparison reference value setting unit is used to output the reference base value to the reference base value input terminal of the digital comparison logic unit.

[0080] The digital comparison logic unit is used for comparing the multi-bit digital signal inputted by the analog-to-digital converter with the reference base value inputted by the digital comparison logic unit, and outputting the comparison result to the control processing unit.

[0081] The control processing unit is used for processing the comparison result according to a preset logic algorithm and then outputting the result to the digital-to-analog converter.

[0082] The function of the above-mentioned digital logic control circuit is to quickly monitor the input signal in real time in the digital domain by the digital-to-analog converter, and quickly compare the output signal size fed back with the built-in comparison table of the input current size of the transimpedance amplifier and output the judgment result. Its characteristic is that it uses high-speed digital circuits to realize the fast comparison function.

[0083] See also Figure 6 As shown, continue to take 9-bit ADC (analog-to-digital converter) and 9-bit iDAC (current-type digital-to-analog converter) as an example. The 9-bit digital signals Vbit1, Vbit2, Vbit3, Vbit4, Vbit5, Vbit6, Vbit7, Vbit8, and Vbit9 output by the ADC are connected to the 9-bit digital input signal terminal corresponding to the digital comparison logic unit. The output terminal of the digital comparison logic unit outputs the 9-bit digital control signals Cbit1, Cbit2, Cbit3, Cbit4, Cbit5, Cbit6, Cbit7, Cbit8, and Cbit9, and is connected to the 9-bit digital input signal terminal corresponding to the control processing unit. The control processing unit processes the 9-bit digital input signal according to a preset logic algorithm, for example, a comparison relationship table of the digital input signal size of the control processing unit and the input current size of the transimpedance amplifier (Table 1 below), and then outputs the 9-bit digital control signals Ibit1, Ibit2, Ibit3, Ibit4, Ibit5, Ibit6, Ibit7, Ibit8, and Ibit9 to the digital-to-analog converter. The analog current signal (iDACout) output by the digital-to-analog converter is usually approximately proportional to the input current size of the transimpedance amplifier.

[0084] Figure 6In the figure, the 9-bit digital control signals Cbit1, Cbit2, Cbit3, Cbit4, Cbit5, Cbit6, Cbit7, Cbit8, Cbit9 are not in a one-to-one correspondence after being processed by the control processing optimization unit. That is, Ibit1 is not obtained only from Cbit1... Ibit9 is not obtained only from Cbit9. The mutual correspondence is obtained based on the comparison table of the digital input signal size of the control processing unit and the input current size of the transimpedance amplifier. In actual design, the correspondence between one of the 9-bit digital control signals Cbit1, Cbit2, Cbit3, Cbit4, Cbit5, Cbit6, Cbit7, Cbit8, Cbit9 and the 9-bit digital control signals Ibit1, Ibit2, Ibit3, Ibit4, Ibit5, Ibit6, Ibit7, Ibit8, Ibit9 is shown in Table 1 below:

[0085] Table 1

[0086]

[0087]

[0088] Further, see Figure 7As shown, the comparison reference value setting unit includes a reference voltage setting digital control unit and 9 reference voltage generator DACs (vDAC1, vDAC2, vDAC3, vDAC4, vDAC5, vDAC6, vDAC7, vDAC8, vDAC9), and the digital comparison logic unit includes 9 digital comparators (digital comparator 1, digital comparator 2, digital comparator 3, digital comparator 4, digital comparator 5, digital comparator 6, digital comparator 7, digital comparator 8, digital comparator 9). Among them, the output end of the reference voltage setting digital control unit is connected to the control signal input ends of 9 reference voltage generators vDAC1, vDAC2, vDAC3, vDAC4, vDAC5, vDAC6, vDAC7, vDAC8, and vDAC9, and controls these 9 reference voltage generators vDAC1, vDAC2, vDAC3, vDAC4, vDAC5, vDAC6, vDAC7, vDAC8, and vDAC9 to generate 9 voltage reference reference values ​​VDref1, VDref2, VDref3, VDref4, VDref5, VDref6, VDref7, VDref8, and VDref9 respectively. The output ends of the 9 reference voltage generators output the voltage reference reference values ​​VDref1, VDref2, VDref3, VDref4, VDref5, VDref6, VDref7, VDref8, and VDref9 respectively, and are respectively connected to the reference reference value input ends of 9 digital comparators, 9bit The 9-bit digital signals Vbit1, Vbit2, Vbit3, Vbit4, Vbit5, Vbit6, Vbit7, Vbit8, and Vbit9 output by the ADC are simultaneously connected to the 9-bit digital input signal ports corresponding to the 9 digital comparators. Digital comparator 1, digital comparator 2, digital comparator 3, digital comparator 4, digital comparator 5, digital comparator 6, digital comparator 7, digital comparator 8, and digital comparator 9. According to the comparison results between the 9-bit digital input signal and the input reference value of each digital comparator, the digital control signals Cbit1, Cbit2, Cbit3, Cbit4, Cbit5, Cbit6, Cbit7, Cbit8, and Cbit9 are output respectively.

[0089] It should be noted that the 9 voltage reference values ​​VDref1, VDref2, VDref3, VDref4, VDref5, VDref6, VDref7, VDref8, and VDref9 output by the reference voltage setting digital control unit to control 9 reference voltage generators (vDAC1, vDAC2, vDAC3, vDAC4, vDAC5, vDAC6, vDAC7, vDAC8, and vDAC9) are not in a linear increasing or decreasing relationship, but are related to the equivalent resistance value of the variable feedback resistor Rf in the current working state. In practical applications, examples of the numerical relationship of the voltage reference values ​​that can be used are as follows:

[0090] VDref2 = VDref1 - 150mV;

[0091] VDref3 = VDref2 - 50mV;

[0092] VDref4 = VDref3 - 40mV;

[0093] VDref5 = VDref4 - 40mV;

[0094] VDref6 = VDref5 - 30mV;

[0095] VDref7 = VDref6 - 30mV;

[0096] VDref8 = VDref7 - 20mV;

[0097] VDref9=VDref8-15mV.

[0098] Further, see Figure 8 As shown, the 9-bit iDAC may include PMOS tube MP80, PMOS tubes MP81 and MP811, PMOS tubes MP82 and MP821, PMOS tubes MP83 and MP831, PMOS tubes MP84 and MP841, PMOS tubes MP85 and MP851, PMOS tubes MP86 and MP861, PMOS tubes MP87 and MP871, PMOS tubes MP88 and MP881, and PMOS tubes MP89 and MP891.

[0099] Among them, the drain and gate of the PMOS tube MP80 are short-circuited and connected to the reference current Iref. The gate of the PMOS tube MP80 is simultaneously connected to the gate of the PMOS tube MP81, the gate of the PMOS tube MP82, the gate of the PMOS tube MP83, the gate of the PMOS tube MP84, the gate of the PMOS tube MP85, the gate of the PMOS tube MP86, the gate of the PMOS tube MP87, the gate of the PMOS tube MP88, and the gate of the PMOS tube MP89. The source of the PMOS tube MP80 and the source of the PMOS tube MP81, the source of the PMOS tube MP82, the source of the PMOS tube MP83, the source of the PMOS tube MP84, the source of the PMOS tube MP85, the source of the PMOS tube MP86, the source of the PMOS tube MP87, the source of the PMOS tube MP88, and the source of the PMOS tube MP89 are all connected to the power supply VCC. The drain of the PMOS tube MP81 outputs a current of I1 and is connected to the source of the PMOS tube MP811. The gate of the PMOS tube MP811 is connected to the control signal Ibit1, and the drain of the PMOS tube MP811 is connected to the output terminal iDACout of the 9-bit iDAC. The drain output current of the PMOS tube MP82 is I2, and is connected to the source of the PMOS tube MP821. The gate of the PMOS tube MP821 is connected to the control signal Ibit2, and the drain of the PMOS tube MP821 is connected to the output terminal iDACout of the 9-bit iDAC. The drain output current of the PMOS tube MP83 is I3, and is connected to the source of the PMOS tube MP831. The gate of the PMOS tube MP831 is connected to the control signal Ibit3, and the drain of the PMOS tube MP831 is connected to the output terminal iDACout of the 9-bit iDAC. The drain output current of the PMOS tube MP84 is I4, and is connected to the source of the PMOS tube MP841; the gate of the PMOS tube MP841 is connected to the control signal Ibit4, and the drain of the PMOS tube MP841 is connected to the output terminal iDACout of the 9-bit iDAC. The drain output current of the PMOS tube MP85 is I5, and is connected to the source of the PMOS tube MP851; the gate of the PMOS tube MP851 is connected to the control signal Ibit5, and the drain of the PMOS tube MP851 is connected to the output terminal iDACout of the 9-bit iDAC. The drain output current of the PMOS tube MP86 is I6, and is connected to the source of the PMOS tube MP861. The gate of the PMOS tube MP861 is connected to the control signal Ibit6, and the drain of the PMOS tube MP861 is connected to the output terminal iDACout of the 9-bit iDAC. The drain output current of the PMOS tube MP87 is I7, and is connected to the source of the PMOS tube MP871; the gate of the PMOS tube MP871 is connected to the control signal Ibit7, and the drain of the PMOS tube MP871 is connected to the output terminal iDACout of the 9-bit iDAC.The drain output current of the PMOS tube MP88 is I8, and is connected to the source of the PMOS tube MP881. The gate of the PMOS tube MP881 is connected to the control signal Ibit8, and the drain of the PMOS tube MP881 is connected to the output terminal iDACout of the 9-bit iDAC. The drain output current of the PMOS tube MP89 is I9, and is connected to the source of the PMOS tube MP891. The gate of the PMOS tube MP891 is connected to the control signal Ibit9, and the drain of the PMOS tube MP891 is connected to the output terminal iDACout of the 9-bit iDAC. The current at the output terminal iDACout of the 9-bit iDAC is equal to the sum of I1, I2, I3, I4, I5, I6, I7, I8, and I9.

[0100] In addition, the currents of I1, I2, I3, I4, I5, I6, I7, I8, and I9 are not linearly increasing. In practical applications, the corresponding relationship between the 9-bit digital input control signals Ibit1, Ibit2, Ibit3, Ibit4, Ibit5, Ibit6, Ibit7, Ibit8, and Ibit9 of the 9-bit iDAC and the currents I1, I2, I3, I4, I5, I6, I7, I8, and I9 needs to be set according to the application scenario and actual needs. One of the corresponding relationships that can be used is shown in Table 2 below:

[0101] Table 2

[0102] When Ibit9=0, I9=1500uA; otherwise, I9=0 When Ibit8=0, I8=400uA; otherwise, I8=0 When Ibit7=0, I7=400uA; otherwise, I7=0 When Ibit6=0, I6=200uA; otherwise, I6=0 When Ibit5=0, I5=200uA; otherwise, I5=0 When Ibit4=0, I4=100uA; otherwise, I4=0 When Ibit3=0, I3=100uA; otherwise, I3=0 When Ibit2=0, I2=50uA; otherwise, I2=0 When Ibit1=0, I1=50uA; otherwise, I1=0

[0103] As an optional implementation, in an embodiment of the invention, see Figure 1 As shown, the differential amplifier buffer circuit includes a first differential amplifier, a second differential amplifier and an output buffer which are connected in sequence.

[0104] The first differential amplifier is used to amplify the output signal of the front-end circuit and the output signal of the multi-order filtering and voltage stabilizing circuit, convert them into a pair of differential signals, and then output them to the second differential amplifier.

[0105] The second differential amplifier is used to amplify the differential signal output by the first differential amplifier again and then output it to the output buffer.

[0106] The output buffer is used to losslessly transmit the differential signal output by the second differential amplifier to the differential output terminal of the transimpedance amplifier, and to provide sufficient output driving capability to the outside, while achieving impedance matching with the outside.

[0107] Specifically, the first differential amplifier converts the input signals mTIAout and mTIAoutDum into a pair of differential output signals DS1outp and DS1outn, and has a certain signal amplification function. The differential output end of the first differential amplifier is connected to the differential input end of the second differential amplifier.

[0108] The second differential amplifier pre-amplifies the input differential signals DS1outp and DS1outn to ensure that the differential output signals DS2outp and DS2outn thereof reach sufficient differential output signal amplitudes. The differential output end of the second differential amplifier is connected to the differential input end of the output buffer.

[0109] The output buffer transmits the differential input signals DS2outp and DS2outn losslessly to the differential output terminals OUTPdie and OUTNdie of the transimpedance amplifier, and provides sufficient output driving capability to the outside and realizes impedance matching with the outside.

[0110] As an optional implementation, in an embodiment of the invention, see Figure 1 As shown, the transimpedance amplifier also includes: a correction circuit, wherein the input end of the correction circuit is connected to the differential output end of the output buffer, the output end of the correction circuit is connected to the differential control end of the first differential amplifier, and the correction circuit is used to quickly correct the DC value and DC mean deviation (DC offset) of the differential output signal of the output buffer according to an external reset signal.

[0111] Specifically, the correction circuit monitors the DC mean deviation (DC offset) between the differential output signals OUTPdie and OUTNdie of the transimpedance amplifier in real time, and under the action of the external reset signal RESET, generates output control signals VDCP and VDCN according to the DC mean deviation between the differential output signals OUTPdie and OUTNdie of the transimpedance amplifier to act on the differential control end of the first differential amplifier, and quickly corrects and eliminates the DC mean deviation between the differential output signals OUTPdie and OUTNdie of the transimpedance amplifier, thereby ensuring that the DC mean value of OUTPdie and the DC mean value of OUTNdie are approximately equal under transient working conditions.

[0112] Further, see Fig. 9AAs shown, the correction circuit includes an inverter 91, an NMOS tube MN910, NMOS tubes MN911 and MN912, PMOS tubes MP911 and MP912, NMOS tubes MN913 and MN914, NMOS tubes MNS911 and MNS912, capacitors C911 and C912, resistors R911 and R912, and resistors R913 and R914. Among them, the gate of the NMOS tube MN911 is connected to the differential output signal OUTPdie and the second end of the resistor R911, and the gate of the NMOS tube MN912 is connected to the differential output signal OUTNdie and the second end of the resistor R912. The source of the NMOS tube MN911 and the source of the NMOS tube MN912 are short-circuited and connected to the drain of the NMOS tube MN910, the gate of the NMOS tube MN910 is connected to the bias voltage Vbias, and the source of the NMOS tube MN910 is grounded. The drain of the NMOS tube MN911 is connected to the drain of the PMOS tube MP911, the gate of the PMOS tube MP911, and the gate of the NMOS tube MN913, and the source of the PMOS tube MP911 is connected to the power supply VCC. The drain of the NMOS tube MN912 is connected to the drain of the PMOS tube MP912, the gate of the PMOS tube MP912, and the gate of the NMOS tube MN914, and the source of the PMOS tube MP912 is connected to the power supply VCC. The drain of the NMOS tube MN913 is connected to the power supply VCC, the source of the NMOS tube MN913 is connected to the source (drain) of the NMOS tube MNS911 and the first end of the resistor R913, the second end of the resistor R913 is grounded, the drain (source) of the NMOS tube MNS911 is connected to the first end of the capacitor C911, and the second end of the capacitor C911 is connected to the first end of the resistor R911. The drain of the NMOS tube MN914 is connected to the power supply VCC, the source of the NMOS tube MN914 is connected to the source (drain) of the NMOS tube MNS912 and the first end of the resistor R914, the second end of the resistor R914 is grounded, the drain (source) of the NMOS tube MNS912 is connected to the first end of the capacitor C912, and the second end of the capacitor C912 is connected to the first end of the resistor R912. The input end of the inverter 91 is connected to the external reset signal RESET, and the output end of the inverter 91 is connected to the gate of the NMOS tube MNS911 and the gate of the NMOS tube MNS912. In addition, the first end of the resistor R913 and the first end of the resistor R914 respectively output control signals VDCP and VDCN to act on the differential control end of the first differential amplifier.

[0113] Further, see Fig. 9B As shown, the embodiment of the present invention provides another circuit structure of the correction circuit. Fig. 9A Capacitors C923 and C924, PMOS tube MP923 and PMOS tube MP924 are added. Fig. 9B and Fig. 9AThe difference is that: the first end of capacitor C923 is connected to the drain of NMOS tube MN911, the second end of capacitor C923 is connected to the drain of PMOS tube MP923, and the source of PMOS tube MP923 is connected to the power supply VCC. The first end of capacitor C924 is connected to the drain of NMOS tube MN912, the second end of capacitor C924 is connected to the drain of PMOS tube MP924, and the source of PMOS tube MP924 is connected to the power supply VCC. The gate of PMOS tube MP923 and the gate of PMOS tube MP924 are short-circuited and connected to the external reset signal RESET.

[0114] See again Figure 2 Schematic diagram of signal transient simulation results shown in FIG. 1 , Ibit1, Ibit2, Ibit3, Ibit4, Ibit5, Ibit6, Ibit7, Ibit8, and Ibit9 are 9-bit digital control signals generated inside the feedback control circuit and output to the 9-bit iDAC, and / RESET is an external reset signal RESET; the transient simulation duration is 1740ns; a total of 10 burst data packets are included: the average current size Isig_1 of the input current signal / R1 / PLUS of the first burst data packet is 30uA, the average current size Isig_2 of the input current signal / R1 / PLUS of the second burst data packet is 180uA, the average current size Isig_3 of the input current signal / R1 / PLUS of the third burst data packet is 30uA, the average current size Isig_4 of the input current signal / R1 / PLUS of the fourth burst data packet is 300uA, and the input current size Isig_5 of the fifth burst data packet is 160uA. The average current size Isig_5 of the flow signal / R1 / PLUS is 30uA, the average current size Isig_6 of the input current signal / R1 / PLUS of the sixth burst data packet is 600uA, the average current size Isig_7 of the input current signal / R1 / PLUS of the seventh burst data packet is 30uA, the average current size Isig_8 of the input current signal / R1 / PLUS of the eighth burst data packet is 900uA, the average current size Isig_9 of the input current signal / R1 / PLUS of the ninth burst data packet is 2700uA, and the average current size Isig_10 of the input current signal / R1 / PLUS of the tenth burst data packet is 30uA.

[0115] In addition, in different burst data packets, the 9-bit signal (Ibit1, Ibit2, Ibit3, Ibit4, Ibit5, Ibit6, Ibit7, Ibit8, Ibit9) generated inside the feedback control circuit to control the iDACout current size will change with the change of the input current signal / R1 / PLUS; and, in each burst data packet, Ibit1, Ibit2, Ibit3, Ibit4, Ibit5, Ibit6, Ibit7, Ibit8, Ibit9 will only be independently locked into one state. For example, for a burst data packet with an average current size of 30uA for the input current signal / R1 / PLUS, Ibit1~Ibit9 are all locked to a low level; for an input current signal / R1 / PLUS, Ibit1~Ibit9 are locked to a low level. For burst data packets with an average current size of 180uA for the input current signal / R1 / PLUS, Ibit1 and Ibit2 are locked at high level, and Ibit3~Ibit9 are locked at low level; for burst data packets with an average current size of 300uA for the input current signal / R1 / PLUS, Ibit1~Ibit6 are locked at high level, and Ibit7~Ibit9 are locked at low level; for burst data packets with an average current size of 600uA and 900uA for the input current signal / R1 / PLUS, Ibit1~Ibit8 are locked at high level, and Ibit9 is locked at low level; for burst data packets with an average current size of 2700uA for the input current signal / R1 / PLUS, Ibit1~Ibit9 are all locked at high level.

[0116] Fig. 10A , Fig. 10B , Fig. 10C , Fig. 10D , Fig. 10E , Fig.10F , Figure 10G , Fig. 10H , Fig.10I , Fig.10J They are Figure 2 The transient simulation results of the signal shown are partial enlarged views of the transient simulation results of the first burst data packet (Isig_1 is 30uA), the second burst data packet (Isig_2 is 180uA), the third burst data packet (Isig_3 is 30uA), the fourth burst data packet (Isig_4 is 300uA), the fifth burst data packet (Isig_5 is 30uA), the sixth burst data packet (Isig_6 is 600uA), the seventh burst data packet (Isig_7 is 30uA), the eighth burst data packet (Isig_8 is 900uA), the ninth burst data packet (Isig_9 is 2700uA), and the tenth burst data packet (Isig_10 is 30uA). FIG. 10A to FIG. 10JIt can be seen that the burst response stabilization time of the transimpedance amplifier of the embodiment of the present invention is about 60ns, and has a fast burst response capability.

[0117] Fig.11 Yes Figure 1 The schematic diagram of transient simulation results of input and output signals of each stage of the transimpedance amplifier is shown in FIG. 1 , where the input current signal / R1 / PLUS size and input conditions of the transimpedance amplifier under each burst packet are the same as those of FIG. Figure 2 Exactly the same as in . Figures 12A to 12J They are Fig.11 The eye diagram of the differential output transient signal (VT(" / OUTPdie")-VT(" / OUTNdie")) of the transimpedance amplifier in each burst packet data period in the signal transient simulation results shown. Fig.11 and Figures 12A to 12J It can be seen that the burst mode input current range supported by the transimpedance amplifier of the embodiment of the present invention can reach 0 to 2700 uA, achieving a large dynamic range.

[0118] An embodiment of the present invention further provides an optical module, comprising the aforementioned transimpedance amplifier.

[0119] In the description of the present invention, it should be noted that the terms "upper", "lower", etc. indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific position, be constructed and operated in a specific position, and therefore cannot be understood as a limitation on the present invention. Unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be an indirect connection through an intermediate medium, or it can be a connection between the two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to the specific circumstances.

[0120] It should be noted that, in the present invention, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0121] The above description is only a specific embodiment of the present invention, so that those skilled in the art can understand or implement the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but should conform to the widest scope consistent with the principles and novel features of the present invention.

Claims

1. A transimpedance amplifier, characterized in that: include: Front-end circuit, multi-stage filtering and voltage stabilization circuit, differential amplifier buffer circuit and feedback control circuit; The front-end circuit is connected to the photodetector, the multi-order filtering and voltage stabilizing circuit and the differential amplifier buffer circuit, and is used to convert the output photocurrent signal of the photodetector into an analog voltage signal; The multi-order filtering and voltage stabilizing circuit is connected to the feedback control circuit and the differential amplifier buffer circuit, and is used to process the output signal of the front-end circuit and output a mean value signal to the feedback control circuit and the differential amplifier buffer circuit; The feedback control circuit is connected to the front-end circuit and is used to control the front-end circuit according to an external reset signal and an output signal of the multi-order filtering and voltage stabilizing circuit, so that the output signal of the front-end circuit changes with the sudden change of the input light signal of the light detector.

2. The transimpedance amplifier according to claim 1, characterized in that: The front-end circuit includes a current extraction unit, a single-ended inverting amplifier, and a variable feedback resistor. The input ends of the current extraction unit and the single-ended inverting amplifier are connected to the photodetector, the output end of the single-ended inverting amplifier is connected to the multi-order filtering and voltage stabilizing circuit and the differential amplifier buffer circuit, the input end and the output end of the variable feedback resistor are connected to the output end and the input end of the single-ended inverting amplifier correspondingly, and the control end of the current extraction unit and the control end of the variable feedback resistor are connected to the feedback control circuit; The feedback control circuit is used to control the control end of the current extraction unit and the control end of the variable feedback resistor according to the external reset signal and the output signal of the multi-order filtering and voltage stabilizing circuit, so that the output signal of the output end of the single-ended inverting amplifier changes with the sudden change of the input light signal of the light detector.

3. The transimpedance amplifier according to claim 2, characterized in that: The multi-order filtering and voltage stabilization circuit includes a multi-order filter and a stabilizer, the input end of the multi-order filter is connected to the output end of the single-ended inverting amplifier, the first output end of the multi-order filter is connected to the input end of the stabilizer, the second output end of the multi-order filter is connected to the input end of the feedback control circuit, and the output end of the stabilizer is connected to the differential amplifier buffer circuit.

4. The transimpedance amplifier according to claim 3, characterized in that: The feedback control circuit includes an analog-to-digital converter, a digital logic control circuit, a digital-to-analog converter, a load circuit, and a transimpedance gain control signal generating circuit connected in sequence; The analog-to-digital converter is used to monitor the output signal of the multi-order filter in real time according to the external reset signal, and perform analog-to-digital conversion to obtain a multi-bit digital signal and output it to the digital logic control circuit; The digital logic control circuit is used to process the multi-bit digital signal according to a preset logic algorithm and then output it to the digital-to-analog converter; The digital-to-analog converter is used to perform digital-to-analog conversion on the multi-bit digital signal processed by the digital logic control circuit to obtain a corresponding analog current signal, and output it to the load circuit; The load circuit is used to convert the analog current signal output by the digital-to-analog converter into an analog voltage signal, and output it to the control end of the current extraction unit and the transimpedance gain control signal generating circuit; The transimpedance gain control signal generating circuit is used for processing the analog voltage signal and outputting it to the control end of the variable feedback resistor.

5. The transimpedance amplifier according to claim 4, characterized in that: The digital logic control circuit comprises a comparison reference value setting unit, a digital comparison logic unit and a control processing unit, wherein the comparison reference value setting unit is connected to the digital comparison logic unit, the digital comparison logic unit is connected to the control processing unit, and the control processing unit is connected to the digital-to-analog converter; The output terminal of the comparison reference value setting unit is used to output the reference reference value to the reference reference value input terminal of the digital comparison logic unit; The digital comparison logic unit is used to compare the multi-bit digital signal input by the analog-to-digital converter with the reference base value input by the digital comparison logic unit, and output the comparison result to the control processing unit; The control processing unit is used for processing the comparison result according to a preset logic algorithm and then outputting it to the digital-to-analog converter.

6. The transimpedance amplifier according to claim 3, characterized in that: The multi-order filter is a second-order low-pass filter or an N-order low-pass filter, where N is an integer greater than 2.

7. The transimpedance amplifier according to claim 2, characterized in that: The current extraction unit adopts a MOS tube.

8. The transimpedance amplifier according to claim 1, characterized in that: The differential amplifier buffer circuit comprises a first differential amplifier, a second differential amplifier and an output buffer connected in sequence; The first differential amplifier is used to amplify the output signal of the front-end circuit and the output signal of the multi-order filtering and voltage stabilizing circuit, convert them into a pair of differential signals, and then output them to the second differential amplifier; The second differential amplifier is used to amplify the differential signal output by the first differential amplifier again and then output it to the output buffer; The output buffer is used to transmit the differential signal output by the second differential amplifier to the differential output terminal of the transimpedance amplifier and provide impedance matching.

9. The transimpedance amplifier according to claim 8, characterized in that: Also includes: A correction circuit, wherein the input end of the correction circuit is connected to the differential output end of the output buffer, the output end of the correction circuit is connected to the differential control end of the first differential amplifier, and the correction circuit is used to correct the differential output signal of the output buffer according to an external reset signal.

10. An optical module, characterized in that: Comprising: a transimpedance amplifier as described in any one of claims 1-9.

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