Amplifier with second harmonic termination

Abstract

The invention relates to an amplifier configured to amplify a signal within a given operating frequency. The invention also relates to an amplifier system and a Doherty amplifier. The invention proposes one or more resonant networks connected to the input terminals of the transistors of the amplifier, each resonant network includes a first inductor disposed between the input terminal and the intermediate node, a first capacitor disposed between the intermediate node and ground, and a series network including a second inductor and a second capacitor disposed between the intermediate node and ground. According to the invention, the susceptance presented by the one or more resonant networks at the input terminals counteracts the input susceptance of the transistor at frequencies within the operating band. Further, each resonant network exhibits an RF short circuit at a second harmonic, the respective fundamental wave of which is located within the operating frequency band.

Description

Technical Field

[0001] The invention relates to an amplifier configured to amplify signals within a given operating frequency band. The invention also relates to an amplifier system, and a Doherty amplifier comprising such an amplifier or amplifier system. Background Art

[0002] Recently, Gallium Nitride field-effect transistors (GaN-FETs) have become a promising candidate for use as power transistors in mobile communication base stations. When compared to more mature technologies such as laterally diffused metal-oxide-semiconductor (LDMOS) transistors, GaN-FETs offer high power density at relatively high frequencies.

[0003] It is known in the art that the performance of a GaN-FET depends greatly on the termination at harmonic frequencies. For example, the impedance presented at the gate and drain of a GaN-FET at the second harmonic is particularly important.

[0004] Regarding the harmonic termination at the input, it is known to use a double low-pass matching network connected to the gate of the GaN-FET. The double low-pass matching network comprises two parts in series, each of which comprises a series inductor and a parallel capacitor. These matching networks can be tuned so that impedance matching is obtained at the fundamental, while at the second harmonic, a short circuit is presented at the gate of the GaN-FET. The input impedance of the GaN-FET is mainly determined by the gate resistance and the gate-source capacitance.

[0005] Applicants have found that the bandwidth possible using the double low-pass approach is not always satisfactory.

[0006] US2023 / 216452 A1 discloses a radio frequency (RF) amplifier according to its abstract, which includes: an amplifier input, a transistor die having a transistor and a transistor input terminal, a fundamental frequency impedance matching circuit coupled between the amplifier input and the transistor input terminal, and a harmonic frequency termination circuit coupled between the transistor input terminal and the ground reference node. The harmonic frequency termination circuit includes a first inductor coupled between the transistor input terminal and a first node, and an energy storage circuit coupled between the first node and the ground reference node. The energy storage circuit includes a first capacitor coupled between the first node and the ground reference node and a second inductor coupled between the first node and the ground reference node. The energy storage circuit is configured to shunt signal energy at or near the second harmonic frequency, while acting as an open circuit to signal energy at the fundamental frequency of operation of the RF amplifier. Summary of the invention

[0007] The object of the present invention is to provide a different method by which termination at the second harmonic at the input of a GaN-FET can be achieved. Note that the present invention is not limited to GaN-FETs. The concept of the present invention can be used in general for transistors or amplifiers.

[0008] According to the present invention, the above object can be achieved using an amplifier as defined in claim 1, which is configured to amplify signals within a given operating frequency band f0±BW / 2. Here, frequency f0 refers to the center frequency in the operating frequency band, and BW refers to bandwidth. For example, f0 can be within the range between 0.9 GHz and 6.0 GHz, and BW / f0 can be within the range between 0.01 and 0.15.

[0009] The amplifier according to the present invention comprises a transistor having an input terminal, and at least one resonant network arranged between the input terminal and ground. Each resonant network comprises a first inductor arranged between the input terminal of the transistor and an intermediate node, a first capacitor arranged between the intermediate node and ground, and a series network arranged between the intermediate node and ground. Furthermore, the series network comprises a second inductor and a second capacitor.

[0010] The susceptance presented at the input terminals by at least one resonant network is equal to -B at frequency f1 FET , the frequency f1 is located in the operating frequency band, where B FET is the input susceptance of the transistor at the frequency f1. In addition, for the nth resonant network in at least one resonant network, the series network exhibits series resonance at a frequency less than f1. In addition, for the nth resonant network, the resonant network exhibits series resonance at the input terminal at a frequency 2×f 2n An RF short circuit occurs at the frequency f 2nLocated within the operating frequency band.

[0011] Above, n represents an integer between 1 and N, where N is the total number of resonant networks.

[0012] According to the present invention, each resonant network presents its own RF short circuit at the input terminal of the transistor at the corresponding second harmonic, and the combined resonant networks cancel the input susceptance of the transistor. For example, the first resonant network may present an RF short circuit at 7.0 GHz and a susceptance equal to at 3.6 GHz, while the second resonant network may present an RF short circuit at 7.4 GH z and a susceptance equal to z at 3.6 GH where B FET is the input susceptance of the GaN-FET at 3.6 GHz. This combination of resonant networks will compensate for the gate-source capacitance of the GaN-FET at 3.6 GHz while also presenting an RF short circuit at 7.0 GHz and 7.4 GH z .

[0013] With the amplifier of the present invention, the impedance matching at the input of the transistor is greatly simplified. More specifically, due to the cancellation of the susceptance, the target impedance of the impedance matching network is real rather than complex. Therefore, the bandwidth for impedance matching is not connected or at least less connected to the bandwidth for harmonic termination.

[0014] In some embodiments, 0.8 < f 2n / f1 < 1.2, preferably, 0.9 < f 2n / f1 < 1.1, more preferably, 0.95 < f 2n / f1 < 1.05. In some embodiments, f 2n = f1. Additionally or alternatively, each resonant network is designed such that at the corresponding frequency f 3n the series network is inductive and resonates with the first capacitor, where 2×f 2n > f 3n > f1.

[0015] In some embodiments, 0.8 < f0 / f1 < 1.2, preferably, 0.9 < f0 / f1 < 1.1, more preferably, 0.95 < f0 / f1 < 1.05. In some embodiments, f0 = f1.

[0016] The amplifier may include at least one bias network for providing a bias voltage to an input terminal of the transistor, wherein each respective bias network is connected to a node between a second inductor and a second capacitor of a respective resonant network. The amplifier may additionally or alternatively include a driver transistor, an output of which is connected to an input terminal of a corresponding transistor via an impedance matching network.

[0017] The general concept of the present invention is Figure 1 , where an amplifier 1 includes a transistor Q1. A driving transistor Q2 is used to drive the transistor Q1 through an impedance matching network 2. The transistor Q1 can be, for example, a GaN-based FET. The amplifier 1 is configured to operate within a given operating frequency band f0±BW / 2. Here, f0=3.6GHz, and BW equals 0.4GHz.

[0018] exist Figure 1 In the figure, the impedance behavior of transistor Q1 at its input terminals is represented by the input capacitance Cgs, which is in series with the input resistance Rg. The input admittance Y of Q1 can be written as the sum of the input conductance G and the input susceptance B:

[0019] Equation 1

[0020]

[0021] The above formula is reduced to:

[0022] Equation 2

[0023] Y=G+jB≈jωCgs+ω 2 Cg 2 R

[0024] In the following, the input susceptance at frequency f1 will be referred to as B FET .

[0025] A single resonant network RN is arranged between the input terminal of Q1 and ground. The resonant network RN includes an inductor L1 arranged between the input terminal of Q1 and an intermediate node N, a first capacitor C1 arranged between the intermediate node N and ground, and a series network SN arranged between the intermediate node N and ground. The series network SN includes a second inductor L2 and a second capacitor C2.

[0026] In the following, component names such as L1 and C1 will also be used to indicate relevant electrical parameters, for example, inductance L1 and capacitance C1, respectively.

[0027] The series network SN at frequency f res The series resonance is shown at the frequency f res Given by:

[0028] Equation 3

[0029]

[0030] Amplifier 1 is designed so that f res <f1. For example, f res <0.1×f1. Therefore, for frequencies in the operating frequency band, the series network SN is inductive. More specifically, the effective inductance L2 of the series network SN in the operating frequency band is * It can be calculated from the following formula:

[0031] Equation 4

[0032]

[0033] The series network SN will show parallel resonance with capacitor C1 at frequency f3, which is given by:

[0034] Equation 5

[0035]

[0036] The amplifier 1 is designed so that the combination of the series network SN and the capacitor C1 will be inductive for frequencies in or close to the operating band. The effective inductance Leff of the combination is equal to:

[0037] Equation 6

[0038]

[0039] Therefore, for frequency f3>f>f res , the total inductance Ltot of the resonant network RN is equal to:

[0040] Equation 7

[0041] Ltot(f)=Leff(f)+L1

[0042] The resonant network RN is designed so that the susceptance associated with the total inductance Ltot(f1) at frequency f1 is equal to the inverse of the effective input susceptance of Q1, i.e., -B FET For ωCgRg<<1, this yields:

[0043] Equation 8

[0044]

[0045] Based on the above formula, Ltot(f1) can be calculated using the following formula:

[0046] Equation 9

[0047]

[0048] According to the invention, the resonant network RN is designed so that the frequency 2×f2 presents an RF short circuit at the input terminals of Q1. This is achieved when Leff(2f2)=-L1:

[0049] Equation 10

[0050]

[0051] Assume f res <<2f2, then the above formula is reduced to:

[0052] Equation 11

[0053]

[0054] Therefore, using the resonant network RN configured as described above, it is possible to A) eliminate or mitigate the negative effects of Cgs in the operating frequency band, and B) present an RF short circuit at the second harmonic frequency.

[0055] Figure 1 Also shown is a bias network BN connected to a node between capacitor C2 and inductor L2. More specifically, capacitor C2 has a ground terminal and a non-ground terminal, wherein the bias network BN is connected to the non-ground terminal.

[0056] The bias network BN is configured to receive a DC supply voltage V1 at an input node. This same node is RF shorted using capacitor C3. This low RF impedance is transformed by a quarter wavelength transformer 3 or its lumped equivalent to an RF open circuit at a frequency within the operating band.

[0057] Figure 2 It shows that Figure 1 The input reflection coefficient S1 is determined at the input terminal of transistor Q1 versus frequency, assuming that the input behavior of transistor Q1 is completely determined by Rg and Cgs. A sharp decrease in S1 can be observed at 7.2 GHz, which corresponds to an RF short circuit present at twice the operating frequency f2 = 2f0. Furthermore, in this example f0 = f1, so that two Cgs are compensated at frequency f0 and an RF short circuit is present at the second harmonic frequency.

[0058] To allow wideband operation, objectives A) and B) may be met at different frequencies f). More specifically, f1≠f2. Furthermore, objectives A) and B) need not be achieved at frequency f0.

[0059] In addition to the above, multiple resonant networks can be connected to the input terminals. In this case, a separate frequency can be designed for each resonant network at which an RF short circuit is presented at the input terminals of Q1. For example, the first resonant network can be composed of a frequency f 21 and f1, and the second resonant network can be characterized by the frequency f 22 and f1, where f 21 and f 22 The corresponding frequency f2 can be determined using Equation 10. The RF short circuit at the second harmonic is implemented individually for each resonant network. Therefore, the frequency at which the nth resonant network among the N resonant networks will present an RF short circuit is called 2×f 2n However, the combined resonant network will cancel the input susceptance of transistor Q1.

[0060] The amplifier may include a substrate and a semiconductor die on which the transistor is integrated. The transistor may include a first bonding component electrically connected to an input terminal of the transistor. The first inductor of each resonant network may be at least partially formed by one or more bonding wires physically connected to the first bonding component. The substrate may be in the form of a printed circuit board, a multi-layer laminate, a lead frame, etc.

[0061] The amplifier may also include another die, at least the first capacitor of each resonant network is arranged on the other die, wherein the first terminal of the first capacitor is electrically connected to a second bonding component arranged on the other die, wherein the other end of the one or more bonding wires is physically connected to the second bonding component, and wherein the second terminal of the first capacitor is configured to be grounded during operation. The first capacitor can be a metal-insulator-metal capacitor integrated on the other die. Additionally or alternatively, the other die can be a semiconductor die, such as a silicon die. Such another die can be configured to integrate only passive components.

[0062] The second inductor may be integrated on another die, wherein the first end of the second inductor is connected to the first terminal of the first capacitor. The second capacitor may be integrated on another die, wherein the first terminal of the second capacitor is connected to the second end of the second inductor, and wherein the second terminal of the second capacitor is configured to be grounded during operation. The second capacitor may be a high density capacitor, such as a deep trench capacitor.

[0063] Another die may be mounted on a die pad arranged on the substrate, wherein the die pad is configured to be electrically grounded during operation. The other die may have a conductive substrate and / or a substrate provided with a via. In this case, the second terminal of the first capacitor and / or the second terminal of the second capacitor may be configured to be grounded during operation through the conductive substrate or through a via in the substrate.

[0064] The impedance matching network may be at least partially arranged on the other die. For example, the impedance matching network may include a shunt capacitor arranged on the other die.

[0065] According to a second aspect, the invention provides an amplifier system comprising a first amplifier and a second amplifier, wherein both the first amplifier and the second amplifier comprise amplifiers as defined above. Furthermore, the output terminals of the transistors of the first amplifier and the output terminals of the transistors of the second amplifier may be short-circuited to each other, and the input terminals of the transistors of the first amplifier and the input terminals of the transistors of the second amplifier may be electrically connected to each other via a resistive connection. The resistive connection ensures that the transistors of the first amplifier and the transistors of the second amplifier are driven symmetrically.

[0066] The transistors of the first amplifier and the transistors of the second amplifier may be arranged on the same semiconductor die. In this case, the transistors of the first amplifier may include a plurality of first input fingers connected to a first junction component of the first amplifier, and the transistors of the second amplifier may include a plurality of second input fingers connected to a first junction component of the second amplifier. In addition, the first junction component of the first amplifier and the first junction component of the second amplifier are electrically connected to each other via a resistive connection.

[0067] In another embodiment, the first amplifier and the second amplifier may use the same other die. In this case, the impedance matching network for the first amplifier may include a first matching capacitor arranged on the other die and having a non-ground terminal and a ground terminal, and one or more bonding wires extending between the non-ground terminal of the first matching capacitor and the first bonding component of the first amplifier. Similarly, the impedance matching network for the second amplifier may include a second matching capacitor arranged on the other die and having a non-ground terminal and a ground terminal, and one or more bonding wires extending between the non-ground terminal of the second matching capacitor and the first bonding component of the second amplifier. The first matching capacitor and the second matching capacitor may be combined into a single matching capacitor arranged on the other die. The single matching capacitor may be arranged between the first capacitor of the first amplifier and the first capacitor of the second amplifier.

[0068] According to a third aspect, the present invention provides a Doherty amplifier, the Doherty amplifier comprising a Doherty splitter configured to split a signal to be amplified into a main signal and a peak signal, a main amplifier configured to amplify the main signal, a peak amplifier configured to amplify the peak signal, and a Doherty combiner for combining the amplified main signal and the amplified peak signal. At least one of the main amplifier and the peak amplifier comprises an amplifier or an amplifier system as defined above. BRIEF DESCRIPTION OF THE DRAWINGS

[0069] Next, the present invention will be described in more detail with reference to the accompanying drawings, in which the same reference numerals will be used to refer to the same or similar components, and in which:

[0070] Figure 1 The general concept of the present invention is shown;

[0071] Figure 2 Shows the corresponding Figure 1 Electrical properties;

[0072] Figure 3 An embodiment of an amplifier system according to the present invention is shown; and

[0073] Figure 4 Shows Figure 3 The actual implementation method of the embodiment. DETAILED DESCRIPTION

[0074] exist Figure 3 , an amplifier system 100 is shown, the amplifier system comprising an amplifier 1A and an amplifier 1B, each of which is configured as Figure 1 Amplifier 1 shown in FIG. Figure 3 Also shown is a bias network for biasing the drains of transistors Q1A, Q1B, which may be GaN-FETs. The bias network comprises a shunt capacitor C5, the non-grounded terminal of which is connected to a voltage source V2, and which is connected to the drains of Q1A, Q1B via a quarter-wave transformer 4 or its lumped equivalent. Furthermore, the gate-source capacitance and gate resistance of these transistors are indicated as Cgs1, Cgs2 and Rg1, Rg2, respectively. The resonant networks RN1, RN2 and the bias networks BN1, BN2 are shown only schematically.

[0075] The amplifier system 100 includes a resistor Rc connected between the gates of the transistors Q1, Q2. The resistor prevents or limits having different gate voltages.

[0076] The amplifier system 100 also includes a driver transistor Q2 and an interstage matching network formed by inductors L4, L3A, L3B and capacitor C4. Here, the interstage matching network and driver transistor Q2 can be considered as two separate branches that have been partially merged, where each branch includes a driver transistor and an interstage matching network for a specific amplifier 1A, 1B.

[0077] Figure 4 An implementation of the amplifier system 100 is shown, wherein Figure 4 Not shown in Figure 3 Each component in .

[0078] The amplifier system 100 includes a substrate 10 in the form of a multi-layer laminate on which a GaN semiconductor die 11 , a first silicon semiconductor die 12 , and a second silicon semiconductor die 13 are mounted.

[0079] The GaN die 11 includes transistors Q1A and Q1B. The drains of the transistors Q1A and Q1B are connected to a drain bonding strip 14, which is connected to a bonding strip 15 on the laminate 10 through one or more bonding wires 16. The bonding strip 15 is connected to a signal pad 17 arranged on the back side of the laminate 10 through one or more vias (not shown).

[0080] The drain bond strip 14 is connected to a plurality of drain fingers 18. Transistors Q1A, Q1B each include a set of individual gate fingers 19, which are connected to gate bond strips 20A, 20B, respectively. A thin film resistor 21 connects the gate bond strips 20A, 20B.

[0081] The bonding strips 20A, 20B are connected to the non-grounded terminals of the metal-insulator-metal capacitors 23A, 23B integrated on the first silicon die 12 via one or more bonding wires 22A, 22B. The other terminals of these capacitors are electrically grounded. For example, the semiconductor substrate of the silicon die 12 can be conductive, or the substrate can be provided with vias. Here, it should be noted that the silicon die 12 is mounted on a die pad (not shown) on the laminate 10, which is electrically grounded during operation. For example, the laminate 10 may include a ground via or a metal coin that connects a large ground pad (not shown) on the back of the laminate 10 to the die pad. Note that the die pad is also used for the dies 11, 13.

[0082] Each capacitor 23A, 23B is connected to a non-grounded terminal of a deep trench capacitor 25A, 25B through an integrated inductor 24A, 24B. The other terminal of the capacitor 25A, 25B is grounded during operation.

[0083] At the nodes between the inductors 24A, 24B and the capacitors 25A, 25B, there is connected a bias network comprising a bond wire 26 connected to a bond pad 27 on the laminate 10. The bond pad 27 is connected to a pad 28 on the back side of the laminate 10.

[0084] Silicon die 12 also includes a shunt capacitor 29 which is only Figure 4Schematically shown in FIG. The non-ground terminal of capacitor 29 is connected to gate bonding strips 20A, 20B using bonding wires 30A, 30B, respectively. The terminal is also connected to the drain bonding strip 31 of the silicon LDMOS transistor Q2 on the silicon die 13 through one or more bonding wires 32. The gate bonding strip 33 of Q2 is connected to the bonding strip 35 on the laminate 10 through one or more bonding wires 34. The bonding strip 35 is connected to the pad on the back of the laminate 10.

[0085] In amplifier system 100, bonding wire 22A corresponds to Figure 1 The first inductor L1, the capacitor 23A corresponds to the capacitor C1, the inductor 24A corresponds to the inductor L2, and the capacitor 25A corresponds to the capacitor C2.

[0086] In this embodiment, the silicon die 13 may be replaced by another GaN die on which the GaN drive transistor is arranged. In addition, the silicon die 12 may be replaced by another die, provided that various capacitive components and inductive components may be implemented on such a die.

[0087] In the above, the present invention has been explained using the detailed embodiments of the present invention. However, the present invention is not limited to these embodiments. On the contrary, various modifications are possible without departing from the scope of the present invention as defined by the appended claims and their equivalents.

Claims

1. An amplifier (1) configured to amplify a signal within a given operating frequency band f0±BW / 2 having a center frequency f0 and a bandwidth BW, wherein: The amplifier comprises a transistor (Q1) having an input terminal and at least one resonant network (RN; RN1, RN2) arranged between the input terminal and ground, wherein each resonant network comprises: a first inductor (L1) arranged between the input terminal and an intermediate node (N); a first capacitor (C1), the first capacitor being arranged between the intermediate node and ground; a series network (SN) arranged between the intermediate node and ground, the series network comprising a second inductor (L2) and a second capacitor (C2); wherein the susceptance presented by the at least one resonant network at the input terminal is equal to -B at frequency f1 FET , the frequency f1 is located in the operating frequency band, where B FET is the input susceptance of the transistor at the frequency f1; Wherein, for the nth resonant network in the at least one resonant network: The series network exhibits series resonance at a frequency less than f1; At frequency 2×f 2n At the input terminal, the resonant network presents an RF short circuit, where the frequency f 2n is within the operating frequency band; Here, n represents an integer between 1 and N, and N is the total number of resonant networks.

2. The amplifier according to claim 1, wherein 0.8 <f 2n / f1<1.2, more preferably, 0.9 <f 2n / f1<1.

1.

3. The amplifier according to claim 2, wherein: Each resonant network is designed so that at the corresponding frequency f 3n At, the series network is inductive and resonates with the first capacitor, where 2×f 2n >f 3n >f1.

4. The amplifier according to claim 1, further comprising at least one bias network (BN) for providing a bias voltage to the input terminal of the transistor, wherein: Each respective bias network is connected to a node between the second inductor and the second capacitor of the respective resonant network.

5. The amplifier according to claim 1, further comprising a driving transistor (Q2), the output terminal of the driving transistor being connected to the input terminal of the transistor through an impedance matching network (2).

6. The amplifier according to claim 1, comprising: base(10); a semiconductor die (11) on which the transistor is integrated, wherein the transistor comprises a first bonding component electrically connected to the input terminal of the transistor; Wherein the first inductor of each resonant network is at least partially formed by one or more bonding wires, and the one or more bonding wires are physically connected to the first bonding component.

7. The amplifier of claim 6, further comprising another die, at least the first capacitor of each resonant network being arranged on the other die, wherein: A first terminal of the first capacitor is electrically connected to a second bonding component disposed on the other die, wherein another end of the one or more bonding wires is physically connected to the second bonding component, and wherein a second terminal of the first capacitor is configured to be grounded during operation.

8. The amplifier according to claim 7, wherein The first capacitor is a metal-insulator-metal capacitor integrated on the other die.

9. The amplifier according to claim 7, wherein: The other die is a semiconductor die, such as a silicon die.

10. The amplifier according to claim 7, wherein: The second inductor is integrated on the other die, wherein a first end of the second inductor is connected to a first terminal of the first capacitor.

11. The amplifier according to claim 10, wherein The second capacitor is integrated on the other die, wherein a first terminal of the second capacitor is connected to a second end of the second inductor, and wherein a second terminal of the second capacitor is configured to be grounded during operation.

12. The amplifier according to claim 11, wherein The second capacitor is a high density capacitor, such as a deep trench capacitor.

13. The amplifier according to claim 7, wherein: The other die is mounted on a die pad, which is arranged on the substrate, wherein the die pad is configured to be electrically grounded during operation, wherein the other die has a conductive substrate and / or a substrate provided with a via, wherein the second terminal of the first capacitor and / or the second terminal of the second capacitor is configured to be grounded through the conductive substrate or through the via in the substrate during operation.

14. The amplifier according to claim 7, further comprising a driving transistor (Q2), the output terminal of the driving transistor being connected to the input terminal of the transistor through an impedance matching network (2), wherein: The impedance matching network is at least partially disposed on the other die.

15. The amplifier according to claim 1, wherein The transistor is a gallium nitride based field effect transistor GaN FET, and wherein the input terminal of the transistor is a gate of the GaN FET.

16. The amplifier according to claim 1, wherein f0 is within the range between 0.9 GHz and 6.0 GHz, and wherein BW / f0 is within the range between 0.01 and 0.

15.

17. An amplifier system, comprising a first amplifier and a second amplifier, wherein: Both the first amplifier and the second amplifier include amplifiers as defined in claim 1, wherein an output terminal of the transistor of the first amplifier and an output terminal of the transistor of the second amplifier are short-circuited to each other, and wherein an input terminal of the transistor of the first amplifier and an input terminal of the transistor of the second amplifier are electrically connected to each other via a resistance connection.

18. The amplifier system of claim 17, wherein: The amplifier of the first amplifier and the amplifier of the second amplifier each include: base(10); A semiconductor die (11) on which the transistor is integrated, wherein the transistor comprises a first bonding component electrically connected to an input terminal of the transistor; wherein the first inductor of each resonant network is at least partially formed by one or more bond wires, the one or more bond wires being physically connected to the first bond component; wherein the transistors of the first amplifier and the transistors of the second amplifier are arranged on the same semiconductor die, wherein the transistors of the first amplifier include a plurality of first input fingers connected to a first bonding component of the first amplifier, wherein the transistors of the second amplifier include a plurality of second input fingers connected to a first bonding component of the second amplifier, wherein the first bonding component of the first amplifier and the first bonding component of the second amplifier are electrically connected to each other via the resistance connection.

19. The amplifier system of claim 18, wherein: The amplifier of the first amplifier and the amplifier of the second amplifier each further include: A driving transistor (Q2), the output end of the driving transistor being connected to the input terminal of the transistor via an impedance matching network (2); another die, at least a first capacitor of each resonant network being disposed on the other die, wherein a first terminal of the first capacitor is electrically connected to a second bonding component disposed on the other die, wherein another end of the one or more bonding wires is physically connected to the second bonding component, and wherein a second terminal of the first capacitor is configured to be connected to ground during operation; wherein the first amplifier and the second amplifier use the same another die; Wherein, the impedance matching network for the first amplifier comprises: a first matching capacitor disposed on the other die, the first matching capacitor having a non-ground terminal and a ground terminal; one or more bond wires extending between a non-ground terminal of the first matching capacitor and a first bond component of the first amplifier; Wherein, the impedance matching network for the second amplifier comprises: a second matching capacitor disposed on the other die, the second matching capacitor having a non-ground terminal and a ground terminal; one or more bond wires extending between a non-ground terminal of the second matching capacitor and a first bond component of the second amplifier; The first matching capacitor and the second matching capacitor are combined into a single matching capacitor, wherein the single matching capacitor is arranged between a first capacitor of the first amplifier and a first capacitor of the second amplifier.

20. A Doherty amplifier, comprising: a Doherty splitter configured to separate the signal to be amplified into a main signal and a peak signal; a main amplifier configured to amplify the main signal; a peak amplifier configured to amplify the peak signal; and a Doherty combiner for combining the amplified main signal and the amplified peak signal; Wherein, at least one of the main amplifier and the peak amplifier comprises an amplifier as defined in claim 1.

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