Built-in filtering anti-single event upset trigger structure applied to silicon-on-insulator process

By designing a built-in filtered anti-single-particle flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip f

CN120017014APending Publication Date: 2025-05-16BEIJING MXTRONICS CORP +1
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Patent Information

Application Number
CN202411892756.1
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2024-12-20
Publication Date
2025-05-16

AI Technical Summary

Technical Problem

The prior art is difficult to effectively reduce the problem of single-particle soft errors caused by high-energy charged particles in space radiation environments, especially in silicon-on-insulator SOI process.

Method used

A built-in filter anti-single-particle flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip flip f

Benefits of technology

It effectively reduces the single-particle soft error problems caused by single-particle transients and single-particle flips, reduces the reinforcement overhead, and maintains the timing overhead on the critical path of data transmission.

✦ Generated by Eureka AI based on patent content.

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Abstract

The invention discloses a built-in filtering single event upset resistant trigger structure applied to a silicon-on-insulator process. Comprising a first-stage stacked clock control circuit, a first-stage latch inverter, a first-stage replica inverter, a delay circuit, a first-stage data signal stacked circuit, a second-stage stacked clock control circuit, a second-stage latch inverter, a second-stage replica inverter, a second-stage data signal stacked circuit and an output inverter circuit. The stacked clock control circuit is used for controlling the working state of the master-slave latch and ensuring that data is correct after the master-slave latch is subjected to single-particle bombardment; the latch inverter is used for transmitting and latching data; the replica inverter is used for providing redundant signals; the delay circuit is used for filtering SET pulses by using delay signals; and the data signal stacking circuit is used for realizing data latching and ensuring that the data is correct after the latch is subjected to single-particle bombardment. The method effectively reduces the single-particle soft error problem, is developed based on the silicon-on-insulator process characteristics, effectively reduces the reinforcement overhead, and is easy to implement.
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Description

Technical Field

[0001] The present application belongs to the technical field of radiation hardened circuits, and in particular to a built-in filtering single event upset resistant trigger circuit applied to a silicon on insulator (SOI) process. Background Art

[0002] High-energy charged particles in the space radiation environment can affect the performance of integrated circuits, especially single-particle soft errors caused by high-energy particle radiation, which can cause malfunctions of electronic components. Since the buried oxide layer in the silicon-on-insulator (SOI) process prevents the collection of radiation-generated charges in the wells and substrates of the transistor, the SOI process can effectively reduce the impact of single-particle effects on integrated circuits. However, with the further reduction of process dimensions and the decrease in power supply voltage, a reinforced design is required to achieve reliable application of integrated circuits in space.

[0003] The inducing mechanisms of single-particle soft errors mainly include single-event upset (SEU) and single-event transient (SET). Single-event upset refers to the generation of a large amount of charge in storage circuits due to the interaction between high-energy charged particles and semiconductor materials. If the critical charge amount that causes the stored data to flip is exceeded, the state of the storage node will be undesirably flipped, and SEU will occur. Single-particle transients occur in logic circuits, and charges are also generated by high-energy particles, which produce erroneous voltage states at the output nodes, and SET will occur. If a certain timing relationship is met, the erroneous voltage state will be captured by a trigger, etc., and the transmission will cause a single-particle upset, forming a soft error. Summary of the invention

[0004] The technical problem solved by the present invention is: to overcome the deficiencies of the prior art, to provide a built-in filtering single event upset resistant trigger structure applied to silicon on insulator SOI process, and to design and reinforce the SEU inside the trigger and the SET at the input end.

[0005] The technical solution of the present invention is:

[0006] A built-in filtering single-particle upset-resistant flip-flop structure applied to silicon-on-insulator technology, comprising: a first-stage stacked clock control circuit, a first-stage latched inverter, a first-stage replica inverter, a delay circuit, a first-stage data signal stacking circuit, a second-stage stacked clock control circuit, a second-stage latched inverter, a second-stage replica inverter, a second-stage data signal stacking circuit and an output inverter circuit;

[0007] The data input end of the first-stage stacked clock control circuit receives an external input signal D, the first clock input end receives an external clock signal CLK, the second clock input end receives an external clock signal CLKN, and the output end is simultaneously connected to the first-stage latch inverter input end, the first-stage replica inverter input end, and the output end of the first-stage data signal stacking circuit;

[0008] The output end of the first-stage latch inverter is connected to the data input end of the second-stage stack clock control circuit and the second data input end of the first-stage data signal stack circuit;

[0009] The output end of the first stage replica inverter is connected to the input end of the delay circuit;

[0010] The output end of the delay circuit is connected to the first data input end of the first-stage data signal stacking circuit;

[0011] The first clock input terminal of the first-stage data signal stacking circuit receives an external clock signal CLKN, and the second clock input terminal receives an external clock signal CLK;

[0012] The first clock input end of the second-stage stacked clock control circuit receives the external clock signal CLKN, the second clock input end receives the external clock signal CLK, and the output end is simultaneously connected to the second-stage latch inverter input end, the second-stage replica inverter input end, and the output end of the second-stage data signal stacking circuit;

[0013] The output end of the second-stage latch inverter is connected to the input end of the output inverter circuit and the second data input end of the second-stage data signal stacking circuit;

[0014] The output end of the second-stage replica inverter is connected to the first data input end of the second-stage data signal stacking circuit;

[0015] The first clock input terminal of the second-stage data signal stacking circuit receives an external clock signal CLK, and the second clock input terminal receives an external clock signal CLKN;

[0016] The output terminal of the output inverter circuit outputs a signal Q.

[0017] Preferably, the first-stage latch inverter, the first-stage replica inverter, the delay circuit, and the first-stage data signal stacking circuit constitute a master latch; the second-stage latch inverter, the second-stage replica inverter, and the second-stage data signal stacking circuit constitute a slave latch;

[0018] The first-level stacked clock control circuit is used to provide data signals to the first-level latch inverter and the first-level replica inverter, and realize the state control of the master latch; the first-level latch inverter is used to realize the data transmission and latching of the master latch; the first-level replica inverter is used to provide redundant signals for the delay circuit; the delay circuit is used to realize SET pulse filtering; the first-level data signal stacking circuit is used to control the latching state of the master latch and realize the correct output of the latch inverter after being bombarded by a single particle; the second-level stacked clock control circuit is used to provide data signals to the second-level latch inverter and the second-level replica inverter, and realize the state control of the slave latch; the second-level latch inverter is used to realize the data transmission and latching of the slave latch; the second-level replica inverter is used to provide redundant signals for the second-level data signal stacking circuit; the second-level data signal stacking circuit is used to control the latching state of the slave latch and realize the correct output of the latch inverter after being bombarded by a single particle; the output inverter circuit is used to realize data signal buffering.

[0019] Preferably, the first-stage stacked clock control circuit includes PMOS transistors P101, P102, P103 and NMOS transistors N101, N102, N103;

[0020] The gate of the PMOS transistor P101 is connected to the gate of the NMOS transistor N101 and serves as a data input terminal of the first-stage stacked clock control circuit to receive an external input signal D. The source of the PMOS transistor P101 is connected to a power supply VDD, and the drain is connected to the source of the PMOS transistor P102. After the gate of the PMOS transistor P102 is connected to the gate of the PMOS transistor P103, the PMOS transistor P102 serves as a first clock input terminal of the first-stage stacked clock control circuit (101) to receive an external clock signal CLK. The drain of the PMOS transistor P102 is connected to the source of the PMOS transistor P103. ; After the drain of the PMOS transistor P103 is connected to the drain of the NMOS transistor N103, it serves as the output terminal C0 of the first-level stacked clock control circuit; after the gate of the NMOS transistor N103 is connected to the gate of the NMOS transistor N102, it serves as the second clock input terminal of the first-level stacked clock control circuit to receive the external clock signal CLKN, and the source of the NMOS transistor N103 is connected to the drain of the NMOS transistor N102; the source of the NMOS transistor N102 is connected to the drain of the NMOS transistor N101, and the source of the NMOS transistor N101 is connected to the power ground GND.

[0021] Preferably, the first-stage latch inverter, the first-stage replica inverter, the second-stage latch inverter, and the second-stage replica inverter have the same structure, and all include a PMOS transistor P201 and an NMOS transistor N201;

[0022] The source of the PMOS transistor P201 is connected to the power supply VDD, the gate of the PMOS transistor P201 is connected to the gate of the NMOS transistor N201 and serves as the input end of the inverter, the drain of the PMOS transistor P201 is connected to the drain of the NMOS transistor N201 and serves as the output end of the inverter; the source of the NMOS transistor N201 is connected to the power ground GND.

[0023] Preferably, the delay circuit is composed of n stages of cascaded inverter units, wherein the first (n-1) stages adopt a stacked inverter structure, and the nth stage adopts a conventional inverter structure;

[0024] Each level of the first (n-1) stacked inverters has the same structure. The m-th stacked inverter includes PMOS transistors P4m1, P4m2, P4m3 and NMOS transistors N4m1, N4m2, N4m3. The gates of the PMOS transistors P4m1, P4m2, P4m3 and the NMOS transistors N4m1, N4m2, N4m3 are connected as the input end of the m-th stacked inverter and connected to the output end of the m-1-th stacked inverter. The source of the PMOS transistor P4m1 is connected to the power supply VDD, and the drain of the PMOS transistor P4m1 is connected to the PMOS transistor P The source of the PMOS transistor P4m2 is connected to the source of the PMOS transistor P4m3; the drain of the PMOS transistor P4m3 is connected to the drain of the NMOS transistor N4m3 and serves as the output of the m-th stacked inverter and is connected to the input of the m+1-th stacked inverter; the source of the NMOS transistor N4m3 is connected to the drain of the NMOS transistor N4m2; the source of the NMOS transistor N4m2 is connected to the drain of the NMOS transistor N4m1; the source of the NMOS transistor N4m1 is connected to the power ground GND; wherein 1<m<n-1;

[0025] The n-th stage inverter of the delay circuit adopts a conventional structure, including a PMOS transistor P4n1 and an NMOS transistor N4n1; the source of the PMOS transistor P4n1 is connected to a power supply VDD, the gate of the PMOS transistor P4n1 is connected to the gate of the NMOS transistor N4n1 and serves as the input end of the n-th stage inverter and is connected to the output end of the (n-1)-th stage stacked inverter, the drain of the PMOS transistor P4n1 is connected to the drain of the NMOS transistor N4n1 and serves as the output end of the delay circuit and is connected to the first input end of the first-stage data signal stacking circuit (105); the source of the NMOS transistor N4n1 is connected to the power ground GND.

[0026] Preferably, the first-level data signal stacking circuit includes PMOS transistors P501, P502, P503 and NMOS transistors N501, N502, N503; the source of the PMOS transistor P501 is connected to the power supply VDD; the gate of the PMOS transistor P501 is connected to the gate of the NMOS transistor N501 and serves as the second data input terminal of the first-level data signal stacking circuit, connected to the output terminal of the first-level latch inverter; the drain of the PMOS transistor P501 is connected to the source of the PMOS transistor P502; the gate of the PMOS transistor P502 is connected to the gate of the NMOS transistor N502 and serves as the first data input terminal of the first-level data signal stacking circuit; the PMOS transistor The drain of P502 is connected to the source of the PMOS transistor P503; the gate of the PMOS transistor P503 serves as a first clock input terminal to receive an external clock signal CLKN; the drain of the PMOS transistor P503 is connected to the drain of the NMOS transistor N503 and serves as an output terminal of the first-level data signal stacking circuit; the gate of the NMOS transistor N503 serves as a second clock input terminal of the first-level data signal stacking circuit to receive an external clock signal CLK, the source of the NMOS transistor N503 is connected to the drain of the NMOS transistor N502; the source of the NMOS transistor N502 is connected to the drain of the NMOS transistor N501; the source of the NMOS transistor N501 is connected to the power ground GND.

[0027] Preferably, the second-stage stacked clock control circuit includes PMOS transistors P601, P602, P603 and NMOS transistors N601, N602, N603; the gate of the PMOS transistor P601 is connected to the gate of the NMOS transistor N601 and then serves as the data input end of the second-stage stacked clock control circuit to connect the master latch output signal C2, the source of the PMOS transistor P601 is connected to the power supply VDD, and the drain of the PMOS transistor P601 is connected to the source of the PMOS transistor P602; the gate of the PMOS transistor P602 is connected to the gate of the PMOS transistor P603 and serves as the second-stage stacked clock control circuit. The first clock input terminal of the circuit receives an external clock signal CLKN, the drain of the PMOS transistor P602 is connected to the source of the PMOS transistor P603; the drain of the PMOS transistor P603 is connected to the drain of the NMOS transistor N603, and serves as the output terminal of the second-level stacked clock control circuit; the gate of the NMOS transistor N603 is connected to the gate of the NMOS transistor N602, and serves as the second clock input terminal of the second-level stacked clock control circuit to receive the external clock signal CLK; the source of the NMOS transistor N602 is connected to the drain of the NMOS transistor N601; the source of the NMOS transistor N601 is connected to the power ground GND.

[0028] Preferably, the second-stage data signal stacking circuit includes PMOS transistors P901, P902, P903 and NMOS transistors N901, N902, N503; the source of the PMOS transistor P901 is connected to the power supply VDD; the gate of the PMOS transistor P901 is connected to the gate of the NMOS transistor N901, and serves as the second data input terminal of the second-stage data signal stacking circuit, connected to the output terminal of the second-stage latch inverter; the drain of the PMOS transistor P901 is connected to the source of the PMOS transistor P902; the gate of the PMOS transistor P902 is connected to the gate of the NMOS transistor N902, and serves as the first data input terminal of the second-stage data signal stacking circuit, connected to the output terminal of the second-stage replica inverter, and the drain of the PMOS transistor P902 is connected to the source of the PMOS transistor P902; the gate of the PMOS transistor P902 is connected to the gate of the NMOS transistor N902, and serves as the first data input terminal of the second-stage data signal stacking circuit, connected to the output terminal of the second-stage replica inverter, and the drain of the PMOS transistor P902 is connected to the gate of the NMOS transistor N902. The gate of the PMOS transistor P903 is connected to the source of the PMOS transistor P903; the gate of the PMOS transistor P903 serves as the first clock input of the second-level data signal stacking circuit to receive the external clock signal CLK; the drain of the PMOS transistor P903 is connected to the drain of the NMOS transistor N903, and serves as the output of the second-level data signal stacking circuit, connected to the output of the second-level stacking clock control circuit; the gate of the NMOS transistor N903 serves as the second clock input of the second-level data signal stacking circuit to receive the external clock signal CLKN, the source of the NMOS transistor N903 is connected to the drain of the NMOS transistor N902; the source of the NMOS transistor N902 is connected to the drain of the NMOS transistor N901; the source of the NMOS transistor N901 is connected to the power ground GND.

[0029] Preferably, the output inverter circuit includes PMOS transistors P111, P112 and NMOS transistors N111, N112; the source of the PMOS transistor P111 is connected to the power supply VDD; the gate of the PMOS transistor P111 is connected to the gate of the NMOS transistor N111, and is connected to the output terminal C5 of the second-stage latch inverter as the input terminal of the output inverter circuit; the drain of the PMOS transistor P111 is connected to the drain of the NMOS transistor N111, the gate of the PMOS transistor P112 and the gate of the NMOS transistor N112; the source of the NMOS transistor N111 is connected to the power supply ground GND; the source of the PMOS transistor P112 is connected to the power supply VDD; the drain of the PMOS transistor P112 is connected to the drain of the NMOS transistor N112, and is used as the output terminal of the output inverter circuit to output the signal Q; the source of the NMOS transistor N112 is connected to the power supply ground GND.

[0030] Compared with the prior art, the present invention provides a built-in filtering anti-single event upset circuit structure applied to SOI process, which has the following advantages:

[0031] 1. The circuit structure designed by the present invention can effectively reduce the single particle soft error problem caused by SET and SEU.

[0032] 2. The present invention is developed based on process characteristics and effectively reduces reinforcement costs. For example, due to the isolation of the well and the substrate by SOI buried oxide, when one of the non-opened MOS tubes in the stacked structure is bombarded by charged high-energy particles, the output node will not flip because the voltage path is blocked by another non-opened device, thereby achieving stacked structure reinforcement and reducing reinforcement costs.

[0033] 3. The filtering inside the main latch in the trigger designed by the present invention is not in the critical path of data transmission, and the timing overhead is small. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 It is a circuit structure principle diagram of the present invention;

[0035] Figure 2 is a structural diagram of a stacked clock control circuit of the present invention;

[0036] Figure 3 is a structural diagram of a latch / replica inverter of the present invention;

[0037] Figure 4 is a structural diagram of a delay circuit of the present invention;

[0038] Figure 5 is a structural diagram of a data signal stacking circuit of the present invention;

[0039] Figure 6 is a structural diagram of an output inverter circuit of the present invention;

[0040] Figure 7 Schematic diagram of the circuit of the present invention. DETAILED DESCRIPTION

[0041] The present application is described in further detail below in conjunction with the accompanying drawings.

[0042] Figure 1The present invention shows a schematic diagram of a built-in filter anti-single-particle upset trigger structure for use in a silicon-on-insulator SOI process. The trigger circuit includes a first-level stacked clock control circuit 101, a first-level latch inverter 102, a first-level replica inverter 103, a delay circuit 104, a first-level data signal stacking circuit 105, a second-level stacked clock control circuit 106, a second-level latch inverter 107, a second-level replica inverter 108, a second-level data signal stacking circuit 109, and an output inverter circuit 110; the output level state flip after a single particle bombardment is avoided by stacking transistor structures, the SEU error inside the trigger is avoided by a data signal stacking circuit, and the SET pulse filtering of the data input terminal is realized based on the embedded filtering structure. The key path of data transmission in the trigger circuit only passes through the stacked clock control circuit, the latch inverter, and the output inverter, and the circuit delay is small.

[0043] The data input terminal of the first-stage stacked clock control circuit 101 receives an external input signal D, the first clock input terminal of the first-stage stacked clock control circuit 101 receives an external clock signal CLK, the second clock input terminal of the first-stage stacked clock control circuit 101 receives an external clock signal CLKN, and the output terminal of the first-stage stacked clock control circuit 101 is connected to the input terminals of the first-stage latch inverter 102 and the first-stage replica inverter 103 and the output terminal of the first-stage data signal stacking circuit 105. This circuit is used to provide a data signal to the inverter and realize the state control of the master latch.

[0044] The output end of the first stage latch inverter 102 is connected to the data input end of the second stage stack clock control circuit 106 and the second data input end of the first stage data signal stack circuit 105. The circuit is composed of inverters and is used to realize master latch data transmission and latching.

[0045] The output terminal of the first stage replica inverter 103 is connected to the input terminal of the delay circuit 104. This circuit is composed of inverters and is used to provide a redundant signal.

[0046] The output end of the delay circuit 104 is connected to the first data input end of the first-stage data signal stacking circuit 105. The circuit is composed of multiple stages of cascade inverters and is used to implement SET pulse filtering.

[0047] The first clock input terminal of the first-stage data signal stacking circuit 105 receives the external clock signal CLKN, and the second clock input terminal of the first-stage data signal stacking circuit 105 receives the external clock signal CLK. The circuit is composed of stacked transistors and is used to control the latch state of the main latch and realize the correct output of the latch inverter after being bombarded by a single particle.

[0048] The first clock input terminal of the second-stage stacked clock control circuit 106 receives the external clock signal CLKN, the second clock input terminal of the second-stage stacked clock control circuit 106 receives the external clock signal CLK, and the output terminal of the second-stage stacked clock control circuit 106 is connected to the input terminals of the second-stage latch inverter 107 and the second-stage replica inverter 108 and the output terminal of the second-stage data signal stacking circuit 109. This circuit is used to provide a data signal to the inverter and realize the state control of the slave latch.

[0049] The output terminal of the second stage latch inverter 107 is connected to the input terminal of the output inverter circuit 110 and the second data input terminal of the second stage data signal stacking circuit 109. This circuit is composed of inverters and is used to realize data transmission and latching from the latch.

[0050] The output terminal of the second-stage replica inverter 108 is connected to the first data input terminal of the second-stage data signal stacking circuit 109. The circuit is composed of inverters and is used to provide a redundant signal.

[0051] The first clock input terminal of the second-stage data signal stacking circuit 109 receives the external clock signal CLK, and the second clock input terminal of the second-stage data signal stacking circuit 109 receives the external clock signal CLKN. The circuit is composed of stacked transistors and is used to control the latch state of the slave latch and realize the correct output of the latch inverter after being bombarded by a single particle.

[0052] The output terminal of the output inverter circuit 110 outputs an output signal Q. The circuit is composed of two stages of cascade inverters and is used to implement data signal buffering.

[0053] Figure 2 The embodiment of the stacked clock control circuit (including the first-level stacked clock control circuit 101 and the second-level stacked clock control circuit 106) is shown. The stacked clock control circuit includes a data input terminal, a first clock input terminal, a second clock input terminal and a data output terminal. The first-level stacked clock control circuit 101 controls the working state of the master latch, and the second-level stacked clock control circuit 106 controls the working state of the slave latch. The circuit structures of the two are the same, and the clock signals are opposite. The function of the stacked clock control circuit is to realize the state control of the master and slave latches and avoid single particle bombardment errors.

[0054] The first-stage stacked clock control circuit 101 is used as an example for description. The first-stage stacked clock control circuit is composed of 6 transistors, namely, PMOS transistors P101, P102, P103 and NMOS transistors N101, N102, N103, and is implemented in a transistor stacking form. The gate of P101 is connected to the gate of N101 and serves as the data input terminal of the first-level stacked clock circuit, the source of P101 is connected to the power supply VDD, and the drain of P101 is connected to the source of P102; the gate of P102 is connected to the gate of P103 and serves as the first clock input terminal of the first-level stacked clock circuit, the drain of P102 is connected to the source of transistor P103; the drain of P103 is connected to the drain of N103 and serves as the output terminal C0 of the stacked clock circuit; the gate of N103 is connected to the gate of N102 and serves as the second clock input terminal of the stacked clock circuit, the source of N103 is connected to the drain of N102; the source of N102 is connected to the drain of N101; the source of N101 is connected to the power ground GND.

[0055] The second-stage stacked clock control circuit 106 includes PMOS transistors P601, P602, P603 and NMOS transistors N601, N602, N603; the gate of the PMOS transistor P601 is connected to the gate of the NMOS transistor N601 and then serves as the data input terminal of the second-stage stacked clock control circuit 106 connected to the master latch output signal C2, the source of the PMOS transistor P601 is connected to the power supply VDD, and the drain of the PMOS transistor P601 is connected to the source of the PMOS transistor P602; the gate of the PMOS transistor P602 is connected to the gate of the PMOS transistor P603 and serves as the second-stage stacked clock control circuit 106. The first clock input terminal receives an external clock signal CLKN, the drain of the PMOS transistor P602 is connected to the source of the PMOS transistor P603; the drain of the PMOS transistor P603 is connected to the drain of the NMOS transistor N603, and serves as the output terminal of the second-level stacked clock control circuit 106; the gate of the NMOS transistor N603 is connected to the gate of the NMOS transistor N602, and serves as the second clock input terminal of the second-level stacked clock control circuit 106 to receive the external clock signal CLK; the source of the NMOS transistor N602 is connected to the drain of the NMOS transistor N601; the source of the NMOS transistor N601 is connected to the power ground GND.

[0056] The implementation principle of the stacked clock control circuit is as follows: the clock control terminals of the first-level and second-level stacked clock control circuits are connected to opposite clock signals. When CLK is low and CLKN is high, the first-level stacked clock control circuit 101 is turned on, the master latch is in transparent mode, and data is transmitted to the master latch; while the second-level stacked clock control circuit 106 is turned off, the data transmission from the latch is blocked, and it is in a latched state. The opposite is true when CLK is high. In the latched state, the SET generated at the input end will not be transmitted to the trigger, and will not be captured by the clock to cause the trigger output to flip.

[0057] In addition, the stacked clock control circuit adopts the form of transistor stacking to avoid output errors caused by single particle bombardment of the control circuit itself. The principle of stacked structure reinforcement is as follows: due to the isolation of the well and the substrate by SOI buried oxide, when one of the non-opened MOS tubes in the stacked structure is bombarded by charged high-energy particles, the output node will not flip because the voltage path is blocked by another non-opened state device.

[0058] Figure 3 The figure shows the implementation form of the inverter unit (including the first-stage latch inverter 102, the first-stage replica inverter 103, the second-stage latch inverter 107, and the second-stage replica inverter 108). The inverter is composed of a PMOS transistor P201 and an NMOS transistor N201; the source of P201 is connected to the power supply VDD, the gate of P201 is connected to the gate of N201 and serves as the input of the inverter, the drain of P201 is connected to the drain of N201 and serves as the output of the inverter; the source of N201 is connected to the power ground GND.

[0059] The latch inverter is used to realize data transmission and latching. In addition, on the basis of the first-stage latch inverter 102 and the second-stage latch inverter 107, the circuit adds a first-stage replica inverter 103 and a second-stage replica inverter 108, and the input and circuit structure of each stage of the replica inverter are the same as those of the latch inverter. The function of the replica inverter is to provide a redundant signal. When any inverter inside the latch is bombarded and data flips, the other inverter can still provide the correct data signal that has not been bombarded, and realize data state recovery in combination with the data signal stacking circuit 105 / 109.

[0060] Figure 41 is an implementation form of the delay circuit 104. The delay circuit 104 is an n-stage cascade inverter unit, which is composed of PMOS transistors P411, P412, P413...P4m1, P4m2, P4m3...P4(n-1)1, P4(n-1)2, P4(n-1)3, P4n1 and NMOS transistors N411, N412, N413...N4m1, N4m2, N4m3...N4(n-1)1, P4(n-1)2, P4(n-1)3, P4n1 (where m and n represent the number of inverter stages, 1<m<n).

[0061] The first (n-1) stacked inverters of the delay circuit (104) have the same structure, which are composed of PMOS transistors P411, P412, P413...P4m1, P4m2, P4m3...P4(n-1)1, P4(n-1)2, P4(n-1)3 and NMOS transistors N411, N412, N413...N4m1, N4m2, N4m3...N4(n-1)1, P4(n-1)2, P4(n-1)3 (1<m<n-1).

[0062] Taking the m-th level stacked inverter as an example, the gates of P4m1, P4m2, P4m3 and N4m1, N4m2, N4m3 are connected as the input of the m-th level stacked inverter, and connected to the output of the m-1-th level stacked inverter. The source of P4m1 is connected to the power supply VDD, and the drain of P4m1 is connected to the source of transistor P4m2; the drain of P4m2 is connected to the source of transistor P4m3; the drain of P4m3 is connected to the drain of transistor N4m3, and serves as the output of the m-th level stacked inverter, and connected to the input of the m+1-th level stack; the source of N4m3 is connected to the drain of transistor N4m2; the source of N4m2 is connected to the drain of transistor N4m1; the source of N4m1 is connected to the power ground GND.

[0063] The n-th stage inverter of the delay circuit 104 adopts a conventional structure, the source of P4n1 is connected to the power supply VDD, the gate of P4n1 is connected to the gate of the transistor N4n1 and serves as the input of the n-th stage inverter, connected to the output of the (n-1)-th stage stacked inverter, the drain of P4n1 is connected to the drain of the transistor N4n1 and serves as the output of the delay circuit 104 and connected to the first input of the first-stage data signal stacking circuit (105); the source of N4n1 is connected to the power ground GND.

[0064] The function of the delay circuit 104 is to implement SET pulse delay based on the delay characteristics of the inverter and to filter out the SET signal at the data end by using a multi-stage cascade structure. The number of cascades of series inverters is determined by the SET pulse width. In addition, the stacked inverter structure in the delay circuit can reduce the probability of errors caused by single particle bombardment of the delay circuit itself.

[0065] Figure 5 The figure shows the implementation form of the data signal stacking circuit (including the first-level data signal stacking circuit 105 and the second-level data signal stacking circuit 109). The data signal stacking circuit includes a first data input terminal, a second data input terminal, a first clock input terminal, a second clock input terminal and a data output terminal. The first-level data signal stacking circuit 105 controls the latching state of the master latch, and the second-level data signal stacking circuit 109 controls the latching state of the slave latch. The circuit structures of the two are the same, and the clock control signals are opposite. The function of the data signal stacking circuit is to realize the latching state control of the master and slave latches, and to realize the single particle reinforcement of the latch structure.

[0066] Taking the first-level data signal stacking circuit 105 as an example, the data signal stacking circuit is composed of PMOS transistors P501, P502, P503 and NMOS transistors N501, N502, N503; the source of P501 is connected to the power supply VDD, the gate of P501 is connected to the gate of N501, and serves as the second data input terminal of the data signal stacking circuit, the drain of P501 is connected to the source of P502; the gate of P502 is connected to the gate of N502 , and serves as the first data input terminal of the data signal stacking circuit, the drain of P502 is connected to the source of P503; the gate of P503 serves as the first clock input terminal, the drain of P503 is connected to the drain of N503, and serves as the output terminal of the data signal stacking circuit; the gate of N503 serves as the second clock input terminal of the data signal stacking circuit, the source of N503 is connected to the drain of N502; the source of N502 is connected to the drain of N501; the source of N501 is connected to the power ground GND.

[0067] The second-stage data signal stacking circuit 109 includes PMOS transistors P901, P902, and P903 and NMOS transistors N901, N902, and N503; the source of the PMOS transistor P901 is connected to the power supply VDD; the gate of the PMOS transistor P901 is connected to the gate of the NMOS transistor N901, and serves as the second data input terminal of the second-stage data signal stacking circuit 109, and is connected to the output terminal of the second-stage latch inverter 107; the drain of the PMOS transistor P901 is connected to the source of the PMOS transistor P902; the gate of the PMOS transistor P902 is connected to the gate of the NMOS transistor N902, and serves as the first data input terminal of the second-stage data signal stacking circuit 109, and is connected to the output terminal of the second-stage replica inverter 108, and the drain of the PMOS transistor P902 The source of the PMOS transistor P903 is connected; the gate of the PMOS transistor P903 serves as the first clock input of the second-level data signal stacking circuit (109) to receive the external clock signal CLK; the drain of the PMOS transistor P903 is connected to the drain of the NMOS transistor N903, and serves as the output of the second-level data signal stacking circuit 109, connected to the output of the second-level stacking clock control circuit 106; the gate of the NMOS transistor N903 serves as the second clock input of the second-level data signal stacking circuit 109 to receive the external clock signal CLKN, the source of the NMOS transistor N903 is connected to the drain of the NMOS transistor N902; the source of the NMOS transistor N902 is connected to the drain of the NMOS transistor N901; the source of the NMOS transistor N901 is connected to the power ground GND.

[0068] The implementation principle of the data signal stacking circuit is as follows: Taking the first-level data signal stacking circuit 105 as an example, the circuit uses stacked transistors to achieve single-particle reinforcement. When the two data input signals are the same and the CLK signal is 1 (i.e., latched state), the data signal stacking circuit outputs a reverse signal; when the two data input signals are different, the output is in a hold state; and when the CLK signal is 0 (i.e., transparent state), the data signal stacking circuit is turned off. Therefore, when a single-particle flip occurs in one of the two inputs, the error will not be transmitted to the output. And the transistors that use the two data signals as inputs in the circuit adopt a stacked structure, so the data signal stacking circuit itself will not cause an output flip after being bombarded by a single particle.

[0069] The implementation principle of the present invention is analyzed below in different situations:

[0070] First, analyze the situation where SEU occurs inside the trigger.

[0071] 1) When the clock signal CLK=0 and CLKN=1, the first-level stacked clock control circuit 101 is turned on, and the first-level data signal stacking circuit 105 is turned off. The master latch is in a transparent state; the second-level stacked clock control circuit 106 is turned off, the first-level data signal stacking circuit 109 is turned on, and the slave latch is in a latched state. If the second-stage latch inverter 107 in the slave latch is struck in this state and an output voltage error occurs, since the output state of the second-stage replica inverter 108 is still correct, the two input terminal signals of the second-stage data signal stack inverter 109 are different, and its output still maintains the correct state before the strike. As the radiation-induced charge disappears through mechanisms such as recombination, the level state of the second-stage latch inverter 107 is restored to be correct, and the second-stage data signal stack inverter 109 outputs correct data. When the second-stage replica inverter 108 is struck and a voltage error occurs, the output error voltage state is consistent with the strike state of the second-stage latch inverter 107, and the data stored in the slave latch will not be flipped. When the second-stage stack clock control circuit 106 or the second-stage data signal stack circuit 109 is struck, the output will not be flipped due to the stacking structure.

[0072] 2) When the clock signal CLK=1 and CLKN=0, the first-level stacked clock control circuit 101 is turned off and the first-level data signal stacking circuit 105 is turned on. The master latch is in a latched state; the second-level stacked clock control circuit 106 is turned on, the second-level data signal stacking circuit 109 is turned off, and the slave latch is in a transparent state. Similar to the above analysis, the output voltage error caused by the bombardment of the first-level latch inverter 102 or the first-level replica inverter 103 in the master latch does not cause the latch output to flip. When the delay circuit 104, the first-level stacked clock control circuit 101, and the first-level data signal stacking circuit 105 are bombarded, the output will not flip.

[0073] Secondly, analyze the situation where the SET transmitted at the trigger input is captured by the clock.

[0074] Only when the master latch is in the transparent state (i.e., CLK=0, CLKN=1), the SET of the external data will be propagated to the first-stage latch inverter 102 and the first-stage replica inverter 103, wherein the SET of the first-stage latch inverter 102 is transmitted to the second data input terminal of the first-stage data signal stacking circuit 105. Since the output of the first-stage replica inverter 103 is connected to the input terminal of the delay circuit 104, the signal transmitted to the second data input terminal of the first-stage data signal stacking circuit 105 through the delay circuit 104 is different from the first input terminal. The first-stage data signal stacking circuit 105 maintains the correct output. Therefore, the SET will not propagate to the slave latch to cause a trigger output error.

[0075] Figure 6The figure shows the implementation form of the output inverter circuit 110. The output inverter circuit is composed of PMOS transistors P111 and P112 and NMOS transistors N111 and N112; the source of P111 is connected to the power supply VDD, the gate of P111 is connected to the gate of N111, and serves as the input of the output inverter circuit 110, the drain of P111 is connected to the drain of N111, the gate of P112 and the gate of N112, and serves as the output of the first-stage inverter and the input of the second-stage inverter; the source of N111 is connected to the power supply ground GND; the source of P112 is connected to the power supply VDD, the drain of P112 is connected to the drain of N112, and serves as the output of the output inverter circuit 110; the source of N112 is connected to the power supply ground GND. The output inverter circuit 110 is used to implement data buffering.

[0076] Figure 7 Schematic diagram of the overall circuit of the trigger of the present invention.

[0077] The stacked clock control circuit of the present invention is used to control the working state of the master-slave latch and ensure that the data is correct after it is bombarded by a single particle; the latch inverter is used to realize data transmission and latching; the replica inverter is used to provide redundant signals; the delay circuit is used to filter the SET pulse with the delayed signal; the data signal stacking circuit is used to realize data latching and ensure that the data is correct after the latch is bombarded by a single particle; the output inverter circuit is used for data buffering and shaping. The circuit structure designed by the present invention can effectively reduce the single particle soft error problem caused by single particle transient and single particle flipping. The circuit design is simple, developed based on the characteristics of silicon on insulator process, effectively reduces the reinforcement cost, and is easy to implement.

[0078] Although the present application is disclosed as above in the form of a preferred embodiment, it is not intended to limit the present application. Any technical personnel in this field may make possible changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be based on the scope defined by the claims of the present application.

Claims

1. A built-in filter single event upset resistant trigger structure applied to silicon-on-insulator technology, characterized in that: include: A first-stage stacked clock control circuit (101), a first-stage latched inverter (102), a first-stage replica inverter (103), a delay circuit (104), a first-stage data signal stacking circuit (105), a second-stage stacked clock control circuit (106), a second-stage latched inverter (107), a second-stage replica inverter (108), a second-stage data signal stacking circuit (109), and an output inverter circuit (110); The data input end of the first-stage stacked clock control circuit (101) receives an external input signal D, the first clock input end receives an external clock signal CLK, the second clock input end receives an external clock signal CLKN, and the output end is simultaneously connected to the input end of the first-stage latch inverter (102), the input end of the first-stage replica inverter (103), and the output end of the first-stage data signal stacking circuit (105); The output end of the first-stage latch inverter (102) is connected to the data input end of the second-stage stack clock control circuit (106) and the second data input end of the first-stage data signal stack circuit (105); The output end of the first stage replica inverter (103) is connected to the input end of the delay circuit (104); The output end of the delay circuit (104) is connected to the first data input end of the first-stage data signal stacking circuit (105); The first clock input end of the first-stage data signal stacking circuit (105) receives an external clock signal CLKN, and the second clock input end receives an external clock signal CLK; The first clock input end of the second-stage stacked clock control circuit (106) receives an external clock signal CLKN, the second clock input end receives an external clock signal CLK, and the output end is simultaneously connected to the input end of the second-stage latch inverter (107), the input end of the second-stage replica inverter (108) and the output end of the second-stage data signal stacking circuit (109); The output end of the second-stage latch inverter (107) is connected to the input end of the output inverter circuit (110) and the second data input end of the second-stage data signal stacking circuit (109); The output end of the second-stage replica inverter (108) is connected to the first data input end of the second-stage data signal stacking circuit (109); The first clock input terminal of the second-stage data signal stacking circuit (109) receives an external clock signal CLK, and the second clock input terminal receives an external clock signal CLKN; The output terminal of the output inverter circuit (110) outputs a signal Q.

2. The built-in filter single event upset (SING) flip-flop structure for silicon-on-insulator (SOI) technology according to claim 1, characterized in that: The first-stage latch inverter (102), the first-stage replica inverter (103), the delay circuit (104), and the first-stage data signal stacking circuit (105) constitute a master latch; the second-stage latch inverter (107), the second-stage replica inverter (108), and the second-stage data signal stacking circuit (109) constitute a slave latch; The first-level stacked clock control circuit (101) is used to provide data signals to the first-level latch inverter (102) and the first-level replica inverter (103), and realize the state control of the main latch; the first-level latch inverter (102) is used to realize the data transmission and latching of the main latch; the first-level replica inverter (103) is used to provide redundant signals for the delay circuit; the delay circuit is used to realize SET pulse filtering; the first-level data signal stacking circuit (105) is used to control the latch state of the main latch and realize the latch inverter after being bombarded by a single particle. The second-level stacking clock control circuit (106) is used to provide data signals to the second-level latch inverter (107) and the second-level replica inverter (108), and realize the state control of the slave latch; the second-level latch inverter (107) is used to realize the data transmission and latching of the slave latch; the second-level replica inverter (108) is used to provide a redundant signal for the second-level data signal stacking circuit; the second-level data signal stacking circuit (109) is used to control the latch state of the slave latch and realize the correct output of the latch inverter after being bombarded by a single particle; The output inverter circuit is used to implement data signal buffering.

3. The built-in filter anti-single event upset trigger structure applied to silicon-on-insulator process according to claim 1, characterized in that: The first-stage stacked clock control circuit (101) comprises PMOS transistors P101, P102, P103 and NMOS transistors N101, N102, N103; The gate of the PMOS transistor P101 is connected to the gate of the NMOS transistor N101 and serves as a data input terminal of the first-stage stacked clock control circuit (101) to receive an external input signal D. The source of the PMOS transistor P101 is connected to a power supply VDD, and the drain is connected to the source of the PMOS transistor P102. After the gate of the PMOS transistor P102 is connected to the gate of the PMOS transistor P103, the PMOS transistor P102 serves as a first clock input terminal of the first-stage stacked clock control circuit (101) to receive an external clock signal CLK. The drain of the PMOS transistor P102 is connected to the source of the PMOS transistor P103. After the drain of the PMOS transistor P103 is connected to the drain of the NMOS transistor N103, it serves as the output terminal C0 of the first-level stacked clock control circuit (101); after the gate of the NMOS transistor N103 is connected to the gate of the NMOS transistor N102, it serves as the second clock input terminal of the first-level stacked clock control circuit (101) to receive the external clock signal CLKN, and the source of the NMOS transistor N103 is connected to the drain of the NMOS transistor N102; the source of the NMOS transistor N102 is connected to the drain of the NMOS transistor N101, and the source of the NMOS transistor N101 is connected to the power ground GND.

4. The built-in filter anti-single event upset trigger structure applied to silicon-on-insulator process according to claim 1, characterized in that: The first-stage latch inverter (102), the first-stage replica inverter (103), the second-stage latch inverter (107), and the second-stage replica inverter (108) have the same structure, and all include a PMOS transistor P201 and an NMOS transistor N201; The source of the PMOS transistor P201 is connected to the power supply VDD, the gate of the PMOS transistor P201 is connected to the gate of the NMOS transistor N201 and serves as the input end of the inverter, the drain of the PMOS transistor P201 is connected to the drain of the NMOS transistor N201 and serves as the output end of the inverter; the source of the NMOS transistor N201 is connected to the power ground GND.

5. The built-in filter single event upset resistant trigger structure applied to silicon-on-insulator process according to claim 1, characterized in that: The delay circuit (104) is composed of n stages of cascaded inverter units, wherein the first (n-1) stages adopt a stacked inverter structure, and the nth stage adopts a conventional inverter structure; Each level of the first (n-1)-level stacked inverter has the same structure. The m-th-level stacked inverter includes PMOS transistors P4m1, P4m2, P4m3 and NMOS transistors N4m1, N4m2, N4m3. The gates of the PMOS transistors P4m1, P4m2, P4m3 and the NMOS transistors N4m1, N4m2, N4m3 are connected as the input end of the m-th-level stacked inverter and connected to the output end of the m-1-th-level stacked inverter. The source of the PMOS transistor P4m1 is connected to the power supply VDD, and the drain of the PMOS transistor P4m1 is connected to the source of the PMOS transistor P4m2; the drain of the PMOS transistor P4m2 is connected to the source of the PMOS transistor P4m3; The drain of the PMOS transistor P4m3 is connected to the drain of the NMOS transistor N4m3 and serves as the output of the m-th stacked inverter and is connected to the input of the m+1-th stacked inverter; the source of the NMOS transistor N4m3 is connected to the drain of the NMOS transistor N4m2; the source of the NMOS transistor N4m2 is connected to the drain of the NMOS transistor N4m1; the source of the NMOS transistor N4m1 is connected to the power ground GND; wherein 1<m<n-1; The nth stage inverter of the delay circuit (104) adopts a conventional structure, including a PMOS transistor P4n1 and an NMOS transistor N4n1; the source of the PMOS transistor P4n1 is connected to a power supply VDD, the gate of the PMOS transistor P4n1 is connected to the gate of the NMOS transistor N4n1 and serves as the input end of the nth stage inverter and is connected to the output end of the (n-1)th stage stacked inverter, the drain of the PMOS transistor P4n1 is connected to the drain of the NMOS transistor N4n1 and serves as the output end of the delay circuit and is connected to the first input end of the first stage data signal stacking circuit (105); the source of the NMOS transistor N4n1 is connected to the power ground GND.

6. The built-in filter single event upset resistant trigger structure applied to silicon-on-insulator process according to claim 1, characterized in that: The first-level data signal stacking circuit (105) comprises PMOS transistors P501, P502, P503 and NMOS transistors N501, N502, N503; the source of the PMOS transistor P501 is connected to a power supply VDD; the gate of the PMOS transistor P501 is connected to the gate of the NMOS transistor N501 and serves as a second data input terminal of the first-level data signal stacking circuit (105), connected to the output terminal of the first-level latch inverter (102); the drain of the PMOS transistor P501 is connected to the source of the PMOS transistor P502; the gate of the PMOS transistor P502 is connected to the gate of the NMOS transistor N502 and serves as a first data input terminal of the first-level data signal stacking circuit (105); The drain of transistor P502 is connected to the source of PMOS transistor P503; the gate of PMOS transistor P503 serves as a first clock input terminal to receive an external clock signal CLKN; the drain of PMOS transistor P503 is connected to the drain of NMOS transistor N503 and serves as an output terminal of a first-level data signal stacking circuit (105); the gate of NMOS transistor N503 serves as a second clock input terminal of the first-level data signal stacking circuit (105) to receive an external clock signal CLK, the source of NMOS transistor N503 is connected to the drain of NMOS transistor N502; the source of NMOS transistor N502 is connected to the drain of NMOS transistor N501; the source of NMOS transistor N501 is connected to a power ground GND.

7. The built-in filter single event upset resistant trigger structure applied to silicon-on-insulator process according to claim 1, characterized in that: The second-stage stacked clock control circuit (106) comprises PMOS transistors P601, P602, and P603 and NMOS transistors N601, N602, and N603; the gate of the PMOS transistor P601 is connected to the gate of the NMOS transistor N601 and then serves as a data input terminal of the second-stage stacked clock control circuit (106) and is connected to the master latch output signal C2; the source of the PMOS transistor P601 is connected to a power supply VDD; the drain of the PMOS transistor P601 is connected to the source of the PMOS transistor P602; the gate of the PMOS transistor P602 is connected to the gate of the PMOS transistor P603 and serves as the second-stage stacked clock control circuit (106). 6) receives an external clock signal CLKN at the first clock input terminal, the drain of the PMOS transistor P602 is connected to the source of the PMOS transistor P603; the drain of the PMOS transistor P603 is connected to the drain of the NMOS transistor N603 and serves as the output terminal of the second-level stacked clock control circuit (106); the gate of the NMOS transistor N603 is connected to the gate of the NMOS transistor N602 and serves as the second clock input terminal of the second-level stacked clock control circuit (106) to receive the external clock signal CLK; the source of the NMOS transistor N602 is connected to the drain of the NMOS transistor N601; the source of the NMOS transistor N601 is connected to the power ground GND.

8. The built-in filter single event upset resistant trigger structure applied to silicon-on-insulator process according to claim 1, characterized in that: The second-stage data signal stacking circuit (109) comprises PMOS transistors P901, P902, and P903 and NMOS transistors N901, N902, and N503; the source of the PMOS transistor P901 is connected to a power supply VDD; the gate of the PMOS transistor P901 is connected to the gate of the NMOS transistor N901 and serves as a second data input terminal of the second-stage data signal stacking circuit (109) and is connected to the output terminal of the second-stage latch inverter (107); the drain of the PMOS transistor P901 is connected to the source of the PMOS transistor P902; the gate of the PMOS transistor P902 is connected to the gate of the NMOS transistor N902 and serves as a first data input terminal of the second-stage data signal stacking circuit (109) and is connected to the output terminal of the second-stage replica inverter (108); The drain is connected to the source of the PMOS transistor P903; the gate of the PMOS transistor P903 serves as the first clock input of the second-level data signal stacking circuit (109) to receive the external clock signal CLK; the drain of the PMOS transistor P903 is connected to the drain of the NMOS transistor N903 and serves as the output of the second-level data signal stacking circuit (109) and is connected to the output of the second-level stacking clock control circuit (106); the gate of the NMOS transistor N903 serves as the second clock input of the second-level data signal stacking circuit (109) to receive the external clock signal CLKN, the source of the NMOS transistor N903 is connected to the drain of the NMOS transistor N902; the source of the NMOS transistor N902 is connected to the drain of the NMOS transistor N901; the source of the NMOS transistor N901 is connected to the power ground GND.

9. The built-in filter single event upset resistant trigger structure applied to silicon-on-insulator process according to claim 1, characterized in that: The output inverter circuit (110) comprises PMOS transistors P111 and P112 and NMOS transistors N111 and N112; the source of the PMOS transistor P111 is connected to a power supply VDD; the gate of the PMOS transistor P111 is connected to the gate of the NMOS transistor N111 and is connected to the output terminal C5 of the second-stage latch inverter (107) as the input terminal of the output inverter circuit (110); the drain of the PMOS transistor P111 is connected to the drain of the NMOS transistor N111, the gate of the PMOS transistor P112 and the gate of the NMOS transistor N112; the source of the NMOS transistor N111 is connected to a power supply ground GND; the source of the PMOS transistor P112 is connected to the power supply VDD; the drain of the PMOS transistor P112 is connected to the drain of the NMOS transistor N112 and is connected to the output terminal of the output inverter circuit (110) to output a signal Q; the source of the NMOS transistor N112 is connected to the power supply ground GND.