Dual-path delay difference PUF circuit

Abstract

The invention discloses a dual-path time delay difference PUF circuit, which comprises two time delay modules, two arbiters, a first exclusive-OR gate, n-1 time delay arbitration modules and an exclusive-OR gate array, each time delay module comprises n switch unit arrays, each switch unit array comprises m switch units, n is an integer greater than or equal to 1, n is an integer greater than or equal to 1, and n is an integer greater than or equal to 1. Each time delay arbitration module comprises two arbiters and an exclusive-OR gate, the exclusive-OR gate array comprises n-1 exclusive-OR gates, each time delay module is divided into n switch unit arrays, and the two time delay modules are divided into n switch unit array combinations, inserting a time delay arbitration module between every two adjacent switch unit array combinations to extract an intermediate response, then performing XOR processing on the intermediate response through an XOR logic gate array to obtain a response, and then performing XOR processing on the response and responses output by two arbiters again through a first XOR gate to obtain a final response; the method has the advantages of high machine learning attack resistance and low hardware overhead.

Description

Technical Field

[0001] The present invention relates to a PUF circuit, and in particular to a dual-path delay difference PUF circuit. Background Art

[0002] With the vigorous development of the Internet of Things, technologies such as long-distance communication and public channel transmission have become an indispensable part of the era of the Internet of Everything. The security of communication between IoT devices is of paramount importance. In the process of user information data transmission, it is particularly important to protect sensitive information from being stolen, copied or tampered with by malicious attackers. In the face of emerging attack technologies, most IoT device encryption and authentication technologies rely on the storage of secure keys. The hardware implementation of encryption algorithms is highly complex and is subject to hardware resources, costs and computing power constraints, making them vulnerable to intrusion attacks and side channel attacks. As a chip fingerprint extraction technology, the physical unclonable function uses the inevitable process deviations introduced in the integrated circuit manufacturing process to generate a unique digital fingerprint of the device. The generated key is unpredictable and unclonable, making it difficult for attackers to break. At the same time, PUF has the advantages of a large number of stimulus-response pairs, non-volatile storage, and difficulty in theft. Therefore, PUF is widely used in encryption, device authentication, key generation and other fields. It provides a new solution to solve traditional information security problems.

[0003] As a typical PUF circuit, APUF has been widely used. Figure 1 As shown, the APUF is composed of a signal delay unit and an arbiter formed by cascading n switch units, wherein the switch unit is as follows Figure 1 As shown in (b), it consists of two parallel multiplexers. The excitation Ci loaded to the switch unit is different, and the way the signal passes through the switch unit will also change, such as Figure 1 As shown in (c), when the stimulus Ci loaded on the switch unit is "0", the signal is transmitted through the parallel path; otherwise, the signal is transmitted through the cross path. After the initial pulse signal is transmitted through the two symmetrical paths (path 1 and path 2) of the APUF, the arbitrator determines the order of signal arrival, as shown in Figure 1 As shown in (d), if the output signal of path 1 reaches the arbitrator faster than the output signal of path 2, the response R output by the arbitrator is 1, otherwise the response R output is 0. Ideally, the signal should reach the arbitrator at the same time after being transmitted through two symmetrical paths. However, due to the inevitable process deviation of the two symmetrical paths, there are differences in signal transmission delay. Therefore, the transmission path of the signal in the switch unit can be changed by controlling the excitation, affecting the signal delay difference of the two symmetrical paths, and generating an unpredictable response R.

[0004] Machine learning enables computers to acquire the ability to learn autonomously without being programmed. For PUF circuit attacks, the collected challenge-response pairs (CRP) are randomly divided into training sets and test sets for learning. Machine learning can analyze the results of training and build a complete mathematical model without knowing the internal structure of the PUF circuit. Since the delay equation in the APUF is close to a linear function, the generated CRPs have linear boundaries and are easy to ML model, which threatens the security of the APUF. The existing anti-machine learning attack technologies, such as Chen et al. in the literature "Chen, Bo, Pengjun Wang, and Gang Li." An obfuscated challenge design for APUF to resist machine learning attacks." 2019 IEEE 13th International Conference on ASIC (ASICON). IEEE, 2019." proposed to blur the direct relationship between excitation and response by exchanging the position of the excitation signal; Chang et al. in the literature "Chang, Zhengtai, et al." Modeling attack resistant arbiter puf with time-variant obfuscation scheme." 2021 31st International Conference on Field-Programmable Logic and Applications (FPL). IEEE, 2021." proposed to add a linear feedback shift register before the excitation to confuse the relationship between the excitation and the response; Shah et al. in the literature "Shah, Nimesh, et al." Introducing recurrence in strong PUFs for enhanced machine learning attack resistance." IEEE Journal on Emerging and Selected Topics in Circuits and Systems 11.2(2021):319-332." A recursive PUF-based method is proposed to combine recursion and XOR operation with traditional APUF to confuse CRPs. Although the above techniques can improve the ability of APUF to resist machine learning attacks, they all require large resource overhead, resulting in large hardware overhead of PUF circuit. Summary of the invention

[0005] The technical problem to be solved by the present invention is to provide a dual-path delay difference PUF circuit which has high resistance to machine learning attacks and low hardware overhead.

[0006] The technical solution adopted by the present invention to solve the above technical problems is: a dual-path delay difference PUF circuit, including two delay modules, two arbitrators and an XOR gate, the XOR gate is called a first XOR gate, the first XOR gate has a first input terminal, a second input terminal and an output terminal, each of the arbitrators has a first input terminal, a second input terminal and an output terminal, each delay module includes n switch unit arrays, n is an integer greater than or equal to 2, each switch unit array includes m switch units, m is an integer greater than or equal to 1, each switch unit has an excitation terminal, a first input terminal, a second input terminal, a first output terminal and a second output terminal, when its excitation terminal is connected to an excitation signal of a high level 1, its first input terminal and The first output terminal is turned on, the second input terminal and the second output terminal are turned on, and when its excitation terminal is connected to an excitation signal of low level 0, its first input terminal and the second output terminal are turned on, and the second input terminal and the first output terminal are turned on; in each switch unit array, the first input terminal of the first switch unit is the first input terminal of the switch unit array, the second input terminal of the first switch unit is the second input terminal of the switch unit array, the first output terminal of the sth switch unit is connected to the first input terminal of the s+1th switch unit, and the second output terminal of the sth switch unit is connected to the second input terminal of the s+1th switch unit, s=1,2,…,m-1, the first output terminal of the mth switch unit is the first output terminal of the switch unit array, the The second output end of the m switch units is the second output end of the switch unit array, and the excitation end of the m switch units is the m-bit excitation end of the switch unit array; in each delay module, the first input end of the 1st switch unit array is the first input end of the delay module, the second input end of the 1st switch unit array is the second input end of the delay module, the first output end of the jth switch unit array is connected to the first input end of the j+1th switch unit array, the second output end of the jth switch unit array is connected to the second input end of the j+1th switch unit array, j=1,2,…,n-1, the first output end of the nth switch unit array is the first output end of the delay module, the second output end of the nth switch unit array is connected to the second input end of the j+1th switch unit array, j=1,2,…,n-1, the first output end of the nth switch unit array is the first output end of the delay module, and the second output end of the nth switch unit is connected to the second input end of the is the second output end of the delay module, and the m-bit excitation end of the n switch unit array is the mn-bit excitation end of the delay module; the first input end and the second input end of the two delay modules are connected, and the connection end thereof is the input end of the dual-path delay difference PUF circuit, the two delay modules correspond one to one with the two arbiters, and in a corresponding delay module and an arbiter, the first output end of the delay module is connected to the first input end of the arbiter, and the second output end of the delay module is connected to the second input end of the arbiter, and the output ends of the two arbiters are connected one to one with the first input end and the second input end of the first XOR gate, and the output end of the first XOR gate is the output end of the dual-path delay difference PUF circuit;The first XOR gate also has a third input terminal. The dual-path delay difference PUF circuit also includes n-1 delay arbitration modules and an XOR logic gate array. Each delay arbitration module includes two arbitrators and an XOR gate. The two arbitrators are called the first arbitrator and the second arbitrator. The XOR gate is called the second XOR gate. The first arbitrator and the second arbitrator both have a first input terminal, a second input terminal and an output terminal. The second XOR gate has a first input terminal, a second input terminal and an output terminal. In each delay arbitration module, the first input terminal of the first arbitrator is the first input terminal of the delay arbitration module. The second input end of the first arbitrator is the second input end of the delay arbitration module, the first input end of the second arbitrator is the third input end of the delay arbitration module, the second input end of the second arbitrator is the fourth input end of the delay arbitration module, the output end of the first arbitrator is connected to the first input end of the second XOR gate, the output end of the second arbitrator is connected to the second input end of the second XOR gate, and the output end of the second XOR gate is the output end of the delay arbitration module; the XOR logic gate array includes n-1 XOR gates, and the XOR gate is called the third XOR gate , each of the third XOR gates has a first input terminal, a second input terminal and an output terminal; the two delay modules are respectively referred to as the first delay module and the second delay module, the first output terminal of the p-th switch unit array of the first delay module is connected to the first input terminal of the p-th delay arbitration module, the first output terminal of the p-th switch unit array of the second delay module is connected to the second input terminal of the p-th delay arbitration module, the second output terminal of the p-th switch unit array of the first delay module is connected to the third input terminal of the p-th delay arbitration module, and the second output terminal of the p-th switch unit array of the second delay module is connected to the third input terminal of the p-th delay arbitration module. The output end of the first delay arbitration module is connected to the first input end of the first third XOR gate, the output end of the second delay arbitration module is connected to the second input end of the first third XOR gate, the output end of the qth delay arbitration module is connected to the second input end of the q-1th third XOR gate, q=3,4,...,n-1; the output end of the fth third XOR gate is connected to the first input end of the f+1th third XOR gate, f=1,2,...,n-2; the output end of the n-1th third XOR gate is connected to the third input end of the first XOR gate. ;

[0007] Compared with the prior art, the advantage of the present invention is that the mn switch units connected in series in each delay module are equally divided into n groups of switch units, that is, n switch unit arrays are formed in each delay module, and then the switch unit arrays located at the same position in the two delay modules are combined as a switch unit array to form n switch unit array combinations, and a delay arbitration module is inserted between each two adjacent switch unit array combinations to extract the intermediate response to obtain n-1 intermediate responses, and then the n-1 intermediate responses are XOR-processed through the XOR logic gate array to obtain a response, and then the response and the responses output by the two arbiters are XOR-processed again through the first XOR gate to obtain a final response. Therefore, the present invention greatly improves the complexity of the mapping relationship between the stimulus and the response by only grouping the switch units in the delay module and inserting the delay arbitration module, and has a high ability to resist machine learning attacks while having a small hardware overhead.

[0008] Further, each switch unit includes two two-choose-one selectors, each of which has a first input terminal, a second input terminal, a selection terminal and an output terminal. When the selection terminal is connected to a high level 1, the second input terminal is connected to the output terminal, and the signal output by the output terminal is the signal connected to the second input terminal. When the selection terminal is connected to a high level 0, the first input terminal is connected to the output terminal, and the signal output by the output terminal is the signal connected to the first input terminal. The two two-choose-one selectors are respectively referred to as the first two-choose-one selector and the second two-choose-one selector. The first input terminal of the first two-choose-one selector is connected to the The second input end of the second two-to-one selector is connected, and its connection end is the first input end of the switch unit, the second input end of the first two-to-one selector is connected to the first input end of the second two-to-one selector, and its connection end is the second input end of the switch unit, the selection end of the first two-to-one selector is connected to the selection end of the second two-to-one selector, and its connection end is the excitation end of the switch unit, the output end of the first two-to-one selector is the first output end of the switch unit, and the output end of the second two-to-one selector is the second output end of the switch unit.

[0009] Furthermore, each arbitrator includes two two-input NAND gates, each of which has a first input terminal, a second input terminal and an output terminal. The two two-input NAND gates are respectively referred to as a first NAND gate and a second NAND gate. The first input terminal of the first NAND gate is the first input terminal of the arbitrator, the second input terminal of the second NAND gate is the second input terminal of the arbitrator, the second input terminal of the first NAND gate is connected to the output terminal of the second NAND gate, the first input terminal of the second NAND gate is connected to the output terminal of the first NAND gate, and the connection terminal thereof is the output terminal of the arbitrator. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 A schematic diagram of the existing APUF and its internal structure, signal transmission and generation;

[0011] Figure 2 It is a structural schematic diagram of a dual-path delay difference PUF circuit of the present invention;

[0012] Figure 3 It is a structural schematic diagram of the delay arbitration module of the dual-path delay difference PUF circuit of the present invention;

[0013] Figure 4 It is a schematic diagram of the structure of the XOR logic gate array of the dual-path delay difference PUF circuit of the present invention;

[0014] Figure 5 It is a structural schematic diagram of a switch unit array of a dual-path delay difference PUF circuit of the present invention;

[0015] Figure 6 A circuit diagram of a switch unit of a dual-path delay difference PUF circuit of the present invention;

[0016] Figure 7 A circuit diagram of an arbiter of a dual-path delay difference PUF circuit of the present invention;

[0017] Figure 8 Schematic diagram of an experimental test platform for a dual-path delay difference PUF circuit of the present invention;

[0018] Fig. 9 A logistic regression attack prediction rate curve diagram of the dual-path delay difference PUF circuit of the present invention and the existing common XOR-PUF;

[0019] Fig.10 It is a curve diagram of the artificial neural network attack prediction rate of the dual-path delay difference PUF circuit of the present invention and the existing common XOR-PUF;

[0020] Fig.11 A curve diagram of the attack prediction rate of the lightweight gradient boosting machine of the dual-path delay difference PUF circuit of the present invention and the existing common XOR-PUF;

[0021] Fig.12 A support vector machine attack prediction rate curve diagram of the dual-path delay difference PUF circuit of the present invention and the existing common XOR-PUF;

[0022] Fig.13 A test result diagram of the output response of the dual-path delay difference PUF circuit of the present invention is tested using an autocorrelation function;

[0023] Fig.14It is a fitting curve diagram of the inter-chip Hamming distance and the intra-chip Hamming distance of the dual-path delay difference PUF circuit of the present invention;

[0024] Fig.15 A diagram showing the relationship between the stability and response quantity of the dual-path delay difference PUF circuit of the present invention and the existing common XOR-PUF;

[0025] Fig.16 The figure is a relationship diagram between the stability and repetition times of the dual-path delay difference PUF circuit of the present invention and the existing common XOR-PUF. DETAILED DESCRIPTION

[0026] The present invention is further described in detail below with reference to the accompanying drawings.

[0027] Embodiment 1: Figure 2 As shown, a dual-path delay difference PUF circuit includes two delay modules, two arbitrators and an XOR gate, the XOR gate is called a first XOR gate XOR1, the first XOR gate XOR1 has a first input terminal, a second input terminal and an output terminal, each arbitrator has a first input terminal, a second input terminal and an output terminal, each delay module includes an array of n switch units, n is an integer greater than or equal to 2, such as Figure 5As shown, each switch unit array includes m switch units, m is an integer greater than or equal to 1, each switch unit has an excitation end, a first input end, a second input end, a first output end, and a second output end. When the excitation end is connected to an excitation signal of a high level 1, the first input end and the first output end are turned on, and the second input end and the second output end are turned on. When the excitation end is connected to an excitation signal of a low level 0, the first input end and the second output end are turned on, and the second input end and the first output end are turned on. In each switch unit array, the first input end of the first switch unit is the first input end of the switch unit array, the second input end of the first switch unit is the second input end of the switch unit array, and the sth switch unit is the second input end of the switch unit array. The first output end of the switch unit is connected to the first input end of the s+1th switch unit, the second output end of the sth switch unit is connected to the second input end of the s+1th switch unit, s=1, 2, ..., m-1, the first output end of the mth switch unit is the first output end of the switch unit array, the second output end of the mth switch unit is the second output end of the switch unit array, and the excitation ends of the m switch units are the m-bit excitation ends of the switch unit array; in each delay module, the first input end of the 1st switch unit array is the first input end of the delay module, the second input end of the 1st switch unit array is the second input end of the delay module, the first output end of the jth switch unit array is connected to the The first input end of the j+1 switch unit array is connected, the second output end of the j-th switch unit array is connected to the second input end of the j+1-th switch unit array, j=1,2,…,n-1, the first output end of the n-th switch unit array is the first output end of the delay module, the second output end of the n-th switch unit is the second output end of the delay module, and the m-bit excitation end of the n-switch unit array is the mn-bit excitation end of the delay module; the first input end and the second input end of the two delay modules are connected, and the connection end thereof is the input end of the dual-path delay difference PUF circuit, the two delay modules correspond one to one with the two arbiters, and in a corresponding delay module and an arbiter, the delay module The first output end is connected to the first input end of the arbitrator, the second output end of the delay module is connected to the second input end of the arbitrator, the output ends of the two arbitrators are connected to the first input end and the second input end of the first XOR gate XOR1 in a one-to-one correspondence, and the output end of the first XOR gate XOR1 is the output end of the dual-path delay difference PUF circuit; the first XOR gate XOR1 also has a third input end, and the dual-path delay difference PUF circuit also includes n-1 delay arbitration modules and an XOR logic gate array, each delay arbitration module includes two arbitrators and an XOR gate, the two arbitrators are called the first arbitrator and the second arbitrator, and the XOR gate is called the second XOR gate XOR2, such as Figure 3As shown, the first arbitrator and the second arbitrator both have a first input terminal, a second input terminal and an output terminal, the second XOR gate XOR2 has a first input terminal, a second input terminal and an output terminal, in each delay arbitration module, the first input terminal of the first arbitrator is the first input terminal of the delay arbitration module, the second input terminal of the first arbitrator is the second input terminal of the delay arbitration module, the first input terminal of the second arbitrator is the third input terminal of the delay arbitration module, the second input terminal of the second arbitrator is the fourth input terminal of the delay arbitration module, the output terminal of the first arbitrator is connected to the first input terminal of the second XOR gate XOR2, the output terminal of the second arbitrator is connected to the second input terminal of the second XOR gate XOR2, and the output terminal of the second XOR gate XOR2 is the output terminal of the delay arbitration module; as shown Figure 4 As shown, the XOR logic gate array includes n-1 XOR gates, which are called third XOR gates XOR3, and each third XOR gate XOR3 has a first input terminal, a second input terminal and an output terminal; the two delay modules are respectively called the first delay module and the second delay module, the first output terminal of the p-th switch unit array of the first delay module is connected to the first input terminal of the p-th delay arbitration module, the first output terminal of the p-th switch unit array of the second delay module is connected to the second input terminal of the p-th delay arbitration module, the second output terminal of the p-th switch unit array of the first delay module is connected to the third input terminal of the p-th delay arbitration module, the second output terminal of the p-th switch unit array of the second delay module is connected to the p-th delay arbitration module, The fourth input terminal of the delay arbitration module is connected, p=1,2…,n-1; the output terminal of the 1st delay arbitration module is connected to the first input terminal of the 1st third XOR gate XOR3, the output terminal of the 2nd delay arbitration module is connected to the second input terminal of the 1st third XOR gate XOR3, the output terminal of the qth delay arbitration module is connected to the second input terminal of the q-1th third XOR gate XOR3, q=3,4,…,n-1; the output terminal of the fth third XOR gate XOR3 is connected to the first input terminal of the f+1th third XOR gate XOR3, f=1,2,…,n-2; the output terminal of the n-1th third XOR gate XOR3 and the third input terminal of the first XOR gate XOR1 are connected to the dual-path delay difference PUF circuit.

[0028] In this embodiment, the response outputted by the output terminal of the delay arbitration module is as shown in Table 1.

[0029] Table 1 The response of the output of the delay arbitration module

[0030]

[0031]

[0032] In Table 1, In1 is the signal connected to the first input of the delay arbitration module, In2 is the signal connected to the second input of the delay arbitration module, In3 is the signal connected to the third input of the delay arbitration module, In4 is the signal connected to the fourth input of the delay arbitration module, A1 corresponds to the signal output from the output of the first arbitrator, that is, the first input of the second XOR logic gate, A2 corresponds to the signal output from the output of the second arbitrator, and the delay arbitration module responds to the signal output from the output of the second XOR logic gate. Δtmin represents the signal with the smallest delay, that is, the fastest (first) input signal to the delay arbitration module; ΔtSmin represents the signal with the second smallest delay, that is, the fastest (second) input signal to the delay arbitration module; ΔtSMax represents the signal with the second largest delay, that is, the slowest (third) input signal to the delay arbitration module; ΔtMax represents the signal with the largest delay, that is, the slowest (fourth) input signal to the delay arbitration module.

[0033] From the analysis of Table 1, we can see that: according to the different delays of the input signals at its four input terminals, the delay arbitration module has 24 output response conditions, of which 12 cases have an output response of 0 and 12 cases have an output response of 1, each accounting for 1 / 2 of the total cases, indicating that the probability of the output response of the delay arbitration module being 0 or 1 is 50%. Since the signal delay conditions of each signal after passing through the switch unit array are random, the output response through the delay arbitration module also has good randomness. The response Rn after passing through the XOR logic gate array enters the first XOR gate XOR1, introducing more nonlinear parameters for the PUF response R, weakening the linear relationship between the stimulus and the response, making machine learning attacks more difficult to model, and improving the ability of the PUF circuit to resist machine learning attacks.

[0034] Embodiment 2: This embodiment is basically the same as Embodiment 1, except that: in this embodiment, Figure 6As shown, each switch unit includes two two-choose-one selectors, each of which has a first input terminal, a second input terminal, a selection terminal and an output terminal. When the selection terminal is connected to a high level 1, the second input terminal is connected to the output terminal, and the signal output by the output terminal is the signal connected to the second input terminal. When the selection terminal is connected to a high level 0, the first input terminal is connected to the output terminal, and the signal output by the output terminal is the signal connected to the first input terminal. The two two-choose-one selectors are respectively referred to as the first two-choose-one selector F1 and the second two-choose-one selector F2. The first two-choose-one selector F The first input end of the first two-selector F1 is connected to the second input end of the second two-selector F2, and the connection end thereof is the first input end of the switch unit, the second input end of the first two-selector F1 is connected to the first input end of the second two-selector F2, and the connection end thereof is the second input end of the switch unit, the selection end of the first two-selector F1 is connected to the selection end of the second two-selector F2, and the connection end thereof is the excitation end of the switch unit, the output end of the first two-selector F1 is the first output end of the switch unit, and the output end of the second two-selector F2 is the second output end of the switch unit.

[0035] Embodiment 3: This embodiment is basically the same as Embodiment 2, except that: in this embodiment, Figure 7 As shown, each arbitrator includes two two-input NAND gates, each of which has a first input terminal, a second input terminal and an output terminal. The two two-input NAND gates are respectively referred to as a first NAND gate NA1 and a second NAND gate NA2. The first input terminal of the first NAND gate NA1 is the first input terminal of the arbitrator, the second input terminal of the second NAND gate NA2 is the second input terminal of the arbitrator, the second input terminal of the first NAND gate NA1 is connected to the output terminal of the second NAND gate NA2, the first input terminal of the second NAND gate NA2 is connected to the output terminal of the first NAND gate NA1, and the connection terminal thereof is the output terminal of the arbitrator.

[0036] In order to verify the performance of the dual-path delay difference PUF circuit of the present invention, a Figure 8The experimental test platform shown in the figure uses Matlab and the MicroBlaze embedded microcontroller of the Xilinx Artix-7 FPGA development board to build the experimental test platform, and sends the generated random excitation to the FPGA through the Universal Asynchronous Receiver / Transmitter (UART) module integrated in the PC communication interface; then, the UART module of the FPGA sends the received excitation data to MicroBlaze for processing, drives each module of the FPGA to generate a pulse signal, generates and returns a PUF response, and sends the output response to the PC through the UART module; finally, the PC uses Matlab to analyze the received response signal, and n=64 and m=8 in the dual-path delay difference PUF circuit of the present invention.

[0037] The logistic regression attack prediction rate curve of the dual-path delay difference PUF circuit of the present invention and the existing common XOR-PUF is shown in the figure Fig. 9 As shown; the artificial neural network attack prediction rate curve of the dual-path delay difference PUF circuit of the present invention and the existing common XOR-PUF is as shown Fig.10 As shown; the lightweight gradient boosting machine attack prediction rate curve of the dual-path delay difference PUF circuit of the present invention and the existing common XOR-PUF is shown in Fig.11 As shown; the support vector machine attack prediction rate curve of the dual-path delay difference PUF circuit of the present invention and the existing common XOR-PUF is as shown Fig.12 shown.

[0038] Figures 9 to 12 In the embodiment, PDA-PUF represents the dual-path delay difference PUF circuit of the present invention, and APUF represents Figure 1 The existing APUF circuit shown in the figure, 2XOR-PUF represents two Figure 1 The APUF response XOR circuit shown in the figure, 3XOR-PUF represents three Figure 1 The APUF response XOR circuit shown in the figure, 4XOR-PUF represents four Figure 1 The APUF response XOR circuit shown, 5XOR-PUF represents five Figure 1 The circuit shown is formed by XORing the APUF's response. Fig. 9 It can be seen that even with a data volume of up to 1 million sets of CRPs (stimulus response pairs), the logistic regression attack prediction rate of PDA-PUF is still close to the ideal value of 50%, and its ability to resist logistic regression attacks far exceeds that of other PUFs; analysis Fig.10 It can be seen that the attack prediction rate of the artificial neural network of PDA-PUF is close to 5XOR-PUF under the data volume of 1 million groups of CRPs; Fig.11 It can be seen that even with a data volume of up to 1 million groups of CRPs, the attack prediction rate of the lightweight gradient boosting machine of PDA-PUF is still close to 60%, and its ability to resist the attack of the lightweight gradient boosting machine is far superior to other PUFs; analysis Fig.12 It can be seen that when the data volume of PDA-PUF is 1 million groups of CRPs, the attack prediction rate of its support vector machine is still close to 60%, and its ability to resist attacks by support vector machines far exceeds that of other PUFs.

[0039] The randomness of the dual-path delay difference PUF circuit of the present invention is evaluated using the randomness test suite (SP 800-22) proposed by the National Institute of Standards and Technology (NIST). NIST includes 15 tests, and each test is judged whether it passes by comparing the relationship between the P value and the preset significance level. It is stipulated that P-value ≥ 0.001 indicates that the sequence is random. PDA-PUF, 4XOR-PUF, 8XOR-PUF (8 Figure 1 The APUF response XOR circuit shown in the figure) and APUF respectively collect 500,000 groups of stimulus response pairs, and the obtained responses are divided into 50 groups for randomness testing. The results are shown in Table 2:

[0040] Table 2 NIST test of PDA-PUF and other PUFs

[0041]

[0042]

[0043] In Table 2, * indicates that the P-value is very small and the test is not passed.

[0044] It can be seen from Table 2 that PDA-PUF passed 13 out of 15 test items and has better randomness than APUF.

[0045] In order to reflect the correlation between the output and the response, the output response of the dual-path delay difference PUF circuit of the present invention is tested using the autocorrelation function. The test results are as follows: Fig.13 Analysis Fig.13 It can be seen that within the 95% confidence interval, the ACF value of the PDA-PUF response is 0.0141, which is close to the ideal value of 0, reflecting that the response of the dual-path delay difference PUF circuit of the present invention has good spatial independence.

[0046] Uniqueness is used to identify the differences between different PUF individuals, and is generally measured by the average intra-chip Hamming distance. Ideally, when the same stimulus acts on multiple different PUF individuals, the different bits between the output responses of any two PUF individuals should account for 1 / 2. The uniqueness is usually expressed by the statistical value of the number of different bits between the output responses when the same stimulus acts on multiple different PUF individuals. Under ideal conditions, the PUF circuit can output the same response under any circumstances given the same stimulus. However, due to factors such as ambient temperature changes, power supply voltage fluctuations, and device aging, noise will inevitably be mixed into the response. Therefore, it is necessary to introduce a reliability index to measure the ability of the PUF circuit to reproduce the response. The reliability index is usually measured by the average inter-chip Hamming distance, that is, by comparing the number of different bits between the output responses of the same PUF individuals under the same stimulus in different environments or voltage conditions.

[0047] The inter-chip Hamming distance and intra-chip Hamming distance fitting curve of the dual-path delay difference PUF circuit of the present invention are shown in FIG. Fig.14 shown. Fig.14 The blue part shows the Gaussian fitting curve obtained by cyclically reading the output response of the PDA-PUF. Fig.14 The red part in the middle shows the Inter-HD curve of PDA-PUF after normalization and Gaussian fitting.

[0048] analyze Fig.14 It can be seen that the normalized average inter-chip Hamming distance of the dual-path delay difference PUF circuit of the present invention is 0.4998, and the corresponding uniqueness is 49.98%, which is close to the ideal value of 50%. It can be seen that the dual-path delay difference PUF circuit of the present invention has good uniqueness. The normalized average intra-chip Hamming distance of the dual-path delay difference PUF circuit of the present invention is 0.0133, and the corresponding reliability is 98.67%, which is close to the ideal value of 100%. It can be seen that the dual-path delay difference PUF circuit of the present invention has good reliability.

[0049] In normal working scenarios, the PUF circuit will be inevitably affected by noise, which may cause the PUF circuit to produce unstable response bits. In order to test the stability of the dual-path delay difference PUF circuit of the present invention, 10K groups of the same stimulus were used to repeat the test of the dual-path delay difference PUF circuit of the present invention 50 times in the same FPGA and the same experimental environment, and its stability was calculated after each repetition. The results are shown in Figure 2. Fig.15 As shown, it can be seen that after 50 repeated tests, the stability of the dual-path delay difference PUF circuit of the present invention is above 97%. Fig.16The relationship between the number of responses (from 100 to 10K) and the response stability after 50 repeated tests of the dual-path delay difference PUF circuit of the present invention and six common XOR-PUFs, that is, the proportion of unstable bits to the current number of responses, is shown. It can be obtained that the stability of the present invention is close to that of 3XOR-PUF.

[0050] The performance and overhead of the dual-path delay difference PUF circuit of the present invention are compared with those of the existing PUF circuit. The comparison data is shown in Table 3:

[0051] Table 3 Comparison of performance and overhead of various PUF circuits

[0052]

[0053] Through Table 3, a comprehensive evaluation is made on the dual-path delay difference PUF circuit of the present invention. As shown in Table 3, the performance comparisons of the dual-path delay difference PUF circuit of the present invention with APUF and common XOR-PUF circuits as well as the circuit structure hardware resource overhead are listed. It can be found that when the number of CRPs used for training is 100w to resist machine learning modeling attacks, the dual-path delay difference PUF circuit of the present invention has the ability to resist machine learning attacks close to 6XOR-PUF, which is better than 5XOR-PUF. The randomness and uniqueness of the dual-path delay difference PUF circuit of the present invention are both close to the ideal value of 50%, and the stability is close to 3XOR-PUF. In terms of hardware overhead, the hardware resources consumed by the dual-path delay difference PUF circuit of the present invention are between 2XOR-PUF and 3XOR-PUF. Compared with the 6XOR-PUF with comparable anti-machine learning attack capabilities, the overhead is reduced by nearly half and it is more stable.

[0054] In summary, the dual-path delay difference PUF circuit of the present invention inserts multiple delay arbitration modules in the parallel delay module, and XORs the extracted intermediate response with the final response, thereby improving the complexity of the mapping relationship between stimulus and response. It has the characteristics of low overhead, strong anti-attack ability, and easy FPGA implementation, and has good randomness, uniqueness, reliability and stability.

Claims

1. A dual-path delay difference PUF circuit, comprising two delay modules, two arbitrators and an XOR gate, the XOR gate being referred to as a first XOR gate, the first XOR gate having a first input terminal, a second input terminal and an output terminal, each of the arbitrators having a first input terminal, a second input terminal and an output terminal, each delay module comprising an n switch unit array, n being an integer greater than or equal to 2, each switch unit array comprising m switch units, m being an integer greater than or equal to 1, each switch unit having an excitation terminal, a first input terminal, a second input terminal, a first output terminal and a second output terminal, when the excitation terminal thereof is connected to an excitation signal of a high level 1, the first input terminal and the first output terminal thereof are turned on, and the second input terminal and the first output terminal thereof are turned on. The first and second output ends are turned on, and when the excitation end thereof is connected to an excitation signal of a low level 0, the first input end and the second output end thereof are turned on, and the second input end and the first output end are turned on; in each switch unit array, the first input end of the first switch unit is the first input end of the switch unit array, the second input end of the first switch unit is the second input end of the switch unit array, the first output end of the sth switch unit is connected to the first input end of the s+1th switch unit, the second output end of the sth switch unit is connected to the second input end of the s+1th switch unit, s=1, 2, ..., m-1, the first output end of the mth switch unit is the first output end of the switch unit array, and the second output end of the mth switch unit is connected to the second input end of the s+1th switch unit. is the second output end of the switch unit array, and the excitation end of the m switch units is the m-bit excitation end of the switch unit array; in each delay module, the first input end of the 1st switch unit array is the first input end of the delay module, the second input end of the 1st switch unit array is the second input end of the delay module, the first output end of the jth switch unit array is connected to the first input end of the j+1th switch unit array, and the second output end of the jth switch unit array is connected to the second input end of the j+1th switch unit array, j=1,2,…,n-1, the first output end of the nth switch unit array is the first output end of the delay module, and the second output end of the nth switch unit is the second input end of the delay module. Output end, the m-bit excitation end of the n switch unit array is the mn-bit excitation end of the delay module; the first input end and the second input end of the two delay modules are connected, and their connection ends are the input ends of the dual-path delay difference PUF circuit, the two delay modules correspond to the two arbiters one-to-one, and in a corresponding delay module and an arbitrator, the first output end of the delay module is connected to the first input end of the arbitrator, and the second output end of the delay module is connected to the second input end of the arbitrator, and the output ends of the two arbitrators are connected to the first input end and the second input end of the first XOR gate one-to-one, and the output end of the first XOR gate is the output end of the dual-path delay difference PUF circuit; it is characterized in that The first XOR gate also has a third input terminal. The dual-path delay difference PUF circuit also includes n-1 delay arbitration modules and an XOR logic gate array. Each delay arbitration module includes two arbitrators and an XOR gate. The two arbitrators are called the first arbitrator and the second arbitrator. The XOR gate is called the second XOR gate. The first arbitrator and the second arbitrator each have a first input terminal, a second input terminal and an output terminal. The second XOR gate has a first input terminal, a second input terminal and an output terminal. In each delay arbitration module, the first input terminal of the first arbitrator is the The first input end, the second input end of the first arbitrator is the second input end of the delay arbitration module, the first input end of the second arbitrator is the third input end of the delay arbitration module, the second input end of the second arbitrator is the fourth input end of the delay arbitration module, the output end of the first arbitrator is connected to the first input end of the second XOR gate, the output end of the second arbitrator is connected to the second input end of the second XOR gate, and the output end of the second XOR gate is the output end of the delay arbitration module; the XOR logic gate array includes n-1 XOR gates, and the XOR gate is called the third XOR gate , each of the third XOR gates has a first input terminal, a second input terminal and an output terminal; the two delay modules are respectively referred to as a first delay module and a second delay module, the first output terminal of the p-th switch unit array of the first delay module is connected to the first input terminal of the p-th delay arbitration module, the first output terminal of the p-th switch unit array of the second delay module is connected to the second input terminal of the p-th delay arbitration module, the second output terminal of the p-th switch unit array of the first delay module is connected to the third input terminal of the p-th delay arbitration module, the second output terminal of the p-th switch unit array of the second delay module is connected to the p-th The fourth input end of the delay arbitration module is connected, p=1,2...,n-1; the output end of the first delay arbitration module is connected to the first input end of the first third XOR gate, the output end of the second delay arbitration module is connected to the second input end of the first third XOR gate, the output end of the qth delay arbitration module is connected to the second input end of the q-1th third XOR gate, q=3,4,...,n-1; the output end of the fth third XOR gate is connected to the first input end of the f+1th third XOR gate, f=1,2,...,n-2; the output end of the n-1th third XOR gate and the third input end of the first XOR gate are connected to the dual-path delay difference PUF circuit.

2. A dual-path delay difference PUF circuit according to claim 1, characterized in that Each switch unit includes two two-choose-one selectors, each of which has a first input terminal, a second input terminal, a selection terminal and an output terminal. When the selection terminal is connected to a high level 1, the second input terminal is connected to the output terminal, and the signal output by the output terminal is the signal connected to the second input terminal. When the selection terminal is connected to a high level 0, the first input terminal is connected to the output terminal, and the signal output by the output terminal is the signal connected to the first input terminal. The two two-choose-one selectors are respectively referred to as the first two-choose-one selector and the second two-choose-one selector. The first input terminal of the first two-choose-one selector is connected to the second two-choose-one selector. The second input end of the first two-selector is connected, and its connection end is the first input end of the switch unit, the second input end of the first two-selector is connected to the first input end of the second two-selector, and its connection end is the second input end of the switch unit, the selection end of the first two-selector is connected to the selection end of the second two-selector, and its connection end is the excitation end of the switch unit, the output end of the first two-selector is the first output end of the switch unit, and the output end of the second two-selector is the second output end of the switch unit.

3. A dual-path delay difference PUF circuit according to claim 1, characterized in that Each arbitrator includes two two-input NAND gates, each of which has a first input terminal, a second input terminal and an output terminal. The two two-input NAND gates are respectively referred to as a first NAND gate and a second NAND gate. The first input terminal of the first NAND gate is the first input terminal of the arbitrator, the second input terminal of the second NAND gate is the second input terminal of the arbitrator, the second input terminal of the first NAND gate is connected to the output terminal of the second NAND gate, the first input terminal of the second NAND gate is connected to the output terminal of the first NAND gate, and the connection terminal thereof is the output terminal of the arbitrator.

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