Digital latch circuit and optical module

Abstract

The invention discloses a digital latch circuit and an optical module, and relates to the technical field of optical communication, the digital latch circuit comprises a signal generator, a logic arithmetic unit and a digital latch, the signal generator is used for outputting a first delay reset signal, a second delay reset signal and a return-to-zero signal according to an external reset signal; the logic-arithmetic unit is used for performing preset logic operation on an external input signal and a first delay reset signal and then outputting the external input signal and the first delay reset signal; and the digital latch is used for performing return-to-zero reset on the output end of the digital latch according to the return-to-zero signal, and is used for latching a high / low level to the output end of the digital latch if a high / low level pulse appears in the output signal of the logic arithmetic unit within the effective time period of the second delay reset signal, otherwise, latching the low / high level to the output end of the digital latch. According to the invention, the output signal is quickly zeroed, and then the input signal is quickly responded and locked, so that the technical problem of a high-speed sudden response control circuit faced by the 50G PON OLT is effectively solved.

Description

Technical Field

[0001] The present invention relates to the field of optical communication technology, and in particular to a digital latch circuit and an optical module. Background Art

[0002] At present, domestic operators are actively promoting the standardization and prototype development of the next generation optical access network 50G PON (optical access network). In the PON system architecture network, OLT represents the central office optical module; ONU represents the terminal optical module; Splitter represents the optical splitter; the downlink service data sent by OLT to ONU is sent in a continuous broadcast form. After each ONU receives the downlink signal through a continuous optical receiver, it determines whether the service data belongs to itself based on the paired ID; the uplink service data sent by ONU to OLT is sent in a time division multiplexing mode. During the ONU registration process, OLT will allocate a time period for sending uplink signals to each online ONU. Although the standardization of 50G PON is nearing completion, all technical difficulties have not yet been overcome, especially high-speed burst response control technology.

[0003] In the PON field, the uplink signal is a burst data packet sent by each ONU according to its own business data upload needs, and the signal power and state of each uplink burst data packet are different. When PONOLT continuously receives the uplink burst data packet signal, in order to ensure the signal transmission quality and avoid failure, its uplink burst signal receiving circuit generally needs to use a real-time detection circuit to quickly detect the signal state of each burst data packet, and then use a high-speed burst control circuit to quickly output the corresponding control signal, and quickly adjust the uplink burst signal receiving circuit to the best working state suitable for the current burst data packet. Since the input signal on the 50G PON OLT side is a high-speed burst data packet with a rate of up to 50Gbps, this requires the optical signal receiver on the OLT side to have a high-speed burst response capability to receive high-speed burst data packets, and further requires a control circuit with high-speed burst response capability to be used in the signal sending and receiving circuits. For example, a digital latch circuit can be used to respond to and lock the control signal in each burst data packet.

[0004] The common digital latch circuit currently uses a level-triggered D latch, and its working principle is: if the input terminal D of the D latch is 1, when the clock signal input terminal CLK of the D latch is 1 or high level, the output terminal Q of the D latch is 1; when the clock signal input terminal CLK of the D latch is 0 or low level, the input terminal D is invalid, the input terminal NAND gate is set to 1, and the output terminal Q remains unchanged, realizing the latch function. If the input terminal D of the D latch is 0, when CLK=1 or high level, the output terminal Q is 0; when CLK=0 or low level, the output terminal Q remains unchanged, realizing the latch function. The characteristics of the above digital latch circuit are: when the clock signal CLK is high level, the output Q follows the input D change; when the clock signal CLK changes from high level to low level, the output Q latches the input D level state at this moment; when CLK is low level, the output Q remains in the previous state. If a high-speed burst response control circuit is designed based on the current digital latch circuit, at least the following two problems will arise:

[0005] First, the control signal for the current burst data packet will continue until the next burst data packet arrives, until the next burst data packet and the CLK signal jointly trigger the output signal of the latch to change, and then it can be adjusted to the control signal for the next burst data packet. Moreover, in some cases, such as when the signal states of the two burst data packets are very different (for example, the optical power is very different), the control signal cannot be adjusted to the control signal for the next burst data packet, thereby affecting and degrading the reception quality of the next burst data packet, and even causing the next burst data packet to fail to be received normally.

[0006] Secondly, for the current burst data packet, during the period when CLK is at a valid level, since the output Q of the latch changes with the change of the input D, the control signal at this time will repeatedly jump with the change of the input burst data packet, causing the uplink burst signal receiving circuit and its output signal to repeatedly jump, resulting in abnormal operation.

[0007] In summary, the existing digital latch circuit has defects in responding to and locking the control signal of each burst data packet in the 50G PON OLT, which makes it difficult to meet the demand for high-speed burst response control circuits in the 50G PON OLT. It is necessary to improve the existing digital latch circuit. Summary of the invention

[0008] The embodiments of the present invention provide a digital latch circuit and an optical module to solve the technical problem that the existing digital latch circuit in the related art has defects in responding to and locking the control signal of each burst data packet in the 50G PON OLT, and it is difficult to meet the requirements of the high-speed burst response control circuit in the 50G PON OLT.

[0009] In a first aspect, a digital latch circuit is provided, comprising:

[0010] A signal generator, which is used to output a first delayed reset signal, a second delayed reset signal and a return-to-zero signal according to an external reset signal;

[0011] A logic operator, connected to the signal generator, configured to perform a preset logic operation on an external input signal and the first delayed reset signal and then output the result;

[0012] A digital latch is connected to the signal generator and the logic operator, and is used to reset its output end to zero according to the zeroing signal; and is used to latch the high / low level to its output end if a high / low level pulse appears in the output signal of the logic operator during the effective period of the second delayed reset signal, otherwise, latch the low / high level to its output end.

[0013] In some embodiments, the signal generator includes a first delay device, a second delay device, a third delay device, and a two-input enable XOR gate;

[0014] The input end of the first delay device, the input end of the second delay device and the second input end of the two-input enable XOR gate are reset signal input ends of the signal generator;

[0015] The output end of the first delay device is connected to the first input end of the two-input enable XOR gate, and the enable signal input end of the two-input enable XOR gate is connected to the reset signal input end of the signal generator;

[0016] The output end of the second delay device is connected to the input end of the third delay device and the logic operator, and the output end of the third delay device is connected to the digital latch.

[0017] In some embodiments, the first delay device, the second delay device, and the third delay device all include a first-order or multi-order RC low-pass filter.

[0018] In some embodiments, the two-input enabled XOR gate includes a first inverter, a second inverter, a first two-input enabled AND gate, a second two-input enabled AND gate, and a two-input enabled OR gate;

[0019] The input end of the first inverter and the first input end of the first two-input enabled AND gate are short-circuited to serve as the first input end of the two-input enabled XOR gate, and the output end of the first inverter is connected to the first input end of the second two-input enabled AND gate;

[0020] The input end of the second inverter and the second input end of the second two-input enabled AND gate are short-circuited to serve as the second input end of the two-input enabled XOR gate, and the output end of the second inverter is connected to the second input end of the first two-input enabled AND gate;

[0021] The enable input terminal of the first two-input enable AND gate and the enable input terminal of the second two-input enable AND gate are short-circuited to serve as the enable signal input terminal of the two-input enable XOR gate;

[0022] The output end of the first two-input enable AND gate is connected to the first input end of the two-input OR gate, the output end of the second two-input enable AND gate is connected to the second input end of the two-input OR gate, and the output end of the two-input OR gate is the output end of the two-input enable XOR gate.

[0023] In some embodiments, the first two-input enable AND gate includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a third inverter, and a fourth inverter;

[0024] The input end of the fourth inverter is connected to the gate of the first NMOS tube and the gate of the fourth PMOS tube as the enable input end of the first two-input enable AND gate, and the output end of the fourth inverter is connected to the gate of the first PMOS tube;

[0025] The gate of the second NMOS tube is connected to the gate of the third PMOS tube and serves as the second input terminal of the first two-input enable AND gate;

[0026] The source of the second NMOS tube is connected to the drain of the first NMOS tube, the source of the first NMOS tube is grounded, and the drain of the second NMOS tube is connected to the source of the third NMOS tube;

[0027] The gate of the third NMOS tube is connected to the gate of the second PMOS tube and serves as the first input end of the first two-input enable AND gate, and the drain of the third NMOS tube is connected to the drain of the second PMOS tube, the drain of the third PMOS tube, the drain of the fourth PMOS tube, and the input end of the third inverter;

[0028] The source of the second PMOS tube is connected to the source of the third PMOS tube and then connected to the drain of the first PMOS tube. The source of the first PMOS tube is connected to a power supply. The source of the fourth PMOS tube is connected to a power supply. The output end of the third inverter serves as the output end of the first two-input enable AND gate.

[0029] In some embodiments, the digital latch includes a power-on self-reset signal generator, a first two-input NAND gate, a second two-input NAND gate, a first power-on self-reset two-input NAND gate, a second power-on self-reset two-input NAND gate, a fourth NMOS transistor, a fifth PMOS transistor, a first resistor, a fifth inverter, a sixth inverter, a seventh inverter, an eighth inverter, a ninth inverter, a tenth inverter, and an eleventh inverter;

[0030] The first input end of the second two-input NAND gate is used as the signal input end of the digital latch and is connected to the input end of the fifth inverter; the second input end of the second two-input NAND gate is connected to the first input end of the first two-input NAND gate and is used as the clock signal input end of the digital latch;

[0031] The output end of the fifth inverter is connected to the second input end of the first two-input NAND gate; the output end of the first two-input NAND gate is connected to the first input end of the first power-on self-reset two-input NAND gate;

[0032] The output end of the second two-input NAND gate is connected to the second input end of the second power-on self-reset two-input NAND gate; the output end of the first power-on self-reset two-input NAND gate is connected to the first input end of the second power-on self-reset two-input NAND gate, the first end of the first resistor, and the input end of the sixth inverter; the second end of the first resistor is connected to the drain of the fifth PMOS tube, the gate of the fifth PMOS tube is grounded, and the source of the fifth PMOS tube is connected to the power supply;

[0033] The output end of the second power-on self-reset two-input NAND gate is connected to the second input end of the first power-on self-reset two-input NAND gate, the drain of the fourth NMOS tube, and the input end of the eighth inverter;

[0034] The power-on self-reset signal input terminal of the first power-on self-reset two-input NAND gate and the power-on self-reset signal input terminal of the second power-on self-reset two-input NAND gate are connected to the output terminal of the power-on self-reset signal generator;

[0035] The output end of the sixth inverter is connected to the input end of the seventh inverter, and the output end of the seventh inverter serves as the inverting output end of the digital latch;

[0036] The input end of the tenth inverter serves as the zeroing control signal input end of the digital latch, the output end of the tenth inverter is connected to the input end of the eleventh inverter, the output end of the eleventh inverter is connected to the gate of the fourth NMOS tube, and the source of the fourth NMOS tube is grounded;

[0037] The output end of the eighth inverter is connected to the input end of the ninth inverter, and the output end of the ninth inverter serves as the in-phase output end of the digital latch.

[0038] In some embodiments, the first power-on self-reset two-input NAND gate includes a fifth NMOS transistor, a sixth NMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, a two-input NOR gate, and a twelfth inverter;

[0039] The gate of the fifth NMOS tube is connected to the gate of the sixth PMOS tube and serves as the first input terminal of the first power-on self-reset two-input NAND gate, and the gate of the sixth NMOS tube is connected to the gate of the seventh PMOS tube and serves as the second input terminal of the first power-on self-reset two-input NAND gate;

[0040] The source of the fifth NMOS tube is connected to the drain of the sixth NMOS tube, the source of the sixth NMOS tube is grounded, and the drain of the fifth NMOS tube is connected to the drain of the sixth PMOS tube, the drain of the seventh PMOS tube, and the first input end of the two-input NOR gate;

[0041] The source of the sixth PMOS tube is connected to the power supply, the source of the seventh PMOS tube is connected to the power supply, and the second input end of the two-input NOR gate is connected to the output end of the power-on self-reset signal generator;

[0042] The output end of the two-input NOR gate is connected to the input end of the twelfth inverter, and the output end of the twelfth inverter serves as the output end of the first power-on self-reset two-input NAND gate.

[0043] In some embodiments, the power-on self-reset signal generator includes a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube, a tenth NMOS tube, a second resistor, an eighth PMOS tube, a ninth PMOS tube, a tenth PMOS tube, and an eleventh PMOS tube;

[0044] The source of the seventh NMOS tube is grounded, and the gate and drain of the seventh NMOS tube are connected and then connected to the first end of the second resistor, the gate of the ninth PMOS tube, the source of the eighth NMOS tube, and the gate of the ninth NMOS tube;

[0045] The second end of the second resistor is connected to the drain of the ninth PMOS tube, the gate and drain of the eighth PMOS tube are connected and then connected to the source of the ninth PMOS tube and the drain of the tenth NMOS tube, and the source of the eighth PMOS tube is connected to a power supply;

[0046] The source of the tenth NMOS tube is grounded, the gate of the tenth NMOS tube is connected to the drain of the ninth NMOS tube and the drain of the eleventh PMOS tube, and serves as the output end of the power-on self-reset signal generator;

[0047] The source of the ninth NMOS tube is grounded, the source of the eleventh PMOS tube is connected to a power source, the source of the tenth PMOS tube is connected to a power source, and the gate and drain of the tenth PMOS tube are connected and then connected to the drain and gate of the eighth NMOS tube.

[0048] In some embodiments, the logic operator is a two-input AND gate.

[0049] In a second aspect, an optical module is provided, comprising the aforementioned digital latch circuit.

[0050] The beneficial effects brought about by the technical solution provided by the present invention include:

[0051] The embodiment of the present invention provides a digital latch circuit and an optical module. The digital latch circuit includes a signal generator, a logic operator and a digital latch. The digital latch, under the cooperation of the signal generator logic operator and the action of an external reset signal (a reset signal that matches the timing, length, etc. of each burst data packet), first resets the output signal to zero and then quickly responds to and locks the input signal (a control signal that matches each burst data packet). The burst locking speed can be less than 100ns, which effectively solves the technical problem of high-speed burst response control circuit faced by 50G PON OLT. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0053] Figure 1 A principle block diagram of a digital latch circuit provided by an embodiment of the present invention;

[0054] Figure 2 A transient signal simulation result diagram of a digital latch circuit provided by an embodiment of the present invention;

[0055] Figure 3 A functional block diagram of a signal generator provided by an embodiment of the present invention;

[0056] Figure 4A transient signal simulation result diagram of a first delayed reset signal and a second delayed reset signal output by a signal generator provided in an embodiment of the present invention;

[0057] Figure 5 A transient signal simulation result diagram of a return-to-zero signal output by a signal generator provided in an embodiment of the present invention;

[0058] Figure 6 A transient signal simulation result diagram of the output signal of the logic operator provided in an embodiment of the present invention;

[0059] Figure 7 A transient signal simulation result diagram of a digital latch provided by an embodiment of the present invention;

[0060] Figure 8 The embodiment of the present invention provides Figure 3 The principle block diagram of the two-input enable XOR gate;

[0061] Fig. 9 The embodiment of the present invention provides Figure 8 A circuit diagram of a two-input enable AND gate;

[0062] Fig.10 A principle block diagram of a digital latch provided by an embodiment of the present invention;

[0063] Fig.11 The embodiment of the present invention provides Fig.10 A circuit diagram of a first power-on self-reset two-input NAND gate;

[0064] Fig.12 The embodiment of the present invention provides Fig.10 A circuit diagram of the power-on self-reset signal generator. DETAILED DESCRIPTION

[0065] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0066] The embodiment of the present invention provides a digital latch circuit, which can solve the technical problem that the existing digital latch circuit has defects when responding to and locking the control signal of each burst data packet in the 50G PON OLT, and it is difficult to meet the requirements of the high-speed burst response control circuit in the 50GPON OLT.

[0067] See also Figure 1As shown, an embodiment of the present invention provides a digital latch circuit, including: a signal generator, a logic operator and a digital latch.

[0068] The signal generator is used to output a first delayed reset signal, a second delayed reset signal and a return-to-zero signal according to an external reset signal, wherein the effective delay period of the second delayed reset signal is greater than the effective delay period of the first delayed reset signal.

[0069] The logic operator is connected to the signal generator, and is used for performing a preset logic operation on the input signal and the first delayed reset signal and then outputting the result.

[0070] The digital latch is connected to the signal generator and the logic operator, and is used to reset the output signal of the digital latch to zero according to the zeroing signal. During the effective delay period of the second delayed reset signal, if a high / low level pulse appears in the output signal of the logic operator (one or more high / low level pulses, which will be further explained later by taking the high level pulse as an example), the high / low level will be latched to the output end of the digital latch; otherwise, the low / high level will be latched to the output end of the digital latch, thereby realizing the "one-trigger-lock" function of the output signal of the digital latch.

[0071] Specifically, see Figure 1 As shown, the logic operator is a two-input AND gate or a logic unit with similar functions, and its first input terminal is used as the data input terminal of the digital latch circuit of the embodiment of the present invention, and is connected to the input signal Din.

[0072] The input end of the signal generator is the reset signal input end RESET, and the first delayed reset signal RST_D10n of the first output end of the signal generator is connected to the second input end of the logic operator. The main function of the logic operator is to limit the input signal Din (connected to the first input end of the logic operator) to the effective delay period of the first delayed reset signal RST_D10n, that is, to perform an AND operation or a similar operation on the input signal Din and the first delayed reset signal RST_D10n, and output the calculated signal CLKandRST10n.

[0073] The second delayed reset signal RST_D20n of the second output terminal of the signal generator is connected to the signal input terminal D of the digital latch. The return-to-zero signal Rto0 of the third output terminal of the signal generator is connected to the return-to-zero control signal input terminal Rto0 of the digital latch. The output signal CLKandRST10n of the logic operator is connected to the clock signal input terminal CLK of the digital latch. The in-phase output terminal Q of the digital latch serves as the in-phase output terminal VQ of the digital latch circuit of the embodiment of the present invention. The inverting output terminal QB of the digital latch serves as the inverting output terminal VQB of the in-phase output port of the digital latch circuit of the embodiment of the present invention. The main function of the digital latch is: within the effective delay period of the second delayed reset signal RST_D20n, the output signal CLKandRST10n within this period is "triggered once and locked". That is, during the effective delay period of the second delayed reset signal RST_D20n, only if the output signal CLKandRST10n has a high level pulse (one or more high level pulses), the output VQ of the digital latch is high; otherwise, the output VQ is low.

[0074] Figure 2 1 is a transient signal simulation result diagram of the digital latch circuit of the embodiment of the present invention, / RESET is an external reset signal, / RST_D10n (black dashed line) is the first delayed reset signal RST_D10n output by the signal generator, / RST_20n (black dotted line) is the second delayed reset signal RST_D20n output by the signal generator, / Din is the external input signal Din, / I29 / CLKandRST10n is the output signal CLKandRST10n of the logic operator (a two-input AND gate or a logic unit with similar functions), / VQ is the in-phase output terminal signal VQ of the digital latch circuit of the embodiment of the present invention, and / Rto0 is the return-to-zero signal Rto0 output by the signal generator.

[0075] Depend on Figure 2It can be seen that: when the external reset signal / RESET (for example, a reset signal that matches the timing, length, etc. of each burst data packet) comes ( / RESET changes from 0 to 1), the signal generator will generate a corresponding return-to-zero signal / Rto0 to perform a return-to-zero reset operation on the in-phase output terminal / VQ of the digital latch. The external input signal / Din (for example, the control signal of each burst data packet) and the first delayed reset signal / RST_D10n are processed by a logic operator (a two-input AND gate or a logic unit with similar functions) to obtain a signal / I29 / CLKandRST10n. Compared with the external input signal / Din, the high-level signal time length of / I29 / CLKandRST10n is compressed within the period when / RST_D10n is high. For the digital latch, I29 / CLKandRST10n is used as the clock input signal of the digital latch, and / RESET_D20n is used as the data input signal of the digital latch. During the period when / RESET_20n is at a high level, only after a high level pulse appears in / I29 / CLKandRST10n, the output signal VQ of the digital latch circuit of the embodiment of the present invention will become a high level; otherwise, the output signal VQ of the digital latch circuit of the embodiment of the present invention is a low level. That is, the digital latch in the digital latch circuit of the embodiment of the present invention completes the latching operation of the external input signal / Din under the cooperation of the signal generator and the logic operator.

[0076] When the digital latch circuit of the embodiment of the present invention is applied to the high-speed burst control circuit structure, firstly, a reset function (control signal reset function) is designed in the initial stage of receiving each burst data packet, that is, in the initial stage of receiving each burst data packet, the control signal is first briefly reset to the initial state (or reset function), so that the working state of the uplink burst signal receiving circuit is uniformly adjusted to the initial state when receiving each burst data packet, thereby avoiding the control signal for the current burst data packet affecting and degrading the working state and quality of the uplink burst signal receiving circuit when receiving the next burst data packet. Secondly, a "one-time excitation and locking" scheme is designed, that is, "when the clock signal CLK is at a valid level (such as a high level), as long as one or more high-level pulses appear at the signal input terminal D, the output terminal Q (VQ) of the digital latch is locked to a high level, avoiding the control signal for the current burst data packet to repeatedly jump with the change of the input burst data packet, thereby ensuring the stability of the working state of the uplink burst signal receiving circuit.

[0077] In summary, the digital latch circuit in the embodiment of the present invention includes a signal generator, a logic operator and a digital latch. The digital latch, under the cooperation of the signal generator logic operator and the external reset signal (a reset signal that matches the timing, length, etc. of each burst data packet), realizes the output signal being reset to zero first and then the input signal (a control signal that matches each burst data packet) being quickly responded to and locked in the burst mode. The burst locking speed can be less than 100ns, which effectively solves the technical difficulties of the high-speed burst response control circuit faced by the 50G PON OLT. The digital latch circuit in the embodiment of the present invention is not only suitable for burst scenarios in the PON field, but also suitable for traditional digital latch circuit application scenarios, and can be used to solve the technical difficulties of high-speed burst response control circuits.

[0078] As an optional implementation, in an embodiment of the invention, see Figure 3 As shown, the signal generator includes a first delay device, a second delay device, a third delay device and a two-input enable XOR gate.

[0079] The input end of the first delayer, the input end of the second delayer and the second input end B of the two-input enable XOR gate are the reset signal end RESET of the signal generator, the output end of the first delayer is connected to the first input end A of the two-input enable XOR gate, and the enable signal input end EN of the two-input enable XOR gate is connected to the reset signal input end of the signal generator. The output end of the second delayer is connected to the input end of the third delayer and the second input end of the logic operator, and the output end of the third delayer is connected to the digital latch (signal input end D).

[0080] The signal generator uses the input reset signal RESET as a reference and derives multiple control signals from a single reset signal RESET to achieve precise control of the working states of other circuits.

[0081] Specifically, see Figure 3 As shown, the first delay device can be a 5ns delay device, and the second delay device and the third delay device are both 10ns delay devices. The 5ns delay device generally adopts a first-order or multi-order RC low-pass filter, and the RC time constant (i.e., the resistance value of the resistor R multiplied by the capacitance value of the capacitor C) is approximately equal to 5ns divided by M (the value range of M is generally 3 to 5). The 10ns delay device can be implemented by connecting two 5ns delay devices in series, or by a first-order or multi-order RC low-pass filter solution similar to the 5ns delay device.

[0082] Figure 4 for Figure 3 Figure 2 shows the transient signal simulation results of the first delayed reset signal / RST_D10n and the second delayed reset signal / RST_D20n output by the signal generator. Figure 4 It can be seen that compared with the external reset signal / RESET, the first delayed reset signal / RST_D10n is delayed by about 10.55ns (=56.22ns-45.67ns)≈10ns, and the second delayed reset signal / RST_D20n is delayed by about 19.58ns (=65.25ns-45.67ns)≈20ns.

[0083] Figure 5 for Figure 3 The transient signal simulation result diagram of the zero return signal / Rto0 (VT(“ / Rto0”)) output by the signal generator. Figure 5 It can be seen that the pulse width of the return-to-zero signal / Rto0 is approximately 4.65ns (=147.35ns-142.78ns)≈5ns.

[0084] Figure 6 for Figure 1 The transient signal simulation result diagram of the output signal of the logic operator in the figure. Figure 6 It can be seen that only when / RESET_10n (black dotted line) is at a high level, the high level of the input signal / Din will be transmitted to / I29 / CLKandRST10n. When / RESET_10n (black dotted line) is at a low level, / I29 / CLKandRST10n is always at a low level.

[0085] Figure 7 for Figure 1 The transient signal simulation result of the digital latch in FIG. Figure 7 It can be seen that: during the period when the return-to-zero signal / Rto0 is at a high level, the output Q (VQ) of the digital latch is cleared to a low level; during the period when the return-to-zero signal / Rto0 is at a low level and / RESET_20n (black dotted line) is at a high level, the output Q (VQ) of the digital latch will be latched to a high level only when a high level pulse appears in the signal / I29 / CLKandRST10n; otherwise, the output Q (VQ) of the digital latch is latched to a low level.

[0086] As an optional implementation, in an embodiment of the invention, see Figure 8 As shown, the two-input enabled XOR gate includes a first inverter, a second inverter, a first two-input enabled AND gate, a second two-input enabled AND gate and a two-input enabled OR gate.

[0087] The input end of the first inverter and the first input end INA of the first two-input enable AND gate are short-circuited to serve as the first input end A of the two-input enable XOR gate, the output end of the first inverter is connected to the first input end INA of the second two-input enable AND gate, the input end of the second inverter and the second input end INB of the second two-input enable AND gate are short-circuited to serve as the second input end B of the two-input enable XOR gate, and the output end of the second inverter is connected to the second input end INB of the first two-input enable AND gate.

[0088] The enable input terminal EN of the first two-input enable AND gate and the enable input terminal EN of the second two-input enable AND gate are short-circuited to serve as the enable signal input terminal EN of the two-input enable XOR gate.

[0089] The output end of the first two-input enable AND gate is connected to the first input end INA of the two-input OR gate, the output end of the second two-input enable AND gate is connected to the second input end INB of the two-input OR gate, and the output end of the two-input OR gate is the output end of the two-input enable XOR gate (the output end of the return-to-zero signal Rto0).

[0090] Further, see Fig. 9 As shown, the first two-input enable AND gate includes a first NMOS tube MN1, a second NMOS tube MN2, a third NMOS tube MN3, a first PMOS tube MP1, a second PMOS tube MP2, a third PMOS tube MP3, a fourth PMOS tube MP4, a third inverter and a fourth inverter.

[0091] The input end of the fourth inverter is the enable input end EN of the first two-input enable AND gate, and is connected to the gate of the first NMOS transistor MN1 and the gate of the fourth PMOS transistor MP4. The output end of the fourth inverter is connected to the gate of the first PMOS transistor MP1.

[0092] The gate of the second NMOS transistor MN2 is connected to the gate of the third PMOS transistor MP3 and serves as the second input terminal INB of the first two-input enable AND gate.

[0093] The source of the second NMOS transistor MN2 is connected to the drain of the first NMOS transistor MN1 , the source of the first NMOS transistor MN1 is grounded, and the drain of the second NMOS transistor MN2 is connected to the source of the third NMOS transistor MN3 .

[0094] The gate of the third NMOS tube MN3 is connected to the gate of the second PMOS tube MP2 and serves as the first input terminal INA of the first two-input enable AND gate; the drain of the third NMOS tube MN3 is simultaneously connected to the drain of the second PMOS tube MP2, the drain of the third PMOS tube MP3, the drain of the fourth PMOS tube MP4, and the input terminal of the third inverter.

[0095] The source of the second PMOS tube MP2 and the source of the third PMOS tube MP3 are short-circuited and then connected to the drain of the first PMOS tube MP1; the source of the first PMOS tube MP1 is connected to the power supply VCC, and the source of the fourth PMOS tube MP4 is connected to the power supply VCC; the output end of the third inverter serves as the output end of the first two-input enable AND gate.

[0096] exist Fig. 9 In the embodiment, the fourth PMOS tube MP4 is used as a device for controlling the output state of the first two-input enable AND gate. When the enable input terminal EN is high, the fourth PMOS tube MP4 is in an off state, the first NMOS tube MN1 and the first PMOS tube MP1 are in an on state, the first two-input enable AND gate works normally, and the input signals INA and INB are normally transmitted to the output end of the first two-input enable AND gate after being processed by the AND operation; when the enable input terminal EN is low, the fourth PMOS tube MP4 is in an on state, the first NMOS tube MN1 and the first PMOS tube MP1 are in an off state, the drain of the fourth PMOS tube MP4 is pulled to a high level, and the output end of the first two-input enable AND gate is a low level.

[0097] In addition, the second two-input enabled AND gate has the same structure as the first two-input enabled AND gate. The two-input enabled XOR gate and its two-input enabled AND gate in the embodiment of the present invention have a simple logic structure and a high operating speed, and can quickly respond and output signals based on the input reset signal RESET, thereby meeting the requirements of high-speed burst response.

[0098] As an optional implementation, in an embodiment of the invention, see Fig.10 As shown, the digital latch includes a power-on self-reset signal generator, a first two-input NAND gate, a second two-input NAND gate, a first power-on self-reset two-input NAND gate, a second power-on self-reset two-input NAND gate, a fourth NMOS tube MN4, a fifth PMOS tube MP5, a first resistor R1, a fifth inverter, a sixth inverter, a seventh inverter, an eighth inverter, a ninth inverter, a tenth inverter, and an eleventh inverter.

[0099] Among them, the first input terminal INA of the second two-input NAND gate serves as the signal input terminal D of the digital latch, connected to the input terminal of the fifth inverter, and the second input terminal INB of the second two-input NAND gate is connected to the first input terminal INA of the first two-input NAND gate as the clock signal input terminal CLK of the digital latch.

[0100] The output end of the fifth inverter is connected to the second input end INB of the first two-input NAND gate; the output end of the first two-input NAND gate is connected to the first input end INA of the first power-on self-reset two-input NAND gate.

[0101] The output end of the second two-input NAND gate is connected to the second input end INB of the second power-on self-reset two-input NAND gate; the output end of the first power-on self-reset two-input NAND gate is connected to the first input end INA of the second power-on self-reset two-input NAND gate, the first end of the first resistor R1, and the input end of the sixth inverter; the second end of the first resistor R1 is connected to the drain of the fifth PMOS tube MP5, the gate of the fifth PMOS tube MP5 is grounded, and the source of the fifth PMOS tube MP5 is connected to the power supply.

[0102] The output end of the second power-on self-reset two-input NAND gate is connected to the second input end INB of the first power-on self-reset two-input NAND gate, the drain of the fourth NMOS transistor MN4, and the input end of the eighth inverter.

[0103] The power-on self-reset signal input terminal of the first power-on self-reset two-input NAND gate and the power-on self-reset signal input terminal of the second power-on self-reset two-input NAND gate are connected to the output terminal pulse_stup0 of the power-on self-reset signal generator.

[0104] The output end of the sixth inverter is connected to the input end of the seventh inverter, and the output end of the seventh inverter serves as the inverting output end QB (VQB) of the digital latch.

[0105] The input end of the tenth inverter serves as the zero control signal input end Rto0 of the digital latch, the output end of the tenth inverter is connected to the input end of the eleventh inverter, the output end of the eleventh inverter is connected to the gate of the fourth NMOS transistor MN4, and the source of the fourth NMOS transistor MN4 is grounded.

[0106] The output end of the eighth inverter is connected to the input end of the ninth inverter, and the output end of the ninth inverter serves as the in-phase output end Q (VQ) of the digital latch.

[0107] As an optional implementation, in an embodiment of the invention, see Fig.11 As shown, the first power-on self-reset two-input NAND gate includes a fifth NMOS tube MN5, a sixth NMOS tube MN6, a sixth PMOS tube MP6, a seventh PMOS tube MP7, a two-input NOR gate, and a twelfth inverter.

[0108] The gate of the fifth NMOS transistor MN5 is connected to the gate of the sixth PMOS transistor MP6 and serves as the first input terminal INA of the first power-on self-reset two-input NAND gate; the gate of the sixth NMOS transistor MN6 is connected to the gate of the seventh PMOS transistor MP7 and serves as the second input terminal INB of the first power-on self-reset two-input NAND gate;

[0109] The source of the fifth NMOS transistor MN5 is connected to the drain of the sixth NMOS transistor MN6, and the source of the sixth NMOS transistor MN6 is grounded; the drain of the fifth NMOS transistor MN5 is connected to the drain of the sixth PMOS transistor MP6, the drain of the seventh PMOS transistor MP7, and the first input terminal INA of the two-input NOR gate;

[0110] The source of the sixth PMOS tube MP6 is connected to the power supply VCC, and the source of the seventh PMOS tube MP7 is connected to the power supply VCC; the second input terminal INB of the two-input NOR gate is connected to the output terminal pulse_stup0 of the power-on self-reset signal generator;

[0111] The output end of the two-input NOR gate is connected to the input end of the twelfth inverter, and the output end of the twelfth inverter serves as the output end of the first power-on self-reset two-input NAND gate.

[0112] In addition, the second power-on self-reset two-input NAND gate has the same structure as the first power-on self-reset two-input NAND gate.

[0113] As an optional implementation, in an embodiment of the invention, see Fig.12 As shown, the power-on self-reset signal generator includes a seventh NMOS tube MN7, an eighth NMOS tube MN8, a ninth NMOS tube MN9, a tenth NMOS tube MN10, a second resistor R2, an eighth PMOS tube MP8, a ninth PMOS tube MP9, a tenth PMOS tube MP10, and an eleventh PMOS tube MP11.

[0114] The source of the seventh NMOS tube MP7 is grounded, the gate of the seventh NMOS tube MP7 and the drain of the seventh NMOS tube MP7 are connected and then connected to the first end of the second resistor R2, the gate of the ninth PMOS tube MP9, the source of the eighth NMOS tube MN8, and the gate of the ninth NMOS tube MN9.

[0115] The second end of the second resistor R2 is connected to the drain of the ninth PMOS tube MP9, the gate and drain of the eighth PMOS tube MP8 are connected and then connected to the source of the ninth PMOS tube MP9 and the drain of the tenth NMOS tube MN10, and the source of the eighth PMOS tube MP8 is connected to the power supply VCC;

[0116] The source of the tenth NMOS transistor MN10 is grounded, and the gate of the tenth NMOS transistor MN10 is connected to the drain of the ninth NMOS transistor MN9 and the drain of the eleventh PMOS transistor MP11 , and serves as the output terminal pulse_stup0 of the power-on self-reset signal generator.

[0117] The source of the ninth NMOS tube MN9 is grounded, the source of the eleventh PMOS tube MP11 is connected to the power supply VCC, the source of the tenth PMOS tube MP10 is connected to the power supply VCC, and the gate and drain of the tenth PMOS tube MP10 are connected and then connected to the drain and gate of the ninth PMOS tube MP9.

[0118] The digital latch in the implementation of the present invention has: first, a power-on self-reset function, a reliable power-on self-reset signal generator circuit structure and a power-on self-reset two-input NAND gate circuit structure are designed. During the power-on process, the power-on self-reset signal generator automatically generates a power-on self-reset signal pulse_stup0, and resets the output end of the digital latch to a default state accordingly; second, it has a zeroing function, a zeroing circuit unit is designed, and the zeroing reset requirement at the initial stage of each burst data packet can be met; third, it has a "one-trigger lock" function, that is, within the CLK effective period, only after the input signal D has a high-level pulse (one or more high-level pulses), the output VQ of this digital latch is locked to high; otherwise, the output VQ is low.

[0119] An embodiment of the present invention provides an optical module, comprising the aforementioned digital latch circuit.

[0120] The optical module in the embodiment of the present invention includes a digital latch circuit with a zeroing function and a "one-trigger-lock" function, which realizes that during the effective period of the reset signal RESET corresponding to each burst data packet, the output is first reset to zero, and then the high-level pulse signal in the input control signal is quickly responded to and locked once triggered, thereby realizing a fast response and locking of the burst mode control signal in each burst data packet. The burst locking speed can be less than 100ns, thereby ensuring that the working state of the uplink burst signal receiving circuit is uniformly adjusted back to the initial state and then quickly adjusted to the optimal working state when receiving each burst data packet, effectively solving the technical difficulties of the high-speed burst response control circuit faced by the 50G PON OLT.

[0121] In the description of the present invention, it should be noted that the terms "upper", "lower", etc. indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific position, be constructed and operated in a specific position, and therefore cannot be understood as a limitation on the present invention. Unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be an indirect connection through an intermediate medium, or it can be a connection between the two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to the specific circumstances.

[0122] It should be noted that, in the present invention, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0123] The above description is only a specific embodiment of the present invention, so that those skilled in the art can understand or implement the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but should conform to the widest scope consistent with the principles and novel features of the present invention.

Claims

1. A digital latch circuit, characterized in that: include: A signal generator, which is used to output a first delayed reset signal, a second delayed reset signal and a return-to-zero signal according to an external reset signal; A logic operator, connected to the signal generator, configured to perform a preset logic operation on an external input signal and the first delayed reset signal and then output the result; A digital latch is connected to the signal generator and the logic operator, and is used to reset its output end to zero according to the zeroing signal; and is used to latch the high / low level to its output end if a high / low level pulse appears in the output signal of the logic operator during the effective period of the second delayed reset signal, otherwise, latch the low / high level to its output end.

2. The digital latch circuit according to claim 1, characterized in that: The signal generator comprises a first delay device, a second delay device, a third delay device and a two-input enable XOR gate; The input end of the first delay device, the input end of the second delay device and the second input end of the two-input enable XOR gate are reset signal input ends of the signal generator; The output end of the first delay device is connected to the first input end of the two-input enable XOR gate, and the enable signal input end of the two-input enable XOR gate is connected to the reset signal input end of the signal generator; The output end of the second delay device is connected to the input end of the third delay device and the logic operator, and the output end of the third delay device is connected to the digital latch.

3. The digital latch circuit according to claim 2, characterized in that: The first delay device, the second delay device and the third delay device all include a first-order or multi-order RC low-pass filter.

4. The digital latch circuit according to claim 2, characterized in that: The two-input enabled XOR gate includes a first inverter, a second inverter, a first two-input enabled AND gate, a second two-input enabled AND gate and a two-input enabled OR gate; The input end of the first inverter and the first input end of the first two-input enabled AND gate are short-circuited to serve as the first input end of the two-input enabled XOR gate, and the output end of the first inverter is connected to the first input end of the second two-input enabled AND gate; The input end of the second inverter and the second input end of the second two-input enabled AND gate are short-circuited to serve as the second input end of the two-input enabled XOR gate, and the output end of the second inverter is connected to the second input end of the first two-input enabled AND gate; The enable input terminal of the first two-input enable AND gate and the enable input terminal of the second two-input enable AND gate are short-circuited to serve as the enable signal input terminal of the two-input enable XOR gate; The output end of the first two-input enable AND gate is connected to the first input end of the two-input OR gate, the output end of the second two-input enable AND gate is connected to the second input end of the two-input OR gate, and the output end of the two-input OR gate is the output end of the two-input enable XOR gate.

5. The digital latch circuit according to claim 4, characterized in that: The first two-input enable AND gate includes a first NMOS tube, a second NMOS tube, a third NMOS tube, a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a third inverter and a fourth inverter; The input end of the fourth inverter is connected to the gate of the first NMOS tube and the gate of the fourth PMOS tube as the enable input end of the first two-input enable AND gate, and the output end of the fourth inverter is connected to the gate of the first PMOS tube; The gate of the second NMOS tube is connected to the gate of the third PMOS tube and serves as the second input terminal of the first two-input enable AND gate; The source of the second NMOS tube is connected to the drain of the first NMOS tube, the source of the first NMOS tube is grounded, and the drain of the second NMOS tube is connected to the source of the third NMOS tube; The gate of the third NMOS tube is connected to the gate of the second PMOS tube and serves as the first input end of the first two-input enable AND gate, and the drain of the third NMOS tube is connected to the drain of the second PMOS tube, the drain of the third PMOS tube, the drain of the fourth PMOS tube, and the input end of the third inverter; The source of the second PMOS tube is connected to the source of the third PMOS tube and then connected to the drain of the first PMOS tube. The source of the first PMOS tube is connected to a power supply. The source of the fourth PMOS tube is connected to a power supply. The output end of the third inverter serves as the output end of the first two-input enable AND gate.

6. The digital latch circuit according to claim 1, characterized in that: The digital latch includes a power-on self-reset signal generator, a first two-input NAND gate, a second two-input NAND gate, a first power-on self-reset two-input NAND gate, a second power-on self-reset two-input NAND gate, a fourth NMOS tube, a fifth PMOS tube, a first resistor, a fifth inverter, a sixth inverter, a seventh inverter, an eighth inverter, a ninth inverter, a tenth inverter and an eleventh inverter; The first input end of the second two-input NAND gate is used as the signal input end of the digital latch and is connected to the input end of the fifth inverter; the second input end of the second two-input NAND gate is connected to the first input end of the first two-input NAND gate and is used as the clock signal input end of the digital latch; The output end of the fifth inverter is connected to the second input end of the first two-input NAND gate; the output end of the first two-input NAND gate is connected to the first input end of the first power-on self-reset two-input NAND gate; The output end of the second two-input NAND gate is connected to the second input end of the second power-on self-reset two-input NAND gate; the output end of the first power-on self-reset two-input NAND gate is connected to the first input end of the second power-on self-reset two-input NAND gate, the first end of the first resistor, and the input end of the sixth inverter; the second end of the first resistor is connected to the drain of the fifth PMOS tube, the gate of the fifth PMOS tube is grounded, and the source of the fifth PMOS tube is connected to the power supply; The output end of the second power-on self-reset two-input NAND gate is connected to the second input end of the first power-on self-reset two-input NAND gate, the drain of the fourth NMOS tube, and the input end of the eighth inverter; The power-on self-reset signal input terminal of the first power-on self-reset two-input NAND gate and the power-on self-reset signal input terminal of the second power-on self-reset two-input NAND gate are connected to the output terminal of the power-on self-reset signal generator; The output end of the sixth inverter is connected to the input end of the seventh inverter, and the output end of the seventh inverter serves as the inverting output end of the digital latch; The input end of the tenth inverter serves as the zeroing control signal input end of the digital latch, the output end of the tenth inverter is connected to the input end of the eleventh inverter, the output end of the eleventh inverter is connected to the gate of the fourth NMOS tube, and the source of the fourth NMOS tube is grounded; The output end of the eighth inverter is connected to the input end of the ninth inverter, and the output end of the ninth inverter serves as the in-phase output end of the digital latch.

7. The digital latch circuit according to claim 6, characterized in that: The first power-on self-reset two-input NAND gate includes a fifth NMOS tube, a sixth NMOS tube, a sixth PMOS tube, a seventh PMOS tube, a two-input NOR gate, and a twelfth inverter; The gate of the fifth NMOS tube is connected to the gate of the sixth PMOS tube and serves as the first input terminal of the first power-on self-reset two-input NAND gate, and the gate of the sixth NMOS tube is connected to the gate of the seventh PMOS tube and serves as the second input terminal of the first power-on self-reset two-input NAND gate; The source of the fifth NMOS tube is connected to the drain of the sixth NMOS tube, the source of the sixth NMOS tube is grounded, and the drain of the fifth NMOS tube is connected to the drain of the sixth PMOS tube, the drain of the seventh PMOS tube, and the first input end of the two-input NOR gate; The source of the sixth PMOS tube is connected to the power supply, the source of the seventh PMOS tube is connected to the power supply, and the second input end of the two-input NOR gate is connected to the output end of the power-on self-reset signal generator; The output end of the two-input NOR gate is connected to the input end of the twelfth inverter, and the output end of the twelfth inverter serves as the output end of the first power-on self-reset two-input NAND gate.

8. The digital latch circuit according to claim 7, characterized in that: The power-on self-reset signal generator includes a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube, a tenth NMOS tube, a second resistor, an eighth PMOS tube, a ninth PMOS tube, a tenth PMOS tube, and an eleventh PMOS tube; The source of the seventh NMOS tube is grounded, and the gate and drain of the seventh NMOS tube are connected and then connected to the first end of the second resistor, the gate of the ninth PMOS tube, the source of the eighth NMOS tube, and the gate of the ninth NMOS tube; The second end of the second resistor is connected to the drain of the ninth PMOS tube, the gate and drain of the eighth PMOS tube are connected and then connected to the source of the ninth PMOS tube and the drain of the tenth NMOS tube, and the source of the eighth PMOS tube is connected to a power supply; The source of the tenth NMOS tube is grounded, the gate of the tenth NMOS tube is connected to the drain of the ninth NMOS tube and the drain of the eleventh PMOS tube, and serves as the output end of the power-on self-reset signal generator; The source of the ninth NMOS tube is grounded, the source of the eleventh PMOS tube is connected to a power source, the source of the tenth PMOS tube is connected to a power source, and the gate and drain of the tenth PMOS tube are connected and then connected to the drain and gate of the eighth NMOS tube.

9. The digital latch circuit according to claim 1, characterized in that: The logic operator is a two-input AND gate.

10. An optical module, characterized in that: include: The digital latch circuit according to any one of claims 1 to 9.

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