PCIe head credit unit size confirmation method, system, device and medium

Abstract

The invention relates to the technical field of data transmission and flow control, and discloses a PCIe head credit unit size confirmation method, system, device and medium, which are applied to an NFM mode of a PCIe link, the PCIe link comprises a home terminal device and an opposite terminal device, the method is executed by the home terminal device, and the method comprises the following steps: after a PCIe flow control initialization process is started, sending the PCIe flow control initialization process to the opposite terminal device; entering a newly added FCINIT0 state for negotiation, and receiving a header field size flow control message sent by opposite terminal equipment; and adjusting the size of the head credit unit of the home terminal device according to the number of TLP Prefix supported by the opposite terminal device. According to the method, related negotiation processes are added for head credit unit size negotiation lacked in a traditional PCIe flow control initialization process, so that a home terminal and an opposite terminal more accurately synchronize the sizes of the head credit units of the two parties, meanwhile, flexible adjustment is performed according to the total cache size of equipment, and more reasonable allocation of resources is realized.

Description

Technical Field

[0001] The present application relates to the technical field of data transmission and flow control, and in particular to a method, system, device and medium for confirming the size of a PCIe header credit unit. Background Art

[0002] In the PCIe protocol, for the NFM (Non-Flit-Mode) mode (applicable to PCIe5.0 and earlier protocols), in the initialization phase of Flow Control, the FC DLLPs (flow control messages) sent by the receiver will only inform the sender of the number of credits on the local side. For Data Buffer Credit, the data is negotiated in a fixed 4DW size of one Credit. The sender can accurately estimate the number of buffers on the receiving end.

[0003] However, for Header Buffer Credit, the size of Header Buffer Credit is determined by the receiver based on whether the local end supports the prefix and the number of prefixes supported, but this information is not included in the existing FC DLLPs. The sender knows the number of Header Credits of the receiver, but does not know the specific size of each Header Credit. Therefore, if the sender and the receiver support different prefix specifications, there may still be overflow packet loss or resource waste due to the inconsistency of the Credit sizes calculated by both parties.

[0004] Therefore, there is an urgent need for a method that can negotiate the size of the header credit unit in the PCIe flow control process to achieve optimal adjustment of resources. Summary of the invention

[0005] In view of this, the present application provides a PCIe header credit unit size confirmation method, system, device and medium, which can negotiate the size of the header credit unit in the PCIe flow control process to achieve optimal adjustment of resources. The technical solution is as follows.

[0006] In a first aspect, the present application provides a method for confirming the size of a PCIe header credit unit, the method being applied to an NFM mode of a PCIe link, the PCIe link comprising a local device and a peer device, the method being executed by the local device, the method comprising:

[0007] When the PCIe flow control initialization process is started, the newly added FC_INIT0 state is entered to receive the header size flow control message sent by the peer device; the FC_INIT0 state is the negotiation stage before entering the FC_INIT1 state; the header size flow control message contains the number of TLP Prefixes supported by the peer device;

[0008] Adjust the header credit unit size of the local device according to the number of TLP Prefixes supported by the peer device.

[0009] In an optional implementation, adjusting the header credit unit size of the local device according to the number of TLP Prefixes supported by the opposite device includes:

[0010] If the number of TLP Prefixes supported by the local device is less than or equal to the number of TLP Prefixes supported by the peer device, the header credit unit size of the local device is not adjusted;

[0011] If the number of TLP Prefixes supported by the local device is greater than the number of TLP Prefixes supported by the peer device, the size of the header credit unit of the local device is adjusted according to the maximum transmittable capability of the peer device.

[0012] In an optional implementation, the method further includes: if the peer device does not support the header field size flow control message, then when the PCIe flow control initialization process is started, directly entering the FC_INIT1 state.

[0013] In an optional implementation, the TLP Prefix quantity includes: a local prefix quantity and an end-to-end prefix quantity.

[0014] In an optional implementation, the method further includes: after completing the adjustment of the head credit unit size of the local device, entering the FC_INIT1 state.

[0015] The PCIe header credit unit size confirmation method provided by the present application has the following advantages:

[0016] The PCIe header credit unit size confirmation method of the present application is applied to the PCIe flow control initialization process in the NFM mode of the PCIe link. The PCIe link includes a local device and a peer device, and the method is executed by the local device. When the PCIe flow control initialization process is started, before entering the FC_INIT1 state, a new negotiation stage is added, namely the FC_INIT0 state. Specifically, before entering the FC_INIT1 state, the newly added FC_INIT0 state is entered to negotiate the header credit unit size, and receive the header field size flow control message sent by the peer device. The header field size flow control message is pre-constructed and contains the number of TLP Prefixes supported by the peer device. The local device compares the number of TLP Prefixes supported by the peer device in the header size flow control message with the number of TLP Prefixes supported by itself. If the number of TLP Prefixes supported by the local device is less than the number of TLP Prefixes supported by the peer device, the head credit unit size of the local device will not be adjusted. If an unsupported message type that exceeds the receiving capacity is received from the peer device later, it will be processed as a PCIE error; if the number of TLP Prefixes supported by the local device is greater than the number of TLP Prefixes supported by the peer device, the head credit unit size of the local device will be recalculated and adjusted according to the maximum transmittable capacity of the peer device, and the excess buffer will be replaced with a deeper depth. After completing the recalculation and adjustment of the head credit unit, enter the FC_INIT1 state. In addition, if the peer device is a device that does not support the header size flow control message, when the PCIe flow control initialization process is started, it directly enters the FC_INIT1 state. After entering the FC_INIT1 state, the process is consistent with the original PCIe5.0 initialization process until entering the DL_Active state. In response to the lack of negotiation on the size of the header credit unit in the PCIe protocol, after adding relevant negotiation processes, both sides of the PCIe bus can more accurately synchronize the size of the header credit unit of both sides. At the same time, according to the total cache size of the device itself, the number of Credits can be flexibly adjusted to squeeze the remaining wasted cache space and achieve a more reasonable allocation of resources.

[0017] In a second aspect, the present application provides a PCIe header credit unit size confirmation system, the system is applied to the NFM mode of a PCIe link, the PCIe link includes a local device and a peer device, the system is executed by the local device, and the system includes:

[0018] The acquisition module is used to enter the newly added FC_INIT0 state after the PCIe flow control initialization process is started, and receive the header size flow control message sent by the opposite device; the FC_INIT0 state is the negotiation stage before entering the FC_INIT1 state; the header size flow control message contains the number of TLP Prefixes supported by the opposite device;

[0019] The adjustment module is used to adjust the header credit unit size of the local device according to the number of TLP Prefixes supported by the opposite device.

[0020] In an optional implementation, the adjustment module is specifically used to:

[0021] If the number of TLP Prefixes supported by the local device is less than or equal to the number of TLP Prefixes supported by the peer device, the header credit unit size of the local device is not adjusted;

[0022] If the number of TLP Prefixes supported by the local device is greater than the number of TLP Prefixes supported by the peer device, the size of the header credit unit of the local device is adjusted according to the maximum transmittable capability of the peer device.

[0023] In an optional embodiment, the system further includes:

[0024] The process control module is used to enter the FC_INIT1 state after completing the adjustment of the head credit unit size of the local device.

[0025] In an optional implementation, the process control module is further used to: if the peer device does not support the header field size flow control message, then when the PCIe flow control initialization process is started, directly enter the FC_INIT1 state.

[0026] In a third aspect, the present application provides a computer device, comprising: a memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, and the processor executing the PCIe header credit unit size confirmation method of the above-mentioned first aspect or any corresponding embodiment thereof by executing the computer instructions.

[0027] In a fourth aspect, the present application provides a computer-readable storage medium having computer instructions stored thereon, the computer instructions being used to enable a computer to execute the PCIe header credit unit size confirmation method of the first aspect or any corresponding embodiment thereof.

[0028] In a fifth aspect, the present application provides a computer program product, including computer instructions, which are used to enable a computer to execute the PCIe header credit unit size confirmation method of the above-mentioned first aspect or any corresponding embodiment thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0030] Figure 1 It is a schematic diagram of the basic principle of PCIe system flow control.

[0031] Figure 2 This is a PCIe process buffer classification diagram.

[0032] Figure 3 It is a schematic diagram of a situation where the sizes of the header credit units of device A and device B do not match and the problem.

[0033] Figure 4 The present invention is a flowchart of a method for confirming a PCIe header credit unit size according to an exemplary embodiment of the present application.

[0034] Figure 5 It is a schematic diagram of optimizing the PCIe flow control initialization process according to an exemplary embodiment of the present application.

[0035] Figure 6 FIG. 1 is a schematic diagram of a newly defined FC DLLP format description according to an exemplary embodiment of the present application.

[0036] Figure 7 It is a structural schematic diagram of a PCIe header credit unit size confirmation system provided in an embodiment of the present application.

[0037] Figure 8 It is a structural schematic diagram of a computer device provided in an optional embodiment of the present application. DETAILED DESCRIPTION

[0038] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of this application.

[0039] It should be understood that the "indication" mentioned in the embodiments of the present application can be a direct indication, an indirect indication, or an indication of an association relationship. For example, A indicates B, which can mean that A directly indicates B, for example, B can be obtained through A; it can also mean that A indirectly indicates B, for example, A indicates C, B can be obtained through C; it can also mean that there is an association relationship between A and B.

[0040] In the description of the embodiments of the present application, the term "corresponding" may indicate a direct or indirect correspondence between two items, or an association relationship between the two items, or a relationship between indication and being indicated, configuration and being configured, and the like.

[0041] In an embodiment of the present application, "predefinition" can be achieved by pre-saving corresponding codes, tables or other methods that can be used to indicate relevant information in a device (for example, including a terminal device and a network device). The present application does not limit its specific implementation method.

[0042] First, the terms involved in this application are introduced.

[0043] PCIe: Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard used to connect various external devices on a computer motherboard, such as graphics cards, network cards, storage controllers, etc.

[0044] FC: Flow control, flow control;

[0045] NFM: Non-Flit-Mode, non-Flit mode;

[0046] DLLP: Data Link Layer Packet, data link layer data packet;

[0047] TLP: Transaction Layer Packets, transaction layer data packets.

[0048] In the earlier PCI versions of PCIe, there is no flow control mechanism, and the sender does not know whether the receiver can receive the corresponding TLP at the current moment. Therefore, the sender can only try to send, during which multiple waiting cycles may be inserted (due to reasons such as the receiving device is not ready), or even retries, etc. These problems have seriously affected the bandwidth performance of the bus as the PCIe bus evolves, including the increase in data rate and transmission bandwidth requirements.

[0049] In order to ensure that the data sent by the sending PCIe device does not exceed the receiving capacity of the receiving device, and to avoid triggering data retransmission to reduce data output efficiency or data overflow leading to data loss, the PCIe protocol provides a set of flow control (FC) methods to improve the data transmission efficiency of the PCIe bus.

[0050] The flow control of the PCIe bus uses the Credit-Based principle, which is coordinated by the transaction layer and the data link layer. Figure 1 The basic principle diagram of PCIe system flow control. FlowControl DLLPs are sent between the data link layers of two adjacent ports. During initialization, the receiving end notifies the sending end of the size of its buffer. Later, during normal operation, FlowControlDLLPs are periodically used to inform the sending end of the size of each buffer of the receiving end. Before sending, the sending end can know whether the receiving end can receive the TLP to be sent through the Flow Control mechanism.

[0051] The TLP types sent and received by PCIe devices are divided into three categories: P (Posted Request) messages, NP (Non-Posted Request) messages, and CPL (Completion) messages, such as Figure 2 As shown. The receiving buffer of the receiving device is also divided into three categories according to the three TLP types, to store the three types of messages P / NP / CPLTLP respectively. Each type of storage is further divided into Header Buffer and Data Buffer according to whether it stores the message header field or the message data field. The cache storing the P type message header field (Header) is defined as PH (Posted request Header buffer), and the cache storing the P type data field is defined as PD (Posted request Data buffer). The same type of messages storing NP / CPL type message header field and data field are defined as: NPH / NPD, CPLH / CPLD.

[0052] The receive buffer of all types of messages of the PCIe receiving device is based on Credits, and the number of Credits is used to reflect the size of the buffer.

[0053] For data cache, 1 Credit represents 4 DW. Specifically, in the data cache scenario, Credit represents a quota or permission for data transmission. For data cache, 1 Credit usually represents 4 DW (DoubleWord, double word, 32-bit data). This means that every time the receiver has a Credit, it can receive 4 DW of data.

[0054] However, for the Header cache, 1 Credit is not fixed and needs to be determined based on whether the receiving device supports the TLP prefix. The size of 1 Credit in the Header cache depends on whether the receiving device supports the TLP (Transaction Layer Packet) prefix. The TLP prefix is ​​an optional data packet part used in the PCIe (PCI Express) bus system to implement specific functions (such as PASID, MR-IOV, etc.). If the receiving device supports the TLP prefix, then 1 Credit in the Header cache may need to contain more space to accommodate these prefixes. If the receiving device does not support the TLP prefix, then 1 Credit in the Header cache may only contain basic Header information.

[0055] In the PCIe system, FM mode (Flit mode) involves breaking down data into small transmission units (Flits) to improve the flow control accuracy and transmission efficiency of the data. This mode is particularly suitable for large-scale parallel processing and data transmission because it reduces the delay at each transmission and improves the throughput of data transmission. Compared with Flit mode, NFM mode (Non-Flit-Mode) generally refers to a mode of communication using larger data transmission units, or without fine segmentation and flow control. In non-Flit mode, the size of the data unit is usually larger, which may be an entire packet (Packet) or a transport layer protocol unit. In the PCIe protocol, standard transmission is usually non-Flit mode, that is, transmission is carried out through larger data packets (TLP), and the flow control mechanism on the signal line is used to manage the order of data transmission and bandwidth usage.

[0056] In the PCIe protocol, for the NFM (Non-Flit-Mode) mode (applicable to PCIe5.0 and earlier protocol types), the calculation rules for the size of a Header Credit Unit are shown in Table 1.

[0057] Table 1

[0058]

[0059] In the PCIe protocol, for the NFM (Non-Flit-Mode) mode (applicable to PCIe5.0 and earlier protocols), in the initialization phase of FlowControl, the FCDLLPs sent by the receiver will only inform the sender of the number of Credits on the local side. For DataBufferCredit, a Credit is negotiated in a fixed 4DW size, so the sender can accurately estimate the number of buffers on the receiving end. However, for HeaderBufferCredit, because the size of HeaderBufferCredit is determined by the receiver based on whether the local side supports Prefix and how many Prefixes it supports, this information is not included in the existing FCDLLPs. The sender knows the number of HeaderCredits of the receiver, but does not know the specific size of each HeaderCredit. Therefore, when the sender and receiver support different Prefix specifications, there may still be overflow packet loss or resource waste due to the inconsistency of the Credit sizes calculated by both parties. For reference, Figure 3 .

[0060] In order to solve the above problems, an embodiment of the present application provides a method for confirming the size of a PCIe header credit unit. In view of the lack of negotiation on the size of the header credit unit in the PCIe protocol, after adding relevant negotiation processes, both parties of the PCIe bus can more accurately synchronize the sizes of the header credit units of both parties. At the same time, according to the total cache size of the device itself, the number of Credits can be flexibly adjusted to squeeze the remaining wasted cache space and achieve a more reasonable allocation of resources.

[0061] The PCIe header credit unit size confirmation method of the embodiment of the present application is applied to the NFM mode of the PCIe link, the PCIe link includes a local device and a peer device, and the method is executed by the local device. The method flow is as follows Figure 4 As shown, the following steps are included:

[0062] S401. After the PCIe flow control initialization process is started, the newly added FC_INIT0 state is entered to receive the header size flow control message sent by the peer device; the FC_INIT0 state is the negotiation stage before entering the FC_INIT1 state; the header size flow control message includes the number of TLP Prefixes supported by the peer device.

[0063] Specifically, in step S401, the number of TLP Prefixes includes: the number of Local-Prefixes (local prefixes, used to indicate the identification information of TLP in the local link) and the number of E2E-Prefixes (End-to-End Prefix, end-to-end prefix, used for identification information when transmitted across links or between devices). Local-Prefix is ​​used to indicate the identification information of TLP in the local link, and E2E-Prefix is ​​used for identification information when transmitted across links or between devices.

[0064] In the above steps, the traditional PCIe flow control initialization process includes FC_INIT1 state and FC_INIT2 state, such as Figure 5 shown. Figure 5 In the example, DL_Inactive means that the physical layer notifies the data link layer that the current PCIe link is unavailable; DL_Init means that the physical layer is in the link initialization state; FC_INIT1 and FC_INIT2 are the two initialization states of Flowcontrol; DL_active means that the current PCIe link layer is in a normal working state. Before entering the FC_INIT1 state, this embodiment adds a header credit unit size negotiation process, which is defined as the FC_INIT0 state. Figure 5 After the PCIe device enters the DL_INIT phase, it enters this state first and sends a header size flow control message to negotiate the size of the header credit unit. The header size flow control message contains the number of Local-Prefix and E2E-Prefix supported by the device itself.

[0065] Based on the original PCIE protocol, the embodiment of the present application proposes a new flow control message format (FC DLLP) in the Non-Flit-Mode mode, and uses the message format to propose an optimized PCIE initialization flow control process. By executing the process, the problem of unreasonable resource allocation introduced by the inability of both parties of the PCIE link to accurately know the size of the Header Credit Size of the opposite device as described in the aforementioned process is solved. By executing the new flow control negotiation process, both ends of the PCIE link can accurately know the size of the Header Credit Unit of the opposite end, and then flexibly allocate and calculate the number of Credits at the local end according to the negotiation results, thereby realizing the optimization and adjustment of the Header Credit buffer resources on both sides.

[0066] In order to better illustrate the above header size flow control message, a specific message format will be used for illustration. In the PCIe protocol Non-Flit-Mode mode, a new FC DLLP message is added, refer to Figure 6 .

[0067] In the FC DLLP message, the DLLP Type has 8 bits, of which the lower 3 bits of the flow control message are used to represent the VC Num. A total of 46 types of DLLP messages are used, and the other codes are reserved. The embodiment of the present application selects 0111 1V2V1V0 (V2V1V0 represents VC num) from the Reserved code type of the DLLP Type as the new custom FC DLLP message type initFC0. The message format definition refers to Figure 6 .

[0068] Figure 6 In the , Byte0 still indicates the DLLP type; Byte1 / 2 / 3 indicate the support of P / NP / CPL TLP message for prefix respectively, and the format is the same; bit[7:3] indicates the number of supported Local-prefix; bit[2:0] indicates the number of supported E2E-prefix; Byte4 / 5 is a 16-bit CRC checksum. The specific meaning of the new custom FC DLLP field is shown in Table 2.

[0069] Table 2

[0070]

[0071] S402: Adjust the header credit unit size of the local device according to the number of TLP Prefixes supported by the opposite device.

[0072] Specifically, in the above steps, if the number of TLP Prefixes supported by the local device is less than or equal to the number of TLP Prefixes supported by the opposite device, the head credit unit size of the local device is not adjusted; if the number of TLP Prefixes supported by the local device is greater than the number of TLP Prefixes supported by the opposite device, the head credit unit size of the local device is adjusted according to the maximum transmittable capacity of the opposite device. After the adjustment of the head credit unit size of the local device is completed, the FC_INIT1 state is entered.

[0073] In addition, in the above steps, if the peer device does not support the header size flow control message, when the PCIe flow control initialization process is started, it directly enters the FC_INIT1 state.

[0074] For example, when the receiving end supports Prefix, but the sending end does not support Prefix, and the receiving end has 64 Header Credits by default, after the Header Credit size is adjusted according to the actual situation using the above-mentioned improved PCIe flow control initialization process, the increase in the number of Header Credits before and after the method of the embodiment of the present application is shown in Table 3. According to Table 3, for the Header Credit unit size negotiation missing in the traditional PCIe protocol, after adding the FCINIT0 state and related negotiation process, the two sides of the PCIe bus can more accurately synchronize the size of the Header Credit unit of both sides, and at the same time, according to the total cache size of the device itself, flexibly adjust the number of Credits, squeeze the remaining wasted cache space, and realize a more reasonable allocation of resources. From the above typical scenario analysis, according to the different support of Prefix by both parties, Credit can be optimized by 18.75% to 79.69%, and the greater the difference in the support of Prefix by both parties, the more obvious the resource optimization results.

[0075] Table 3

[0076]

[0077] In summary, the PCIe header credit unit size confirmation method provided in the embodiment of the present application is applied to the PCIe flow control initialization process in the NFM mode of the PCIe link. The PCIe link includes a local device and a peer device, and the method is executed by the local device. When the PCIe flow control initialization process is started, before entering the FC_INIT1 state, a new negotiation stage is added, namely the FC_INIT0 state. Specifically, before entering the FC_INIT1 state, the newly added FC_INIT0 state is entered to negotiate the header credit unit size, and receive the header field size flow control message sent by the peer device. The header field size flow control message is pre-constructed and contains the number of TLP Prefixes supported by the peer device. The local device compares the number of TLP Prefixes supported by the peer device in the header size flow control message with the number of TLP Prefixes supported by itself. If the number of TLP Prefixes supported by the local device is less than the number of TLP Prefixes supported by the peer device, the head credit unit size of the local device will not be adjusted. If an unsupported message type that exceeds the receiving capacity is received from the peer device later, it will be processed as a PCIE error; if the number of TLP Prefixes supported by the local device is greater than the number of TLP Prefixes supported by the peer device, the head credit unit size of the local device will be recalculated and adjusted according to the maximum transmittable capacity of the peer device, and the excess buffer will be replaced with a deeper depth. After completing the recalculation and adjustment of the head credit unit, enter the FC_INIT1 state. In addition, if the peer device is a device that does not support the header size flow control message, when the PCIe flow control initialization process is started, it directly enters the FC_INIT1 state. After entering the FC_INIT1 state, the process is consistent with the original PCIe5.0 initialization process until entering the DL_Active state. In response to the lack of negotiation on the size of the header credit unit in the PCIe protocol, after adding relevant negotiation processes, both sides of the PCIe bus can more accurately synchronize the size of the header credit unit of both sides. At the same time, according to the total cache size of the device itself, the number of Credits can be flexibly adjusted to squeeze the remaining wasted cache space and achieve a more reasonable allocation of resources.

[0078] In the embodiments of the present application, a PCIe header credit unit size confirmation system is also provided, which is used to implement the above embodiments and preferred implementation modes, and will not be repeated hereafter. As used below, the term "module" may be a combination of software and / or hardware that implements a predetermined function. Although the systems described in the following embodiments are preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceivable.

[0079] The present application embodiment provides a PCIe header credit unit size confirmation system, Figure 7: is a structural diagram of a PCIe header credit unit size confirmation system provided by an embodiment of the present application. The system is applied to the NFM mode of a PCIe link. The PCIe link includes a local device and a peer device. The system is executed by the local device. The system includes:

[0080] The acquisition module 701 is used to enter the newly added FC_INIT0 state after the PCIe flow control initialization process is started, and receive the header size flow control message sent by the opposite device; the FC_INIT0 state is the negotiation stage before entering the FC_INIT1 state; the header size flow control message includes the number of TLP Prefixes supported by the opposite device;

[0081] The adjustment module 702 is used to adjust the header credit unit size of the local device according to the number of TLP Prefixes supported by the opposite device.

[0082] In an optional implementation, the adjustment module 702 is specifically configured to:

[0083] If the number of TLP Prefixes supported by the local device is less than or equal to the number of TLP Prefixes supported by the peer device, the header credit unit size of the local device is not adjusted;

[0084] If the number of TLP Prefixes supported by the local device is greater than the number of TLP Prefixes supported by the peer device, the size of the header credit unit of the local device is adjusted according to the maximum transmittable capability of the peer device.

[0085] In an optional embodiment, the system further includes:

[0086] The process control module 703 is used to enter the FC_INIT1 state after completing the adjustment of the head credit unit size of the local device.

[0087] In an optional implementation, the process control module 703 is further used to: if the peer device does not support the header size flow control message, directly enter the FC_INIT1 state after the PCIe flow control initialization process is started.

[0088] The further functional description of each of the above modules and units is the same as that of the above corresponding embodiments and will not be repeated here.

[0089] The PCIe header credit unit size confirmation system in this embodiment is presented in the form of a functional unit, where the unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that executes one or more software or fixed programs, and / or other devices that can provide the above functions.

[0090] The present application also provides a computer device having the above Figure 8 The PCIe header credit unit size confirmation system is shown.

[0091] See also Figure 8 , Figure 8 It is a structural diagram of a computer device provided by an optional embodiment of the present application, and the computer device includes: one or more processors 10, a memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. The various components are connected to each other using different buses for communication, and can be installed on a common mainboard or installed in other ways as needed. The processor can process instructions executed in the computer device, including instructions stored in or on the memory to display graphic information in a graphical user interface on an external input / output device (such as a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple computer devices can be connected, and each device provides some necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Figure 8 A processor 10 is taken as an example.

[0092] The processor 10 may be a central processing unit, a network processor or a combination thereof. The processor 10 may further include a hardware chip. The hardware chip may be a dedicated integrated circuit, a programmable logic device or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic or any combination thereof.

[0093] The memory 20 stores instructions executable by at least one processor 10, so that the at least one processor 10 executes the method shown in the above embodiment.

[0094] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created according to the use of the computer device, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may optionally include a memory remotely arranged relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0095] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid state drive; the memory 20 may also include a combination of the above types of memory.

[0096] The computer device also includes an input device 30 and an output device 40. The processor 10, the memory 20, the input device 30 and the output device 40 may be connected via a bus or other means. Figure 8 The example of connecting through bus is taken in the following.

[0097] The embodiment of the present application also provides a computer-readable storage medium. The above method according to the embodiment of the present application can be implemented in hardware, firmware, or can be implemented as a computer code that can be recorded in a storage medium, or can be implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and will be stored in a local storage medium through a network download, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state hard disk, etc.; further, the storage medium can also include a combination of the above types of memories. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor, or hardware, the method shown in the above embodiment is implemented.

[0098] Part of the present application may be applied as a computer program product, such as a computer program instruction, which, when executed by a computer, can call or provide the method and / or technical solution according to the present application through the operation of the computer. Those skilled in the art should understand that the existence of computer program instructions in computer-readable media includes but is not limited to source files, executable files, installation package files, etc., and accordingly, the way in which computer program instructions are executed by a computer includes but is not limited to: the computer directly executes the instruction, or the computer compiles the instruction and then executes the corresponding compiled program, or the computer reads and executes the instruction, or the computer reads and installs the instruction and then executes the corresponding installed program. Here, the computer-readable medium can be any available computer-readable storage medium or communication medium accessible to the computer.

[0099] Although the embodiments of the present application are described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present application, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A method for confirming the size of a PCIe header credit unit, characterized in that: The method is applied to the NFM mode of a PCIe link, the PCIe link includes a local device and a peer device, the method is executed by the local device, and the method includes: When the PCIe flow control initialization process is started, the newly added FC_INIT0 state is entered to receive the header size flow control message sent by the peer device; the FC_INIT0 state is the negotiation stage before entering the FC_INIT1 state; the header size flow control message contains the number of TLP Prefixes supported by the peer device; According to the number of TLP Prefixes supported by the opposite-end device, the size of the header credit unit of the local-end device is adjusted.

2. The method according to claim 1, characterized in that The step of adjusting the header credit unit size of the local device according to the number of TLP Prefixes supported by the opposite device includes: If the number of TLP Prefixes supported by the local device is less than or equal to the number of TLP Prefixes supported by the peer device, the header credit unit size of the local device is not adjusted; If the number of TLP Prefixes supported by the local device is greater than the number of TLP Prefixes supported by the peer device, the size of the header credit unit of the local device is adjusted according to the maximum transmittable capability of the peer device.

3. The method according to claim 2, characterized in that The method further comprises: If the peer device does not support the header size flow control message, when the PCIe flow control initialization process is started, it directly enters the FC_INIT1 state.

4. The method according to claim 3, characterized in that The TLP Prefix quantity includes: a local prefix quantity and an end-to-end prefix quantity.

5. The method according to claim 4, characterized in that The method further comprises: After completing the adjustment of the head credit unit size of the local device, enter the FC_INIT1 state.

6. A PCIe header credit unit size confirmation system, characterized in that: The system is applied to the NFM mode of a PCIe link, the PCIe link includes a local device and a peer device, the system is executed by the local device, and the system includes: The acquisition module is used to enter the newly added FC_INIT0 state after the PCIe flow control initialization process is started, and receive the header field size flow control message sent by the opposite device; the FC_INIT0 state is the negotiation stage before entering the FC_INIT1 state; the header field size flow control message contains the number of TLP Prefixes supported by the opposite device; The adjustment module is used to adjust the header credit unit size of the local device according to the number of TLP Prefixes supported by the opposite device.

7. The system according to claim 6, characterized in that The adjustment module is specifically used for: If the number of TLP Prefixes supported by the local device is less than or equal to the number of TLP Prefixes supported by the peer device, the header credit unit size of the local device is not adjusted; If the number of TLP Prefixes supported by the local device is greater than the number of TLP Prefixes supported by the peer device, the size of the header credit unit of the local device is adjusted according to the maximum transmittable capability of the peer device.

8. The system according to claim 7, characterized in that The system further comprises: The process control module is used to enter the FC_INIT1 state after completing the adjustment of the head credit unit size of the local device.

9. A computer device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the PCIe header credit unit size confirmation method according to any one of claims 1 to 5 by executing the computer instructions.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute the PCIe header credit unit size confirmation method according to any one of claims 1 to 5.

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