Printed circuit board and manufacturing method thereof

Abstract

The invention provides a printed circuit board and a method of manufacturing the same. The printed circuit board includes: an insulating layer; a cavity disposed in the insulating layer; a contact portion provided in the cavity; and a dummy layer disposed on a bottom portion of a sidewall of the cavity and disposed between the insulating layers. A first thickness of the dummy layer is smaller than a second thickness of the contact portion.

Description

Technical Field

[0001] The present disclosure relates to a printed circuit board and a method for manufacturing the same. Background Art

[0002] A printed circuit board is a board having a circuit pattern made of a conductive material such as copper on an insulating material, and as electronic devices including mobile phones in the field of information technology (IT) have been miniaturized, a method of forming a cavity in a printed circuit board and placing an electronic component such as an integrated circuit (IC), an active component, or a passive component in the cavity has been proposed.

[0003] The deeper the cavity depth of the printed circuit board is, the more parts of the electronic component can be mounted in the cavity, and the overall thickness of a product packaging the electronic component and the printed circuit board can be reduced.

[0004] When forming a cavity on a printed circuit board, it is difficult to control the depth of the cavity, a contact pattern for connecting with an electronic component in the cavity may be damaged, and it may be difficult to accurately mount the electronic component in the cavity. Summary of the invention

[0005] The present disclosure is directed to providing a printed circuit board having a cavity for increasing mounting accuracy without damaging a contact portion in the cavity having a desired depth, and a method of manufacturing the same.

[0006] The objects of the present disclosure are not limited to the above objects, and can be expanded in various ways within the scope of the idea and field of the present disclosure.

[0007] An embodiment of the present disclosure provides a printed circuit board, the printed circuit board comprising: an insulating layer; a cavity disposed in at least a portion of the insulating layer; a contact portion disposed in the cavity; and a dummy layer disposed on a bottom portion of a sidewall of the cavity and between the insulating layers. A first thickness of the dummy layer is less than a second thickness of the contact portion.

[0008] An edge of one of the insulating layers covering the dummy layer as a portion of the sidewall of the cavity may be aligned with an edge of the dummy layer in a height direction perpendicular to an upper surface of one or more of the insulating layers.

[0009] The dummy layer may include a first dummy layer and a second dummy layer disposed on the first dummy layer, and an upper side of the second dummy layer may be covered by one insulating layer or a plurality of insulating layers among the insulating layers.

[0010] The printed circuit board may further include a seed layer disposed under the contact portion. The first dummy layer may include the same material as that of the seed layer, and the first dummy layer and the seed layer may be formed in the same layer.

[0011] The first dummy layer and the second dummy layer may include materials different from each other.

[0012] A portion of the sidewall of the cavity may be aligned with an edge of the first dummy layer and an edge of the second dummy layer in the height direction.

[0013] The dummy layer may further include a third dummy layer disposed on a lateral side of the first dummy layer adjacent to the cavity.

[0014] The printed circuit board may further include: a cover layer disposed on the contact portion, wherein the third dummy layer may include a same material as that of the cover layer.

[0015] The printed circuit board may further include: a seed layer disposed below the contact portion, wherein the dummy layer may include a metal layer different from the seed layer.

[0016] The width of the cavity may not be constant in the height direction.

[0017] Another embodiment of the present disclosure provides a method for manufacturing a printed circuit board, the method comprising: forming a contact portion on a first insulating layer; forming a barrier layer on the contact portion; forming a second insulating layer having a cavity for exposing the barrier layer and covering an edge of the barrier layer; forming a sacrificial layer on the barrier layer in the cavity; removing the sacrificial layer; and forming a dummy layer by removing a portion of the barrier layer exposed by the cavity, the dummy layer being disposed on a bottom portion of a side wall of the cavity and below the second insulating layer.

[0018] The method may further include forming a seed layer on the first insulating layer before forming the contact.

[0019] The method may further include removing a portion of the seed layer not covered by the second insulating layer and the contact portion after removing the portion of the barrier layer exposed by the cavity.

[0020] The dummy layer may be formed to include a first dummy layer and a second dummy layer disposed on the first dummy layer, and an upper side of the second dummy layer may be covered by the second insulating layer.

[0021] The first dummy layer may be formed using the same layer as the seed layer, and the second dummy layer may be formed using the same layer as the barrier layer.

[0022] The method may further include forming a cover layer on a surface of the contact part after forming the first dummy layer and the second dummy layer.

[0023] The method may further include further forming a third dummy layer on a lateral side of the first dummy layer adjacent to the cavity.

[0024] The third dummy layer may be formed using the same material as that of the capping layer.

[0025] The width of the cavity may be formed to be non-constant in a height direction perpendicular to an upper surface of the second insulating layer.

[0026] According to the embodiments, a printed circuit board having a cavity (having a desired depth) for increasing mounting accuracy without damaging a contact portion in the cavity and a method of manufacturing the same may be provided.

[0027] The objects of the present disclosure are not limited to the above objects, and can be expanded in various ways within the scope of the idea and field of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 A cross-sectional view of a printed circuit board according to an embodiment is shown.

[0029] Figure 2 Shows Figure 1 Magnified view of part A.

[0030] Figures 3 to 14 A cross-sectional view is shown regarding a method for manufacturing a printed circuit board according to an embodiment.

[0031] Fig.15 A cross-sectional view of a printed circuit board according to another embodiment is shown.

[0032] Fig.16 Shows Fig.15 Magnified view of part B.

[0033] Figures 17 to 21 A cross-sectional view is shown regarding a method for manufacturing a printed circuit board according to another embodiment. DETAILED DESCRIPTION

[0034] Embodiments will be described more fully hereinafter with reference to the accompanying drawings, in which embodiments are shown.As those skilled in the art will realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present disclosure.

[0035] Parts irrelevant to the description will be omitted to clearly describe the present disclosure, and the same elements will be denoted by the same reference numerals throughout the specification.

[0036] The accompanying drawings are provided only to easily understand the embodiments disclosed in this specification, and the accompanying drawings should not be interpreted as limiting the spirit disclosed in this specification, and it should be understood that the present disclosure includes all modifications, equivalents, and replacements without departing from the scope or spirit of the present disclosure.

[0037] For better understanding and ease of description, the size (e.g., thickness) of each structure shown in the drawings is arbitrarily shown, but the present disclosure is not limited thereto. In the drawings, the sizes of layers, films, panels, regions, etc. are exaggerated for clarity. For example, the thickness of some layers and regions is exaggerated for ease of explanation.

[0038] It should be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element, or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements. The terms "on..." or "over..." refer to being positioned above an object part or below an object part, and do not necessarily refer to being positioned on the upper side of an object part based on the direction of gravity.

[0039] Unless explicitly described to the contrary, the words “comprises,” “comprising,” “having” and the like will be understood to imply the inclusion of stated elements but not the exclusion of any other elements.

[0040] The phrase "in a plan view" means observing an object part from the top, and the phrase "in a cross-sectional view" means observing a section vertically cutting the object part from the side.

[0041] When a part is described as being “connected” to another part, the part may be “directly connected” to the other part, may be “connected” to the other part through a third part, or may be physically or electrically connected to the other part, and they may be referred to by different labels according to position or function, but basically, the parts integrated into one body may be connected to each other.

[0042] Various embodiments and modifications will now be described in detail with reference to the accompanying drawings.

[0043] Now refer to Figure 1 and Figure 2 A printed circuit board 100 according to an embodiment is described. Figure 1 shows a cross-sectional view of a printed circuit board according to an embodiment, and Figure 2 Shows Figure 1 Magnified view of part A.

[0044] Reference Figure 1 and Figure 2According to the present embodiment, the printed circuit board 100 may include: a plurality of insulating layers IL; a plurality of wiring layers ML buried in the insulating layer IL; a plurality of vias VL disposed in the via holes VA of the insulating layer IL; a plurality of pad layers PD; a solder resist layer SR; a cavity CV formed in a portion of the insulating layer IL; a contact portion CM disposed in the cavity CV; and a dummy layer SM disposed along a lower edge of the cavity CV.

[0045] The plurality of insulating layers IL may include a first insulating layer IL1 , a second insulating layer IL2 , a third insulating layer IL3 , a fourth insulating layer IL4 , and a fifth insulating layer IL5 stacked in the height direction DRH.

[0046] The wiring layer ML may include a first wiring layer ML1 buried by the second insulating layer IL2 , a second wiring layer ML2 buried by the third insulating layer IL3 , a third wiring layer ML3 buried by the fourth insulating layer IL4 , and a fourth wiring layer ML4 buried by the fifth insulating layer IL5 .

[0047] The vias VL may include a first via VL1 disposed in a first via hole VA1 formed in the first insulating layer IL1, a second via hole VL2 disposed in a second via hole VA2 formed in the second insulating layer IL2, a third via hole VL3 disposed in a third via hole VA3 formed in the third insulating layer IL3, a fourth via hole VL4 disposed in a fourth via hole VA4 formed in the fourth insulating layer IL4, and a fifth via hole VL5 disposed in a fifth via hole VA5 formed in the fifth insulating layer IL5.

[0048] The pad layer PD may include a first pad layer PD1 disposed under the first insulating layer IL1 and a second pad layer PD2 disposed on the fifth insulating layer IL5 .

[0049] A portion of the first wiring layer ML1 may be connected to the first pad layer PD1 through the first via VL1, a portion of the first wiring layer ML1 may be connected to a portion of the second wiring layer ML2 through the second via VL2, a portion of the second wiring layer ML2 may be connected to a portion of the third wiring layer ML3 through the third via VL3, a portion of the third wiring layer ML3 may be connected to a portion of the fourth wiring layer ML4 through the fourth via VL4, and a portion of the fourth wiring layer ML4 may be connected to the second pad layer PD2 through the fifth via VL5.

[0050] The solder resist layer SR may include a first solder resist layer SR1 disposed under the first insulating layer IL1 and exposing a portion of the first pad layer PD1 and a second solder resist layer SR2 disposed over the fifth insulating layer IL5 and exposing a portion of the second pad layer PD2 .

[0051] A cavity CV may be formed in the third, fourth, and fifth insulating layers IL3, IL4, and IL5.

[0052] The contact portion CM may be disposed in the cavity CV. The contact portion CM may be formed using the same layer as the second wiring layer ML2 buried in the third insulating layer IL3, and may have the same thickness as the second wiring layer ML2 buried in the third insulating layer IL3. The contact portion CM may include the same material as the material of the second wiring layer ML2 buried in the third insulating layer IL3.

[0053] The dummy layer SM may be disposed along a bottom portion edge of the sidewall of the cavity CV, and may include a first dummy layer SM1 , a second dummy layer SM2 , and a third dummy layer SM3 .

[0054] The second dummy layer SM2 may be disposed on the first dummy layer SM1 , an upper side of the second dummy layer SM2 may be covered by the third insulating layer IL3 , and the third dummy layer SM3 may be disposed on a lateral side of the first dummy layer SM1 close to the cavity CV.

[0055] The first dummy layer SM1 and the second dummy layer SM2 may include different layers. The first dummy layer SM1 and the second dummy layer SM2 may include different materials. For example, the first dummy layer SM1 may include copper (Cu), and the second dummy layer SM2 may include nickel (Ni), but the embodiment is not limited thereto.

[0056] The cover layer CT may be disposed on the second pad layer PD2 , and the first cover layer CT1 may be disposed on the contact part CM.

[0057] The third dummy layer SM3 may be formed using the same material as that of the first cover layer CT1 , and may have the same thickness as that of the first cover layer CT1 .

[0058] The seed layer SD may be disposed under the wiring layer ML and the contact portion CM. The seed layer SD may include metal.

[0059] Reference Figure 2 The cavity CV may include a first cavity CV1 formed in the third insulating layer IL3 , a second cavity CV2 (including a first portion CV21 and a second portion CV22 ) formed in the fourth insulating layer IL4 , and a third cavity CV3 (including a first portion CV31 and a second portion CV32 ) formed in the fifth insulating layer IL5 .

[0060] The second cavity CV2 formed in the fourth insulating layer IL4 may include a first portion CV21 having a first width W1 in a plane direction DRW perpendicular to the height direction DRH and a second portion CV22 having a second width W2 different from the first width W1. The first portion CV21 of the second cavity CV2 may be disposed on a lateral side of the third wiring layer ML3 buried in the fourth insulating layer IL4 and may have the same height as the third wiring layer ML3 in the height direction DRH, and the second portion CV22 of the second cavity CV2 may be disposed on a lateral side of the fourth via hole VL4 (disposed in the fourth via hole VA4 formed in the fourth insulating layer IL4) and may have the same height as the fourth via hole VL4 in the height direction DRH. The first width W1 of the first portion CV21 may be greater than the second width W2 of the second portion CV22.

[0061] The third cavity CV3 formed in the fifth insulating layer IL5 may include a first portion CV31 having a third width W3 in the plane direction DRW and a second portion CV32 having a fourth width W4 different from the third width W3. The first portion CV31 of the third cavity CV3 may be disposed on a lateral side of the fourth wiring layer ML4 buried in the fifth insulating layer IL5 and may have the same height as that of the fourth wiring layer ML4 in the height direction DRH, and the second portion CV32 of the third cavity CV3 may be disposed on a lateral side of the fifth via hole VL5 (disposed in the fifth via hole VA5 formed in the fifth insulating layer IL5) and may have the same height as that of the fifth via hole VL5 in the height direction DRH. The third width W3 of the first portion CV31 may be greater than the fourth width W4 of the second portion CV32.

[0062] The dummy layer SM may be disposed along the bottom portion edge of the sidewall of the cavity CV, and the dummy layer SM may include a first dummy layer SM1, a second dummy layer SM2, and a third dummy layer SM3. The second dummy layer SM2 may be disposed on the first dummy layer SM1, the upper side of the second dummy layer SM2 may be covered by the third insulating layer IL3, and the third dummy layer SM3 may be disposed on the lateral side of the first dummy layer SM1. The first dummy layer SM1 and the second dummy layer SM2 may be inserted into the insulating layer IL, and one lateral side of the first dummy layer SM1 and one lateral side of the second dummy layer SM2 may form a portion of the sidewall of the cavity CV.

[0063] The first cover layer CT1 may be disposed on the contact portion CM. The first cover layer CT1 may surround lateral sides and an upper side of the contact portion CM.

[0064] The third dummy layer SM3 may be disposed on a lateral side of the first dummy layer SM1, and the third dummy layer SM3 may include the same layer as the first cover layer CT1 and may have the same thickness as the first cover layer CT1. That is, the third dummy layer SM3 may include the same material as the first cover layer CT1, and the third dummy layer SM3 may be disposed in the same layer as the first cover layer CT1.

[0065] A first thickness T1 of the first and second dummy layers SM1 and SM2 may be less than a second thickness T2 of the contact portion CM.

[0066] The first edge E1 of the first and second dummy layers SM1 and SM2 may be aligned with a second edge E2 of the first cavity CV1 formed in the third insulating layer IL3 in the cavity CV (ie, a portion of a sidewall of the cavity CV) in the height direction DRH.

[0067] The seed layer SD may be disposed under the contact portion CM, and the first dummy layer SM1 may include the same layer as the seed layer SD disposed under the contact portion CM, and the first dummy layer SM1 may have the same thickness as that of the seed layer SD. That is, the first dummy layer SM1 may include the same material as that of the seed layer SD disposed under the contact portion CM, and the first dummy layer SM1 may be disposed in the same layer as the seed layer SD disposed under the contact portion CM.

[0068] The second dummy layer SM2 may cover the contact portion CM to protect the contact portion CM when the cavity CV is formed, and a portion of the second dummy layer SM2 may be removed during the manufacturing process.

[0069] According to the printed circuit board according to the present embodiment, a cavity CV may be formed in the third insulating layer IL3, the fourth insulating layer IL4, and the fifth insulating layer IL5 in the insulating layer IL, and a cavity CV having a desired depth may be formed by adjusting the thickness and number of the insulating layers in which the cavity CV is formed. In addition, when forming the cavity CV, the contact portion CM may be covered and protected by using the second dummy layer SM2, and a portion of the second dummy layer SM2 covering the contact portion CM may be removed during the manufacturing process, so that the contact portion CM in the cavity CV may not be damaged during the formation of the cavity CV, thereby preventing the contact characteristics of the semiconductor chip mounted in the cavity CV from being deteriorated with the contact portion CM.

[0070] Now refer to Figures 3 to 14 as well as Figure 1 and Figure 2 A method for manufacturing a printed circuit board according to an embodiment is described. Figures 3 to 14 A cross-sectional view is shown regarding a method for manufacturing a printed circuit board according to an embodiment.

[0071] Reference Figure 3, forming a second via hole VL2 and a second wiring layer ML2, wherein the second via hole VL2 is disposed in a second access hole VA2 formed in the second insulating layer IL2, the second wiring layer ML2 is disposed on the second insulating layer IL2 and connected to the second via hole VL2, and a first seed layer SD1 is formed on the second insulating layer IL2 and a contact portion CM is formed on the first seed layer SD1. A barrier layer CPL is formed to cover the first seed layer SD1 and the contact portion CM.

[0072] The barrier layer CPL may include a different metal layer from the first seed layer SD1 and the contact portion CM, and an etching rate of the barrier layer CPL may be different from that of the first seed layer SD1 and the contact portion CM. Therefore, the dummy layer may include a different metal layer from the seed layer.

[0073] The first seed layer SD1 may be formed together with the seed layer SD disposed under the second wiring layer ML2 .

[0074] Reference Figure 4 , a third insulating layer IL3 may be stacked on the second wiring layer ML2 , the barrier layer CPL, and the second insulating layer IL2 , and a second seed layer SD2 may be stacked on the third insulating layer IL3 .

[0075] Reference Figure 5 By etching the second seed layer SD2 and the third insulating layer IL3 , a first hole CV1A is formed at a position where a first cavity CV1 where a cavity CV is to be formed, and a third via hole VA3 is formed in the third insulating layer IL3 .

[0076] Edge portions of the barrier layer CPL and the first seed layer SD1 are not exposed by the first hole CV1A, and the third insulating layer IL3 and the second seed layer SD2 may be disposed on the edge portions of the barrier layer CPL and the first seed layer SD1 .

[0077] In this case, the barrier layer CPL covers and protects the first seed layer SD1 and the contact portion CM, thereby preventing the contact portion CM from being damaged when the first hole CV1A is formed.

[0078] Reference Figure 6 , a dry film DF1 may be formed on a portion of the second seed layer SD2, a metal layer may be stacked on the second wiring layer ML2 and the second seed layer SD2 exposed by the third via hole VA3 formed in the third insulating layer IL3, the metal layer may be patterned, the dry film DF1 may be removed, and the exposed portion of the second seed layer SD2 may be removed, so that a third via hole VL3 and a third wiring layer ML3 may be formed, and a first sacrificial layer SFL1 may be formed in the first hole CV1A.

[0079] Reference Figure 7, a fourth insulating layer IL4 is stacked on the third wiring layer ML3, the first sacrificial layer SFL1, and the third insulating layer IL3, and a third seed layer SD3 is stacked on the fourth insulating layer IL4. By etching the third seed layer SD3 and the fourth insulating layer IL4, a second hole CV2A is formed at the position of the second cavity CV2 where the cavity CV is to be formed, and a fourth via hole VA4 is formed in the fourth insulating layer IL4. In this case, the barrier layer CPL and the first sacrificial layer SFL1 cover and protect the first seed layer SD1 and the contact portion CM, thereby preventing the contact portion CM from being damaged when the second hole CV2A is formed.

[0080] Reference Figure 8 , a fourth via hole VL4 connected to the third wiring layer ML3 may be formed in the fourth via hole VA4, a fourth wiring layer ML4 connected to the fourth via hole VL4 may be formed on the fourth insulating layer IL4, and a second sacrificial layer SFL2 may be formed in the second hole CV2A.

[0081] Reference Fig. 9 , a fifth insulating layer IL5 is stacked on the fourth wiring layer ML4, the second sacrificial layer SFL2, and the fourth insulating layer IL4, and a fourth seed layer SD4 is stacked on the fifth insulating layer IL5. By etching the fourth seed layer SD4 and the fifth insulating layer IL5, a third hole CV3A is formed in the position of the third cavity CV3 where the cavity CV is to be formed, and a fifth via hole VA5 is formed in the fifth insulating layer IL5. In this case, the first sacrificial layer SFL1 and the second sacrificial layer SFL2 together with the barrier layer CPL cover and protect the first seed layer SD1 and the contact part CM, thereby preventing the contact part CM from being damaged when the third hole CV3A is formed.

[0082] Reference Fig.10 , a fifth via hole VL5 connected to the fourth wiring layer ML4 may be formed in the fifth via hole VA5, a second pad layer PD2 connected to the fifth via hole VL5 may be formed on the fifth insulating layer IL5, and a third sacrificial layer SFL3 may be formed in the third hole CV3A.

[0083] Reference Fig.11 , a first solder resist layer SR1 may be formed under the first insulating layer IL1 to expose a portion of the first pad layer PD1, and a second solder resist layer SR2 may be formed over the fifth insulating layer IL5 to expose a portion of the second pad layer PD2.

[0084] Reference Fig.12 A mask layer MSK may be formed on the second solder resist layer SR2. The mask layer MSK may expose the third sacrificial layer SFL3.

[0085] Reference Fig.13, the third sacrificial layer SFL3, the second sacrificial layer SFL2, and the first sacrificial layer SFL1 are etched and removed by using the mask layer MSK as an etching mask. In this case, the barrier layer CPL may cover and protect the first seed layer SD1 and the contact part CM, thereby preventing the contact part CM from being damaged.

[0086] Reference Fig.14 , portions of the barrier layer CPL and the first seed layer SD1 exposed by the cavity CV are sequentially removed by using the mask layer MSK as an etching mask to form the seed layer SD disposed under the contact portion CM and the first and second dummy layers SM1 and SM2 disposed at the edge of the bottom surface of the first cavity CV1. The first dummy layer SM1 may be formed using the same layer as the seed layer SD, and the second dummy layer SM2 may be formed using the same layer as the barrier layer CPL.

[0087] The mask layer MSK may be removed, and the exposed portion of the contact portion CM, the exposed portion of the second pad layer PD2, and the exposed portion of the first dummy layer SM1 may be surface-treated to form a cover layer CT on the second pad layer PD2, a first cover layer CT1 may be formed on the contact portion CM, and a third dummy layer SM3 may be formed on a lateral side of the first dummy layer SM1 close to the cavity. The third dummy layer SM3 may be formed using the same material as that of the cover layer CT, thereby forming Figure 1 and Figure 2 The printed circuit board 100 is shown in FIG.

[0088] According to the method for manufacturing a printed circuit board according to the present embodiment, a cavity CV may be formed in the third insulating layer IL3, the fourth insulating layer IL4, and the fifth insulating layer IL5 as an example, but the number of insulating layers in which the cavity CV is formed may be more or less than the number shown in the drawings. Therefore, a cavity CV having a desired depth may be formed by adjusting the thickness and number of insulating layers in which the cavity CV is formed.

[0089] In addition, when forming the cavity CV, the contact portion CM set in the cavity CV is covered and protected by the barrier layer CPL and the first sacrificial layer SFL1, the second sacrificial layer SFL2 and the third sacrificial layer SFL3, so when forming the cavity CV, the contact portion CM in the cavity CV will not be damaged, thereby preventing the contact characteristics between the semiconductor chip installed in the cavity CV and the contact portion CM from deteriorating.

[0090] Now refer to Fig.15 and Fig.16 A printed circuit board 200 according to another embodiment is described. Fig.15 shows a cross-sectional view of a printed circuit board according to another embodiment, and Fig.16 Shows Fig.15 Magnified view of part B.

[0091] Reference Fig.15 , the printed circuit board 200 according to the present embodiment is similar to the printed circuit board 100 according to the previous embodiment. A detailed description on the same constituent elements will not be provided.

[0092] The printed circuit board 200 may include: a plurality of insulating layers IL; a plurality of wiring layers ML buried in the insulating layer IL; a plurality of vias VL arranged in the via holes VA of the insulating layer IL; a plurality of pad layers PD; a solder resist layer SR; a cavity CV formed in a portion of the insulating layer IL; a contact portion CM arranged in the cavity CV; and a second dummy layer SM2 arranged along the lower edge of the cavity CV.

[0093] The insulating layer IL may include a first insulating layer IL1 , a second insulating layer IL2 , a third insulating layer IL3 , a fourth insulating layer IL4 , and a fifth insulating layer IL5 stacked in the height direction DRH.

[0094] The wiring layer ML may include a first wiring layer ML1 buried by the second insulating layer IL2 , a second wiring layer ML2 buried by the third insulating layer IL3 , a third wiring layer ML3 buried by the fourth insulating layer IL4 , and a fourth wiring layer ML4 buried by the fifth insulating layer IL5 .

[0095] The vias VL may include a first via VL1 disposed in a first via hole VA1 formed in the first insulating layer IL1, a second via hole VL2 disposed in a second via hole VA2 formed in the second insulating layer IL2, a third via hole VL3 disposed in a third via hole VA3 formed in the third insulating layer IL3, a fourth via hole VL4 disposed in a fourth via hole VA4 formed in the fourth insulating layer IL4, and a fifth via hole VL5 disposed in a fifth via hole VA5 formed in the fifth insulating layer IL5.

[0096] The pad layer PD may include a first pad layer PD1 disposed under the first insulating layer IL1 and a second pad layer PD2 disposed on the fifth insulating layer IL5 .

[0097] A portion of the first wiring layer ML1 may be connected to the first pad layer PD1 through the first via VL1, a portion of the first wiring layer ML1 may be connected to a portion of the second wiring layer ML2 through the second via VL2, a portion of the second wiring layer ML2 may be connected to a portion of the third wiring layer ML3 through the third via VL3, a portion of the third wiring layer ML3 may be connected to a portion of the fourth wiring layer ML4 through the fourth via VL4, and a portion of the fourth wiring layer ML4 may be connected to the second pad layer PD2 through the fifth via VL5.

[0098] The solder resist layer SR may include a first solder resist layer SR1 disposed under the first insulating layer IL1 and exposing a portion of the first pad layer PD1 , and a second solder resist layer SR2 disposed over the fifth insulating layer IL5 and exposing a portion of the second pad layer PD2 .

[0099] A cavity CV may be formed in the third, fourth, and fifth insulating layers IL3, IL4, and IL5.

[0100] The contact portion CM may be disposed in the cavity CV. The contact portion CM may be formed using the same layer as the second wiring layer ML2 buried in the third insulating layer IL3, and may have the same thickness as the second wiring layer ML2 buried in the third insulating layer IL3. The contact portion CM may include the same material as the material of the second wiring layer ML2 buried in the third insulating layer IL3.

[0101] The second dummy layer SM2 may be disposed along an edge of a bottom portion of the sidewall of the cavity CV. The printed circuit board 200 according to the present embodiment is different from the printed circuit board 100 according to the aforementioned embodiment in that the printed circuit board 200 according to the present embodiment does not include the first dummy layer SM1 (including the same layer as the seed layer SD) and the third dummy layer SM3 (including the same material as the cover layer CT and the first cover layer CT1).

[0102] An upper side of the second dummy layer SM2 may be covered by the third insulating layer IL3 , and the second dummy layer SM2 may include nickel (Ni), and the embodiment is not limited thereto.

[0103] The second dummy layer SM2 may be inserted into the insulating layer IL, and one lateral side of the second dummy layer SM2 may constitute a portion of the sidewall of the cavity CV.

[0104] The cavity CV may include a first cavity CV1 formed in the third insulating layer IL3 , a second cavity CV2 (including a first portion CV21 and a second portion CV22 ) formed in the fourth insulating layer IL4 , and a third cavity CV3 (including a first portion CV31 and a second portion CV32 ) formed in the fifth insulating layer IL5 .

[0105] The second cavity CV2 formed in the fourth insulating layer IL4 may include a first portion CV21 having a first width W1 in a plane direction DRW perpendicular to the height direction DRH and a second portion CV22 having a second width W2 different from the first width W1. The first portion CV21 of the second cavity CV2 may be disposed on a lateral side of the third wiring layer ML3 buried in the fourth insulating layer IL4 and may have the same height as the third wiring layer ML3 in the height direction DRH, and the second portion CV22 of the second cavity CV2 may be disposed on a lateral side of the fourth via hole VL4 (disposed in the fourth via hole VA4 formed in the fourth insulating layer IL4) and may have the same height as the fourth via hole VL4 in the height direction DRH. The first width W1 of the first portion CV21 may be greater than the second width W2 of the second portion CV22.

[0106] The third cavity CV3 formed in the fifth insulating layer IL5 may include a first portion CV31 having a third width W3 in the plane direction DRW and a second portion CV32 having a fourth width W4 different from the third width W3 in the plane direction DRW. The first portion CV31 of the third cavity CV3 may be disposed on a lateral side of the fourth wiring layer ML4 buried in the fifth insulating layer IL5 and may have the same height as that of the fourth wiring layer ML4 in the height direction DRH, and the second portion CV32 of the third cavity CV3 may be disposed on a lateral side of the fifth via hole VL5 (disposed in the fifth via hole VA5 formed in the fifth insulating layer IL5) and may have the same height as that of the fifth via hole VL5 in the height direction DRH. The third width W3 of the first portion CV31 may be greater than the fourth width W4 of the second portion CV32.

[0107] The first thickness T1 of the second dummy layer SM2 may be less than the second thickness T2 of the contact portion CM.

[0108] Reference Fig.16 , the first edge E1 of the second dummy layer SM2 may be aligned with the second edge E2 of the first cavity CV1 formed in the third insulating layer IL3 in the cavity CV (ie, a portion of the sidewall of the cavity CV) in the height direction DRH.

[0109] The second dummy layer SM2 may cover the contact portion CM and may protect the contact portion CM when the cavity CV is formed, and a portion of the second dummy layer SM2 may be removed during the manufacturing process.

[0110] According to the printed circuit board according to the present embodiment, a cavity CV may be formed in the third insulating layer IL3, the fourth insulating layer IL4, and the fifth insulating layer IL5 in the insulating layer IL, and a cavity CV having a desired depth may be formed by adjusting the thickness and number of the insulating layers in which the cavity CV is formed. In addition, when forming the cavity CV, the second dummy layer SM2 may be used to cover the contact portion CM and protect the contact portion CM, and a portion of the second dummy layer SM2 covering the contact portion CM may be removed during the manufacturing process, and therefore, the contact portion CM in the cavity CV may not be damaged during the formation of the cavity CV, thereby preventing the contact characteristics of the semiconductor chip mounted in the cavity CV from being deteriorated with the contact portion CM.

[0111] Now refer to Figures 17 to 21 as well as Fig.15 and Fig.16 A method for manufacturing a printed circuit board according to another embodiment is described. Figures 17 to 21 A cross-sectional view is shown regarding a method for manufacturing a printed circuit board according to another embodiment.

[0112] Reference Figures 17 to 21 , the method for manufacturing a printed circuit board according to the present embodiment is similar to the method for manufacturing a printed circuit board according to the previously described embodiment. A detailed description on the same manufacturing process will not be provided.

[0113] Reference Fig.17 When the second wiring layer ML2 is formed on the second insulating layer IL2, a portion of the first seed layer SD1 that is not disposed under the contact portion CM may be removed, thereby forming a seed layer SD under the contact portion CM.

[0114] Reference Fig.18 , a barrier layer CPL for covering the contact part CM may be formed on the second insulating layer IL2.

[0115] The barrier layer CPL may include a different metal layer from the seed layer SD and the contact portion CM, and the barrier layer CPL may have an etch rate different from those of the seed layer SD and the contact portion CM.

[0116] Reference Fig.19 , a third insulating layer IL3, a fourth insulating layer IL4, a fifth insulating layer IL5, a third via hole VA3, a fourth via hole VA4, a fifth via hole VA5, a third via hole VL3, a fourth via hole VL4, a fifth via hole VL5, a second pad layer PD2, a first sacrificial layer SFL1, a second sacrificial layer SFL2, a third sacrificial layer SFL3, a first solder resist layer SR1, and a second solder resist layer SR2, and a mask layer MSK may be formed. The third insulating layer IL3, the fourth insulating layer IL4, and the fifth insulating layer IL5 may be disposed on an edge portion of the barrier layer CPL.

[0117] Reference Fig. 20 , the third sacrificial layer SFL3, the second sacrificial layer SFL2, and the first sacrificial layer SFL1 may be etched and removed by using the mask layer MSK as an etching mask. In this case, the barrier layer CPL may cover the contact portion CM and may protect the contact portion CM, thereby preventing the contact portion CM from being damaged.

[0118] Reference Fig.21 , the barrier layer CPL exposed by the cavity CV is etched and removed by using the mask layer MSK as an etching mask to form a second dummy layer SM2 disposed at an edge of the bottom surface of the first cavity CV1.

[0119] The exposed portion of the contact part CM and the exposed portion of the second pad layer PD2 are surface-treated to form a cover layer CT on the second pad layer PD2 and a first cover layer CT1 on the contact part CM, thereby forming Fig.15 and Fig.16 The printed circuit board 200 is shown in FIG.

[0120] According to the method for manufacturing a printed circuit board according to the present embodiment, a cavity CV may be formed in the third insulating layer IL3, the fourth insulating layer IL4, and the fifth insulating layer IL5 as an example, but the number of insulating layers in which the cavity CV is formed may be more or less than the number shown in the drawings. Therefore, a cavity CV having a desired depth may be formed by adjusting the thickness and number of insulating layers in which the cavity CV is formed.

[0121] In addition, when forming the cavity CV, the contact portion CM set in the cavity CV is covered and protected by the barrier layer CPL and the first sacrificial layer SFL1, the second sacrificial layer SFL2 and the third sacrificial layer SFL3, so when forming the cavity CV, the contact portion CM in the cavity CV will not be damaged, thereby preventing the contact characteristics between the semiconductor chip installed in the cavity CV and the contact portion CM from deteriorating.

[0122] While the present disclosure has been described in connection with what are presently considered to be practical embodiments, it should be understood that the disclosure is not limited to the disclosed embodiments, but is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A printed circuit board, comprising: Insulation layer; a cavity disposed in at least a portion of the insulating layer; a contact portion disposed in the cavity; as well as a dummy layer disposed on a bottom portion of a sidewall of the cavity and between the insulating layers, Wherein, a first thickness of the dummy layer is smaller than a second thickness of the contact portion.

2. The printed circuit board according to claim 1, wherein: An edge of one of the insulating layers covering the dummy layer as a portion of the sidewall of the cavity is aligned with an edge of the dummy layer in a height direction perpendicular to an upper surface of the insulating layer.

3. The printed circuit board according to claim 1, wherein: The dummy layer includes a first dummy layer and a second dummy layer disposed on the first dummy layer, and An upper side of the second dummy layer is covered by one or more of the insulating layers.

4. The printed circuit board according to claim 3, further comprising: a seed layer disposed below the contact portion, The first dummy layer includes a material that is the same as a material of the seed layer, and the first dummy layer and the seed layer are formed in the same layer.

5. The printed circuit board according to claim 4, wherein: The first dummy layer and the second dummy layer include materials different from each other.

6. The printed circuit board according to claim 5, wherein: A portion of the sidewall of the cavity is aligned with an edge of the first dummy layer and an edge of the second dummy layer in a height direction perpendicular to an upper surface of the insulating layer.

7. The printed circuit board according to claim 3, wherein: The dummy layer further includes a third dummy layer disposed on a lateral side of the first dummy layer adjacent to the cavity.

8. The printed circuit board according to claim 7, further comprising: a covering layer disposed on the contact portion, The third dummy layer includes a material that is the same as that of the cover layer.

9. The printed circuit board according to claim 1, further comprising: a seed layer disposed below the contact portion, Wherein, the dummy layer includes a metal layer different from the seed layer.

10. The printed circuit board according to claim 9, wherein: A portion of the sidewall of the cavity is aligned with an edge of the dummy layer in a height direction perpendicular to an upper surface of the insulating layer.

11. The printed circuit board according to claim 1, wherein: The width of the cavity is not constant in a height direction perpendicular to the upper surface of the insulating layer.

12. A method for manufacturing a printed circuit board, the method comprising: forming a contact portion on the first insulating layer; forming a barrier layer on the contact portion; forming a second insulating layer having a cavity for exposing the barrier layer and covering an edge of the barrier layer; forming a sacrificial layer on the barrier layer in the cavity; removing the sacrificial layer; as well as A dummy layer is formed by removing a portion of the barrier layer exposed by the cavity, the dummy layer being disposed on a bottom portion of a sidewall of the cavity and under the second insulating layer.

13. The method according to claim 12, further comprising: Before forming the contact portion, a seed layer is formed on the first insulating layer.

14. The method according to claim 13, further comprising: After removing the portion of the barrier layer exposed by the cavity, the portion of the seed layer not covered by the second insulating layer and the contact portion is removed.

15. The method according to claim 14, wherein: The dummy layer includes a first dummy layer and a second dummy layer disposed on the first dummy layer, and An upper side of the second dummy layer is covered by the second insulating layer.

16. The method according to claim 15, wherein: The first dummy layer is formed using the same layer as the seed layer, and The second dummy layer is formed using the same layer as the barrier layer.

17. The method according to claim 15, further comprising: After forming the first dummy layer and the second dummy layer, a cover layer is formed on the surface of the contact portion.

18. The method according to claim 17, further comprising: A third dummy layer is further formed on a lateral side of the first dummy layer adjacent to the cavity.

19. The method according to claim 18, wherein: The third dummy layer is formed using the same material as that of the cover layer.

20. The method according to claim 12, wherein: The width of the cavity is formed to be non-constant in a height direction perpendicular to an upper surface of the second insulating layer.

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