Semiconductor device and method of manufacturing the same, electronic device

Abstract

A semiconductor device and a manufacturing method thereof, and an electronic device, relate to but are not limited to the technical field of semiconductors, and the semiconductor device comprises a transistor and a capacitor arranged on a substrate; the capacitor comprises a first capacitor electrode, a capacitor dielectric layer and a second capacitor electrode, the capacitor dielectric layer is arranged at least between the first capacitor electrode and the second capacitor electrode; the first capacitor electrode is connected with the first electrode; at least part of the first capacitor electrode is arranged on the sidewall of the first electrode; thereby improving the stability of the first capacitor electrode.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to, but are not limited to, semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, and an electronic device. BACKGROUND

[0002] With the development of integrated circuit technology, the critical dimension of devices is increasingly reduced, and the types and quantities of devices contained in a single chip are also increased, so that any slight difference in process production can affect the performance of the devices.

[0003] In order to reduce the cost of products as much as possible, people want to make as many device units as possible on a limited substrate. Since the advent of Moore's Law, various semiconductor structure designs and process optimizations have been proposed in the industry to meet people's current product needs. SUMMARY

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] Embodiments of the present disclosure provide a semiconductor device, comprising: a substrate, a plurality of memory cells disposed on the substrate, the memory cells comprising transistors and capacitors arranged along a first direction parallel to the substrate;

[0006] The transistor comprises a channel, a gate insulating layer, a gate, a first electrode and a second electrode, the gate insulating layer is disposed between the gate and the channel, and the first electrode and the second electrode are respectively connected with the channel;

[0007] The capacitor comprises a first capacitor electrode, a capacitor dielectric layer and a second capacitor electrode, the capacitor dielectric layer is at least disposed between the first capacitor electrode and the second capacitor electrode; and the first capacitor electrode is connected with the first electrode;

[0008] The first capacitor electrode and the first electrode connected with each other have an overlap in the first direction.

[0009] In some embodiments, the first capacitor electrode comprises a main body portion and a clamping portion connected with each other, the clamping portion is disposed on a side of the main body portion close to the first electrode, a clamping groove is disposed in the clamping portion, an opening of the clamping groove is disposed towards the first electrode, at least part of the first electrode is disposed in the clamping groove, and the clamping portion and the first electrode have an overlap in the first direction.

[0010] In some embodiments, the clamping portion comprises two clamping walls, the two clamping walls are parallel to the substrate and are disposed on opposite sides of at least part of the first electrode in a direction perpendicular to the substrate.

[0011] In some embodiments, the main body portion and the clamping portion are integrally formed and comprise the same conductive material.

[0012] In some embodiments, the main body portion and the clamping portion are integrally formed and comprise the same conductive material.

[0013] In some embodiments, the main body portion has a U-shaped cross section perpendicular to the substrate, the main body portion comprises a top wall, a bottom wall, and a side wall connecting the top wall and the bottom wall, the top wall and the bottom wall are oppositely arranged and both are parallel to the substrate, the side wall is perpendicular to the substrate, the side wall is connected with the clamping portion and forms the clamping groove with the clamping portion.

[0014] In some embodiments, an insulating layer is further included, the insulating layer is located on at least one side of the first capacitor electrode perpendicular to the substrate, and the insulating layer overlaps with the orthographic projection of the clamping portion on the substrate.

[0015] In some embodiments, the insulating layer overlaps with the orthographic projection of at least part of the main body portion on the substrate.

[0016] In some embodiments, the first capacitor electrode has an H-shaped cross section perpendicular to the substrate.

[0017] In some embodiments, an isolation layer is arranged on the first surface of the first electrode, the part of the first surface of the first capacitor electrode is not provided with the isolation layer, and at least part of the first capacitor electrode is arranged on the part of the first surface.

[0018] In some embodiments, the isolation layer is in contact with the first electrode and the first capacitor electrode.

[0019] In some embodiments, the isolation layer is different from the material of the first capacitor electrode.

[0020] In some embodiments, a hole perpendicular to the substrate is further included, a part of the first electrode is arranged in the hole, and the first capacitor electrode, the capacitor dielectric layer, and the second capacitor electrode are sequentially arranged on the surface of the first electrode in the hole and on the side wall of the hole.

[0021] In some embodiments, the first capacitor electrode, the capacitor dielectric layer, and the second capacitor electrode are all thin films, the capacitor further comprises a conductive filling layer, the conductive filling layer fills the hole, and the conductive filling layer is connected with the second capacitor electrode.

[0022] In some embodiments, a bit line is further included, the bit line is parallel to the substrate, and the bit line is connected with the second electrode.

[0023] In some embodiments, a word line is further included, the word line is perpendicular to the substrate, and the word line is connected with the gate.

[0024] The embodiments of the present disclosure further provide a manufacturing method of a semiconductor device, comprising:

[0025] forming a stack structure comprising first electrodes and insulating layers arranged alternately on a substrate, and an isolation layer arranged on a surface of the first electrode;

[0026] forming a hole perpendicular to the substrate in the stack structure by using an etching process, and exposing a sidewall of the isolation layer and a sidewall of the insulating layer by the hole;

[0027] exposing the first electrode by removing part of the isolation layer along a direction parallel to the substrate by using an etching process;

[0028] forming a first capacitor electrode, a capacitor dielectric layer and a second capacitor electrode on the exposed first electrode and the sidewall of the hole in sequence to form a capacitor, and arranging the first electrode and the capacitor along a first direction parallel to the substrate, connecting the first capacitor electrode and the first electrode with each other, and having an overlap in the first direction.

[0029] In some embodiments, a size of the hole at a position of the insulating layer in the first direction is smaller than a size of the hole at a position of the first electrode in the first direction.

[0030] In some embodiments, forming a first capacitor electrode, a capacitor dielectric layer and a second capacitor electrode on the exposed first electrode and the sidewall of the hole in sequence comprises:

[0031] forming a capacitor electrode film and a barrier film on the exposed first electrode and the sidewall of the hole in sequence;

[0032] exposing the capacitor electrode film on the sidewall of the insulating layer by removing the barrier film at the position of the insulating layer by using an etching process, and retaining the barrier film at the position of the first electrode to form an etching barrier layer;

[0033] exposing the first capacitor electrode by removing the capacitor electrode film on the sidewall of the insulating layer by using an etching process, and retaining the capacitor electrode film at the position of the first electrode to form a first capacitor electrode;

[0034] exposing an inner surface of the first capacitor electrode by removing the etching barrier layer along a direction parallel to the substrate;

[0035] exposing an outer surface of at least part of the first capacitor electrode by removing part of the insulating layer along a direction parallel to the substrate.

[0036] a capacitive dielectric layer and a second capacitive electrode are sequentially formed on the inner surface of the exposed first capacitive electrode and the outer surface of the exposed first capacitive electrode.

[0037] In some embodiments, etching to remove part of the insulating layer in a direction parallel to the substrate includes: etching to remove part of the insulating layer in the first direction, the distance of the insulating layer etched being less than the length of the first capacitive electrode in the first direction.

[0038] The semiconductor device of the embodiments of the present disclosure also provides an electronic device.

[0039] The semiconductor device of the embodiments of the present disclosure has the first capacitive electrode and the first electrode connected to each other in the first direction, so that the first capacitive electrode is pressed and fixed by the first electrode, thereby improving the stability of the connection between the first capacitive electrode and the first electrode and avoiding collapse of the first capacitive electrode.

[0040] The semiconductor device of the embodiments of the present disclosure has the first electrode clamped by the clamping portion of the first capacitive electrode, thereby improving the stability of the connection between the first capacitive electrode and the first electrode.

[0041] The semiconductor device of the embodiments of the present disclosure has the main body portion and the clamping portion of the first capacitive electrode in an integrated structure and made of the same conductive material, thereby simplifying the production process and ensuring the strength of the first capacitive electrode.

[0042] The semiconductor device of the embodiments of the present disclosure has the clamping portion of the first capacitive electrode clamped by the insulating layer, thereby improving the stability of the first capacitive electrode and avoiding collapse of the first capacitive electrode.

[0043] The semiconductor device of the embodiments of the present disclosure has at least part of the first capacitive electrode arranged on the exposed first electrode, so that the first capacitive electrode clamps the first electrode, thereby improving the stability of the connection between the first capacitive electrode and the first electrode.

[0044] The manufacturing method of the semiconductor device of the embodiments of the present disclosure exposes the first electrode by etching to remove part of the insulating layer exposed by the hole in a direction parallel to the substrate, and then forms the first capacitive electrode on the exposed first electrode, so that at least part of the first capacitive electrode is arranged on the exposed first electrode, thereby improving the stability of the connection between the first capacitive electrode and the first electrode and avoiding collapse of the first capacitive electrode.

[0045] The manufacturing method of the semiconductor device of the embodiment of the present disclosure can retain part of the barrier film in the hole corresponding to the first electrode when removing the barrier film on the sidewall of the hole corresponding to the insulating layer in subsequent etching, and form an etching barrier layer.

[0046] The manufacturing method of the semiconductor device of the embodiment of the present disclosure can block the etching liquid from etching the capacitor electrode film on the sidewall of the hole corresponding to the first electrode and the first electrode when removing the capacitor electrode film on the sidewall of the hole corresponding to the insulating layer in etching, retain the capacitor electrode film on the sidewall of the hole corresponding to the first electrode and the first electrode, and form a first capacitor electrode.

[0047] The manufacturing method of the semiconductor device of the embodiment of the present disclosure can expose the inner surface and the outer surface of the first capacitor electrode by removing the etching barrier layer and part of the insulating layer in etching, enable the second capacitor electrode to be arranged opposite to the exposed inner surface and outer surface of the first capacitor electrode, thereby increasing the relative area of the second capacitor electrode and the first capacitor electrode, and improving the capacity of the capacitor.

[0048] Other features and advantages of the present application will be set forth in the following description, and in part will become apparent to those skilled in the art upon examination of the following or can be learned by practice of the present application. The objects and advantages of the present application can be realized and attained by means of the instrumentalities and combinations particularly pointed out in the description and appended claims.

[0049] Other aspects can become apparent to those of ordinary skill in the art upon reading and understanding the following detailed description with reference to the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0050] The accompanying drawings are included to provide a further understanding of the technical solutions of the present disclosure, and constitute a part of the specification, and are used to explain the technical solutions of the present disclosure together with the embodiments of the present disclosure, and do not constitute a limitation on the technical solutions.

[0051] Figure 1 The semiconductor device provided for some embodiments is shown in a cross-sectional view along a direction parallel to the substrate;

[0052] Figure 2a The semiconductor device provided for some embodiments is shown in a cross-sectional view along a direction parallel to the substrate; Figure 1 The semiconductor device provided for some embodiments is shown in a cross-sectional view along a direction parallel to the substrate;

[0053] Figure 2b The semiconductor device provided for some embodiments is shown in a cross-sectional view along a direction parallel to the substrate; Figure 1 The semiconductor device provided for some embodiments is shown in a cross-sectional view along a direction parallel to the substrate;

[0054] Figure 2c The semiconductor device provided for some embodiments is shown in a cross-sectional view along a direction parallel to the substrate; Figure 1A cross-sectional view of a semiconductor device in a plane passing through the d-d' line and perpendicular to the substrate;

[0055] Figure 3 This is a schematic diagram showing the connection between a first electrode and a first capacitor electrode in a semiconductor device provided in some embodiments;

[0056] Figure 4 A schematic diagram of the structure of the first capacitor electrode in a semiconductor device provided in some embodiments;

[0057] Figure 5a for Figure 1 A cross-sectional view of a semiconductor device after the first electrode, second electrode, and hole are formed in the process of manufacturing the semiconductor device, in a plane passing through line a-a' and perpendicular to the substrate;

[0058] Figure 5b for Figure 1 A cross-sectional view of a plane passing through the b-b' line and perpendicular to the substrate after the first electrode, second electrode and hole are formed during the manufacturing process of a semiconductor device.

[0059] Figure 5c for Figure 1 A cross-sectional view of a plane passing through the c-c' line and perpendicular to the substrate after the first electrode, second electrode and hole are formed during the manufacturing process of a semiconductor device.

[0060] Figure 5d for Figure 1 A cross-sectional view of a plane passing through the d-d' line and perpendicular to the substrate after the first electrode, second electrode and hole are formed during the manufacturing process of a semiconductor device.

[0061] Figure 6 for Figure 1 A cross-sectional view of the first electrode after one end is exposed during the manufacturing process of a semiconductor device, in a plane passing through line a-a' and perpendicular to the substrate;

[0062] Figure 7a for Figure 1 A cross-sectional view of the semiconductor device after the formation of the capacitor electrode film and the barrier film in a plane passing through line a-a' and perpendicular to the substrate during the manufacturing process of the semiconductor device.

[0063] Figure 7b for Figure 1 A cross-sectional view of the semiconductor device after the formation of the capacitor electrode film and the barrier film in a plane passing through the d-d' line and perpendicular to the substrate.

[0064] Figure 8a for Figure 1 A cross-sectional view of a plane passing through line a-a' and perpendicular to the substrate after the etch barrier layer is formed during the manufacturing process of a semiconductor device;

[0065] Figure 8b for Figure 1 A cross-sectional view of a plane passing through the d-d' line and perpendicular to the substrate after the etch barrier layer is formed during the manufacturing process of a semiconductor device.

[0066] Figure 9a for Figure 1 A cross-sectional view of a plane passing through line a-a' and perpendicular to the substrate after the first capacitor electrode is formed during the manufacturing process of a semiconductor device.

[0067] Figure 9b for Figure 1 A cross-sectional view of a plane passing through the d-d' line and perpendicular to the substrate after the first capacitor electrode is formed during the manufacturing process of a semiconductor device.

[0068] Figure 10a for Figure 1 A cross-sectional view of the first capacitor electrode in a plane passing through line a-a' and perpendicular to the substrate after the inner surface of the first capacitor electrode is exposed during the manufacturing process of a semiconductor device.

[0069] Figure 10b for Figure 1 A cross-sectional view of the first capacitor electrode in a plane passing through the d-d' line and perpendicular to the substrate after the inner surface of the first capacitor electrode is exposed during the manufacturing process of a semiconductor device.

[0070] Figure 11a for Figure 1 A cross-sectional view of the first capacitor electrode in a plane passing through line a-a' and perpendicular to the substrate after the outer surface of the first capacitor electrode is exposed during the manufacturing process of a semiconductor device.

[0071] Figure 11b for Figure 1 A cross-sectional view of the first capacitor electrode in a plane passing through the d-d' line and perpendicular to the substrate after the outer surface of the first capacitor electrode is exposed during the manufacturing process of a semiconductor device. Detailed Implementation

[0072] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Unless otherwise specified, the embodiments of this disclosure and the features thereof can be combined arbitrarily with each other.

[0073] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention pertains.

[0074] The embodiments disclosed herein are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect actual proportions. Furthermore, the drawings schematically illustrate ideal examples, and the embodiments of this disclosure are not limited to the shapes or values ​​shown in the drawings.

[0075] The ordinal numbers “first,” “second,” “third,” etc., used in this disclosure are provided to avoid confusion among the constituent elements and do not indicate any order, quantity, or importance.

[0076] In this disclosure, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification of the specification, and does not imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the direction in which each constituent element is described. Therefore, the disclosure is not limited to the terms used herein and may be appropriately replaced as appropriate.

[0077] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art can understand the specific meaning of these terms in this disclosure according to the specific circumstances.

[0078] In this disclosure, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0079] In this disclosure, the first electrode may be the drain electrode and the second electrode may be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this disclosure, the "source electrode" and the "drain electrode" can be interchanged.

[0080] In this disclosure, "electrical connection" includes the situation where constituent elements are connected together by a component having a certain electrical function. There are no particular limitations on the "component having a certain electrical function," as long as it enables the transmission and reception of electrical signals between the connected constituent elements. Examples of "component having a certain electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0081] In this disclosure, "parallel" means approximately parallel or nearly parallel, for example, two straight lines forming an angle of -10° or more and less than 10°, and therefore also includes angles of -5° or more and less than 5°. Similarly, "perpendicular" means approximately perpendicular, for example, two straight lines forming an angle of 80° or more and less than 100°, and therefore also includes angles of 85° or more and less than 95°.

[0082] In this disclosure, the terms "film" and "layer" can be interchanged. For example, sometimes "conductive layer" can be replaced with "conductive film". Similarly, sometimes "insulating film" can be replaced with "insulating layer".

[0083] The phrase "A and B are set on the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process. "The orthographic projection of B is within the range of the orthographic projection of A" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0084] In this embodiment of the disclosure, "A and B are an integral structure" can refer to a structure without obvious boundaries such as discontinuities or gaps in its microstructure. Generally, an integral structure is formed by patterning interconnected membrane layers on a single membrane layer. For example, A and B may be formed using the same material as a single membrane layer and simultaneously created through the same patterning process, resulting in a structure with interconnected relationships.

[0085] This disclosure provides a semiconductor device, including: a substrate and a plurality of memory cells disposed on the substrate, wherein the memory cells include transistors and capacitors arranged along a first direction parallel to the substrate;

[0086] The transistor includes a channel, a gate insulating layer, a gate, a first electrode, and a second electrode. The channel surrounds the gate, the gate insulating layer is disposed between the gate and the channel, and the first electrode and the second electrode are respectively connected to the channel.

[0087] The capacitor includes a first capacitor electrode, a capacitor dielectric layer, and a second capacitor electrode, wherein the capacitor dielectric layer is at least disposed between the first capacitor electrode and the second capacitor electrode; the first capacitor electrode is connected to the first electrode.

[0088] The first capacitor electrode and the first electrode, which are interconnected, overlap in the first direction.

[0089] In some embodiments, the first capacitor electrode includes a main body portion and a clamping portion connected to each other. The clamping portion is disposed on the side of the main body portion near the first electrode. The clamping portion is provided with a clamping groove, the opening of which faces the first electrode. At least a portion of the first electrode is disposed in the clamping groove. The clamping portion and the first electrode overlap in the first direction.

[0090] The semiconductor devices disclosed herein are illustrated below through some exemplary embodiments.

[0091] Figure 1 A schematic cross-sectional view of a semiconductor device along a direction parallel to the substrate, provided for some embodiments. In some embodiments, such as... Figure 1 As shown, a semiconductor device may include: a word line, a bit line 3, a transistor 1, and a capacitor 2 disposed on a substrate. In one embodiment, the semiconductor device containing only transistor 1 and capacitor 2 forms a 1T1C structure. The first electrode of transistor 1 is connected to the first capacitor electrode of capacitor 2, and the second electrode of transistor 1 is connected to the bit line 3; the word line is connected to the gate of transistor 1; and the bit line 3 is connected to the second electrode of transistor 1. The capacitor in this application can be understood as a capacitor.

[0092] In some embodiments, the transistor 1 may include a channel 23, a gate insulating layer 24, a gate 25, a first electrode, and a second electrode. The gate 25 may be perpendicular to the substrate. The gate insulating layer 24 is disposed between the gate 25 and the channel 23. The channel 23 surrounds the sidewalls of the gate 25 through the gate insulating layer 24. The first electrode and the second electrode are respectively connected to the channel. Figure 1 The first electrode and the second electrode are not shown. The sidewall of the channel surrounding the gate includes at least one of the following: the channel completely surrounds the gate, the channel partially surrounds the gate, or the channel is disposed on one side of the gate.

[0093] In some embodiments, the gate and the word line are an integral structure.

[0094] In some embodiments, a channel surrounds the gate and extends along the sidewalls of the gate, forming an annular shape extending in a direction perpendicular to the substrate. The thickness direction of the channel film is parallel to the substrate.

[0095] In this context, "channel surrounding the gate" can be understood as the channel partially or completely surrounding the gate. In some embodiments, the surrounding can be a complete surround, resulting in a closed annular cross-section of the channel. The cross-section is taken in a direction parallel to the substrate. In some embodiments, the surrounding can be a partial surround, where the resulting cross-section is not closed but exhibits a ring shape. For example, an annular shape with an opening.

[0096] In some embodiments, the word line may be perpendicular to the substrate and connected to the gates of a plurality of transistors stacked along a direction perpendicular to the substrate, and the plurality of transistors may share the word line.

[0097] In some embodiments, the bit line may extend parallel to the substrate along a second direction D2. The bit line is connected to the second electrode of a transistor located in the same layer, and the transistors in the same layer may share the bit line. The second direction D2 intersects the first direction D1; for example, the second direction D2 and the first direction D1 are perpendicular to each other.

[0098] In some embodiments, the capacitor 2 includes a first capacitor electrode 71, a second capacitor electrode 72, and a capacitor dielectric layer 73, wherein the first capacitor electrode 71 is connected to a first electrode. The capacitor dielectric layer 73 is at least disposed between the first capacitor electrode 71 and the second capacitor electrode 72. At least a portion of the second capacitor electrode 72 is disposed on the sidewall of the first capacitor electrode 71 through the capacitor dielectric layer 73.

[0099] In some embodiments, the first capacitor electrode 71, the second capacitor electrode 72, and the capacitor dielectric layer 73 are all thin films. The capacitor 2 further includes a conductive filling layer 74. The second capacitor electrode 72 is disposed on the sidewall of the conductive filling layer 74, and the first capacitor electrode 71 is disposed on the second capacitor electrode 72 through the capacitor dielectric layer 73.

[0100] In some embodiments, the materials of the first capacitor electrode 71 and the second capacitor electrode 72 may both be titanium nitride.

[0101] In some embodiments, the conductive filling layer 74 may be made of germanium-doped polycrystalline silicon.

[0102] Figure 2a for Figure 1 A cross-sectional view of the semiconductor device in a plane passing through line a-a' and perpendicular to the substrate; Figure 2b for Figure 1 A cross-sectional view of the semiconductor device in a plane passing through line b-b' and perpendicular to the substrate; 3c is... Figure 1 A cross-sectional view of the semiconductor device in a plane passing through the d-d' line and perpendicular to the substrate. In some embodiments, such as Figure 2a , Figure 2b and Figure 2cAs shown, the first electrode 21 and the second electrode 22 are located on opposite sides of the channel in a direction parallel to the substrate 101 and are connected through the channel. The first electrode 21 is located on the side of the channel closer to the capacitor, with its first end connected to the first capacitor electrode 71 and its second end connected to the channel. The second electrode 22 is located on the side of the channel away from the capacitor, with its first end connected to the channel and its second end connected to the bit line. The channel between the first electrode and the second electrode is a horizontal channel.

[0103] In some embodiments, word line 2 may be perpendicular to the substrate and connected to the gates of a plurality of transistors stacked along a direction perpendicular to the substrate, and the plurality of transistors may share the word line.

[0104] In some embodiments, the semiconductor device of this application further includes a hole K extending along a direction perpendicular to the substrate. The sidewall of the hole K exposes a first end of a first electrode 21. A portion of the first electrode 21 is disposed in the hole K. A first capacitor electrode 71, a capacitor dielectric layer 73, and a second capacitor electrode 72 can be sequentially disposed on the surface of the first electrode 21 in the hole K and on the sidewall of the hole K using an atomic deposition process. A conductive filling layer 74 fills the hole K. The hole K exposes the first end of the first electrode 21, and the first capacitor electrode 71 on the sidewall of the hole K is disposed on the exposed first electrode 21, thereby clamping the first end of the exposed first electrode 21 with the first capacitor electrode 71.

[0105] Figure 3 This is a schematic diagram illustrating the connection between a first electrode and a first capacitor electrode in a semiconductor device according to some embodiments. In some embodiments, such as... Figure 3 As shown, the first capacitor electrode 71 and the first electrode 21, which are interconnected, overlap in a first direction D1 parallel to the substrate, such that at least a portion of the first capacitor electrode 71 is disposed on the sidewall of the first electrode 21. Specifically, at least a portion of the first capacitor electrode 71 is disposed on opposite sides of the first electrode 21 in a direction perpendicular to the substrate, allowing the first capacitor electrode 71 to clamp the first electrode 21.

[0106] In some embodiments, the first capacitor electrode may contact only one of the upper surface, lower surface, and two side surfaces of the first electrode, or it may contact two, three, or four of the upper surface, lower surface, and two side surfaces of the first electrode.

[0107] In this embodiment of the semiconductor device, a first capacitor electrode is disposed on a first electrode, which enables the first capacitor electrode to clamp the first electrode, thereby improving the stability of the connection between the first capacitor electrode and the first electrode and preventing the first capacitor electrode from collapsing.

[0108] In some embodiments, an insulating layer 211 is provided on the first surface of the first electrode 21. The portion of the first surface near the first capacitor electrode 71 is not provided with the insulating layer 211, and at least a portion of the first capacitor electrode 71 is disposed on this portion of the first surface. One end of the insulating layer 211 near the first capacitor electrode 71 exposes the first electrode 21, meaning that the end of the first electrode 21 near the first capacitor electrode 71 is not covered by the insulating layer 211. The end of the insulating layer 211 near the first capacitor electrode 71 is connected to the first capacitor electrode 71. At least a portion of the first capacitor electrode 71 is disposed on the exposed first electrode 21.

[0109] In this embodiment of the semiconductor device, at least a portion of the first capacitor electrode is disposed on the exposed first electrode, so that the first capacitor electrode clamps the first electrode, thereby improving the stability of the connection between the first capacitor electrode and the first electrode.

[0110] In some embodiments, one end of the isolation layer 211 near the first capacitor electrode 71 is connected to one end of the first capacitor electrode 71 near the isolation layer 211, and the orthographic projections of the isolation layer 211 and the corresponding first capacitor electrode 71 on the substrate do not overlap.

[0111] In some embodiments, the isolation layer 211 is in contact with both the first electrode 21 and the first capacitor electrode 71.

[0112] In some embodiments, the insulating layer 211 and the first capacitor electrode 71 may be made of the same or different materials. For example, the insulating layer may be made of copper, ITO, IZO, etc., which can reduce the contact resistance between the first electrode and the first capacitor electrode. In some embodiments, the insulating layer 211 may be made of titanium nitride.

[0113] In some embodiments, the material of the first electrode 21 may include tungsten.

[0114] Figure 4 This is a schematic diagram of the structure of a first capacitor electrode in a semiconductor device provided for some embodiments. In some embodiments, such as... Figure 3 and Figure 4As shown, the first capacitor electrode 71 includes a main body portion 711 and a clamping portion 712 connected to each other. The clamping portion 712 is disposed on the side of the main body portion 711 near the first electrode 21, and the clamping portion 712 overlaps with the first electrode 21 in a first direction D1 parallel to the substrate. The clamping portion 712 is provided with a clamping groove 713, the opening of the clamping groove 713 is disposed facing the first electrode 21, and one end of the first electrode 21 near the first capacitor electrode 71 extends into the clamping groove 713 through the opening of the clamping groove 713, so that one end of the first electrode 21 near the first capacitor electrode 71 is disposed in the clamping groove 713, and the clamping portion 713 is disposed on the end of the first electrode 21 near the first capacitor electrode 71, thereby clamping the first electrode 21 tightly and improving the stability of the connection between the first capacitor electrode 71 and the first electrode 21.

[0115] In some embodiments, the clamping portion 712 includes two clamping walls parallel to the substrate and disposed on opposite sides of at least a portion of the first electrode 21 in a direction perpendicular to the substrate. First ends of the two clamping walls are connected to the main body portion 711, and second ends of the two clamping walls are connected to the end of the insulating layer 211.

[0116] In some embodiments, the end of the first electrode 21 exposed by the isolation layer 211 is disposed in the clamping groove 713, such that the two clamping walls are disposed on the end of the first electrode 21 exposed by the isolation layer 211 and located on opposite sides of the exposed first electrode 21 in a direction perpendicular to the substrate.

[0117] In some embodiments, the two clamping walls and the isolation layer 211 are located in the same film layer. The two clamping walls and the isolation layer 211 are made of the same material; for example, the materials of both clamping walls and the isolation layer 211 may include titanium nitride.

[0118] In some embodiments, the main body portion 711 has a U-shaped cross-section perpendicular to the substrate. The main body portion 711 includes a top wall 7111, a bottom wall 7112, and a side wall 7113 connecting the top wall 7111 and the bottom wall 7112. The top wall 7111 and the bottom wall 7112 are disposed opposite each other and are both parallel to the substrate. The side wall 7113 is perpendicular to the substrate and is located on the side of the top wall 7111 and the bottom wall 7112 closest to the first electrode 21. The side of the side wall 7113 away from the top wall 7111 and the bottom wall 7112 is connected to a first end of the two clamping walls, and the side wall 7113 and the two clamping walls form the clamping groove 713.

[0119] In some embodiments, at least a portion of the second capacitor electrode is disposed on the inner and outer surfaces of the top wall 7111, the inner and outer surfaces of the bottom wall 7112, and the inner surface of the side wall 7113, thereby increasing the relative area between the second capacitor electrode and the first capacitor electrode and improving the capacitance.

[0120] In some embodiments, the first capacitor electrode 71 formed by the main body portion 711 and the clamping portion 712 has an H-shaped cross section perpendicular to the substrate direction.

[0121] In some embodiments, the main body portion 711 and the clamping portion 712 are integrally formed structures and comprise the same conductive material. For example, the material of both the main body portion 711 and the clamping portion 712 may comprise titanium nitride.

[0122] The semiconductor device of this disclosure simplifies the manufacturing process and ensures the strength of the first capacitor electrode by making the main body and the clamping part of the first capacitor electrode an integral structure and including the same conductive material.

[0123] In some embodiments, such as Figure 2a As shown, the semiconductor device in this embodiment further includes an insulating layer 41. The insulating layer 41 is disposed between adjacent first electrodes 21 in a direction perpendicular to the substrate, separating the adjacent first electrodes 21. The insulating layer 41 is located on at least one side of the first capacitor electrode 71 in a direction perpendicular to the substrate. The insulating layer 41 overlaps with the orthographic projection of the clamping portion 712 on the substrate, and the insulating layer 41 overlaps with the orthographic projection of at least a portion of the main body portion 711 on the substrate, enabling the insulating layer 41 to clamp the first capacitor electrode 71 and provide support for the first capacitor electrode 71.

[0124] In this embodiment of the semiconductor device, the clamping portion of the first capacitor electrode is clamped by an insulating layer, thereby improving the stability of the first capacitor electrode and preventing it from collapsing.

[0125] In some embodiments, a capacitor dielectric layer 73 and a second capacitor electrode 72 are sequentially disposed on the end face of the insulating layer 41 near one end of the capacitor.

[0126] In some embodiments, a groove is formed between the end face of the insulating layer 41 near one end of the capacitor and the adjacent first capacitor electrode 71, and the capacitor dielectric layer 73 and the second capacitor electrode 72 are sequentially disposed on the inner wall of the groove.

[0127] In some embodiments, in the direction perpendicular to the substrate, the second capacitor electrode 72 of the capacitors in the same column of different layers can be connected into an integral structure, that is, the capacitors in the same column of different layers share the same second capacitor electrode 72.

[0128] In some embodiments, the capacitor dielectric layers 73 of capacitors in the same column of different layers can be connected into a single structure in the direction perpendicular to the substrate; that is, capacitors in the same column of different layers share the same capacitor dielectric layer 73. The capacitors in the same column of different layers refer to capacitors located in different film layers stacked along the direction perpendicular to the substrate and arranged along the same direction.

[0129] The technical solution of this embodiment is further illustrated below through the manufacturing process of the semiconductor device in this embodiment. The "patterning process" mentioned in this embodiment includes deposition of a film layer, coating with photoresist, mask exposure, development, etching, and photoresist stripping, which are mature manufacturing processes in related technologies. The "photolithography process" mentioned in this embodiment includes coating of a film layer, mask exposure, and development, which are mature manufacturing processes in related technologies. Deposition can employ known processes such as sputtering, evaporation, and chemical vapor deposition; coating can employ known coating processes; and etching can employ known methods, without specific limitations. In the description of this embodiment, it should be understood that a "thin film" refers to a thin film made of a certain material on a substrate using a deposition or coating process. If the "thin film" does not require a patterning process or photolithography process during the entire manufacturing process, it can also be called a "layer." If the "thin film" requires a patterning process or photolithography process during the entire manufacturing process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process or photolithography process contains at least one "pattern."

[0130] In some embodiments, the semiconductor device may be any of the semiconductor devices described above, and the manufacturing process of the semiconductor device may include:

[0131] Step 101: Form the first electrode, the second electrode, and the hole.

[0132] The formation of the first electrode, the second electrode, and the vias includes: forming a stacked structure on a substrate 101 comprising alternating insulating sacrificial layers and insulating layers 41; subsequently, patterning the stacked structure using a mask to form multiple trenches perpendicular to the substrate, wherein each insulating layer 41 forms a first patterned structure stacked and cyclically distributed, and each insulating sacrificial layer forms a second patterned structure stacked and cyclically distributed; subsequently, etching the stacked structure using a dry etching process to form multiple vias penetrating the multiple insulating sacrificial layers and the multiple insulating layers 41, wherein the sidewalls of the vias expose the sidewalls of each insulating sacrificial layer and the insulating layer 41; subsequently, removing at least a portion of each insulating sacrificial layer through lateral etching of the vias, and in the area where each insulating sacrificial layer is removed by etching... A first electrode 21 and a second electrode 22 are formed on opposite sides of the via in a direction parallel to the substrate. An isolation layer is formed on the surface of both the first electrode 21 and the second electrode 22. The via exposes the isolation layers on the sidewalls of the first electrode 21 and the second electrode 22. Subsequently, a sacrificial layer 43 is formed within the vias, filling them. Then, a barrier layer 44 is formed on the stacked structure. The barrier layer 44 can be made of silicon nitride. Finally, the stacked structure is etched using a dry etching process to form a hole K penetrating the barrier layer 44, the multiple insulating sacrificial layers, and the multiple insulating layers 41. The hole K extends in a direction perpendicular to the substrate. The hole K does not overlap with the orthographic projection of the sacrificial layer 43 onto the substrate 101. The hole K exposes the sidewalls of the isolation layer 211 and the insulating layer 41. Figure 5a , Figure 5b , Figure 5c and Figure 5d As shown.

[0133] In some embodiments, the size of the hole K portion at the location of the insulating layer 41 in the first direction D1 parallel to the substrate is smaller than the size of the hole K portion at the location of the first electrode 21 in the first direction D1. The area of ​​the hole K portion at the location of the insulating layer 41 projected onto the substrate 101 is smaller than the area of ​​the hole K portion at the location of the first electrode 21 projected onto the substrate. The sidewall of the hole K corresponding to the insulating layer 41 and the sidewall of the hole K corresponding to the first electrode 21 form a step shape. The first electrode 21 and the adjacent insulating layer 41 form a first groove, which is parallel to the substrate.

[0134] In some embodiments, in subsequent processes, the sacrificial layer 43 may be removed, and a semiconductor layer, a gate insulating layer, and a gate may be sequentially formed on the sidewall of the via.

[0135] In some embodiments, the insulating layer and the insulating sacrificial layer may be deposited using a chemical vapor deposition method.

[0136] In some embodiments, the substrate may be a semiconductor substrate, such as a silicon substrate, or any substrate that serves as a support, not just a substrate, but a substrate formed by peripheral circuits on the substrate.

[0137] In some embodiments, the insulating layer serves to isolate devices and may be a low-K dielectric layer, i.e., a dielectric layer with a dielectric constant K < 3.9, including but not limited to silicon oxide, such as silicon dioxide (SiO2).

[0138] Step 102: Expose one end of the first electrode.

[0139] Exposing one end of the first electrode includes: on the substrate forming the aforementioned pattern, using an etching process, etching away the portion of the isolation layer 211 of the first electrode 21 exposed by the hole K along a direction parallel to the substrate 101, thereby exposing one end of the first electrode 21. For example, the etched-away isolation layer 211 exposes the end face, upper surface, and lower surface of one end of the first electrode 21. The upper and lower surfaces are the two opposing surfaces of one end of the first electrode 21 on the substrate 101 perpendicular to it. Figure 6 As shown.

[0140] Step 103: Forming a capacitor electrode thin film and a barrier film.

[0141] The formation of the capacitor electrode film and the barrier film includes: based on the substrate with the aforementioned pattern, using an atomic deposition process, sequentially forming a capacitor electrode film 70 and a barrier film 60 on the exposed first electrode and the sidewall of the hole K. The barrier film 60 covers the capacitor electrode film 70. The barrier film 60 fills the first groove formed by the first electrode 21 and the adjacent insulating layer 41, and the barrier film 60 does not completely fill the hole K. The barrier film 60 forms a second groove in the hole, and the second groove is perpendicular to the substrate 101. Figure 7a and Figure 7b As shown.

[0142] Step 104: Form an etching barrier layer.

[0143] Forming the etch barrier layer includes: on the substrate with the aforementioned pattern, using a wet etching process to etch away the barrier film at the location of the insulating layer 41, exposing the capacitor electrode film 70 on the sidewall of the insulating layer 41, retaining the barrier film at the location of the first electrode 21, forming an etch barrier layer 61. The etch barrier layer 61 fills the first groove formed by the first electrode 21 and the adjacent insulating layer 41, such as... Figure 8a and Figure 8b As shown.

[0144] Step 105: Form the first capacitor electrode.

[0145] Forming the first capacitor electrode includes: on the substrate with the aforementioned pattern, using a wet etching process to etch away the capacitor electrode film on the sidewall of the insulating layer 41, so that the capacitor electrode films on the inner walls of adjacent first grooves are disconnected from each other; the etching barrier layer 61 can prevent the etching solution from etching the capacitor electrode film at the location of the first electrode and on the sidewall of the hole corresponding to the first electrode, so that the remaining capacitor electrode film forms the first capacitor electrode 71, as shown below. Figure 9a and Figure 9b As shown.

[0146] Step 106: Expose the inner surface of the first capacitor electrode.

[0147] Exposing the first capacitor electrode includes: on the substrate on which the aforementioned pattern is formed, using a wet etching process, etching away the etching barrier layer along a direction parallel to the substrate, thereby exposing the inner surface of the first capacitor electrode 71, such as... Figure 10a and Figure 10b As shown.

[0148] Step 107: Expose the outer surface of the first capacitor electrode.

[0149] Exposing the outer surface of the first capacitor electrode includes: on a substrate forming the aforementioned pattern, using a wet etching process, etching away a portion of the insulating layer 41 along a direction parallel to the substrate, thereby exposing at least a portion of the outer surface of the first capacitor electrode 71, such as... Figure 11a and Figure 11b As shown.

[0150] In some embodiments, a portion of the insulating layer 41 is etched away along the first direction D1, wherein the distance at which the insulating layer 41 is etched is less than the length of the first capacitor electrode in the first direction D1.

[0151] Step 108: Form the capacitor dielectric layer and the second capacitor electrode.

[0152] The formation of the capacitor dielectric layer and the second capacitor electrode includes: based on the substrate with the aforementioned pattern, using an atomic deposition process, sequentially forming a capacitor dielectric layer 73 and a second capacitor electrode 72 on the exposed inner and outer surfaces of the first capacitor electrode 71; subsequently, using a chemical deposition process, forming a conductive filling layer 74 that fills the pores K, and polishing the conductive filling layer 74, as shown below. Figure 2a , Figure 2b and Figure 2c As shown.

[0153] In some embodiments, the capacitor dielectric layer 73 may be made of a high-k dielectric material, i.e., a dielectric material with a dielectric constant K ≥ 3.9. The high-k dielectric material may include, but is not limited to, at least one of the following: silicon oxide, aluminum oxide (Al2O3), and hafnium oxide.

[0154] In some embodiments, the second capacitor electrode 72 may be made of titanium nitride.

[0155] In some embodiments, the conductive filling layer 74 may be made of germanium-doped polycrystalline silicon.

[0156] Step 109: Form the channel, gate insulating layer, and gate.

[0157] Forming the channel, gate insulating layer, and gate includes: on the substrate with the aforementioned pattern formed, removing the sacrificial layer, and sequentially forming the channel, gate insulating layer, and gate on the inner wall of the via.

[0158] The solution provided in this embodiment simplifies the process flow, is easy to implement, and improves production efficiency. It has the advantages of easy process implementation, low production cost, and high yield.

[0159] This disclosure also provides a method for manufacturing a semiconductor device, comprising:

[0160] A stacked structure comprising a first electrode and an insulating layer alternately arranged in sequence is formed on a substrate, wherein an isolation layer is disposed on the surface of the first electrode;

[0161] An etching process is used to form holes perpendicular to the substrate in the stacked structure, the holes exposing the sidewalls of the isolation layer and the sidewalls of the insulating layer;

[0162] An etching process is used to etch away a portion of the isolation layer along a direction parallel to the substrate, thereby exposing the first electrode;

[0163] A first capacitor electrode, a capacitor dielectric layer, and a second capacitor electrode are sequentially formed on the exposed first electrode and the sidewall of the hole to form a capacitor. The first electrode and the capacitor are arranged along a first direction parallel to the substrate, such that the first capacitor electrode and the first electrode are connected to each other and overlap in the first direction.

[0164] In some embodiments, the size of the hole portion at the location of the insulating layer in the first direction is smaller than the size of the hole portion at the location of the first electrode in the first direction.

[0165] In some embodiments, forming a first capacitor electrode, a capacitor dielectric layer, and a second capacitor electrode sequentially on the exposed first electrode and the sidewall of the hole includes:

[0166] A capacitor electrode film and a barrier film are sequentially formed on the exposed first electrode and the sidewall of the hole;

[0167] An etching process is used to etch away the barrier film at the location of the insulating layer, exposing the capacitor electrode film on the sidewall of the insulating layer, while retaining the barrier film at the location of the first electrode, thus forming an etch barrier layer;

[0168] An etching process is used to etch away the capacitor electrode film on the sidewall of the insulating layer, while retaining the capacitor electrode film at the first electrode location to form the first capacitor electrode.

[0169] The etching barrier layer is removed by etching along a direction parallel to the substrate, exposing the inner surface of the first capacitor electrode.

[0170] Along a direction parallel to the substrate, a portion of the insulating layer is etched away, exposing at least a portion of the outer surface of the first capacitor electrode;

[0171] A capacitor dielectric layer and a second capacitor electrode are sequentially formed on the inner surface and the outer surface of the exposed first capacitor electrode.

[0172] In some embodiments, etching away a portion of the insulating layer along a direction parallel to the substrate includes: etching away a portion of the insulating layer along the first direction, wherein the distance by which the insulating layer is etched is less than the length of the first capacitor electrode in the first direction.

[0173] The method for manufacturing a semiconductor device according to embodiments of this disclosure exposes the first electrode by etching away a portion of the isolation layer exposed by the hole along a direction parallel to the substrate. Subsequently, a first capacitor electrode is formed on the exposed first electrode, such that at least a portion of the first capacitor electrode is disposed on the exposed first electrode, thereby improving the stability of the connection between the first capacitor electrode and the first electrode and preventing the first capacitor electrode from collapsing.

[0174] The semiconductor device manufacturing method of this disclosure, by having a smaller size in the first direction of the hole portion at the location of the insulating layer than the size in the first direction of the hole portion at the location of the first electrode, can retain a portion of the barrier film at the location of the first electrode during subsequent etching to remove the barrier film at the location of the insulating layer, thereby forming an etching barrier layer.

[0175] The semiconductor device manufacturing method of this disclosure uses an etching barrier layer to prevent the etching solution from etching the first electrode and the capacitor electrode film at the first electrode location when etching away the capacitor electrode film at the location of the insulating layer, thereby retaining the first electrode and the capacitor electrode film at the first electrode location to form a first capacitor electrode.

[0176] The semiconductor device manufacturing method of this disclosure removes the etch barrier layer and part of the insulating layer by etching, exposing the inner and outer surfaces of the first capacitor electrode, so that the second capacitor electrode can be disposed opposite to the exposed inner and outer surfaces of the first capacitor electrode, thereby increasing the relative area between the second capacitor electrode and the first capacitor electrode and improving the capacitance.

[0177] This disclosure also provides an electronic device, including the semiconductor device described in any of the foregoing embodiments. The electronic device may be a storage device, smartphone, computer, tablet computer, artificial intelligence device, wearable device, or power bank, etc. The storage device may include memory in a computer, etc., and is not limited thereto.

[0178] While the embodiments disclosed in this invention are as described above, the content is merely for the purpose of facilitating understanding of the invention and is not intended to limit the invention. Any person skilled in the art to which this invention pertains may make any modifications and changes to the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this invention shall still be determined by the scope defined in the appended claims.

Claims

1. A semiconductor device, characterized by, The application relates to a memory cell, comprising: a substrate, a plurality of memory cells arranged on the substrate, the memory cell comprising a transistor and a capacitor arranged along a first direction parallel to the substrate; the transistor comprising a channel, a gate insulating layer, a gate, a first electrode and a second electrode, the gate insulating layer being arranged between the gate and the channel, the first electrode and the second electrode being connected with the channel respectively; the capacitor comprising a first capacitor electrode, a capacitor dielectric layer and a second capacitor electrode, the capacitor dielectric layer being arranged at least between the first capacitor electrode and the second capacitor electrode; the first capacitor electrode being connected with the first electrode; the first capacitor electrode and the first electrode being connected with each other and having an overlap in the first direction; the first capacitor electrode comprising a main body portion and a clamping portion, the clamping portion being arranged on one side of the main body portion close to the first electrode, the clamping portion being provided with a clamping groove, the opening of the clamping groove being arranged towards the first electrode, at least part of the first electrode being arranged in the clamping groove, the clamping portion and the first electrode having an overlap in the first direction; the clamping portion comprising two clamping walls parallel to the substrate and arranged on opposite sides of at least part of the first electrode in a direction perpendicular to the substrate; the main body portion and the clamping portion being integrally formed and comprising the same conductive material; the main body portion and the clamping portion comprising titanium nitride; the main body portion being in a U-shaped cross section in a direction perpendicular to the substrate, the main body portion comprising a top wall, a bottom wall and a side wall connecting the top wall and the bottom wall, the top wall and the bottom wall being arranged oppositely and parallel to the substrate, the side wall being perpendicular to the substrate, the side wall being connected with the clamping portion and forming the clamping groove with the clamping portion; further comprising an insulating layer arranged on at least one side of the first capacitor electrode in a direction perpendicular to the substrate, the insulating layer overlapping with the orthographic projection of the clamping portion on the substrate; the insulating layer overlapping with the orthographic projection of at least part of the main body portion on the substrate; the first capacitor electrode being in an H-shaped cross section in a direction perpendicular to the substrate; the first electrode being provided with an isolation layer on a first surface thereof, part of the first surface close to the first capacitor electrode being free of the isolation layer, at least part of the first capacitor electrode being arranged on the part of the first surface; the isolation layer being in contact with the first electrode and the first capacitor electrode; the isolation layer being different from the material of the first capacitor electrode; further comprising a hole perpendicular to the substrate, part of the first electrode being arranged in the hole, the first capacitor electrode, the capacitor dielectric layer and the second capacitor electrode being arranged in sequence on the surface of the first electrode in the hole and on the side wall of the hole; the first capacitor electrode, the capacitor dielectric layer and the second capacitor electrode all being thin films, the capacitor further comprising a conductive filling layer, the conductive filling layer filling the hole and being connected with the second capacitor electrode. ​ ​ ​ ​ ​ 2. The semiconductor device according to claim 1, wherein ​ 3. The semiconductor device of claim 1, wherein ​ 4. The semiconductor device according to claim 3, wherein ​ 5. The semiconductor device of claim 1, wherein ​ 6. The semiconductor device of claim 1, wherein ​ 7. The semiconductor device of claim 6, wherein, ​ 8. The semiconductor device according to any one of claims 1 to 7, wherein ​ 9. The semiconductor device according to any one of claims 1 to 7, wherein ​ 10. The semiconductor device of claim 9, wherein, ​ 11. The semiconductor device of claim 9, wherein ​ 12. The semiconductor device according to any one of claims 1 to 7, wherein ​ 13. The semiconductor device of claim 12, wherein, ​ 14. The semiconductor device according to any one of claims 1 to 7, wherein Further comprising a bit line parallel to the substrate, the bit line connected to the second electrode.

15. The semiconductor device according to any one of Claims 1 to 7, wherein Further comprising a word line perpendicular to the substrate, the word line connected to the gate.

16. A method of manufacturing a semiconductor device, characterized by Comprising: forming a stack structure comprising first electrodes and insulating layers arranged alternately on a substrate, the first electrodes provided with isolation layers on surfaces thereof; forming a hole perpendicular to the substrate in the stack structure by an etching process, the hole exposing sidewalls of the isolation layers and sidewalls of the insulating layers; exposing the first electrodes by etching and removing part of the isolation layers along a direction parallel to the substrate by an etching process; forming a first capacitor electrode, a capacitor dielectric layer and a second capacitor electrode on the exposed first electrodes and sidewalls of the hole in sequence to form a capacitor, the first electrodes and the capacitor arranged along a first direction parallel to the substrate, the first capacitor electrode and the first electrodes connected to each other and having an overlap in the first direction; the first capacitor electrode comprising a main body portion and a clamping portion connected to each other, the clamping portion arranged on a side of the main body portion close to the first electrodes, the clamping portion provided with a clamping groove, an opening of the clamping groove facing the first electrodes, at least part of the first electrodes arranged in the clamping groove, the clamping portion having an overlap with the first electrodes in the first direction.

17. The method of manufacturing a semiconductor device according to Claim 16, wherein a size of the hole at a position of the insulating layers in the first direction is smaller than a size of the hole at a position of the first electrodes in the first direction.

18. The method of manufacturing a semiconductor device according to Claim 17, wherein forming a first capacitor electrode, a capacitor dielectric layer and a second capacitor electrode on the exposed first electrodes and sidewalls of the hole in sequence comprises: forming a capacitor electrode film and a barrier film on the exposed first electrodes and sidewalls of the hole in sequence; removing the barrier film at the position of the insulating layers by an etching process to expose the capacitor electrode film on the sidewalls of the insulating layers, the barrier film at the position of the first electrodes being reserved to form an etching barrier layer; removing the capacitor electrode film on the sidewalls of the insulating layers by an etching process to reserve the capacitor electrode film at the position of the first electrodes to form a first capacitor electrode; exposing an inner surface of the first capacitor electrode by etching and removing the etching barrier layer along a direction parallel to the substrate; exposing an outer surface of the first capacitor electrode by etching and removing part of the insulating layers along a direction parallel to the substrate; forming a capacitor dielectric layer and a second capacitor electrode on the exposed inner surface of the first capacitor electrode and the exposed outer surface of the first capacitor electrode in sequence.

19. The method of manufacturing a semiconductor device according to Claim 18, wherein the etching and removing part of the insulating layers along a direction parallel to the substrate comprises: etching and removing part of the insulating layers along the first direction, a distance of the insulating layers etched being smaller than a length of the first capacitor electrode in the first direction.

20. An electronic device, comprising: comprising the semiconductor device according to any one of claims 1 to 19.

Images