Merging schemes in semiconductor devices

Abstract

The present disclosure relates to methods, devices, systems, and techniques for a merge scheme in a semiconductor device, such as a three-dimensional (3D) semiconductor device. In one aspect, a semiconductor device includes a semiconductor structure including a stack of conductive layers and insulating layers alternating with each other in a first direction. The semiconductor structure includes an array region and a connection region adjacent to the array region in a second direction perpendicular to the first direction. The semiconductor device also includes a plurality of contact structures extending in a first direction through the connection region. Each conductive layer in the stack of conductive layers and insulating layers is coupled to a corresponding contact structure of the plurality of contact structures and isolated from one or more other contact structures of the plurality of contact structures. Each of the plurality of contact structures includes a body and a head extending beyond the body.

Description

Technical Field

[0001] The present disclosure relates to semiconductor devices and manufacturing processes for semiconductor devices. Background Art

[0002] Semiconductor devices (e.g., memory devices) may have various structures to increase the density of memory cells and lines on a chip. For example, three-dimensional (3D) memory devices are attractive because they can increase array density by stacking more layers within a similar footprint. A 3D memory device typically includes a memory array of memory cells and peripheral circuits for facilitating the operation of the memory array. Summary of the invention

[0003] The present disclosure describes methods, devices, systems, and techniques for merging schemes in semiconductor devices (eg, 3D memory devices).

[0004] One aspect of the present disclosure is characterized by a semiconductor device including a semiconductor structure. The semiconductor structure includes a stack of conductive layers and insulating layers that alternate with each other along a first direction. The semiconductor structure may include an array region and a connection region adjacent to the array region in a second direction perpendicular to the first direction. The semiconductor device also includes a plurality of contact structures extending through the connection region along the first direction. Each conductive layer in the stack of conductive layers and insulating layers is coupled to a corresponding contact structure in the plurality of contact structures and isolated from one or more other contact structures in the plurality of contact structures. Each contact structure in the plurality of contact structures includes a body and a head extending beyond the body. An end of the head contacts an end of the body. The end of the body is wider than an end of the head.

[0005] In some embodiments, the shape of the head is similar to a frustum of a cone, and the diameter of the head gradually decreases from the surface of the head to the end of the head along the first direction.

[0006] In some embodiments, the body includes an outer layer, an inner layer, and an intermediate layer between the outer layer and the inner layer. The head includes an outer layer, an inner layer, and an intermediate layer between the outer layer and the inner layer. The outer layer of the body, the intermediate layer of the body, and the inner layer of the body are respectively continuously connected to the outer layer of the head, the intermediate layer of the head, and the inner layer of the head.

[0007] In some embodiments, the outer layer of the body includes a high-k dielectric material, the middle layer of the body includes a titanium nitride material, the inner layer of the body includes a conductive material, the outer layer of the head includes a high-k dielectric material, the middle layer of the head includes a titanium nitride material, and the inner layer of the head includes a conductive material.

[0008] In some embodiments, the outer layer of the head, the middle layer of the head, and the inner layer of the head are filled in the end portion, and the body includes a hollow area surrounded by the inner layer of the body.

[0009] In some embodiments, the contact structure extends through a set of conductive layers of a stack of conductive layers and insulating layers. The contact structure contacts one of the set of conductive layers, the one conductive layer being closest to the head of the contact structure among the set of conductive layers. A contact spacer comprising a dielectric material is located between the contact structure and one or more other conductive layers in the set of conductive layers that are isolated from the contact structure.

[0010] In some embodiments, the protective layer includes a first portion extending along a first direction and covering a group of conductive layers and one side of one or more insulating layers between the group of conductive layers. The protective layer also includes a second portion extending along a second direction parallel to and in contact with one conductive layer.

[0011] In some embodiments, the body of the contact structure is connected to the one conductive layer via a connecting portion. The connecting portion includes the same material as the body of the contact structure and the one conductive layer. The connecting portion contacts the one conductive layer, the second portion of the protective layer, and a contact spacer located between the body of the contact structure and the one conductive layer.

[0012] In some embodiments, the semiconductor structure includes one or more decks stacked together in sequence along a first direction. The body of the contact structure includes one or more sections connected together in sequence along the first direction. Each of the one or more sections is shaped like a truncated cone and corresponds to a corresponding deck in the one or more decks of the semiconductor structure.

[0013] In some embodiments, each of the one or more sections of the body has a diameter that gradually decreases along the first direction.

[0014] In some embodiments, the semiconductor device further includes a gate line gap and a channel structure, both of which extend through the semiconductor structure along the first direction.

[0015] In some embodiments, the channel structure includes a first channel structure in the array region and a second channel structure in the connection region.

[0016] In some embodiments, the end of the contact structure is a first end. The contact structure includes a second end opposite to the first end along a first direction. The contact structure is coupled from the semiconductor structure to an external conductive contact at the first end or the second end.

[0017] Another aspect of the present disclosure is characterized by a method comprising providing a semiconductor structure comprising sacrificial layers and insulating layers alternating with each other along a first direction. The semiconductor structure comprises one or more stacks stacked in sequence in the first direction. Each stack in the one or more stacks comprises a subset of sacrificial layers and insulating layers. The semiconductor structure comprises an array region and a connection region adjacent to the array region in a second direction perpendicular to the first direction. The method further comprises: a) forming a first gate line hole in the array region, b) forming a second gate line hole and a contact hole in the connection region, c) forming a first channel hole in the array region, and d) forming a second channel hole in the connection region. The first gate line hole, the second gate line hole, the contact hole, the first channel hole, and the second channel hole extend through the semiconductor structure along the first direction. The first gate line hole, the second gate line hole, the contact hole, the first channel hole, and the second channel hole in each stack of the one or more stacks are formed during the same etching process.

[0018] In some embodiments, the first gate line hole, the second gate line hole, the first channel hole, the second channel hole, and the contact hole are formed using a single etching mask.

[0019] In some embodiments, each of the sacrificial layers includes silicon nitride, and each of the insulating layers includes silicon oxide.

[0020] In some embodiments, each of the first gate line hole and the second gate line hole has a circular or elliptical cross-section.

[0021] In some embodiments, the contact hole in each of the one or more stacks includes a frustum that tapers along a first direction.

[0022] In some embodiments, the connection region includes an isolation structure, and the protection layer is formed between the isolation structure and the sacrificial layer.

[0023] In some embodiments, the isolation structure has a stepped shape.

[0024] In some embodiments, the isolation structure includes silicon oxide, and the protection layer includes a nitrogen-doped carbide (NDC) material.

[0025] In some embodiments, the method further includes filling the first channel hole, the second channel hole, the first gate line hole, the second gate line hole, and the contact hole with a polysilicon material.

[0026] In some embodiments, the method further includes forming a channel structure in the first channel hole and the second channel hole.

[0027] In some embodiments, the method further includes etching and recessing the sacrificial layer exposed by the contact hole using a first etchant, wherein the first etchant etches the sacrificial layer faster than the protective layer. The method further includes forming a contact spacer layer in each contact hole. The contact spacer layer contacts the recessed sacrificial layer. The method further includes etching and recessing the protective layer exposed by each contact hole using a second etchant, wherein the second etchant etches the protective layer faster than the contact spacer layer in each contact hole.

[0028] In some embodiments, the contact spacer layer includes silicon oxide.

[0029] In some embodiments, the method further includes filling the contact hole with a sacrificial material.The method further includes polishing a top surface of the semiconductor structure and depositing an isolation layer on the top surface of the semiconductor structure.

[0030] In some embodiments, the depth of the isolation layer is about 100 nanometers (nm).

[0031] In some embodiments, the method further includes forming a gate line opening in the isolation layer for each of the first gate line hole and the second gate line hole to expose the first gate line hole and the second gate line hole. The method further includes removing polysilicon material in the first gate line hole and the second gate line hole. The method further includes enlarging the first gate line hole and the second gate line hole to form a plurality of gate line grooves extending in the second direction. Each of the plurality of gate line grooves includes a series of enlarged gate line holes connected to each other along the second direction.

[0032] In some embodiments, the method further includes oxidizing a bottom surface of each gate line trench in the plurality of gate line trenches. The bottom surface is in the substrate of the semiconductor structure.

[0033] In some embodiments, the method further includes forming a contact opening in the isolation layer for each of the contact holes. The width of the contact opening is less than the width of the contact hole. The method further includes removing the sacrificial material in the contact hole.

[0034] In some embodiments, the width of the contact opening is about 40 nm.

[0035] In some embodiments, the method further includes removing a sacrificial layer in the semiconductor structure.

[0036] In some embodiments, the method further includes depositing at least one conductive material into the multi-gate line trench and the contact hole to form a conductive layer between the insulating layer and the contact structure extending through the connection region of the semiconductor structure in the first direction. Each conductive layer in the conductive layer is connected to a corresponding contact structure in the contact structure and is isolated from one or more other contact structures in the contact structure. Each contact structure in the contact structure includes a main body and a head extending beyond the main body. The end of the head contacts the end of the main body. The end of the main body is wider than the end of the head.

[0037] In some embodiments, the conductive material includes tungsten.

[0038] In some embodiments, the method further includes etching the inner surface of each of the plurality of gate line grooves to expose and recess the conductive layer. The method further includes etching a portion of the end of each of the contact structures without creating an opening in each of the contact structures. The method further includes depositing a spacer layer. The spacer layer covers the inner surface of each of the plurality of gate line grooves to isolate the conductive layers from each other. The spacer layer also covers the end of each of the contact structures.

[0039] Another aspect of the present disclosure is characterized by a method, which includes providing a semiconductor structure, the semiconductor structure including sacrificial layers and insulating layers alternating with each other along a first direction. The semiconductor structure has an array region and a connection region adjacent to the array region along a second direction perpendicular to the first direction. The semiconductor structure includes a gate line groove and a contact hole. The contact hole extends through the connection region of the semiconductor structure along the first direction. The connection region includes an isolation structure and a protective layer formed between the isolation structure and the sacrificial layer. The method also includes etching and recessing the sacrificial layer exposed by the contact hole using a first etching solution, the first etching solution having an etching rate faster than the etching rate of the sacrificial layer for the protective layer. The method also includes forming a contact spacer layer in each contact hole. The contact spacer layer contacts the recessed sacrificial layer. The method also includes etching and recessing the protective layer exposed by each contact hole using a second etching solution, the second etching solution having an etching rate faster than the etching rate of the contact spacer layer for the protective layer in each contact hole.

[0040] In some embodiments, the method further includes forming a contact opening for each contact hole. The width of the contact opening is less than the width of the contact hole. The method further includes removing a sacrificial layer in the semiconductor structure. The method further includes depositing at least one conductive material into the gate line trench and the contact hole in a conformal deposition process to form a conductive layer and a contact structure.

[0041] In some embodiments, each of the contact structures includes a first end and a second end opposite the first end along a first direction. The method also includes coupling the contact structure from the semiconductor structure to an external conductive contact at the first end or the second end.

[0042] Embodiments of the present disclosure may provide one or more of the following technical advantages and / or benefits. For example, gate line holes, contact holes, and channel holes in a stack of semiconductor structures may be formed during the same etching process using the same mask. Therefore, the technology enables to reduce manufacturing costs (e.g., using fewer etching steps and masks) and manufacturing difficulty, especially when the semiconductor structure includes a plurality of stacks. In addition, the contact structure of the semiconductor structure may be coupled to an external component at the front, back, or both of the semiconductor structure. Therefore, a peripheral circuit (e.g., a complementary metal oxide semiconductor (CMOS) control circuit of a memory array) may be folded and located at both sides of the semiconductor structure, which reduces the size of the peripheral circuit (e.g., in a lateral surface) and makes the circuit design more flexible. The technology also provides a method for forming a narrow opening on the top of each contact hole of a semiconductor structure. Due to the size of these openings, the conductive layer and the contact structure of the semiconductor structure may be formed in the same deposition process, which may further reduce manufacturing costs. Specifically, a header structure formed in each narrow opening may prevent the contact structure from being recessed during the etching process (e.g., for separating the conductive layers from each other).

[0043] The technology can be applied to various types of semiconductor devices, volatile memory devices (e.g., DRAM memory devices), or non-volatile memory (NVM) devices, such as NAND flash memory, NOR flash memory, resistive random access memory (RRAM), phase change memory (PCM) (e.g., phase change random access memory (PCRAM)), spin transfer torque (STT)-magnetoresistive random access memory (MRAM), etc. The technology can also be applied to charge trapping-based memory devices, such as silicon-oxide-nitride-oxide-silicon (SONOS) memory devices and floating gate-based memory devices. The technology can be applied to three-dimensional (3D) memory devices. The technology can be applied to various memory types, such as SLC (single-level cell) devices, MLC (multi-level cell) devices such as 2-level cell devices, TLC (three-level cell) devices, QLC (quadruple-level cell) devices, or PLC (five-level cell) devices. In addition or alternatively, the technology can be applied to various types of devices and systems, such as secure digital (SD) cards, embedded multimedia cards (eMMC), or solid-state drives (SSDs), embedded systems, etc.

[0044] The details of one or more implementations of the subject matter of the present disclosure are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the subject matter will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] The accompanying drawings, which are incorporated herein and form a part of the present disclosure, illustrate various aspects of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and to enable one of ordinary skill in the relevant art to make and use the present disclosure.

[0046] Figure 1A A top view of an example semiconductor device according to some aspects of the present disclosure is shown.

[0047] Figure 1B Some aspects of the present disclosure are shown Figure 1A A cross-sectional view of a semiconductor device.

[0048] Figure 2 Some aspects of the present disclosure are shown Figure 1B An enlarged schematic diagram of an example structure in a semiconductor device.

[0049] Figure 3 Some aspects of the present disclosure are shown Figure 1B An enlarged schematic diagram of another example structure in a semiconductor device.

[0050] Figure 4A-4W Cross-sectional views of example semiconductor structures at various stages of a fabrication process are shown in accordance with aspects of the present disclosure.

[0051] Figure 5A-Figure 5B A flow chart illustrating an example process of forming a semiconductor device according to some aspects of the present disclosure is shown.

[0052] Figure 6 A block diagram of an example system having one or more semiconductor devices according to some aspects of the present disclosure is shown.

[0053] Like reference numbers and designations in the various drawings indicate like elements.It should also be understood that the various exemplary embodiments shown in the drawings are merely illustrative representations and are not necessarily drawn to scale. DETAILED DESCRIPTION

[0054] Figure 1A-1B An example semiconductor device 100 according to some aspects of the present disclosure is shown. The semiconductor device 100 may be used to form a memory device, such as a 3D NAND memory device.

[0055] It should be noted that Figure 1A-1BThe X, Y, and Z axes (also referred to as the X, Y, and Z directions) are included to further illustrate the spatial relationships of various components in the semiconductor device. The substrate of the semiconductor device includes two lateral surfaces extending laterally in the XY plane: a top surface on the front side of the wafer, on which components of the semiconductor device can be formed; and a bottom surface on the back side opposite to the front side of the wafer. The Z direction is perpendicular to the X and Y directions. As used herein, when the substrate is positioned in the lowest plane of the semiconductor device in the Z direction (a vertical direction perpendicular to the XY plane, for example, the thickness direction of the substrate), a component (e.g., a layer or device) is determined in the Z direction relative to the substrate of the semiconductor device to be "on", "above", or "below" another component (e.g., a layer or device) of the semiconductor device. The same concepts used to describe spatial relationships are applied throughout this disclosure.

[0056] Figure 1A A top view of a semiconductor device 100 according to some aspects of the present disclosure is shown. The semiconductor device 100 includes an array region 102 and a connection region 104. The connection region 104 (which may also be referred to as a step region) is adjacent to the array region 102 in a horizontal direction (e.g., the Y direction). The array region 102 includes an array of channel structures 106. Each channel structure 106 can be used to form a string of memory cells coupled in series along a vertical direction (e.g., the Z direction) perpendicular to the XY plane. The connection region 104 includes a channel structure 108 and a contact structure 110. The channel structure 108 in the connection region 104 may also be referred to as a dummy channel structure. The semiconductor device 100 includes a gate line gap 112 extending through both the array region 102 and the connection region 104 along the Y direction. In some embodiments, the gate line gap in the connection region 104 has a larger width (in the X direction) than the gate line gap in the array region 102. In some embodiments, the gate line gaps in the connection region 104 have the same width as the gate line gaps in the array region 102. In some embodiments, the gate line gaps in the connection region 104 have a smaller width than the gate line gaps in the array region 102. Figure 1A Also shown is the method for generating Figure 1B Cutting lines AA' and BB' in the cross-sectional view.

[0057] Figure 1B 1 shows a cross-sectional view of a semiconductor device 100 according to some aspects of the present disclosure (a cross-sectional view of the array region 102 along line AA' and a cross-sectional view of the connection region 104 along line BB'). Figure 1BAs shown in , the semiconductor device 100 includes a substrate 114 and a stack 115 of a conductive layer 116 and an insulating layer 118 disposed on the substrate 114. The substrate 114 can be any suitable semiconductor substrate having any suitable semiconductor material (such as a single crystal, a polycrystalline, or a single crystalline semiconductor). For example, the substrate 114 can include silicon, silicon germanium (SiGe), germanium (Ge), gallium arsenide (GaAs), silicon on insulator (SOI), germanium on insulator (GOI), gallium nitride, silicon carbide, III-V compounds, or any combination thereof.

[0058] The stack 115 may extend parallel to the top surface of the substrate 114 in the XY plane. The conductive layer 116 and the insulating layer 118 may alternate in a vertical direction (e.g., Z direction) perpendicular to the XY plane. The conductive layer 116 and the insulating layer 118 may extend from the array region 102 into the connection region 104 and be arranged in a stepped structure in the connection region 104. The thickness of the conductive layer 116 may be the same or different from each other, for example, ranging from 10-500 nanometers (nm), such as about 35nm. The thickness of the insulating layer 118 may also be the same or different from each other, for example, ranging from 10-500nm, such as about 25nm. The conductive layer 116 may include any suitable conductive material, such as tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), titanium nitride (TiN), polycrystalline silicon (polysilicon), doped silicon, silicide, or any combination thereof. The insulating layer 118 may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In some embodiments, the insulating layer 118 may also include a high-k dielectric material such as hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, lanthanum oxide, or any combination thereof. Figure 1B The number of conductive layers 116 and insulating layers 118 shown in FIG. 1 is for illustration only, and any suitable number of conductive layers and insulating layers may be included in semiconductor device 100 .

[0059] The semiconductor device 100 further includes a spacer layer 120 disposed on the stack 115. The spacer layer 120 extends in the XY plane parallel to the substrate 114 and the stack 115 consisting of the conductive layer 116 and the insulating layer 118. The spacer layer 120 may include a dielectric material (e.g., silicon oxide). In some embodiments, the thickness of the spacer layer 120 may be about 100 nm.

[0060] like Figure 1BAs shown, each contact structure 110 has a head 122 and a body 124. The contact structure 110 may extend through the connection region 104 in a vertical direction (e.g., the Z direction). Specifically, the head 122 of the contact structure 110 may extend through the spacer layer 120, and the bottom end of the body 124 may extend through the substrate 114. Due to the stair-like structure formed by the stack 115 in the connection region 104, the body 124 may extend through a portion of the stack 115, including at the step of the stair-like structure (e.g., as shown in FIG. Figure 1B In the step 126 shown in .

[0061] The stepped structure formed by the conductive layer 116 and the insulating layer 118 allows the contact structure 110 to connect the conductive layer 116 to an external component. Each conductive layer 116 can be coupled to a corresponding contact structure and can be isolated from one or more other contact structures. In some embodiments, each contact structure 110 can be coupled to a corresponding conductive layer. The contact structure 110 can extend through a group of conductive layers of the stack 115. The contact structure 110 can contact a conductive layer in the group of conductive layers that is closest to the head 122 of the contact structure 110. For example, Figure 1B As shown, each contact structure 110 can extend through a conductive layer in a ladder rung (e.g., rung 126) and can be coupled to a topmost conductive layer in the ladder rung. One or more contact spacers (e.g., contact spacer 128) can be located between the contact structure 110 and one or more other conductive layers in the set of conductive layers and can isolate the contact structure 110 from the conductive layers. Each contact spacer can include a dielectric material. In some other embodiments ( Figure 1B 1 ), each contact structure 110 may be coupled to a plurality of conductive layers 116. In some embodiments, the contact structure 110 may be coupled to a conductive contact on the top surface of the semiconductor device 100 through the header 122, or coupled to a conductive contact on the bottom surface of the semiconductor device 100 through the bottom end of the body 124, or coupled to a conductive contact on the top surface of the semiconductor device 100 through the header 122 and coupled to a conductive contact on the bottom surface of the semiconductor device 100 through the bottom end of the body 124.

[0062] The connection region 104 further includes an isolation structure 130 and a protection layer 132 formed between the isolation structure 130 and the stack 115. The protection layer 132 may cover the top surface and side surfaces of the stepped shape formed by the stack 115 in the connection region 104. The isolation structure 130 may include a dielectric material such as silicon oxide. The protection layer 132 may include a nitrogen-doped carbide (NDC) material.

[0063] like Figure 1BAs shown in , the semiconductor device 100 includes three stacks 134, 136 and 138 stacked together vertically (i.e., along the Z direction) in sequence. Each stack includes a corresponding subset of the conductive layers and insulating layers of the stack 115. The body 124 of each contact structure 110 includes three segments, each of which is formed in a corresponding stack. The three segments of the body 124 are connected together in sequence along the vertical direction. Each segment of the body 124 can be shaped like a pillar or a truncated cone, and can have a diameter that gradually decreases from top to bottom in the vertical direction. At the intersection of two adjacent stacks, the top of the lower segment of the body 124 can have a larger diameter than the bottom of the upper segment of the body 124. For example, for each contact structure 110, the top of the segment of its body in the stack 138 is thicker than the bottom of another segment of its body in the stack 136. It should be noted that Figure 1B The three stacks shown in FIG. 1 are for illustration purposes only, and any suitable number (including one) of stacks may be included in the semiconductor device 100 .

[0064] The channel structure 106 and the dummy channel structure 108 extend through the stack 115 in a vertical direction (e.g., Z direction). Each channel structure 106 may have one or more sections. Each of the one or more sections is in a corresponding stack of the semiconductor device 100 and is shaped like a pillar or a truncated cone. The channel structure 106 may include a storage film and a semiconductor channel. In some examples, the storage film includes a blocking layer, a charge trapping layer, and a tunneling layer. In some examples, the material for the blocking layer may include silicon oxide, silicon nitride, silicon oxynitride, and a high-k dielectric material such as aluminum oxide or hafnium oxide; the material for the charge trapping layer may include polysilicon, silicon nitride, silicon oxynitride, and the like; and the material for the tunneling layer may include silicon oxide, silicon nitride, silicon oxynitride, a high-k dielectric material such as aluminum oxide or hafnium oxide, and the like. In an example, the materials of the blocking layer, the charge trapping layer, the tunneling layer, and the semiconductor channel may include silicon oxide, silicon nitride, silicon oxide, and polysilicon, respectively. Each dummy channel structure 108 may include a structure and material similar to the channel structure 106. In some embodiments, the dummy channel structures 108 may be used to support the stack 115 within the connection region 104.

[0065] Figure 1BA cross-sectional view of a gate line slit 112 along line AA' is shown. The gate line slit 112 extends through the stack 115 along the Z direction. The gate line slit 112 can divide the semiconductor device 100 into a plurality of blocks. Each gate line slit 112 can include a gate line groove filled with a groove filling material (e.g., polysilicon). The gate line groove can be formed in the following process. A series of gate line holes can be formed in the semiconductor device 100 along the Y direction. Each of the gate line holes extends through the semiconductor device along the Z direction. Each of the series of gate line holes can then be enlarged (e.g., by etching). Two adjacent gate line holes can be connected to each other after enlargement, which turns a series of gate line holes into gate line grooves.

[0066] Figure 2 Some aspects of the present disclosure are shown Figure 1B FIG. 1 is an enlarged schematic diagram of a structure 140 in a semiconductor device 100. The structure 140 shows a portion of a contact structure 200. The contact structure 200 may be Figure 1A-1B The contact structure 200 includes a head 202 and a body 204. The head 202 extends beyond the body 204 in a vertical direction (e.g., Z direction). The end of the head 202 contacts the end of the body 204. The end of the body 204 is wider than the end of the head 202 in a horizontal direction (e.g., Y direction). The head 202 can be shaped like a frustum. The diameter of the head 202 can gradually decrease from the surface of the head 202 (e.g., top surface 206) toward the body 204 in the vertical direction.

[0067] In some embodiments, Figure 2 As shown, the head 202 includes an outer layer 208, an inner layer 212, and an intermediate layer 210 between the outer layer 208 and the inner layer 212. The body 204 also includes an outer layer 214, an inner layer 218, and an intermediate layer 216 between the outer layer 214 and the inner layer 218. The outer layer 214 of the body 204, the intermediate layer 216 of the body 204, and the inner layer 218 of the body 204 are continuously connected to the outer layer 208 of the head 202, the intermediate layer 210 of the head 202, and the inner layer 212 of the head 202, respectively.

[0068] In some embodiments, each of the outer layer 214 of the body 204 and the outer layer 208 of the head 202 includes a high-k dielectric material. Each of the middle layer 216 of the body 204 and the middle layer 210 of the head 202 includes a titanium nitride material. Each of the inner layer 218 of the body 204 and the inner layer 212 of the head 202 includes a conductive material, such as tungsten (W).

[0069] In some embodiments, Figure 2As shown, the outer layer 208 of the head 202, the middle layer 210 of the head 202, and the inner layer 212 of the head 202 are filled in the end. The body 204 can include a hollow area 220 surrounded by the inner layer 218.

[0070] In some embodiments, Figure 2 As shown, the contact structure 200 can be coupled to the via 222 through the header 202. The via 222 can include a conductive material and can be in contact with the top surface 206 of the header 202.

[0071] Figure 3 Some aspects of the present disclosure are shown Figure 1B FIG. 1 is an enlarged schematic diagram of a structure 142 in a semiconductor device 100 of FIG. 1. The structure 142 shows an example connection of a contact structure 300, a conductive layer 302, and a protective layer 304. The contact structure 300 may be Figure 1B The conductive layer 302 may be an example of a contact structure 110. Figure 1B The protective layer 304 may be Figure 1B An example of a protective layer 132. Figure 3 As shown, the protective layer 304 includes at least a portion 308 and a portion 310. The portion 308 extends in a vertical direction and covers one side of a set of alternating conductive layers and insulating layers. The portion 310 extends in a horizontal direction and is parallel to and in contact with the conductive layer 302. The contact structure 300 is connected to the conductive layer 302 through a connecting portion 306. The connecting portion 306 extends in a horizontal direction. The connecting portion 306 contacts the portion 310 of the protective layer 304 in a horizontal direction and contacts the conductive layer 302 in a vertical direction. The connecting portion 306 may have substantially the same thickness as the portion 310 of the protective layer 304. The connecting portion 306 may include the same (one or more) materials as the contact structure 300 and the conductive layer 302. The contact spacer 312 is located between the conductive layer 302 and the contact structure 300 in a horizontal direction. The contact spacer 312 contacts the connecting portion 306 in a vertical direction. The contact spacer 312 may be Figure 1B An example of a contact spacer 128 is shown.

[0072] Figure 4A-4W 1 shows cross-sectional views of example semiconductor structures at various stages of a fabrication process according to some aspects of the present disclosure. Each of these semiconductor structures may be Figure 1A-1B The semiconductor device 100 or the structure of the semiconductor device 100 during an intermediate manufacturing process is similar or identical.

[0073] Figure 4A A semiconductor structure 400a is shown. Figure 4A As shown, the semiconductor structure 400a includes an array region 402 (along a similar Figure 1A AA') and the connection area 404 (in a cross-sectional view of a cutting line of the line Figure 1A In the cross-sectional view taken along the line BB' of FIG. 4 , the semiconductor structure 400a includes a substrate 406 and a stack 408 of alternating sacrificial layers 410 and insulating layers 412 disposed on the substrate 406. The substrate 406 may be Figure 1B The stack 408 may extend parallel to the top surface of the substrate 406 in the lateral direction. The sacrificial layers 410 and the insulating layers 412 may alternate in a vertical direction perpendicular to the lateral direction. The thicknesses of the sacrificial layers 410 may be the same or different from each other, for example, ranging from 10-500nm, for example, about 35nm. The thicknesses of the insulating layers 412 may also be the same or different from each other, for example, ranging from 10-500nm, for example, about 25nm. It should be noted that Figure 4A-4W The number of sacrificial layers 410 and insulating layers 412 shown in the figure is for illustration only, and any suitable number of sacrificial layers 410 and insulating layers 412 may be included in the stack 408. The sacrificial layer 410 may include silicon oxide, silicon nitride, polysilicon, or other suitable materials. The insulating layer 412 may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In some embodiments, the insulating layer 412 may also include a high-k dielectric material, such as hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, lanthanum oxide, or any combination thereof. The insulating layer 412 may be Figure 1B 4. In some embodiments, sacrificial layer 410 includes silicon nitride and insulating layer 412 includes silicon oxide.

[0074] like Figure 4A As shown, the stack 408 forms a stepped structure 414 in the connection region 404. The stepped structure 414 may include a plurality of steps 416. The sacrificial layer 410 and the insulating layer 412 of the stack 408 may be deposited one by one on the substrate 406. The steps 416 of the stepped structure 414 may be formed by removing portions of the sacrificial layer 410 and the insulating layer 412 during the etching process. The topmost layer in each step 416 is the sacrificial layer 410. The semiconductor structure 400a further includes a protective layer 418 in contact with the top surface and side surface of the stepped structure 414. The protective layer 418 is in contact with the topmost sacrificial layer 410 in each step 416. The protective layer 418 includes a nitrogen-doped carbide (NDC) material. The NDC material may be a top selective material in an etching process and may have a slower etching rate than other materials (such as silicon oxide and silicon nitride). The protection layer 418 may be formed by filling the NDC material in the gap on top of the stepped structure 414 and then removing any redundant portions.

[0075] Figure 4BThe semiconductor structure 400b is shown. The difference between the semiconductor structure 400b and the semiconductor structure 400a is that the semiconductor structure 400b includes an isolation structure 420 in contact with the protection layer 418. The isolation structure 420 may be Figure 1B 4. The isolation structure 420 may be formed by depositing a dielectric material such as silicon oxide on top of the protective layer 418. The top surface of the semiconductor structure 400b may be polished (e.g., using chemical mechanical planarization (CMP)). Any portion of the protective layer 418 that is not in contact with the stepped structure 414 may be removed.

[0076] Figure 4C A semiconductor structure 400c is shown. In order to better illustrate the different components of the semiconductor structure 400c, Figure 4C The diagrams are shown along the cutting lines CC', DD', EE', FF', GG' and HH' (eg Figure 1A The semiconductor structure 400c is different from the semiconductor structure 400b in that the semiconductor structure 400c includes a channel hole 422 in the array region 402, a gate line hole 424 in both the array region 402 and the connection region 404, a channel hole 426 in the connection region 404, and a contact hole 428 in the connection region 404. Figure 4C As shown, channel holes 422 and 426, gate line hole 424, and contact hole 428 can extend through stack 408 into substrate 406 along the Z direction. Channel holes 422 and 426, gate line hole 424, and contact hole 428 can be formed by using an etch mask ( Figure 4C The mask may have a pattern designed for these holes. In some embodiments, the semiconductor structure 400c has only one stack, and the channel holes 422 and 426, the gate line hole 424, and the contact hole 428 may be formed during one etching process using a mask. In some embodiments, the semiconductor structure 400c has a plurality of stacks (e.g., Figure 4C In this case, the stacks can be formed one by one from the bottom to the top. For example, the stack 430 on the bottom can be formed as described above. Figure 4BThe stack 430 is formed first. Then, a mask may be used to form a first section of channel holes 422 and 426, gate line holes 424, and contact holes 428 in the stack 430 during a first etching process. Next, a stack 432 is formed on top of the stack 430, and the same mask may be used to form a second section of channel holes 422 and 426, gate line holes 424, and contact holes 428 in the stack 432 during a second etching process. Finally, a stack 434 is formed on top of the stack 432, and the same mask may be used to form a third section of channel holes 422 and 426, gate line holes 424, and contact holes 428 in the stack 432 during a third etching process. It should be noted that Figure 4C The three stacks shown in FIG. are for illustration only, and any suitable number of stacks may be included in the semiconductor structure 400 c. In some embodiments, a plurality of stacks (e.g., stacks 430, 432, and 434) may be formed first, and then holes (e.g., channel holes 422 and 426, gate line holes 424, and contact holes 428) extending through the plurality of stacks may be formed in one etching process.

[0077] The gate line holes 424 can include a series or multiple series of gate line holes in both the array area 402 and the connection area 404. The gate line holes of each series are arranged in a line along the Y direction and are positioned adjacent to each other. The size and position of the gate line holes of each series are designed so that enlarging these gate line holes can connect them and turn them into gate line grooves extending along the Y direction. The opening and cross section of the gate line holes 424 can have any suitable shape (e.g., circular or elliptical).

[0078] In some embodiments, Figure 4C As shown, a protection structure 436 may be formed on the bottoms of the channel holes 422 and 426, the gate line hole 424, and the contact hole 428 (which are in contact with the substrate 406) to protect the substrate 406. For example, the protection structure 436 may be formed using polysilicon oxidation.

[0079] Figure 4D A semiconductor structure 400d is shown. The difference between the semiconductor structure 400d and the semiconductor structure 400c is that the channel holes 422 and 426, the gate line hole 424, and the contact hole 428 of the semiconductor structure 400d are filled with a filling material 438 (eg, polysilicon).

[0080] Figure 4EA semiconductor structure 400e is shown. The difference between the semiconductor structure 400e and the semiconductor structure 400d is that a silicon oxide layer 440 may be deposited on top of the semiconductor structure 400e. An opening 442 may be formed in the silicon oxide layer 440 to expose the filling material 438 in the channel holes 422 and 426. The opening 442 may be formed by an etching process using a mask having a pattern matching the channel holes 422 and 426.

[0081] Figure 4F A semiconductor structure 400f is shown. The difference between the semiconductor structure 400f and the semiconductor structure 400e is that in the semiconductor structure 400f, the filling material 438 in the channel holes 422 and 426 has been removed (eg, etched away using acid).

[0082] Figure 4G The semiconductor structure 400g is shown. The difference between the semiconductor structure 400g and the semiconductor structure 400f is that the semiconductor structure 400g includes a channel structure 444 formed in the channel hole 422 and a channel structure 446 formed in the channel hole 426. The channel structure 444 may be Figure 1A-1B An example of the channel structure 106, and the channel structure 446 may be Figure 1A-1B 4. Example of a dummy channel structure 108. Each of the channel structures 444 and 446 can be in the shape of a cylinder or a pillar, and includes a high-k layer, a barrier layer surrounded by the high-k layer, a charge trapping layer (or storage layer) surrounded by the barrier layer, a tunneling layer surrounded by the charge trapping layer, a channel layer surrounded by the tunneling layer, and a core filling layer surrounded by the channel layer (not shown), which extends through the stack 408 of the sacrificial layer 410 and the insulating layer 412. In some embodiments, the channel layer can include silicon, such as amorphous silicon, polycrystalline silicon, or single crystal silicon, the tunneling layer can include silicon oxide, silicon nitride, or any combination thereof, the barrier layer can include silicon oxide, silicon nitride, a high-k dielectric, or any combination thereof, and the charge trapping layer can include silicon nitride, silicon oxynitride, silicon, or any combination thereof. In some embodiments, the tunneling layer, the charge trapping layer, and the barrier layer (collectively referred to as a storage film) can include an ONO dielectric (silicon oxide-silicon nitride-silicon oxide). Each of the channel structures 444 and 446 may be formed by subsequently depositing a high-k layer, a barrier layer, a charge trapping layer, a tunneling layer, a channel layer, and a core fill layer within the channel holes 422 and 426. In some embodiments, a plug 448 may be formed on top of each of the channel structures 444 and 446. In a later process, the plug 448 may be removed, and the channel structures 444 and 446 may be connected to external components through their tops.

[0083] Figure 4HA semiconductor structure 400h is shown. The difference between the semiconductor structure 400h and the semiconductor structure 400g is that the semiconductor structure 400h includes a silicon oxide layer 450 deposited on top.

[0084] Fig. 4I The semiconductor structure 400i is shown. The difference between the semiconductor structure 400i and the semiconductor structure 400h is that the portion of the silicon oxide layer 450 on the top of the isolation structure 420 and in contact with the isolation structure 420 in the semiconductor structure 400i can be removed, so that the opening of the contact hole 428 in the semiconductor structure 400i and the filling material 438 in the contact hole 428 are exposed.

[0085] Figure 4J A semiconductor structure 400j is shown. The difference between the semiconductor structure 400j and the semiconductor structure 400i is that the filling material 438 in the contact hole 428 of the semiconductor structure 400j is removed (eg, etched away using acid).

[0086] Figure 4K A semiconductor structure 400k is shown. The difference between the semiconductor structure 400k and the semiconductor structure 400j is that the semiconductor structure 400k includes one or more recesses 452 in each of the sacrificial layers 410 at locations where the sacrificial layers 410 are exposed by one or more of the contact holes 428. The recesses 452 may be formed by applying an etchant 458 (not shown) to the contact holes 428. The etchant 458 may have a faster etching rate for the sacrificial layer 410 than for the protective layer 418 and the insulating layer 412. In some embodiments, the size of the recesses 452 may be about 20-30 nm in the horizontal direction.

[0087] Figure 4L A semiconductor structure 4001 is shown. The difference between the semiconductor structure 4001 and the semiconductor structure 400k is that the semiconductor structure 4001 includes a contact spacer layer 454 each located in one of the contact holes 428. The contact spacer layer 454 contacts the sacrificial layer 410 and occupies the recess 452. The contact spacer layer 454 may include a dielectric material (e.g., silicon oxide).

[0088] Figure 4M The semiconductor structure 400m is shown. The difference between the semiconductor structure 400m and the semiconductor structure 400l is that the semiconductor structure 400m includes a groove 456 in the protective layer 418 at a position where the protective layer 418 is exposed by the contact hole 428. The groove 456 is deeper than the groove 452 in the horizontal direction. In this way, the sacrificial layer 410 in contact with the protective layer 418 in the vertical direction can be exposed through the groove 456. The groove 456 can be formed by applying an etchant 460 (not shown) into the contact hole 428. The etchant 460 can be used with respect to Figure 4K The depicted etchant 458 is different and may have a faster etch rate for the protection layer 418 than for the contact spacer layer 454 and the insulating layer 412 .

[0089] Figure 4N A semiconductor structure 400n is shown. The difference between the semiconductor structure 400n and the semiconductor structure 400m is that the contact hole 428 and the groove 456 of the semiconductor structure 400n are filled with a sacrificial material 462 (e.g., carbon). The top surface of the semiconductor structure 400n can be polished (e.g., using CMP) so that the remaining portion of the silicon oxide layer 450 can be removed.

[0090] Fig.4O A semiconductor structure 400o is shown. The difference between semiconductor structure 400o and semiconductor structure 400n is that semiconductor structure 400o includes an isolation layer 464 deposited on top. In some embodiments, the depth of isolation layer 464 may be about 100 nm. Isolation layer 464 may include a dielectric material (eg, silicon oxide).

[0091] Figure 4P A semiconductor structure 400 p is shown. The difference between the semiconductor structure 400 p and the semiconductor structure 400 o is that the isolation layer 464 of the semiconductor structure 400 p includes an opening 466 exposing the filling material 438 in the gate line hole 424 .

[0092] Figure 4Q The semiconductor structure 400q is shown. The difference between the semiconductor structure 400q and the semiconductor structure 400p is that the filling material 438 in the gate line hole 424 of the semiconductor structure 400q is removed. In addition, the gate line hole 424 of the semiconductor structure 400q is enlarged (for example, using acid etching and enlargement) so that the enlarged gate line hole 424 is connected along the Y direction. Therefore, one or more gate line grooves 468 extending along the Y direction can be formed ( Figure 4Q In some embodiments, removing the filling material 438 in the gate line hole 424 and enlarging the gate line hole 424 can expose the substrate 406 in contact with the bottom of the gate line hole 424 or the gate line trench 468. It should be noted that Figure 4Q For illustration purposes only, and Figure 4Q The width of the enlarged gate line hole 424 in FIG. 4 should be greater than the width shown in other figures before enlargement (e.g., Figure 4P ).

[0093] Figure 4RA semiconductor structure 400r is shown. The difference between the semiconductor structure 400r and the semiconductor structure 400q is that a protection structure 470 is formed on the bottom of the gate line trench 468 in the semiconductor structure 400r to protect the substrate 406. For example, polysilicon oxidation can be used to form the protection structure 470. The protection structure 470 can protect the substrate 406 from being etched away in a later process (for example, when the sacrificial layer 410 is etched away).

[0094] Figure 4S A semiconductor structure 400s is shown. The difference between the semiconductor structure 400s and the semiconductor structure 400r is that the isolation layer 464 of the semiconductor structure 400s includes a contact opening 472, which extends through the isolation layer 464 in the Z direction and exposes the sacrificial material 462 (e.g., carbon) in the contact hole 428. Each contact opening 472 is located on the top of the corresponding contact hole 428. The contact opening 472 can be shaped like a cylinder or a truncated cone. The contact opening 472 is narrower than the contact hole 428. Specifically, the bottom of the contact opening 472 is smaller than the opening at the top of the contact hole 428. The width of the contact opening 472 can be, for example, about 40-50nm.

[0095] Figure 4T A semiconductor structure 400t is shown. The difference between the semiconductor structure 400t and the semiconductor structure 400s is that the sacrificial material 462 in the contact hole 428 and the recess 456 of the semiconductor structure 400t is removed. In some embodiments, the sacrificial material 462 includes carbon and can be burned off.

[0096] Figure 4U The semiconductor structure 400u is shown. The difference between the semiconductor structure 400u and the semiconductor structure 400t is that the sacrificial layer 410 of the semiconductor structure 400u is removed. The sacrificial layer 410 can be removed by filling an etchant 474 (not shown) into the contact hole 428 and the gate line trench 468. The etchant 474 can have a faster etching rate for the sacrificial layer 410 than for the insulating layer 412, the protective layer 418, and the contact spacer layer 454.

[0097] Figure 4VA semiconductor structure 400v is shown. The difference between the semiconductor structure 400v and the semiconductor structure 400u is that the semiconductor structure 400v includes a conductive layer 476 and a contact structure 478. The conductive layer 476 and the contact structure 478 can be formed by filling at least one conductive material (e.g., tungsten) into the gate line trench 468 and the contact hole 428. In some embodiments, the conductive layer 476 and the contact structure 478 each include multiple layers (e.g., an outer layer including a high-k dielectric material, an intermediate layer including a titanium nitride material, and an inner layer including tungsten). Therefore, the conductive layer 476 and the contact structure 478 can be formed in multiple steps. For example, the first step includes depositing a high-k dielectric material to form an outer layer; the second step includes depositing a titanium nitride material to form an intermediate layer; and the third step includes depositing tungsten to form an inner layer. In some embodiments, at least one conductive material can be filled into the gate line trench 468 and the contact hole 428 during a conformal deposition process.

[0098] Due to the size difference between the contact holes 428 and the contact openings 472, each of the contact holes 428 may not be completely filled. Therefore, each of the contact structures 478 may have a hollow area inside thereof. On the other hand, the contact openings 472 may be completely filled, which closes the contact structures 478 from the top. The conductive material may remain on the top surface 480 of the semiconductor structure 400v and on the inner surface 482 of the gate line trench 468.

[0099] Figure 4W Semiconductor structure 400w is shown. The difference between semiconductor structure 400w and semiconductor structure 400v is that the conductive material on the inner surface 482 of gate line groove 468 and the top surface 480 of semiconductor structure 400v is removed (e.g., etched away). The etching process can expose the conductive layer 476 in the gate line groove 468 and produce a groove 484 on the inner surface 482 of the gate line groove 468. Therefore, the conductive layer 476 is separated from each other. The etching process can also remove the conductive material in the upper portion of each contact opening 472 and produce a groove 486. The lower portion of each contact opening 472 is still filled, which can form the head of the contact structure 478. In this way, the contact structures 478 are also separated from each other. In some embodiments, a spacer layer can be filled in the grooves 484 and 486.

[0100] The conductive layer 476 formed in the semiconductor structure 400w may be Figure 1B The contact structure 478 formed in the semiconductor structure 400w may be Figure 1B , Figure 2 and Figure 3 An example of a contact structure 110 .

[0101] Figure 5A-Figure 5B 1 shows a flow chart of an example process 500 for forming a semiconductor device according to some aspects of the present disclosure. The semiconductor device may be Figure 1A-1B The semiconductor device 100, or a portion of the semiconductor device 100, or a structure in an intermediate manufacturing process of the semiconductor device 100 is similar or identical. Figure 4A-4W The process 500 may include forming Figure 4A-4W Process 500 includes steps that may be performed in any suitable order and / or in any combination.

[0102] In step 502, a semiconductor structure including sacrificial layers and insulating layers alternating with each other along a first direction (eg, Z direction) is provided. The semiconductor structure may be Figure 4B The semiconductor structure includes an array region and a connection region adjacent to the array region in a second direction (eg, Y direction) perpendicular to the first direction. The array region may be Figure 4B The array area 402, and the connection area can be Figure 4B The sacrificial layer may be Figure 4A-4B The sacrificial layer 410. The insulating layer may be Figure 4A-4B Insulating layer 412. In some embodiments, each of the sacrificial layers includes silicon nitride, and each of the insulating layers includes silicon oxide.

[0103] The semiconductor structure may include one or more stacks stacked in sequence in a first direction. Each of the one or more stacks may include a subset of sacrificial layers and insulating layers. The one or more stacks may be Figure 1B of stacks 134 , 136 and 138 .

[0104] In some embodiments, the connection region includes an isolation structure, and the protection layer is formed between the isolation structure and the sacrificial layer. The isolation structure may be Figure 4B The protection layer may be Figure 4B The protective layer 418 is formed of a silicon oxide layer. The isolation structure may have a stepped shape. In some embodiments, the isolation structure includes silicon oxide, and the protective layer includes an NDC material.

[0105] In step 504, a first gate line hole, a second gate line hole, a contact hole, a first channel hole, and a second channel hole are formed. The first gate line hole is formed in the array region. The second gate line hole and the contact hole are formed in the connection region. The first gate line hole may be Figure 4C The second gate line hole may be Figure 4CIn some embodiments, each of the first gate line hole and the second gate line hole has a circular or elliptical cross-section. The first channel hole may be Figure 4C The first channel hole is formed in the array region. The second channel hole may be Figure 4C The first gate line hole, the second gate line hole, the contact hole, the first channel hole and the second channel hole extend through the semiconductor structure along the first direction.

[0106] The first gate line hole, the second gate line hole, the contact hole, the first channel hole, and the second channel hole in each of the one or more stacks are formed during the same etching process. In some embodiments, the first gate line hole, the second gate line hole, the first channel hole, the second channel hole, and the contact hole are formed using a single etching mask.

[0107] The contact holes can be Figure 4C The contact hole 428. In some embodiments, the contact hole in each of the one or more stacks comprises a truncated cone that tapers along the first direction.

[0108] At step 506 , the first channel hole, the second channel hole, the first gate line hole, the second gate line hole, and the contact hole are filled with a polysilicon material.

[0109] At step 508, a channel structure is formed in the first channel hole and the second channel hole. The channel structure may be Figure 4G Channel structures 444 and 446 .

[0110] At step 510, the sacrificial layer exposed by the contact hole is etched and recessed using a first etchant. The first etchant may be the etchant 458 described with respect to FIG. 4k. The first etchant etches the sacrificial layer faster than the protective layer.

[0111] At step 512, a contact spacer layer is formed in each contact hole. The contact spacer layer may be Figure 4L The contact spacer layer 454 is in contact with the recessed sacrificial layer. In some embodiments, the contact spacer layer includes silicon oxide.

[0112] At step 514, a second etchant is used to etch and recess the protective layer exposed by each contact hole. The second etchant may be about Figure 4M The second etchant may etch the protection layer faster than the contact spacer layer in each contact hole.

[0113] At step 516, the contact holes are filled with a sacrificial material. The sacrificial material may be Figure 4Nof sacrificial material 462. In some embodiments, the sacrificial material may include carbon.

[0114] At step 518, the top surface of the semiconductor structure is polished.

[0115] At step 520, an isolation layer is deposited on the top surface of the semiconductor structure. The isolation layer may be Fig.4O The isolation layer 464 is formed of a silicon oxide. In some embodiments, the isolation layer may include silicon oxide. In some embodiments, the depth of the isolation layer is about 100 nm.

[0116] At step 522, a gate line opening for each of the first gate line hole and the second gate line hole is formed in the isolation layer to expose the first gate line hole and the second gate line hole. The gate line opening may be Figure 4P One of the gate line openings 466.

[0117] At step 524 , the polysilicon material in the first gate line hole and the second gate line hole is removed.

[0118] At step 526, the first gate line hole and the second gate line hole are enlarged to form a plurality of gate line grooves extending in the second direction. The plurality of gate line grooves may be Figure 1A-1B The gate line gaps 112 are similar or identical. The plurality of gate line grooves may also be about Figure 4Q The gate line trench 468 is depicted. Each of the plurality of gate line trenches includes a series of enlarged gate line holes connected to each other along the second direction.

[0119] At step 528, a bottom surface of each of the plurality of gate line trenches is oxidized. The bottom surface is formed on a substrate (eg, Figure 4A As a result, a protection structure (eg, Figure 4R The protective structure 470 is formed to protect the substrate of the semiconductor structure. In some embodiments, polysilicon oxidation can be used to form the protective structure. The protective structure can protect the substrate of the semiconductor structure from being etched away in a later process or step (for example, when the sacrificial layer is etched away).

[0120] At step 530, a contact opening for each of the contact holes is formed in the isolation layer. The contact opening may be Figure 4S The contact opening 472 has a width (eg, 40-50 nm) smaller than the width of the contact hole.

[0121] At step 532, the sacrificial material in the contact hole is removed. In some embodiments, the sacrificial material includes carbon and can be burned off.

[0122] At step 534, the sacrificial layer in the semiconductor structure is removed. In some embodiments, the sacrificial layer can be removed by applying a third etchant (e.g., Figure 4U The third etchant 474 described above is filled into the contact hole and the gate line trench to remove the sacrificial layer. The etching rate of the third etchant on the sacrificial layer can be faster than the etching rate on the insulating layer, the protection layer and the contact spacer layer.

[0123] At step 536, at least one conductive material is deposited into the plurality of gate line trenches and contact holes to form a conductive layer (eg, Figure 4V conductive layer 476) and contact structures (e.g., Figure 4V The contact structure 478 of the semiconductor structure. The conductive layer can be located between the insulating layers. The contact structure can extend in the first direction through the connection region of the semiconductor structure. In some embodiments, each of the conductive layers is connected to a corresponding contact structure in the contact structure and is isolated from one or more other contact structures in the contact structure. In some embodiments, each of the contact structures includes a body and a head extending beyond the body. The end of the head can contact the end of the body. The end of the body is wider than the end of the head. In some embodiments, the conductive material includes tungsten.

[0124] At step 538 , an inner surface of each of the plurality of gate line trenches is etched to expose and recess the conductive layer.

[0125] At step 540 , a portion of an end of each of the contact structures is etched without creating an opening in the contact structure.

[0126] At step 542, a spacer layer (e.g., Figure 4W The spacer layer described above) is formed to cover the inner surface of each of the plurality of gate line trenches and the end of each of the contact structures. The spacer layer can isolate the conductive layers from each other.

[0127] Figure 6 A block diagram of a system 600 having one or more semiconductor devices (e.g., memory devices) according to one or more embodiments of the present disclosure is shown. The system 600 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory therein. Figure 6As shown in , system 600 may include a host device 608 and a memory system 602 having one or more memory devices 604 and a memory controller 606. The host device 608 may include a processor of an electronic device, such as a central processing unit (CPU), or a system on a chip (SoC), such as an application processor (AP). The host device 608 may be configured to send data to or receive data from the one or more memory devices 604.

[0128] The memory device 604 may be any memory device disclosed herein, such as a memory device based on Figure 1A-1B and 4A- Figure 4W A memory device (e.g., a 3D memory device) of a semiconductor structure. In some embodiments, the memory device 604 includes a NAND flash memory. A memory controller 606 (also referred to as a controller circuit) is coupled to the memory device 604 and the host device 608. Consistent with embodiments of the present disclosure, the memory device 604 may include a plurality of conductive interconnects through a cover layer, the plurality of conductive interconnects contacting a conductive pad in a conductive pad layer, and the memory controller 606 may be coupled to the memory device 604 through at least one of the plurality of conductive interconnects. The memory controller 606 is configured to control the memory device 604. For example, the memory controller 606 may be configured to operate a plurality of channel structures via word lines. The memory controller 606 may manage data stored in the memory device 604 and communicate with the host device 608.

[0129] In some embodiments, the memory controller 606 is designed / configured to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices (such as personal computers, digital cameras, mobile phones, etc.). In some embodiments, the memory controller 606 is designed / configured to operate in a high duty cycle environment SSD or embedded multimedia card (eMMC), which is used as a data storage body for mobile devices (such as smart phones, tablets, laptops, etc.) and enterprise storage arrays. The memory controller 606 can be configured to control the operation of the memory device 604, such as read, erase and program (or write) operations. The memory controller 606 can also be configured to manage various functions related to data stored or to be stored in the memory device 604, including but not limited to bad block management, garbage collection, logical to physical address conversion, wear leveling, etc. In some embodiments, the memory controller 606 is also configured to process error correction code (ECC) on data read from or written to the memory device 604. Any other suitable functions may also be performed by memory controller 606 , such as formatting memory device 604 .

[0130] The memory controller 606 may communicate with an external device (e.g., the host device 608) according to a specific communication protocol. For example, the memory controller 606 may communicate with the external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, an express PCI (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer mini interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc.

[0131] The memory controller 606 and the one or more memory devices 604 may be integrated into various types of storage devices, for example, included in the same package, such as a universal flash storage (UFS) package or an eMMC package. That is, the memory system 602 may be implemented and packaged into different types of terminal electronic products. Figure 6 In one example shown, the memory controller 606 and the single memory device 604 may be integrated into the memory card 602. The memory card 602 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc.

[0132] The subject matter described in the present disclosure and the implementation of the actions and operations can be implemented in digital electronic circuits, in tangibly embodied computer software or firmware, in computer hardware, including the structures disclosed in the present disclosure and their structural equivalents, or a combination of one or more of them. The implementation of the subject matter described in the present disclosure can be implemented as one or more computer programs (e.g., one or more modules of computer program instructions encoded on a computer program carrier) for execution by a data processing device or for controlling the operation of a data processing device. The carrier can be a tangible, non-transitory computer storage medium. Alternatively or in addition, the carrier can be an artificially generated propagation signal, such as a machine-generated electrical, optical or electromagnetic signal, which is generated to encode information for transmission to a suitable receiver device for execution by a data processing device. The computer storage medium can be a part of the following items: a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, or a combination of one or more of them. The computer storage medium is not a propagation signal.

[0133] It should be noted that references in this disclosure to "one embodiment," "an embodiment," "an example embodiment," "some embodiments," "some implementations," etc. indicate that the described embodiments may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. In addition, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, whether or not explicitly described, it is within the knowledge of a technician in the relevant art to implement such feature, structure, or characteristic in conjunction with other implementations.

[0134] Typically, a term can be understood at least in part from usage in context. For example, the term "one or more" as used herein depends at least in part on the context and can be used to describe any feature, structure or characteristic in a singular sense, or can be used to describe a combination of features, structures or features in a plural sense. Similarly, terms such as "a", "an" or "the" can also be understood to express singular usage or to express plural usage, depending at least in part on the context. In addition, the term "based on" can be understood to not necessarily be intended to convey an exclusive set of factors, but can allow for the presence of other factors that are not necessarily explicitly described, which also depends at least in part on the context.

[0135] It should be readily understood that the meaning of "on", "over", and "over" in the present disclosure should be interpreted in the broadest manner, such that "on" means not only "directly on something", but also includes the meaning of "on something" with intervening features or layers. Furthermore, "over" or "on" means not only "over something" or "on something", but also includes the meaning of "over something" or "on something" without intervening features or layers (i.e., directly on something).

[0136] Additionally, for ease of description, spatially relative terms such as "under," "beneath," "lower," "over," "upper," etc. may be used herein to describe the relationship of one element or feature as shown in the figures to another element or features. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

[0137] As used herein, the term "substrate" refers to a material to which subsequent material layers are added. The substrate includes a "top" surface and a "bottom" surface. The top surface of the substrate is typically where the semiconductor device is formed, and therefore, unless otherwise specified, the semiconductor device is formed on the top side of the substrate. The bottom surface is opposite to the top surface, and therefore the bottom side of the substrate is opposite to the top side of the substrate. The substrate itself can be patterned. The material added on top of the substrate can be patterned or can remain unpatterned. In addition, the substrate can include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of a non-conductive material, such as glass, plastic, or sapphire wafer.

[0138] As used herein, the term "layer" refers to a material portion including an area with thickness. The layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate, and the top side is relatively far from the substrate. The layer may extend over the entire lower or upper structure, or may have a range less than the range of the lower or upper structure. In addition, the layer may be a region of a homogeneous or heterogeneous continuous structure, the thickness of which is less than the thickness of the continuous structure. For example, the layer may be located between the top and bottom surfaces of the continuous structure or between any set of horizontal planes at the top and bottom surfaces. The layer may extend horizontally, vertically and / or along a tapered surface. The substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above and / or below it. The layer may include multiple layers. For example, the interconnect layer may include one or more conductive and contact layers (wherein contacts, interconnect lines, and / or vertical interconnect access portions (vertical interconnect access (VIA)) are formed) and one or more dielectric layers.

[0139] As used herein, the term "nominal / nominal" refers to an expected or target value for a characteristic or parameter of a component or process step set during the design phase of a product or process, as well as a range of values ​​above and / or below the expected value. As used herein, a range of values ​​may be due to slight variations in manufacturing processes or tolerances. As used herein, the term "approximately" refers to a value of a given quantity that may vary based on a particular technology node associated with the subject semiconductor device. Based on a particular technology node, the term "approximately" may refer to a value of a given quantity that varies, for example, within 10-30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0140] In this disclosure, the terms “horizontal / horizontally / lateral / laterally” refer to nominally parallel to a lateral surface of a substrate, and the terms “vertical” or “vertically” refer to nominally perpendicular to a lateral surface of a substrate.

[0141] As used herein, the term "3D memory" refers to a three-dimensional (3D) semiconductor device having a vertically oriented string of memory cell transistors (referred to herein as a "memory string", such as a NAND string) on ​​a laterally oriented substrate, such that the memory string extends in a vertical direction relative to the substrate.

[0142] The present disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not restrictive. For example, forming a first feature on or on a second feature in the following description may include an embodiment in which the first feature and the second feature may be in direct contact, and may also include an embodiment in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various implementations and / or configurations discussed.

[0143] The foregoing description of specific embodiments can be readily modified and / or adapted for various applications. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein.

[0144] Although the present disclosure contains many specific implementation details, these should not be interpreted as limitations on the scope of the claimed protection defined by the claims themselves, but rather as descriptions of features that may be specific to a particular implementation of a particular invention. Certain features described in the context of separate implementations in the present disclosure may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented in multiple embodiments individually or in any suitable sub-combination. In addition, although features may be described above as functioning in certain combinations and even initially claimed as such, one or more features from the claimed combination may be deleted from the combination in some cases, and claims may be directed to sub-combinations or variations of sub-combinations.

[0145] Similarly, although operations are shown in the drawings and described in a particular order in the claims, this should not be understood as requiring that the operations be performed in the particular order shown or in a sequential order, or that all of the operations shown be performed, to achieve the desired results. In some cases, multitasking and parallel processing may be advantageous. In addition, the separation of various system modules and components in the above-described embodiments should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0146] Specific implementations of the subject matter have been described. Other implementations are also within the scope of the appended claims. For example, the actions recited in the claims can be performed in a different order and still achieve the desired results. As an example, the processes shown in the accompanying drawings do not necessarily require the specific order shown or sequential order to achieve the desired results. In some cases, multitasking and parallel processing may be advantageous.

[0147] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. A semiconductor device comprising: A semiconductor structure comprising a stack of conductive layers and insulating layers alternating with each other along a first direction, wherein the semiconductor structure comprises an array region and a connection region adjacent to the array region in a second direction perpendicular to the first direction; and a plurality of contact structures extending through the connection area along the first direction, wherein each conductive layer in the stack of conductive layers and insulating layers is coupled to a corresponding contact structure of the plurality of contact structures and isolated from one or more other contact structures of the plurality of contact structures, and Each of the plurality of contact structures includes a main body and a head extending beyond the main body, an end of the head contacts an end of the main body, and the end of the main body is wider than an end of the head.

2. The semiconductor device according to claim 1, wherein The main body includes an outer layer, an inner layer, and a middle layer between the outer layer and the inner layer, the head includes an outer layer, an inner layer, and a middle layer between the outer layer and the inner layer, and the outer layer of the main body, the middle layer of the main body, and the inner layer of the main body are respectively continuously connected to the outer layer of the head, the middle layer of the head, and the inner layer of the head.

3. The semiconductor device according to claim 2, wherein: The outer layer of the body comprises a high-k dielectric material, the middle layer of the body comprises a titanium nitride material, the inner layer of the body comprises a conductive material, the outer layer of the head comprises a high-k dielectric material, the middle layer of the head comprises a titanium nitride material, and the inner layer of the head comprises a conductive material.

4. The semiconductor device according to any one of claims 1 to 3, wherein: The contact structure extends through a set of conductive layers of the stack of conductive layers and insulating layers, wherein the contact structure contacts one of the set of conductive layers, the one conductive layer being closest to the head of the contact structure among the set of conductive layers, and wherein a contact spacer comprising a dielectric material is located between the contact structure and one or more other conductive layers in the set of conductive layers that are isolated from the contact structure.

5. The semiconductor device according to any one of claims 1 to 4, wherein: The semiconductor structure includes one or more stacked layers stacked in sequence along the first direction, and The body of the contact structure includes one or more segments connected in sequence along the first direction, and each of the one or more segments is shaped like a truncated cone and corresponds to a corresponding stack in the one or more stacks of the semiconductor structure. 6 . The semiconductor device according to claim 4 , further comprising a gate line gap and a channel structure, wherein both the gate line gap and the channel structure extend through the semiconductor structure along the first direction.

7. A method comprising: Providing a semiconductor structure, the semiconductor structure comprising sacrificial layers and insulating layers alternating with each other along a first direction, wherein the semiconductor structure comprises one or more stacks stacked in sequence in the first direction, and each of the one or more stacks comprises a subset of the sacrificial layers and the insulating layers, and wherein the semiconductor structure comprises an array region and a connection region adjacent to the array region in a second direction perpendicular to the first direction; and a) forming a first gate line hole in the array region, b) forming a second gate line hole and a contact hole in the connection region, c) forming a first channel hole in the array region, and d) forming a second channel hole in the connection region, wherein the first gate line hole, the second gate line hole, the contact hole, the first channel hole, and the second channel hole extend through the semiconductor structure along the first direction, and wherein the first gate line hole, the second gate line hole, the contact hole, the first channel hole, and the second channel hole in each of the one or more stacks are formed during the same etching process.

8. The method according to claim 7, wherein: The connection region includes an isolation structure, and a protection layer is formed between the isolation structure and the sacrificial layer.

9. The method according to claim 7 or 8, further comprising: The first channel hole, the second channel hole, the first gate line hole, the second gate line hole, and the contact hole are filled with a polysilicon material.

10. The method according to claim 9, further comprising: A channel structure is formed in the first channel hole and the second channel hole.

11. The method according to claim 10, further comprising: Etching and recessing the sacrificial layer exposed by the contact hole using a first etchant, wherein the first etchant has a faster etching rate on the sacrificial layer than on the protective layer; forming a contact spacer layer in each of the contact holes, wherein the contact spacer layer contacts the recessed sacrificial layer; as well as The protection layer exposed by each of the contact holes is etched and recessed using a second etchant, the second etchant having an etching rate of the protection layer faster than an etching rate of the contact spacer layer in each of the contact holes.

12. The method according to claim 11, further comprising: filling the contact holes with a sacrificial material; polishing a top surface of the semiconductor structure; as well as An isolation layer is deposited on the top surface of the semiconductor structure.

13. The method according to claim 12, further comprising: forming a gate line opening for each of the first gate line hole and the second gate line hole in the isolation layer to expose the first gate line hole and the second gate line hole; removing the polysilicon material in the first gate line hole and the second gate line hole; as well as The first gate line hole and the second gate line hole are enlarged to form a plurality of gate line trenches extending in the second direction, wherein each of the plurality of gate line trenches includes a series of enlarged gate line holes connected to each other along the second direction.

14. The method according to claim 13, further comprising: A bottom surface of each of the plurality of gate line trenches is oxidized, wherein the bottom surface is in a substrate of the semiconductor structure.

15. The method according to claim 14, further comprising: forming a contact opening in the isolation layer for each of the contact holes, wherein a width of the contact opening is smaller than a width of the contact hole; and The sacrificial material in the contact hole is removed.

16. The method according to claim 15, further comprising: The sacrificial layer in the semiconductor structure is removed.

17. The method according to claim 16, further comprising: depositing at least one conductive material into the multi-gate line trenches and the contact holes to form a conductive layer between the insulating layer and the contact structure extending through the connection region of the semiconductor structure in the first direction, wherein each of the conductive layers is connected to a corresponding one of the contact structures and is isolated from one or more other ones of the contact structures, Each of the contact structures comprises a main body and a head extending beyond the main body, wherein an end of the head contacts an end of the body, and Wherein, the end of the main body is wider than the end of the head.

18. The method according to claim 17, further comprising: etching an inner surface of each of the plurality of gate line grooves to expose and recess the conductive layer; etching a portion of an end of each of the contact structures without creating an opening in each of the contact structures; as well as A spacer layer is deposited, wherein the spacer layer covers an inner surface of each of the plurality of gate line trenches to isolate the conductive layers from each other, and the spacer layer also covers an end of each of the contact structures.

19. A method comprising: A semiconductor structure is provided, comprising sacrificial layers and insulating layers alternating with each other along a first direction, wherein: The semiconductor structure has an array region and a connection region adjacent to the array region along a second direction perpendicular to the first direction; The semiconductor structure includes a gate line trench and a contact hole; The contact hole extends through the connection region of the semiconductor structure along the first direction; and The connection region includes an isolation structure and a protection layer formed between the isolation structure and the sacrificial layer; Etching and recessing the sacrificial layer exposed by the contact hole using a first etching solution, wherein the first etching solution has a faster etching rate on the sacrificial layer than on the protective layer; forming a contact spacer layer in each of the contact holes, wherein the contact spacer layer contacts the recessed sacrificial layer; and The protection layer exposed by each of the contact holes is etched and recessed using a second etching solution, wherein the second etching solution etches the protection layer faster than the contact spacer layer in each of the contact holes.

20. The method according to claim 19, further comprising: forming a contact opening for each of the contact holes, wherein a width of the contact opening is smaller than a width of the contact hole; removing the sacrificial layer in the semiconductor structure; and At least one conductive material is deposited into the gate line trench and the contact hole in a conformal deposition process to form a conductive layer and a contact structure.

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