Semiconductor structure and preparation method thereof
By forming a stacked dielectric layer structure in a shielded gate trench type power transistor, balancing the stress between the dielectric layers, the problem of high source and drain current in the off-state of traditional transistors is solved, and the source and drain current is reduced.
Patent Information
- Application Number
- CN202510219513.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-26
- Publication Date
- 2025-05-16
AI Technical Summary
The source-drain drain current (IDSS) of traditional shielded gate trench power transistors still need to be reduced in the off-state.
By forming a stacked dielectric layer structure covering transistors, it includes a first interlayer dielectric layer, a second interlayer dielectric layer, and a third interlayer dielectric layer sequentially stacked in a direction perpendicular to the top surface of the substrate. The tensile stress generated by the first interlayer dielectric layer and the tensile stress generated by the third interlayer dielectric layer at least balance part of the compressive stress generated by the second interlayer dielectric layer, thereby reducing the compressive stress to the transistor.
By reducing the compressive stress on the transistor, the source-drain drain current (IDSS) in the off-state of the transistor is reduced.
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Figure CN120018540A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for preparing the same. Background Art
[0002] As a new type of power semiconductor device, shielded gate trench power transistor (SGT) has the advantages of high unit density, low on-resistance and low switching loss, making it widely used in new energy electric vehicles, new photovoltaic power generation, energy-saving home appliances and other fields.
[0003] However, the off-state source-drain leakage current (IDSS) of conventional shielded gate trench power transistors still needs to be reduced. Summary of the invention
[0004] Based on this, the present application provides a semiconductor structure and a method for manufacturing the same, so as to reduce the source-drain leakage current (IDSS) of a transistor (especially a power transistor) in an off state.
[0005] In a first aspect, an embodiment of the present application provides a method for preparing a semiconductor structure, including:
[0006] providing a substrate, the substrate comprising a transistor;
[0007] A stacked dielectric layer structure covering the transistor is formed, wherein the stacked dielectric layer structure includes a first interlayer dielectric layer, a second interlayer dielectric layer, and a third interlayer dielectric layer sequentially stacked in a direction perpendicular to the top surface of the substrate; wherein the tensile stress generated by the first interlayer dielectric layer and the tensile stress generated by the third interlayer dielectric layer at least balance part of the compressive stress generated by the second interlayer dielectric layer, so that the compressive stress generated by the first interlayer dielectric layer, the second interlayer dielectric layer, and the third interlayer dielectric layer on the transistor together is less than a preset value, and the preset value is associated with the source-drain leakage current of the transistor in an off state.
[0008] In some embodiments of the present application, the sum of the absolute value of the tensile stress of the first interlayer dielectric layer and the absolute value of the tensile stress of the third interlayer dielectric layer is smaller than the absolute value of the compressive stress of the second interlayer dielectric layer.
[0009] In some embodiments of the present application, the top of the first interlayer dielectric layer is higher than the top surface of the transistor, the thickness of the first interlayer dielectric layer is less than the thickness of the second interlayer dielectric layer, and the thickness of the third interlayer dielectric layer is less than the thickness of the second interlayer dielectric layer.
[0010] In some embodiments of the present application, the material of the first interlayer dielectric layer includes silicon oxide, and the thickness ranges from 1000 angstroms to 3000 angstroms; the material of the second interlayer dielectric layer includes borosilicate glass, phosphosilicate glass or borophosphosilicate glass, and the thickness ranges from 3000 angstroms to 5000 angstroms; the material of the third interlayer dielectric layer includes silicon oxide, and the thickness ranges from 800 angstroms to 1500 angstroms.
[0011] In some embodiments of the present application, the first interlayer dielectric layer and the third interlayer dielectric layer are formed by a chemical vapor deposition process, the chemical vapor deposition process includes a low-pressure chemical vapor deposition process or a plasma enhanced chemical vapor deposition process, the silicon source gas used in the chemical vapor deposition process includes tetraethyl orthosilicate SiH4, and the oxygen source gas includes O2 or O3; after the third interlayer dielectric layer is formed by the chemical vapor deposition process, the third interlayer dielectric layer is planarized by a chemical mechanical polishing process.
[0012] In some embodiments of the present application, the second interlayer dielectric layer is formed by a chemical vapor deposition process, and the chemical vapor deposition process includes a normal pressure chemical vapor deposition process or a plasma enhanced chemical vapor deposition process. The silicon source gas used in the chemical vapor deposition process includes tetraethyl orthosilicate or SiH4, the oxygen source gas includes O2 or O3, the boron source gas includes B2H6, and the phosphorus source gas includes PH3.
[0013] In some embodiments of the present application, after the second interlayer dielectric layer is formed by a chemical vapor deposition process, the method further includes: performing a first reflow process to planarize the second interlayer dielectric layer.
[0014] In some embodiments of the present application, the preparation method also includes: forming an inorganic anti-reflection layer on the top surface of the third interlayer dielectric layer; performing a second reflow process after forming the inorganic anti-reflection layer; forming a patterned photoresist layer on the top surface of the inorganic anti-reflection layer; using the patterned photoresist layer as a mask, sequentially etching the inorganic anti-reflection layer, the third interlayer dielectric layer, the second interlayer dielectric layer and the first interlayer dielectric layer, forming a through hole exposing the connection end of the transistor in the inorganic anti-reflection layer, the third interlayer dielectric layer, the second interlayer dielectric layer and the first interlayer dielectric layer; and forming a conductive plug in the through hole.
[0015] In some embodiments of the present application, the transistor is a power transistor, and the power transistor includes a trench power transistor, an insulated gate bipolar power transistor, or a bipolar power transistor.
[0016] In a first aspect, an embodiment of the present application further provides a semiconductor structure, including:
[0017] a substrate, the substrate comprising a transistor;
[0018] A stacked dielectric layer structure covering the transistor, the stacked dielectric layer structure comprising a first interlayer dielectric layer, a second interlayer dielectric layer and a third interlayer dielectric layer stacked in sequence in a direction perpendicular to the top surface of the substrate; wherein the tensile stress generated by the first interlayer dielectric layer and the tensile stress generated by the third interlayer dielectric layer at least balance a portion of the compressive stress generated by the second interlayer dielectric layer, so that the compressive stress generated by the first interlayer dielectric layer, the second interlayer dielectric layer and the third interlayer dielectric layer on the transistor together is less than a preset value, and the preset value is associated with a leakage current between a drain and a source of the transistor.
[0019] The embodiments of the present application may or at least have the following advantages:
[0020] In the embodiments of the present application, a semiconductor structure and a method for forming the same are provided, by forming a stacked dielectric layer structure covering a transistor in a substrate, wherein the stacked dielectric layer structure includes a first interlayer dielectric layer, a second interlayer dielectric layer and a third interlayer dielectric layer stacked in sequence in a direction perpendicular to the top surface of the substrate; wherein the tensile stress generated by the first interlayer dielectric layer and the tensile stress generated by the third interlayer dielectric layer at least balance part of the compressive stress generated by the second interlayer dielectric layer, so that the compressive stress generated by the first interlayer dielectric layer, the second interlayer dielectric layer and the third interlayer dielectric layer on the transistor together is less than a preset value, and the preset value is associated with the source-drain leakage current in the off state of the transistor, and thus the compressive stress generated by the stacked dielectric layer structure on the transistor is reduced by stacking the dielectric layer structure with the aforementioned specific structure, thereby reducing the source-drain leakage current (IDSS) in the off state of the transistor.
[0021] The details of one or more embodiments of the present application are set forth in the following drawings and description. Other features, objects, and advantages of the present application will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0023] Figure 1-Figure 7 A schematic diagram of the cross-sectional structure of each stage in a method for preparing a semiconductor structure provided in some embodiments of the present application. DETAILED DESCRIPTION
[0024] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.
[0025] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.
[0026] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.
[0027] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.
[0028] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.
[0029] The structure of the embodiments of the present invention should not be limited to the specific shapes shown in the drawings of the specification, but includes shape deviations due to, for example, manufacturing technology.
[0030] It can be understood that in the drawings of the present application, some adjacent film layers with the same processed film material are drawn to be connected to make them close to the actual structure.
[0031] The existing shielded gate trench power transistor includes: a trench located in the substrate; a gate electrode located in the trench; and a shielded gate located below the gate electrode. The shielded gate can significantly reduce the gate-drain capacitance, and the drift region of the shielded gate trench power transistor also has a higher impurity carrier concentration, which can correspondingly reduce the on-resistance.
[0032] The existing shielded gate trench power transistor includes: a substrate, the substrate includes a top surface and a back surface relative to each other; a trench that penetrates the top surface of the substrate and is located in the substrate; a gate electrode located in the trench; a shielding gate located below the gate electrode; a source region located on the top surface of the substrate outside the gate electrode; and a drain region located on the back surface of the substrate. After the shielded gate trench power transistor is formed on the substrate, an interlayer dielectric layer covering the shielded gate trench power transistor is formed on the substrate, and then a metal plug electrically connected to the shielded gate trench power transistor (for example, a metal plug electrically connected to the gate, source, and shielding gate, respectively) is formed in the interlayer dielectric layer. The existing interlayer dielectric layer is generally a double-layer stacked structure, including a tetraethylorthosilicate (TEOS) dielectric layer located on the top surface of the substrate and a boron- and phosphorus-doped silicon oxide layer or boro-phosphorus glass (BPSG) located on the top surface of the tetraethylorthosilicate dielectric layer. The boron- and phosphorus-doped silicon oxide layer serves as the main body of the interlayer dielectric layer. The thickness of the tetraethylorthosilicate dielectric layer is less than that of the boron- and phosphorus-doped silicon oxide layer. The tetraethylorthosilicate dielectric layer is used to prevent the B element and the P element in the boron- and phosphorus-doped silicon oxide layer from diffusing outward. However, the aforementioned interlayer dielectric layer of this specific structure will produce a large compressive stress on the shielded gate trench power transistor formed on the substrate, so that a large source-drain leakage current (IDSS) will be generated between the source region located on the top surface of the substrate and the drain region located on the back side of the substrate of the shielded gate trench power transistor in the off state. In particular, since the channel of the shielded gate trench power transistor is vertical, and the source region and the drain region are vertically arranged (the source region is located on the top surface of the substrate, and the drain region is located on the back side of the substrate), under the downward compressive stress of the interlayer dielectric layer, compared with the laterally arranged channel and the laterally arranged source region and drain region, a larger source-drain leakage current (IDSS) is more likely to be generated between the drain region on the back side of the shielded gate trench power transistor in the off state.
[0033] To this end, an embodiment of the present application provides a semiconductor structure and a preparation method thereof. The formation method forms a stacked dielectric layer structure covering a transistor, wherein the stacked dielectric layer structure includes a first interlayer dielectric layer, a second interlayer dielectric layer, and a third interlayer dielectric layer stacked in sequence in a direction perpendicular to a top surface of a substrate; wherein the tensile stress generated by the first interlayer dielectric layer and the tensile stress generated by the third interlayer dielectric layer at least balance part of the compressive stress generated by the second interlayer dielectric layer, so that the compressive stress generated by the first interlayer dielectric layer, the second interlayer dielectric layer, and the third interlayer dielectric layer on the transistor together is less than a preset value, and the preset value is associated with the source-drain leakage current (IDSS) of the transistor in an off state.
[0034] The specific process of the method for preparing the semiconductor structure is described in detail below with reference to the accompanying drawings. Figure 1-Figure 7A schematic diagram of the cross-sectional structure of each stage in a method for preparing a semiconductor structure provided in some embodiments of the present application.
[0035] refer to Figure 1 , a substrate 100 is provided, and the substrate 100 includes a transistor.
[0036] The substrate 100 may include a relative top surface and a back surface, and the material of the substrate 100 may include silicon (Si), germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); it may also be silicon on insulator (SOI), germanium on insulator (GOI); or it may also include other materials, such as III-V compounds such as gallium arsenide. The substrate 100 may also be implanted with certain doping ions to change electrical parameters according to design requirements. In one embodiment, the substrate 100 may include a semiconductor substrate and a semiconductor epitaxial layer located on the top surface of the semiconductor substrate, and the materials of the semiconductor substrate and the semiconductor epitaxial layer are both semiconductor materials, for example, the materials of the semiconductor substrate and the semiconductor epitaxial layer may both be silicon (Si).
[0037] The transistor is a power transistor. In some embodiments, the power transistor includes a trench power transistor, an insulated gate bipolar power transistor or a bipolar power transistor, wherein the trench power transistor includes a shielded gate trench power transistor and a trench power transistor without a shielded gate, and the common features of these power transistors are: the source is located on the top surface of the substrate, the drain is located on the back surface of the substrate, and the vertically arranged source and drain are prone to generate source-drain leakage current (IDSS) under the downward compressive stress generated by the interlayer dielectric layer, so the present application will optimize the formation process of the interlayer dielectric layer, and refer to the subsequent description for details.
[0038] In some embodiments, when the transistor is a shielded gate trench power transistor, continue to refer to Figure 1The shielded gate trench power transistor includes: a drain region (not shown in the figure) located on the back side of the substrate 100, the drain region is formed by performing an ion doping process on the back side of the substrate 100, the impurity ions doped by the ion doping process are N-type impurity ions or P-type impurity ions, the P-type impurity ions include one or more of boron ions, gallium ions or indium ions, and the N-type impurity ions include one or more of phosphorus ions, arsenic ions or antimony ions; a drift region (not shown in the figure) located in the substrate 100, the drift region is located above the drain region, the drift region is doped with impurity ions, the type of impurity ions doped in the drift region is the same as the type of impurity ions doped in the drain region, and the concentration of impurity ions doped in the drift region is lower than that of impurity ions doped in the drain region. impurity ion concentration, for example, when the impurity ions doped in the drain region are N-type, the impurity ions doped in the drift region are N-type; at least one first trench penetrating the top surface of the substrate 100 and located in the drift region; a first shielding gate 101 located in the first trench, the top surface of the first shielding gate 101 is lower than the top surface of the substrate 100, and the material of the first shielding gate 101 includes doped polysilicon; a first isolation dielectric layer 103 located in the first trench and covering the first shielding gate 101, the first isolation dielectric layer 103 may include a first sub-isolation dielectric layer located between the side and bottom surfaces of the first shielding gate 101 and the inner wall of the first trench portion, and a second sub-isolation dielectric layer located on the top surface of the first shielding gate 101, the second sub-isolation dielectric layer The edge of the layer is in contact with the first sub-isolation dielectric layer, and the material of the first isolation dielectric layer 103 includes silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide or a combination thereof; a gate electrode 105 located in the first trench remaining above the first shielding gate 101, and a gate dielectric layer 106 located between the sidewall of the gate electrode and the inner wall of the first trench, the top surface of the gate electrode 105 can be lower than the top surface of the substrate 100, the material of the gate electrode 105 includes doped polysilicon or a conductive metal, and the material of the gate dielectric layer 106 is silicon oxide or a high dielectric constant (K) material; a body region 107 located in the substrate 100 outside the gate electrode 105, the body region 107 is doped with impurity ions, and the type of the impurity ions doped in the body region 107 is the same as that in the drain region or the drift region. The impurity ions doped in the drift region are of opposite types, for example, when the impurity ions doped in the drain region or the drift region are of N type, the impurity ions doped in the body region 107 are of P type; the heavily doped region 109 located in the body region 107, the doping type in the heavily doped region 109 is the same as the doping type of the body region 107, and the doping concentration of the heavily doped region 109 is greater than the doping concentration of the body region 107; the source region 108 located in the substrate 100 outside the gate electrode 105, the source region 108 is doped with impurity ions, and the type of impurity ions doped in the source region 108 is opposite to the type of impurity ions doped in the body region 107, for example, when the impurity ions doped in the body region 107 are of P type, the impurity ions doped in the source region 108 are of N type.The shielded gate trench power transistor also includes: a second trench penetrating the top surface of the substrate 100 and located in the drift region; a second shielding gate 102 located in the second trench, the top surface of the first shielding gate 101 is flush with the top surface of the substrate 100, a second isolation dielectric layer 104 is located between the sidewalls and bottom of the first shielding gate 101 and the sidewalls of the second trench, the second shielding gate 102 is used as a shielding gate of the source, the material of the second shielding gate 102 includes doped polysilicon, and the material of the second isolation dielectric layer 104 includes silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide or a combination thereof. The difference between the trench power transistor without a shielding gate and the shielded gate trench power transistor is that the trench power transistor without a shielding gate does not have the aforementioned shielding gate (such as the first shielding gate and the second shielding gate).
[0039] refer to Figure 4 , forming a stacked dielectric layer structure covering the transistor, the stacked dielectric layer structure comprising a first interlayer dielectric layer 113, a second interlayer dielectric layer 114 and a third interlayer dielectric layer 115 stacked in sequence along a direction perpendicular to the top surface of the substrate 100; wherein the tensile stress generated by the first interlayer dielectric layer 113 and the tensile stress generated by the third interlayer dielectric layer 115 at least balance part of the compressive stress generated by the second interlayer dielectric layer 114, so that the compressive stress generated by the first interlayer dielectric layer 113, the second interlayer dielectric layer 114 and the third interlayer dielectric layer 115 on the transistor together is less than a preset value, and the preset value is associated with the source-drain leakage current (IDSS) of the transistor in the off state.
[0040] In some embodiments, the following Figure 2-Figure 4 The formation process of the stacked dielectric layer structure is described in detail.
[0041] First, refer to Figure 2 , a first interlayer dielectric layer 113 covering the transistor is formed on the top surface of the substrate 100 .
[0042] The first interlayer dielectric layer 113 is provided for subsequent formation of the second interlayer dielectric layer 114 (refer to Figure 3 ) provides a flat surface; on the other hand, the first interlayer dielectric layer 113 is also used to prevent the boron element (B) and / or the phosphorus element (P) in the subsequently formed second interlayer dielectric layer 114 from diffusing outward to avoid affecting the device; on still another hand, the first interlayer dielectric layer 113 will also generate a certain tensile stress on the subsequently formed second interlayer dielectric layer 114 to balance the partial compressive stress generated by the subsequently formed second interlayer dielectric layer 114.
[0043] In some embodiments, the top of the first interlayer dielectric layer 113 is higher than the top surface of the transistor, and the thickness of the first interlayer dielectric layer 113 is less than the thickness of the second interlayer dielectric layer 114 formed subsequently. In some specific embodiments, the material of the first interlayer dielectric layer 113 includes silicon oxide, and the thickness ranges from 1000 angstroms to 3000 angstroms, and can be 1000 angstroms, 1500 angstroms, 2000 angstroms, 2500 angstroms or 3000 angstroms; the first interlayer dielectric layer is formed by a chemical vapor deposition process, and the chemical vapor deposition process includes a low pressure chemical vapor deposition process (LPCVD) or a plasma enhanced chemical vapor deposition process (PECVD). The silicon source gas used in the chemical vapor deposition process includes tetraethylorthosilicate (TEOS) or SiH4, and the oxygen source gas includes O2 or O3. The silicon dioxide film (first interlayer dielectric layer 113) formed by using tetraethylorthosilicate as the silicon source has a lower dielectric constant, which helps to reduce the capacitive coupling effect in the circuit, and has good step coverage and gap filling ability.
[0044] Next, refer to Figure 3 A second interlayer dielectric layer 114 is formed on the top surface of the first interlayer dielectric layer 113 .
[0045] The thickness of the second interlayer dielectric layer 114 is greater than the thickness of the first interlayer dielectric layer 113 and the thickness of the subsequently formed third interlayer dielectric layer 115 (refer to Figure 4 ), the second interlayer dielectric layer 114 serves as the main structure of the stacked dielectric layer structure to provide a better insulation effect for the connecting lines.
[0046] In one embodiment, the material of the second interlayer dielectric layer 114 includes borosilicate glass (BSG, boron-doped silicon oxide), phospho-silicate glass (PSG, phosphorus-doped silicon oxide) or boro-phospho-silicate glass (BPSG, boron- and phosphorus-doped silicon oxide), and the thickness of the second interlayer dielectric layer 114 ranges from 3000 angstroms to 5000 angstroms, and can be 3000 angstroms, 3500 angstroms, 4000 angstroms, 4500 angstroms or 5000 angstroms. The second interlayer dielectric layer 114 is formed by a chemical vapor deposition process, the chemical vapor deposition process includes an atmospheric pressure chemical vapor deposition process (APCVD) or a plasma enhanced chemical vapor deposition process (PECVD), and the silicon source gas used in the chemical vapor deposition process includes tetraethyl orthosilicate (TEOS) or SiH4, the oxygen source gas includes O2 or O3, the boron source gas includes B2H6, and the phosphorus source gas includes PH3. Specifically, when forming borosilicate glass, silicon source gas, oxygen source gas and boron source gas need to be introduced; when forming phosphosilicate glass, silicon source gas, oxygen source gas and phosphorus source gas need to be introduced; when forming borophosphosilicate glass, silicon source gas, oxygen source gas, boron source gas and phosphorus source gas need to be introduced. In some embodiments, after forming the second interlayer dielectric layer 114 by chemical vapor deposition process, it also includes: performing a first reflow process to flatten the second interlayer dielectric layer 114, the temperature range of the first reflow process is 900 degrees Celsius-1000 degrees Celsius, which can be 900 degrees Celsius, 920 degrees Celsius, 950 degrees Celsius, 980 degrees Celsius or 1000 degrees Celsius.
[0047] When the material of the second interlayer dielectric layer 114 is borosilicate glass, phosphosilicate glass or borophosphosilicate glass, the borosilicate glass, phosphosilicate glass or borophosphosilicate glass has a loose texture due to the addition of boron and / or phosphorus impurities to its original ordered network structure in silicon oxide (silicon dioxide), and has the ability to flow like a liquid under high temperature conditions (Reflow). Therefore, the film of borosilicate glass, phosphosilicate glass or borophosphosilicate glass material has excellent hole-filling ability and can improve the flatness of the entire substrate surface, thereby providing a larger process range for subsequent lithography processes and other processes. However, the disadvantage of the thin film of borosilicate glass, phosphosilicate glass or borosilicate glass material is that it will produce a large compressive stress on the material directly or indirectly in contact with it. Therefore, in the present application, the second interlayer dielectric layer 114 will produce compressive stress on the transistor in the substrate 100, so that the transistor, especially the power transistor (trench power transistor, insulated gate bipolar power transistor or bipolar power transistor) is easy to generate a source-drain leakage current (IDSS) in the off state. Therefore, in the present application, before forming the second dielectric layer 114, a first interlayer dielectric layer 113 is first formed on the top surface of the substrate 100, and after the second interlayer dielectric layer 114 is formed on the top surface of the first interlayer dielectric layer 113, a third interlayer dielectric layer 114 is formed on the top surface of the second interlayer dielectric layer 114. The first interlayer dielectric layer 115, the tensile stress generated by the first interlayer dielectric layer 113 and the tensile stress generated by the third interlayer dielectric layer 115 at least balance part of the compressive stress generated by the second interlayer dielectric layer 114, so that the compressive stress generated by the first interlayer dielectric layer 113, the second interlayer dielectric layer 114, and the third interlayer dielectric layer 115 on the transistor together is less than a preset value, and the preset value is associated with the source-drain leakage current of the transistor in the off state, thereby reducing the source-drain leakage current (IDSS) of the transistor in the off state (the source-drain leakage current in the off state is positively associated with the preset value, the smaller the preset value is, that is, the smaller the compressive stress generated by the first interlayer dielectric layer 113, the second interlayer dielectric layer 114, and the third interlayer dielectric layer 115 on the transistor together, the smaller the source-drain leakage current in the off state will be).
[0048] Next, refer to Figure 4 A third interlayer dielectric layer 115 is formed on the top surface of the second interlayer dielectric layer 114, so that a stacked dielectric layer structure is formed.
[0049] On the one hand, the third interlayer dielectric layer 115 provides a flat surface for subsequent processes; on the other hand, the third interlayer dielectric layer 115 is also used to prevent the boron element (B) and / or phosphorus element (P) in the subsequently formed second interlayer dielectric layer 114 from diffusing outward to avoid affecting the device; on the other hand, the third interlayer dielectric layer 115 will also generate a certain tensile stress on the second interlayer dielectric layer 114 to further balance the partial compressive stress generated by the second interlayer dielectric layer 114.
[0050] In some embodiments, the thickness of the third interlayer dielectric layer 115 is less than the thickness of the second interlayer dielectric layer 114 formed subsequently. In some specific embodiments, the material of the third interlayer dielectric layer 115 includes silicon oxide, and the thickness ranges from 800 angstroms to 1500 angstroms, and can be 800 angstroms, 1000 angstroms, 1200 angstroms, or 1500 angstroms; the third interlayer dielectric layer 115 is formed by a chemical vapor deposition process, and the chemical vapor deposition process includes a low pressure chemical vapor deposition process (LPCVD) or a plasma enhanced chemical vapor deposition process (PECVD). The silicon source gas used in the chemical vapor deposition process includes tetraethylorthosilicate (TEOS) or SiH4, and the oxygen source gas includes O2 or O3. The silicon dioxide film (third interlayer dielectric layer 115) formed by using tetraethylorthosilicate as the silicon source has a lower dielectric constant, which helps to reduce the capacitive coupling effect in the circuit, and has good step coverage and gap filling capabilities.
[0051] In one embodiment, the sum of the absolute value of the tensile stress of the first interlayer dielectric layer 113 and the absolute value of the tensile stress of the third interlayer dielectric layer 115 is smaller than the absolute value of the compressive stress of the second interlayer dielectric layer 114 .
[0052] In one embodiment, after the third interlayer dielectric layer 115 is formed by a chemical vapor deposition process, the method further includes: planarizing the third interlayer dielectric layer 115 by a chemical mechanical polishing process, so that the third interlayer dielectric layer 115 has a flat surface to facilitate the consistency of subsequent processes (such as photolithography and etching processes).
[0053] In some embodiments, reference Figure 5 The preparation method further includes: forming an inorganic anti-reflection layer 116 on the top surface of the third interlayer dielectric layer 115, the material of the inorganic anti-reflection layer 116 is SiON, and the inorganic anti-reflection layer 116 is used as an anti-reflection layer in the subsequent photolithography process to prevent the reflection of the exposure light in the photolithography process, improve the uniformity of the size and position of the formed photolithography pattern, thereby improving the consistency of the subsequent etching process of the plurality of through holes formed in the stacked dielectric layer structure; after the inorganic anti-reflection layer 116 is formed, a second reflow process is performed to further reduce the compressive stress of the stacked dielectric layer structure, and the temperature range of the second reflow process is 900 degrees Celsius-1000 degrees Celsius, which can be 900 degrees Celsius, 920 degrees Celsius, 950 degrees Celsius, 980 degrees Celsius or 1000 degrees Celsius; reference Figure 6, forming a patterned photoresist layer (not shown in the figure) on the top surface of the inorganic anti-reflection layer 116; using the patterned photoresist layer as a mask, sequentially etching the inorganic anti-reflection layer 116, the third interlayer dielectric layer 115, the second interlayer dielectric layer 114 and the first interlayer dielectric layer 113, forming through holes exposing the connection terminals (such as gate electrodes, source regions, shielding gates) of the transistors in the inorganic anti-reflection layer 116, the third interlayer dielectric layer 115, the second interlayer dielectric layer 114 and the first interlayer dielectric layer 113; forming conductive plugs (110, 111, 112) in the through holes, the conductive plug 110 being electrically connected to the source region 108 of the transistor (such as a shielding gate trench power transistor), the conductive plug 111 being electrically connected to the gate electrode 105 of the transistor (such as a shielding gate trench power transistor), and the conductive plug 112 being electrically connected to the second shielding gate 102; then, continue to refer to Figure 6 , a metal layer 117 is formed on the top surface of the inorganic anti-reflection layer 116 (refer to Figure 6 );refer to Figure 7 , the metal layer 117 is patterned to form metal wires (118, 119, 120) electrically connected to the corresponding metal plugs (110, 111, 112). Specifically, the metal wire 118 is electrically connected to the metal plug 110, the metal wire 119 is electrically connected to the metal plug 111, and the metal wire 120 is electrically connected to the metal plug 112.
[0054] The present application also provides a semiconductor structure, referring to Figure 7 ,include:
[0055] A substrate 100, the substrate including a transistor;
[0056] A stacked dielectric layer structure covering the transistor, the stacked dielectric layer structure comprising a first interlayer dielectric layer 113, a second interlayer dielectric layer 114 and a third interlayer dielectric layer 115 stacked in sequence along a direction perpendicular to the top surface of the substrate 100; wherein the tensile stress generated by the first interlayer dielectric layer 113 and the tensile stress generated by the third interlayer dielectric layer 115 at least balance a portion of the compressive stress generated by the second interlayer dielectric layer 114, so that the compressive stress generated by the first interlayer dielectric layer 113, the second interlayer dielectric layer 114 and the third interlayer dielectric layer 115 on the transistor is less than a preset value, and the preset value is related to the leakage current between the drain and the source of the transistor.
[0057] In some embodiments, the power transistor includes a trench power transistor, an insulated gate bipolar power transistor, or a bipolar power transistor.
[0058] In some embodiments, the semiconductor structure further includes: an inorganic anti-reflection layer 116 located on the top surface of the third interlayer dielectric layer 115; after the inorganic anti-reflection layer 116 is formed, a second reflow process is performed to further reduce the compressive stress of the stacked dielectric layer structure, and the temperature range of the second reflow process is 900 degrees Celsius-1000 degrees Celsius; conductive plugs (110, 111, 112) electrically connected to the connection ends of the transistors located in the inorganic anti-reflection layer 116, the third interlayer dielectric layer 115, the second interlayer dielectric layer 114 and the first interlayer dielectric layer 113; and metal wirings (118, 119, 120) electrically connected to the corresponding metal plugs (110, 111, 112).
[0059] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.
[0060] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0061] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.
Claims
1. A method for preparing a semiconductor structure, characterized in that: include: providing a substrate, the substrate comprising a transistor; forming a stacked dielectric layer structure covering the transistor, the stacked dielectric layer structure comprising a first interlayer dielectric layer, a second interlayer dielectric layer and a third interlayer dielectric layer sequentially stacked in a direction perpendicular to the top surface of the substrate; The tensile stress generated by the first interlayer dielectric layer and the tensile stress generated by the third interlayer dielectric layer at least balance part of the compressive stress generated by the second interlayer dielectric layer, so that the compressive stress generated by the first interlayer dielectric layer, the second interlayer dielectric layer, and the third interlayer dielectric layer on the transistor together is less than a preset value, and the preset value is associated with the source-drain leakage current of the transistor in the off state.
2. The method for preparing a semiconductor structure according to claim 1, characterized in that: The sum of the absolute value of the tensile stress of the first interlayer dielectric layer and the absolute value of the tensile stress of the third interlayer dielectric layer is smaller than the absolute value of the compressive stress of the second interlayer dielectric layer.
3. The method for preparing a semiconductor structure according to claim 1 or 2, characterized in that: The top of the first interlayer dielectric layer is higher than the top surface of the transistor, the thickness of the first interlayer dielectric layer is less than the thickness of the second interlayer dielectric layer, and the thickness of the third interlayer dielectric layer is less than the thickness of the second interlayer dielectric layer.
4. The method for preparing a semiconductor structure according to claim 3, characterized in that: The material of the first interlayer dielectric layer includes silicon oxide, with a thickness ranging from 1000 angstroms to 3000 angstroms; the material of the second interlayer dielectric layer includes borosilicate glass, phosphosilicate glass or borophosphosilicate glass, with a thickness ranging from 3000 angstroms to 5000 angstroms; the material of the third interlayer dielectric layer includes silicon oxide, with a thickness ranging from 800 angstroms to 1500 angstroms.
5. The method for preparing a semiconductor structure according to claim 4, characterized in that: The first interlayer dielectric layer and the third interlayer dielectric layer are formed by a chemical vapor deposition process, wherein the chemical vapor deposition process includes a low-pressure chemical vapor deposition process or a plasma enhanced chemical vapor deposition process, wherein the silicon source gas used in the chemical vapor deposition process includes tetraethyl orthosilicate or SiH4, and the oxygen source gas includes O2 or O3; after the third interlayer dielectric layer is formed by the chemical vapor deposition process, the third interlayer dielectric layer is planarized by a chemical mechanical polishing process.
6. The method for preparing a semiconductor structure according to claim 4, characterized in that: The second interlayer dielectric layer is formed by a chemical vapor deposition process, wherein the chemical vapor deposition process includes a normal pressure chemical vapor deposition process or a plasma enhanced chemical vapor deposition process, wherein the silicon source gas used in the chemical vapor deposition process includes tetraethyl orthosilicate or SiH4, the oxygen source gas includes O2 or O3, the boron source gas includes B2H6, and the phosphorus source gas includes PH3.
7. The method for preparing a semiconductor structure according to claim 6, characterized in that: After the second interlayer dielectric layer is formed by a chemical vapor deposition process, the method further includes: performing a first reflow process to planarize the second interlayer dielectric layer.
8. The method for preparing a semiconductor structure according to claim 1 or 7, characterized in that: The preparation method also includes: forming an inorganic anti-reflection layer on the top surface of the third interlayer dielectric layer; performing a second reflow process after forming the inorganic anti-reflection layer; forming a patterned photoresist layer on the top surface of the inorganic anti-reflection layer; using the patterned photoresist layer as a mask, sequentially etching the inorganic anti-reflection layer, the third interlayer dielectric layer, the second interlayer dielectric layer and the first interlayer dielectric layer, forming a through hole in the inorganic anti-reflection layer, the third interlayer dielectric layer, the second interlayer dielectric layer and the first interlayer dielectric layer to expose the connection end of the transistor; and forming a conductive plug in the through hole.
9. The method for preparing a semiconductor structure according to claim 8, characterized in that: The transistor is a power transistor, and the power transistor includes a trench power transistor, an insulated gate bipolar power transistor or a bipolar power transistor.
10. A semiconductor structure, characterized in that: include: a substrate, the substrate comprising a transistor; A stacked dielectric layer structure covering the transistor, the stacked dielectric layer structure comprising a first interlayer dielectric layer, a second interlayer dielectric layer and a third interlayer dielectric layer sequentially stacked in a direction perpendicular to the top surface of the substrate; The tensile stress generated by the first interlayer dielectric layer and the tensile stress generated by the third interlayer dielectric layer at least balance part of the compressive stress generated by the second interlayer dielectric layer, so that the compressive stress generated by the first interlayer dielectric layer, the second interlayer dielectric layer, and the third interlayer dielectric layer on the transistor is less than a preset value, and the preset value is associated with the leakage current between the drain and source of the transistor.