Nanotube junctionless field effect transistor

Abstract

A nanotube junctionless field effect transistor comprises: a nanotube structure, the nanotube structure comprising an inner surface, an outer surface and a center surface, the center surface being located between the inner surface and the outer surface; along the extension direction of the nanotube structure, the nanotube structure comprises a channel region, a Gauss ring region and a source-drain doped region, the Gauss ring region is located on both sides of the channel region, and the source-drain doped region is located on one side of each of the Gauss ring regions away from the channel region; along the inner surface to the center surface and along the outer surface to the center surface, the concentration of doped ions in the Gauss ring region gradually increases; a gate structure located on the inner surface and the outer surface of the channel region. The performance of the nanotube junctionless field effect transistor is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and in particular, to a nanotube junctionless field effect transistor. BACKGROUND

[0002] With the shrinking of the size of planar metal-oxide-semiconductor field-effect transistors (MOSFETs), the devices have serious short channel effects (SCEs) and the static power consumption caused by the leakage current continues to increase. In order to overcome the short channel effect, various advanced 3D MOSFET architectures are proposed, such as fin field effect transistors and gate-all-around transistors. The nanotube junctionless field effect transistor (NT-JLFET) in the gate-all-around transistor architecture is proposed as the best device architecture for the final scaling of field effect transistors, because of its superior gate control capability, and the inner gate and outer gate jointly control the opening and closing of the nanotube junctionless field effect transistor. In addition, the junctionless device not only reduces the thermal budget and manufacturing complexity, but also suffers less short channel effect.

[0003] However, the performance of the nanotube junctionless field effect transistor still needs to be continuously improved. SUMMARY

[0004] The technical problem solved by the present application is to provide a nanotube junctionless field effect transistor, which improves the performance of the nanotube junctionless field effect transistor.

[0005] The embodiment of the present application provides a nanotube junctionless field effect transistor, which comprises a nanotube structure, the nanotube structure comprises an inner surface, an outer surface and a center surface, the center surface is located between the inner surface and the outer surface; along the extension direction of the nanotube structure, the nanotube structure comprises a channel region, a Gauss ring region and a source-drain doped region, the Gauss ring region is located on both sides of the channel region, and the source-drain doped region is located on the side of each Gauss ring region away from the channel region; along the inner surface to the center surface and along the outer surface to the center surface, the doping ion concentration in the Gauss ring region gradually increases; and a gate structure located on the inner surface and the outer surface of the channel region.

[0006] Optionally, the Gauss ring region comprises a center region and a gradual change region located on both sides of the center region, the center region comprises the center surface; along the direction of the inner surface to the center region and along the direction of the outer surface to the center region, the doping ion concentration in the gradual change region gradually increases.

[0007] Optionally, the doping ion concentration in the center region is the same as the doping ion concentration in the source-drain doping region.

[0008] Optionally, along the extension direction of the nanotube structure, the channel region has a first length, and the gate structure has a second length, the second length being greater than the first length.

[0009] Optionally, the difference between the second length and the first length ranges from 1 nanometer to 3 nanometers.

[0010] Optionally, further comprising: an electrical contact layer located on one side of the outer surface of the nanotube structure, along the extension direction of the nanotube structure, the electrical contact layer is located on both sides of the gate structure.

[0011] Optionally, the electrical contact layer is in electrical contact with part of the source-drain doping region.

[0012] Optionally, the gate structure comprises: a gate dielectric layer located on the inner surface and the outer surface of the channel region; and a gate layer located on the gate dielectric layer.

[0013] Optionally, further comprising: a dielectric structure located on the inner surface and the outer surface of the nanotube structure, along the extension direction of the nanotube structure, the dielectric structure is located on both sides of the gate structure.

[0014] Optionally, further comprising: a gate extension layer in the dielectric structure on one side of the inner surface, the gate extension layer being in electrical connection with the gate structure.

[0015] Compared with the prior art, the technical scheme of the embodiment of the present application has the following beneficial effects:

[0016] In the nanotube junctionless field effect transistor of the technical scheme of the present application, by providing a Gaussian ring region, the Gaussian ring region is located on both sides of the channel region, the source-drain doping region is located on one side of each Gaussian ring region away from the channel region, along the inner surface to the center surface, and along the outer surface to the center surface, the doping ion concentration in the Gaussian ring region gradually increases. Thus, the off current can be reduced, the threshold voltage can be increased, the threshold voltage roll-off effect can be overcome, and the effective gate control capability is improved without affecting the on current.

[0017] Further, the channel region has a first length, and the gate structure has a second length, the second length being greater than the first length. The gate structure and the Gaussian ring region have an overlapping length range, which can increase the potential barrier height from the source doping region to the channel region and the potential barrier height from the drain doping region to the channel region, and increase the effective channel length, while keeping the threshold voltage from being too large and avoiding hindering the opening of the device. BRIEF DESCRIPTION OF DRAWINGS

[0018] Figure 1 and Figure 2 is a schematic diagram of a structure of a nanotube junctionless field effect transistor in an embodiment;

[0019] Figure 3 is a schematic diagram of a principle of generating off current in an off state of a nanotube junctionless field effect transistor in an embodiment;

[0020] Figures 4 to 8 is a schematic diagram of a structure of a nanotube junctionless field effect transistor in an embodiment. DETAILED DESCRIPTION

[0021] As described in the background, the performance of the nanotube junctionless field effect transistor still needs to be continuously improved. The following will be described in detail in combination with the drawings.

[0022] Figure 1 and Figure 2 is a schematic diagram of a structure of a nanotube junctionless field effect transistor in an embodiment.

[0023] Please refer to Figure 1 and Figure 2 , Figure 1 is a perspective view of a nanotube junctionless field effect transistor, Figure 2 is Figure 1 a schematic diagram of a cross-sectional structure of a nanotube junctionless field effect transistor along a cross-sectional line AA1 in an embodiment, the nanotube junctionless field effect transistor comprising: a nanotube structure 100, the nanotube structure 100 comprising an inner surface P1 and an outer surface P2, along an extension direction of the nanotube structure 100, the nanotube structure 100 comprising a channel region 101 and source and drain doped regions 104 and 102 located on both sides of the channel region 101; a gate structure 103 located on the inner surface P1 and the outer surface P2 of the channel region 101; a first electrical contact layer 110 and a second electrical contact layer 105 located on the outer surface P2 of the nanotube structure 100, the first electrical contact layer 110 being in electrical contact with part of the source doped region 104, and the second electrical contact layer 105 being in electrical contact with part of the drain doped region 102; a dielectric structure 106 located on the inner surface P1 and the outer surface P2 of the nanotube structure 100, the gate structure 103 being located in the dielectric structure 106; a gate extension layer 108 located in the dielectric structure 106, the gate extension layer 108 being in electrical connection with the gate structure 103.

[0024] The gate structure 103 includes a gate dielectric layer on the inner surface PI and the outer surface P2 of the channel region 101, and a gate layer 121 on the gate dielectric layer 120. The material of the gate dielectric layer 120 includes silicon dioxide, the material of the gate layer 121 includes titanium nitride, and the material of the electrical contact layer 105 includes tungsten.

[0025] The nanotube junctionless field effect transistor has N-type doping and a doping concentration of 1 x 1019cm-3 in the channel region 101, the source doped region 104, and the drain doped region 102. 19 cm -3 With continued reference to Figure 2 , the work function of the gate structure 103 is set to 5.1 eV. The high work function of the gate structure 103 results in repelling electrons and accumulating holes under the gate dielectric layer, forming a hole inversion layer that appears as a triangle with the length of the gate structure 103 as the base. The inversion layers formed by the gate structure 103 on the inner surface PI and the outer surface P2 of the channel region 101 overlap, causing the nanotube junctionless field effect transistor to be turned off. When a positive voltage is applied to the gate structure 103, the thickness of the hole inversion layer formed by the gate structure 103 on the inner surface PI and the outer surface P2 decreases, forming an electron channel in the channel region 101, causing the nanotube junctionless field effect transistor to be turned on. Thus, the transmission path of the on-state current is in the center of the channel region 101 (3 nm to 5 nm below the gate dielectric layer).

[0026] Please refer to Figure 3 , Figure 3 is Figure 1 and Figure 2 the principle diagram of the off-state current I off generated by the nanotube junctionless field effect transistor in the off state. The principle of the off-state current I off generation includes: along the line BB1 in Figure 2 (BB1 is located 1 nm below the gate dielectric layer), in the off state of the nanotube junctionless field effect transistor (drain-source voltage V DS = 1.0 V, gate-source V GS = 0.0 V), holes accumulate under the channel region 101. According to the quantum mechanical effect, the point with the highest hole concentration in the channel region 101 is located 1 nm below the gate dielectric layer, with a concentration close to 10 19 cm -3 , while the electron concentration in the drain doped region 102 is 10 19 cm -3 , which results in a very small depletion region width of the PN junction at the channel-drain interface, causing the conduction band in the drain doped region 102 to be very close to the valence band of the channel region 101. As Figure 3The proximity of the bands results in electron tunneling from the channel region 101 to the drain through longitudinal band-to-band tunneling (L-BTBT), resulting in an increase in the off-state current I OFF The farther the distance from the gate dielectric layer, the lower the hole concentration, the wider the depletion region width of the PN junction, and the smaller the off-state current caused by longitudinal band-to-band tunneling. Therefore, the leakage path of the off-state current is mainly located 1 nm below the gate dielectric layer.

[0027] To solve the above problems, the usual way is: (1) Adjust the energy band of the nanotube junctionless field effect transistor in the off state by adjusting the gate layer 121 and the gate dielectric layer 120, so as to increase the tunneling width, suppress longitudinal band-to-band tunneling, and reduce the off-state current. The material of the gate layer 121 adopts a material with a small work function, and the material of the gate dielectric layer 120 adopts a material with a low dielectric constant, so as to reduce the electric field at the channel-drain interface and alleviate the band bending. However, when the channel length is 10 nm, the off-state current of the nanotube junctionless field effect transistor is only reduced by one order of magnitude, but the threshold voltage is sharply reduced.

[0028] (2) Use the valence band discontinuity of the heterojunction to increase the tunneling width of the nanotube junctionless field effect transistor, for example, the source doped region and the drain doped region are made of Si 1-x Ge x (x is the mole component) material, and the channel region is made of Si material, so as to form a heterojunction at the source / drain-channel interface. However, when the channel length of the nanotube junctionless field effect transistor is gradually reduced from 20 nm, the existence of the heterojunction will sharply reduce the threshold voltage, making the nanotube junctionless field effect transistor invalid.

[0029] (3) Use the intrinsic pocket to increase the tunneling width of the nanotube junctionless field effect transistor and reduce the off-state current. The intrinsic pocket is a region with a length of L inserted in the source / drain of the nanotube junctionless field effect transistor close to the channel region, and the doping concentration is 10 15 cm -3 The doping concentration of the intrinsic pocket is low and the resistance is high, but this will cause the on-state current to drop sharply.

[0030] To solve the above problems, the technical scheme of the present application provides a nanotube junctionless field effect transistor, by setting a Gaussian ring region, the Gaussian ring region is located on both sides of the channel region, the source / drain doped region is located on the side of each Gaussian ring region away from the channel region, along the inner surface to the center surface, and along the outer surface to the center surface, the doping ion concentration in the Gaussian ring region gradually increases. Thus, the off-state current can be reduced, the threshold voltage can be increased, the threshold voltage roll-off effect can be overcome, the effective gate control capability can be improved without affecting the on-state current, and the effective gate length can be increased.

[0031] In order to make the above objectives, characteristics and benefits of the present application more obvious and comprehensible, specific embodiments of the present application are described in detail below with reference to the drawings.

[0032] Figures 4 to 8 is a structural schematic diagram of a nanotube junctionless field effect transistor in the embodiments of the present application.

[0033] Please refer to Figure 4 and Figure 8 , Figure 4 is a perspective view of a nanotube junctionless field effect transistor, Figure 5 is Figure 4 is a sectional structural schematic diagram of a nanotube junctionless field effect transistor in the embodiments of the present application along the direction of the section line AA1, Figure 6 is a top view of a first side S1 of a nanotube junctionless field effect transistor, Figure 7 is a top view of a first side S2 of a nanotube junctionless field effect transistor, Figure 8 is Figure 5 is an enlarged schematic diagram of a Gauss ring region, and the nanotube junctionless field effect transistor can include:

[0034] The nanotube structure 200 can include an inner surface P1, an outer surface P2 and a central surface (not shown) between the inner surface and the outer surface; along the extension direction of the nanotube structure 200, the nanotube structure 200 can include a channel region 201, a Gauss ring region 202 located on both sides of the channel region 201, and a source-drain doped region located on the side of each Gauss ring region 202 away from the channel region 201; along the direction from the inner surface P1 to the central surface, and along the direction from the outer surface P2 to the central surface, the doping ion concentration in the Gauss ring region 202 gradually increases.

[0035] The gate structure 204 is located on the inner surface P1 and the outer surface P2 of the channel region 201.

[0036] The cross-sectional shape of the nanotube structure 200 can include a circular ring or an elliptical ring.

[0037] In the present embodiment, the cross-sectional shape of the nanotube structure 200 can include a circular ring.

[0038] In the present embodiment, the source-drain doped region can include a source doped region 213 and a drain doped region 203. The conductive types of the channel region 201, the source doped region 213 and the drain doped region 203 can be the same, and the doping ion concentrations of the channel region 201, the source doped region 213 and the drain doped region 203 can be the same.

[0039] In the above embodiment, the doping ion concentration of the channel region 201, the source doping region 213 and the drain doping region 203 is the same, which can reduce the short channel effect of the nanotube junctionless field effect transistor.

[0040] In the embodiment, the doping ion conductivity type in the channel region 201, the source doping region 213 and the drain doping region 203 is N type, and the N type ion can include phosphorus ion, arsenic ion or antimony ion, etc.

[0041] In the embodiment, the doping ion concentration in the channel region 201, the source doping region 213 and the drain doping region 203 can be 1×10 19 cm -3 .

[0042] In one of the embodiments, when the cross-sectional shape of the nanotube structure 200 is a circular ring, the central surface is concentrically distributed with the inner surface and the outer surface, and the distance between the central surface and the inner surface and the outer surface is equal.

[0043] In another embodiment, when the cross-sectional shape of the nanotube structure 200 is an elliptical ring, the cross-sectional shape of the central surface can also be an elliptical ring, and the distance between the central surface and the inner surface and the outer surface is equal.

[0044] Please refer to Figure 8 , in the embodiment, the Gaussian ring region 202 can include a central region C1 and a gradient region C2 located on both sides of the central region C1, the central region C1 can include the central surface; along the direction of the inner surface P1 to the central region C1, and along the direction of the outer surface P2 to the central region C1, the doping ion concentration in the gradient region C2 gradually increases.

[0045] In a specific embodiment, the doping ion concentration in the gradient region C2 is Gaussian distribution, that is, along the direction of the inner surface P1 to the central region C1, and along the direction of the outer surface P2 to the central region C1, the doping ion concentration in the gradient region C2 gradually increases.

[0046] In the embodiment, the doping ion concentration of the surface P2 / P1 farthest from the central region C1 in the gradient region C2 is 10 15 cm -3 , and the doping ion concentration of the innermost side close to the central region C1 in the gradient region C2 is 10 19 cm -3 .

[0047] In the embodiment, the dopant ion concentration in the center region C1 is the same as the dopant ion concentration in the source / drain doped region. The center region C1 of the Gaussian ring region 202 is the current path of the on-current, and the dopant ion concentration in the center region C1 is the same as the dopant ion concentration in the source / drain doped region, so that the on-resistance of the on-current transmission path is unchanged and does not affect the on-current.

[0048] In the embodiment, along the extension direction of the nanotube structure 200, the channel region 201 has a first length L1, and the gate structure 204 has a second length L2, which is greater than the first length L1.

[0049] In the embodiment, the first length L1 ranges from 10 nanometers to 20 nanometers.

[0050] In the embodiment, the gate structure 204 can include a gate dielectric layer 220 located on the inner surface P1 and the outer surface P2 of the channel region 201, and a gate layer 221 located on the gate dielectric layer 220.

[0051] In the embodiment, the material of the gate dielectric layer 220 can include silicon dioxide, and the material of the gate layer 221 can include titanium nitride.

[0052] In the embodiment, along the extension direction of the nanotube structure, the gate structure 204 can also extend to the inner surface P1 and the outer surface P2 corresponding to the Gaussian ring region 202. That is, the gate structure 204 has an overlapping region with the Gaussian ring region 202, so as to increase the barrier height of the source doped region 213 to the channel region 201 and the barrier height of the drain doped region 203 to the channel region 201, and increase the effective channel length.

[0053] In one embodiment, the gate structure can be in contact with the inner surface P1 and the outer surface P2 corresponding to the Gaussian ring region 202 on either side of the channel region, or can be in contact with the inner surface P1 and the outer surface P2 corresponding to the Gaussian ring region 202 on both sides of the channel region. That is, the gate structure 204 has an overlapping region with the Gaussian ring region 202 on either side or both sides of the channel region.

[0054] In one of the embodiments, when the gate structure is in contact with the inner surface P1 and the outer surface P2 corresponding to the Gaussian ring region 202 on both sides of the channel region, the lengths of the two sides of the contact can be equal or not equal. That is, referring to Figure 5 , the length L3 of the gate structure in contact with the Gaussian ring region on both sides of the channel region can be equal or not equal.

[0055] In another embodiment, the length L3 of the gate structure 204 on the inner surface P1 and the outer surface P2 of the Gaussian ring region 202 ranges from 1 nm to 3 nm. That is, the gate structure 204 has an overlapping length L3 on each surface of the Gaussian ring region 202.

[0056] In this embodiment, the length L3 of the gate structure 204 on the inner surface P1 and the outer surface P2 of the Gaussian ring region 202 ranges from 2 nm.

[0057] In the above embodiments, the gate structure 204 has an overlapping length L3 on the Gaussian ring region 202, which can increase the height of the potential barrier from the source doped region 213 to the channel region 201 and the height of the potential barrier from the drain doped region 203 to the channel region 201, and increase the effective channel length, while keeping the threshold voltage from being too large and avoiding hindering the opening of the device.

[0058] In this embodiment, the nanotube junctionless field effect transistor can further include an electrical contact layer (not shown) on one side of the outer surface P2 of the nanotube structure 200 along the extension direction of the nanotube structure 200, and the electrical contact layer is located on both sides of the gate structure 204.

[0059] In this embodiment, the electrical contact layer can be in electrical contact with part of the source / drain doped region.

[0060] In this embodiment, the electrical contact layer can include a first electrical contact layer 215 in electrical contact with the source doped region 213 and a second electrical contact layer 205 in electrical contact with the drain doped region 203.

[0061] In this embodiment, the material of the electrical contact layer can include a metal, and the metal can include tungsten.

[0062] In this embodiment, the nanotube junctionless field effect transistor can further include a dielectric structure 206 on the inner surface P1 and the outer surface P2 of the nanotube structure 200 along the extension direction of the nanotube structure 200, and the dielectric structure 206 is located on both sides of the inner surface P1 and the outer surface P2 of the gate structure 204.

[0063] In this embodiment, the dielectric structure 206 is located on the inner surface P1 and the outer surface P2 of the nanotube structure 200, that is, the dielectric structure 206 fills the inside of the nanotube structure 200 and covers the outer surface P2 of the nanotube structure 200.

[0064] In this embodiment, the material of the dielectric structure 206 can include silicon dioxide.

[0065] In the embodiment, the nanotube junctionless field effect transistor can further include a gate extension layer 207 in the dielectric structure 206 on the side of the inner surface P1, the gate extension layer 207 being electrically connected with the gate structure 204.

[0066] In the embodiment, the gate extension layer 207 is in the dielectric structure 206 on the side of the inner surface P1 of the nanotube structure 200, and the gate extension layer 207 is at one end of the drain doped region 203.

[0067] In one embodiment, the material of the gate extension layer 207 can include metal or metal nitride; the metal can include one or more of a combination of copper, aluminum, tungsten, cobalt, nickel and tantalum; and the metal nitride can include one or more of a combination of tantalum nitride and titanium nitride.

[0068] In the embodiment, in the nanotube junctionless field effect transistor, a Gaussian ring region 202 is arranged between the source doped region 213 and the channel region 201 and between the drain doped region 203 and the channel region 201, and the ion doping concentration in the Gaussian ring region 202 gradually increases in the direction from the inner surface P1 to the center region C1 and in the direction from the outer surface P2 to the center region C1. Thus, the off current I OFF is reduced, the threshold voltage is increased, the threshold voltage roll-off effect is overcome, the effective gate control capability is improved without affecting the on current, and the effective gate length is increased.

[0069] Specifically, please refer to Figure 5 The nanotube junctionless field effect transistor is analyzed along the line BB1.

[0070] First, when the nanotube junctionless field effect transistor is in the off state, holes will be accumulated under the gate dielectric layer, and the holes and the electrons form a PN junction. The introduction of the Gaussian ring increases the depletion layer width of the PN junction at the interface between the source doped region 213 and the channel region 201 and between the drain doped region 203 and the channel region 201, reduces the electric field at the interface, alleviates the bending of the energy band, increases the tunneling width of the lateral band to band tunneling (L-BTBT), reduces the off current IOFF, and reduces the static power consumption.

[0071] Secondly, the Gaussian ring region 202 and the gate structure have an overlapping length L3 at the interface between the source doped region 213 and the channel region 201 and between the drain doped region 203 and the channel region 201. Within the length L3, due to the low ion doping concentration of the Gaussian ring region 202 away from the inner surface P1 and the outer surface P2 of the center region C1, the potential barrier height of the source doped region 213 to the channel region 201 and the drain doped region 203 to the channel region 201 is increased. The increased potential barrier height can effectively overcome the threshold voltage roll-off effect and also reduce the off current IOFF .

[0072] Again, the region of high resistance (electron doping concentration of about 10 15 cm -3 ) in the Gaussian ring region 202 is located on the surface of the silicon channel, and the doping ion concentration gradually increases from the inner surface P1, the outer surface P2 to the center region C1, that is, the resistance decreases from the inner surface P1, the outer surface P2 to the center region C1. The transmission path of the on-current is located in the center region C1, therefore, the gradual change region C2 of the Gaussian ring region 202 has almost no effect on the on-current.

[0073] Again, the Gaussian ring region 202 prevents the electrons in the channel region 201 from being transported by the lateral band-to-band tunneling (L-BTBT) to the drain doped region 203, increases the electron concentration in the channel region 201, and the increased electron concentration reduces the hole concentration. The reduced hole concentration weakens the shielding effect of the holes in the channel region 201 on the control ability of the gate structure 204, thereby improving the effective gate control ability. The subthreshold swing and the drain-induced barrier lowering (DIBL) effect are reduced.

[0074] Finally, the length L3 of the overlap of the Gaussian ring region 202 and the gate structure 204 further improves the barrier height. The length of the PN junction depletion region at the interface between the source doped region 213 to the channel region 201 and the drain doped region 203 to the channel region 201 is increased, and the degree of band bending is alleviated. The increase of the barrier height and the alleviation of the degree of band bending increase the effective gate length. The shorter the length of the channel region 201 is, the more significant the effect of the Gaussian ring region 202 on reducing the off-current I OFF and weakening the short channel effect.

[0075] Although the present application has been disclosed as above, the present application is not limited to the above. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, and therefore the protection scope of the present application should be defined by the scope defined in the claims.

Claims

1. A nanotube junctionless field effect transistor, characterized by, Comprising: a nanotube structure, the nanotube structure comprising an inner surface, an outer surface and a center surface, the center surface being located between the inner surface and the outer surface; along the extension direction of the nanotube structure, the nanotube structure comprises a channel region, a Gaussian ring region and a source-drain doped region, the Gaussian ring region is located on both sides of the channel region, and the source-drain doped region is located on the side of each Gaussian ring region away from the channel region; along the inner surface to the center surface, and along the outer surface to the center surface, the concentration of doped ions in the Gaussian ring region gradually increases; a gate structure located on the inner surface and the outer surface of the channel region.

2. The nanotube junctionless field effect transistor of claim 1, wherein, The Gaussian ring region comprises a center region and a gradual change region located on both sides of the center region, and the center region comprises the center surface; along the direction of the inner surface to the center region, and along the direction of the outer surface to the center region, the concentration of doped ions in the gradual change region gradually increases.

3. The nanotube junctionless field effect transistor of claim 2, wherein, The concentration of doped ions in the center region is the same as the concentration of doped ions in the source-drain doped region.

4. The nanotube junctionless field effect transistor of claim 1, wherein, Along the extension direction of the nanotube structure, the channel region has a first length, and the gate structure has a second length, and the second length is greater than the first length.

5. The nanotube junctionless field effect transistor of claim 4, wherein, The difference between the second length and the first length ranges from 1 nanometer to 3 nanometers.

6. The nanotube junctionless field effect transistor of claim 1, wherein the nanotube is a semiconducting nanotube. Further comprising: an electrical contact layer located on one side of the outer surface of the nanotube structure, and along the extension direction of the nanotube structure, the electrical contact layer is located on both sides of the gate structure.

7. The nanotube junctionless field effect transistor of claim 6, wherein, The electrical contact layer is in electrical contact with part of the source-drain doped region.

8. The nanotube junctionless field effect transistor of claim 1, wherein, The gate structure comprises: a gate dielectric layer located on the inner surface and the outer surface of the channel region; a gate layer located on the gate dielectric layer.

9. The nanotube junctionless field effect transistor of claim 1, wherein, Further comprising: a dielectric structure, the dielectric structure is located on the inner surface and the outer surface of the nanotube structure, and along the extension direction of the nanotube structure, the dielectric structure is located on both sides of the gate structure.

10. The nanotube junctionless field effect transistor of claim 9, wherein, Further comprising: a gate extension layer located in the dielectric structure on one side of the inner surface, the gate extension layer is in electrical connection with the gate structure.

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