Semiconductor structure and manufacturing method thereof

Abstract

The invention relates to a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a substrate, a gate trench, a breakdown protection layer, a gate structure, and a drain structure. The substrate comprises an epitaxial layer and a well region positioned on one side of the epitaxial layer; the gate trench is located on one side, provided with the well region, of the substrate; the gate trench at least penetrates through the well region and extends into the epitaxial layer along a direction vertical to the substrate; the breakdown protection layer is located at the bottom of the gate trench; the gate structure is located on one side, deviating from the substrate, of the breakdown protection layer and is embedded in the gate trench; the drain electrode structure is located on the side, away from the gate electrode structure, of the substrate in the direction perpendicular to the substrate. The voltage resistance of the semiconductor power device can be effectively improved, and the breakdown risk of the semiconductor power device can be reduced.

Description

Technical Field

[0001] The present application relates to the field of power electronics, and in particular to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] Trench Metal Oxide Semiconductor Field Effect Transistor (Trench MOSFET) is a power field effect transistor that is currently widely used in the field of power electronics. Trench MOSFET embeds the gate structure into the silicon wafer to form a vertical trench, which can increase the channel density and improve the current handling capacity, thereby optimizing the performance of semiconductor power devices.

[0003] As power electronics technology tends to develop in the direction of high power, high frequency and integration, in order to meet production and work needs, it is necessary to improve the working efficiency of semiconductor power devices. However, due to the small radius of curvature of the bottom of the trench in the trench MOSFET and the concentrated electric field distribution, the breakdown risk of the bottom of the gate trench is high. The breakdown problem at the bottom of the trench will reduce the working stability and reliability of semiconductor power devices, especially in high voltage or high power application environments, and in severe cases may cause semiconductor device failure. Summary of the invention

[0004] Based on this, the embodiments of the present application provide a semiconductor structure and a method for manufacturing the same, which can effectively improve the voltage resistance performance of semiconductor power devices and help reduce the breakdown risk of semiconductor power devices.

[0005] In order to achieve the above-mentioned purpose, on the one hand, some embodiments of the present application provide a semiconductor structure. The semiconductor structure includes a substrate, a gate trench, a breakdown protection layer, a gate structure and a drain structure. The substrate includes an epitaxial layer and a well region located on one side of the epitaxial layer; the gate trench is located on the side of the substrate having the well region; the gate trench at least penetrates the well region and extends into the epitaxial layer in a direction perpendicular to the substrate; the breakdown protection layer is located at the bottom of the gate trench; the gate structure is located on the side of the breakdown protection layer away from the substrate and is embedded in the gate trench; the drain structure is located on the side of the substrate away from the gate structure in a direction perpendicular to the substrate.

[0006] In some embodiments, a surface of the breakdown protection layer facing away from the epitaxial layer in a direction perpendicular to the substrate is lower than a surface of the well region close to the epitaxial layer in a direction perpendicular to the substrate, or is flush with a surface of the well region close to the substrate in a direction perpendicular to the substrate.

[0007] In some embodiments, the semiconductor structure further includes a source region; the source region is located in the well region on both sides of the gate trench in a direction parallel to the substrate.

[0008] In some embodiments, the base further includes a substrate; the substrate is located on a side of the epitaxial layer away from the well region in a direction perpendicular to the substrate; wherein the drain structure is located on a side of the substrate away from the epitaxial layer in a direction perpendicular to the substrate.

[0009] In some embodiments, the gate structure includes a gate dielectric layer and a gate conductive layer; the gate dielectric layer is at least located on the sidewall of the gate trench; the gate conductive layer covers the gate dielectric layer and the breakdown protection layer and fills the gate trench.

[0010] In some embodiments, the material of the breakdown protection layer includes an insulating material.

[0011] On the other hand, the present application also provides a method for manufacturing a semiconductor structure according to some embodiments; the method for manufacturing a semiconductor structure can be used to prepare the semiconductor structures in some of the above embodiments.

[0012] In some embodiments, a method for manufacturing a semiconductor structure includes: providing a substrate; the substrate includes an epitaxial layer; forming a gate trench in the epitaxial layer; the gate trench extends in a direction perpendicular to the substrate; forming a breakdown protection material layer in the gate trench; forming well regions on both sides of the breakdown protection material layer in a direction parallel to the substrate; etching the breakdown protection material layer so that the breakdown protection material layer retained at the bottom of the gate trench corresponds to a breakdown protection layer; forming a gate structure on a side of the breakdown protection layer away from the substrate; the gate structure is embedded in the gate trench; and forming a drain structure on a side of the substrate away from the gate structure in a direction perpendicular to the substrate.

[0013] In some embodiments, after forming well regions on both sides of the breakdown protection material layer in a direction parallel to the substrate, the method for manufacturing the semiconductor structure further includes: forming source regions in the well regions on both sides of the gate trench in a direction parallel to the substrate.

[0014] In some embodiments, providing a substrate includes: providing a substrate; forming an epitaxial layer on one side of the substrate; wherein the drain structure is formed on a side of the substrate away from the epitaxial layer in a direction perpendicular to the substrate.

[0015] In some embodiments, the gate structure is formed on the side of the breakdown protection layer away from the substrate, including: forming a gate dielectric material layer at least on the sidewall of the gate trench and the surface of the substrate; forming a gate conductive material layer at least on the surface of the gate dielectric material layer and the surface of the breakdown protection material layer on the side away from the epitaxial layer in a direction perpendicular to the substrate; at least a portion of the gate conductive material layer is embedded in the gate trench; grinding the gate dielectric material layer and the gate conductive material layer so that the portion of the gate dielectric material layer retained in the gate trench corresponds to the gate dielectric layer, and the portion of the gate conductive material layer retained in the gate trench corresponds to the gate conductive layer, so as to form the gate structure.

[0016] The embodiments of the present application may or at least have the following advantages:

[0017] In the embodiment of the present application, the gate trench is located in the substrate and penetrates the well region and extends into the epitaxial layer, a breakdown protection layer is provided at the bottom of the gate trench, and the gate structure is located on the side of the breakdown protection layer away from the substrate and is embedded in the gate trench. In this way, by embedding the gate structure into the substrate to form a gate of a vertical trench structure, the current in the gate structure flows vertically, effectively reducing the characteristic on-resistance (Rsp) of the semiconductor device, and there is no junction field effect transistor (JFET) resistance, effectively reducing the power consumption of the semiconductor device and improving the current handling capacity; by providing a breakdown protection layer at the bottom of the trench, the electric field at the bottom of the trench can be effectively dispersed, and the peak electric field can be reduced, the breakdown voltage can be increased, and the withstand voltage performance of the semiconductor device with a trench gate structure can be ensured; and, by forming a breakdown protection layer below the gate structure, the distance between the gate structure and the drain structure below the substrate can be increased to a certain extent, so as to reduce the gate leakage current without affecting the on-off of the P well, thereby improving the switching ratio of the semiconductor device, improving the device response speed and the device frequency.

[0018] The details of one or more embodiments of the present application are set forth in the following drawings and description. Other features, objects, and advantages of the present application will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0020] Figure 1 A schematic diagram of a semiconductor structure provided in some embodiments;

[0021] Figure 2 A schematic flow chart of a method for manufacturing a semiconductor structure provided in some embodiments;

[0022] Figure 3 A schematic flow chart of another method for manufacturing a semiconductor structure provided in some embodiments;

[0023] Figure 4 A schematic flow chart of another method for manufacturing a semiconductor structure provided in some embodiments;

[0024] Figure 5 A schematic diagram of a flow chart of step S600 provided in some embodiments;

[0025] Figure 6 is a schematic structural diagram of a substrate provided in some embodiments;

[0026] Figure 7 A schematic diagram of a structure obtained after forming a gate trench provided in some embodiments;

[0027] Figure 8 A schematic diagram of a structure obtained after a breakdown protection material layer is formed in some embodiments;

[0028] Fig. 9 A schematic diagram of a structure obtained after forming a well region provided in some embodiments;

[0029] Fig.10 A schematic diagram of a structure obtained after forming a source region provided in some embodiments;

[0030] Fig.11 A schematic diagram of a structure obtained after a breakdown protection layer is formed in some embodiments;

[0031] Fig.12 A schematic diagram of a structure obtained after forming a gate dielectric material layer and a gate conductive material layer provided in some embodiments;

[0032] Fig.13 A schematic diagram of a structure obtained after forming a gate structure provided in some embodiments.

[0033] Description of reference numerals:

[0034] 1-substrate, 2-epitaxial layer, 3-well region, 4-substrate, G-gate trench, 5-breakdown protection layer, 51-breakdown protection material layer, 6-gate structure, 61-gate conductive layer, 611-gate conductive material layer, 62-gate dielectric layer, 621-gate dielectric material layer, 7-drain structure, 8-source region. DETAILED DESCRIPTION

[0035] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0037] It should be understood that when an element or layer is referred to as being "on," "adjacent to," or "connected to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion.

[0038] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0039] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic representations of idealized embodiments (and intermediate structures) of the present application, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Embodiments of the present application should not be limited to the specific shapes of the regions shown herein, but include deviations in shapes due to, for example, manufacturing techniques. Therefore, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shapes of the regions of the device, and do not limit the scope of the present application.

[0040] The embodiments of the present application provide a semiconductor structure and a method for manufacturing the same, so as to effectively improve the voltage resistance performance of a semiconductor power device, thereby helping to reduce the breakdown risk of the semiconductor power device.

[0041] In some embodiments, see Figure 1 , the semiconductor structure includes a substrate 1, a gate trench G, a breakdown protection layer 5, a gate structure 6 and a drain structure 7. The substrate 1 includes an epitaxial layer 2 and a well region 3 located on one side of the epitaxial layer 2; the gate trench G is located on the side of the substrate 1 having the well region 3; the gate trench G at least penetrates the well region 3 and extends into the epitaxial layer 2 in a direction perpendicular to the substrate 1; the breakdown protection layer 5 is located at the bottom of the gate trench G; the gate structure 6 is located on the side of the breakdown protection layer 5 away from the substrate 1, and is embedded in the gate trench G; the drain structure 7 is located on the side of the substrate 1 away from the gate structure 6 in a direction perpendicular to the substrate 1.

[0042] By way of example, the semiconductor structure includes but is not limited to a power field effect transistor, such as a trench metal oxide semiconductor field effect transistor (Trench Metal Oxide Semiconductor Field Effect Transistor, Trench MOSFET for short), etc.

[0043] For example, a size of the gate trench G in a first direction (eg, Y direction) perpendicular to the substrate 1 is larger than a size of the well region 3 in the first direction (eg, Y direction) perpendicular to the substrate 1 .

[0044] By way of example, the material of the drain structure 7 includes, but is not limited to, a conductive material; the material of the drain structure 7 may be, for example, a conductive metal.

[0045] For example, please continue to see Figure 1 The gate trench G extends into the epitaxial layer 2 along a first direction (eg, Y direction) perpendicular to the substrate 1 , and does not penetrate the epitaxial layer 2 .

[0046] For example, the gate structure 6 is embedded in the gate trench G, and a surface of the gate structure 6 facing away from the substrate 1 in a first direction (eg, Y direction) perpendicular to the substrate 1 is flush with the surface of the substrate 1 .

[0047] By way of example, the well region 3 is located on both sides of the gate structure 6 in a second direction (eg, X direction) parallel to the substrate 1 .

[0048] In some embodiments, the material of the breakdown protection layer 5 includes an insulating material.

[0049] For example, the material of the breakdown protection layer 5 includes oxide; the material of the breakdown protection layer 5 may be, for example, silicon dioxide (SiO 2 ) or the like.

[0050] In the embodiment of the present application, the gate trench G is located in the substrate 1 and penetrates the well region 3 and extends into the epitaxial layer 2. A breakdown protection layer 5 is provided at the bottom of the gate trench G. The gate structure 6 is located on the side of the breakdown protection layer 5 away from the substrate 1 and is embedded in the gate trench G. In this way, by embedding the gate structure 6 into the substrate 1 to form a gate of a vertical trench structure, the current in the gate structure 6 flows vertically, which effectively reduces the characteristic on-resistance (Rsp) of the semiconductor device, and there is no junction field effect transistor (JFET) resistance, which effectively reduces the power consumption of the semiconductor device and improves the current handling capability; by providing a breakdown protection layer 5 at the bottom of the trench, the electric field at the bottom of the trench can be effectively dispersed, and the peak electric field can be reduced, thereby increasing the breakdown voltage and ensuring the voltage resistance of the semiconductor device with the trench gate structure 6; and, by forming the breakdown protection layer 5 below the gate structure 6, the distance between the gate structure 6 and the drain structure 7 below the substrate 1 can be increased to a certain extent, so as to reduce the gate leakage current without affecting the on-off of the P well, thereby improving the switching ratio of the semiconductor device, and improving the device response speed and device frequency.

[0051] In some embodiments, please refer to Figure 1 The surface of the breakdown protection layer 5 facing away from the epitaxial layer 2 in the first direction perpendicular to the substrate 1 (for example, the Y direction) is lower than the surface of the well region 3 close to the epitaxial layer 2 in the first direction perpendicular to the substrate 1 (for example, the Y direction), or is flush with the surface of the well region 3 close to the substrate 1 in the first direction perpendicular to the substrate 1 (for example, the Y direction).

[0052] In the embodiment of the present application, the breakdown protection layer 5 is located below the well region 3 in a first direction (for example, the Y direction) perpendicular to the substrate 1; in this way, the breakdown protection layer 5 in the embodiment of the present application can reduce the gate leakage current without affecting the on and off of the P well, and effectively disperse the electric field at the bottom of the trench and reduce the peak electric field, thereby improving the breakdown voltage of the semiconductor device and ensuring the voltage resistance performance of the semiconductor device with the trench gate structure 6.

[0053] In some embodiments, please refer to Figure 1 The semiconductor structure further includes a source region 8 ; the source region 8 is located in the well region 3 on both sides of the gate trench G in a second direction (eg, X direction) parallel to the substrate 1 .

[0054] For example, please continue to see Figure 1 The well region 3 is located on a side of the source region 8 that is away from the gate structure 6 in a second direction (eg, X direction) parallel to the substrate 1 ; the well region 3 is also located on a side of the source region 8 that is away from the surface of the substrate 1 in a first direction (eg, Y direction) perpendicular to the substrate 1 .

[0055] In some embodiments, the substrate 1 also includes a substrate 4; the substrate 4 is located on a side of the epitaxial layer 2 that is away from the well region 3 in a first direction (for example, the Y direction) perpendicular to the substrate 1; wherein the drain structure 7 is located on a side of the substrate 4 that is away from the epitaxial layer 2 in the first direction (for example, the Y direction) perpendicular to the substrate 1.

[0056] For example, the substrate 4 can be made of semiconductor material, insulating material, conductor material or any combination thereof. The substrate 4 can be a single-layer structure or a multi-layer structure. For example, the substrate 4 can be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate 4 can be a layered substrate including Si / SiGe, Si / SiC, silicon on insulator (SOI) or silicon germanium on insulator. Therefore, the type of substrate 4 should not limit the scope of protection of the present application.

[0057] It should be noted that, in some embodiments, the semiconductor structure includes a drain structure 7, a substrate 4, an epitaxial layer 2, a well region 3 and a source region 8 stacked in sequence from bottom to top along a first direction (eg, Y direction) perpendicular to the substrate 1.

[0058] In some embodiments, the gate structure 6 includes a gate dielectric layer 62 and a gate conductive layer 61 ; the gate dielectric layer 62 is at least located on the sidewall of the gate trench G; the gate conductive layer 61 covers the gate dielectric layer 62 and the breakdown protection layer 5 , and fills the gate trench G.

[0059] For example, the material of the gate dielectric layer 62 includes but is not limited to an insulating material; the material of the gate dielectric layer 62 may be, for example, an oxide, such as silicon dioxide (SiO 2 ).

[0060] By way of example, the material of the gate conductive layer 61 includes but is not limited to polysilicon (Poly).

[0061] The present application also provides a method for manufacturing a semiconductor structure according to some embodiments; the method for manufacturing a semiconductor structure can be used to prepare the semiconductor structures in some of the above embodiments. The method for manufacturing the semiconductor structure also possesses the technical advantages of the above semiconductor structure. It should be noted that for the parts that are the same or corresponding to the above embodiments, reference can be made to the corresponding description of the above embodiments, and will not be described in detail below.

[0062] In some embodiments, see Figure 2 , the manufacturing method of the semiconductor structure includes the following steps S100~S700.

[0063] S100, providing a substrate; the substrate includes an epitaxial layer.

[0064] S200, forming a gate trench in the epitaxial layer; the gate trench extends in a direction perpendicular to the substrate.

[0065] S300 , forming a breakdown protection material layer in the gate trench.

[0066] S400 , forming well regions on both sides of the breakdown protection material layer in a direction parallel to the substrate.

[0067] S500, etching the breakdown protection material layer, so that the breakdown protection material layer retained at the bottom of the gate trench correspondingly constitutes a breakdown protection layer.

[0068] S600, forming a gate structure on a side of the breakdown protection layer away from the substrate; the gate structure is embedded in the gate trench.

[0069] S700 , forming a drain structure on a side of the substrate away from the gate structure in a direction perpendicular to the substrate.

[0070] In the embodiment of the present application, a gate trench is formed in the substrate and penetrates the well region and extends into the epitaxial layer, a breakdown protection layer is provided at the bottom of the gate trench, and a gate structure is formed on the side of the breakdown protection layer away from the substrate and embedded in the gate trench. In this way, by embedding the gate structure into the substrate to form a gate of a vertical trench structure, the current in the gate structure flows vertically, effectively reducing the characteristic on-resistance (Rsp) of the semiconductor device, and there is no junction field effect transistor (JFET) resistance, effectively reducing the power consumption of the semiconductor device and improving the current handling capacity; by providing a breakdown protection layer at the bottom of the trench, the electric field at the bottom of the trench can be effectively dispersed, and the peak electric field can be reduced, the breakdown voltage can be increased, and the withstand voltage performance of the semiconductor device with a trench gate structure can be ensured; and, by forming a breakdown protection layer below the gate structure, the distance between the gate structure and the drain structure below the substrate can be increased to a certain extent, so as to reduce the gate leakage current without affecting the on-off of the P well, thereby improving the switching ratio of the semiconductor device, improving the device response speed and the device frequency.

[0071] In some embodiments, see Figure 3 After step S400, the method for manufacturing the semiconductor structure further includes the following step S410.

[0072] S410 , forming source regions in the well regions on both sides of the gate trench in a direction parallel to the substrate.

[0073] In some embodiments, see Figure 4 , step S100 includes the following steps S110~S120.

[0074] S110, providing a substrate.

[0075] S120, forming an epitaxial layer on one side of the substrate.

[0076] Accordingly, the drain structure is formed on a side of the substrate away from the epitaxial layer in a direction perpendicular to the base.

[0077] In some embodiments, see Figure 5 , step S600 includes the following steps S610~S630.

[0078] S610, forming a gate dielectric material layer at least on the sidewalls of the gate trench and the surface of the substrate.

[0079] S620, forming a gate conductive material layer at least on the surface of the gate dielectric material layer and on the surface of the breakdown protection material layer on a side away from the epitaxial layer in a direction perpendicular to the substrate; at least a portion of the gate conductive material layer is embedded in the gate trench.

[0080] S630, grinding the gate dielectric material layer and the gate conductive material layer so that the portion of the gate dielectric material layer remaining in the gate trench corresponds to the gate dielectric layer, and the portion of the gate conductive material layer remaining in the gate trench corresponds to the gate conductive layer, so as to form a gate structure.

[0081] It should be understood that although Figure 2~Figure 5 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 2~Figure 5 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0082] In order to more clearly illustrate the manufacturing method of the semiconductor structure in some of the above embodiments, the following embodiments are combined with Figure 1 and Figure 6~Figure 13 Understand.

[0083] In some embodiments, the method for manufacturing a semiconductor structure includes the following steps S100 - S700 .

[0084] In step S100, refer to Figure 6 , providing a substrate 1; the substrate 1 includes an epitaxial layer 2.

[0085] In some embodiments, step S100 includes the following steps S110 to S120.

[0086] In step S110 , a substrate 4 is provided.

[0087] For example, the substrate 4 can be made of semiconductor material, insulating material, conductor material or any combination thereof. The substrate 4 can be a single-layer structure or a multi-layer structure. For example, the substrate 4 can be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate 4 can be a layered substrate including Si / SiGe, Si / SiC, silicon on insulator (SOI) or silicon germanium on insulator. Therefore, the type of substrate 4 should not limit the scope of protection of the present application.

[0088] In step S120, please continue to refer to Figure 6 , an epitaxial layer 2 is formed on one side of the substrate 4.

[0089] By way of example, the process for forming the epitaxial layer 2 includes, but is not limited to, an epitaxial growth (Epitaxy) process and the like.

[0090] In step S200, refer to Figure 7 , a gate trench G is formed in the epitaxial layer 2 ; the gate trench G extends along a first direction (eg, Y direction) perpendicular to the substrate 1 .

[0091] For example, the process for forming the gate trench G includes but is not limited to a dry etching process; the process for forming the gate trench G may be, for example, a photolithography process.

[0092] For example, the gate trench G extends along a first direction (eg, Y direction) perpendicular to the substrate 1 to the inside of the epitaxial layer 2 and does not penetrate the epitaxial layer 2 .

[0093] In step S300, refer to Figure 8 , a breakdown protection material layer 51 is formed in the gate trench G.

[0094] By way of example, the formation process of the breakdown protection material layer 51 includes but is not limited to a filling process and the like.

[0095] By way of example, the material of the breakdown protection material layer 51 includes oxide; the material of the breakdown protection layer 51 may be, for example, silicon dioxide (SiO 2 ) or the like.

[0096] In step S400, refer to Fig. 9, well regions 3 are formed on both sides of the breakdown protection material layer 51 in a second direction (eg, X direction) parallel to the substrate 1 .

[0097] By way of example, the formation process of the well region 3 includes but is not limited to an ion implantation (IMP) process and the like.

[0098] For some examples, see Fig. 9 , a size of the breakdown protection material layer 51 in a first direction (eg, Y direction) perpendicular to the substrate 1 is larger than a size of the well region 3 in the first direction (eg, Y direction) perpendicular to the substrate 1 .

[0099] In some embodiments, after step S400 , the method for manufacturing a semiconductor structure further includes the following step S410 .

[0100] In step S410, refer to Fig.10 , a source region 8 is formed in the well region 3 on both sides of the gate trench G in a direction parallel to the substrate 1 .

[0101] By way of example, the process for forming the source region 8 includes, but is not limited to, an ion implantation (IMP) process and the like.

[0102] For example, see Fig.10 The well region 3 is located on a side of the source region 8 that is away from the gate structure 6 in a second direction (eg, X direction) parallel to the substrate 1 ; the well region 3 is also located on a side of the source region 8 that is away from the surface of the substrate 1 in a first direction (eg, Y direction) perpendicular to the substrate 1 .

[0103] In step S500, refer to Fig.11 , the breakdown protection material layer 51 is etched so that the breakdown protection material layer 51 retained at the bottom of the gate trench G correspondingly constitutes the breakdown protection layer 5 .

[0104] For example, the etching process for breaking through the protective material layer 51 includes, but is not limited to, an isotropic etching process; the etching process for breaking through the protective material layer 51 may be, for example, a wet etching process.

[0105] It should be noted that the surface of the breakdown protection layer 5 away from the epitaxial layer 2 in the first direction perpendicular to the substrate 1 (for example, the Y direction) is lower than the surface of the well region 3 close to the epitaxial layer 2 in the first direction perpendicular to the substrate 1 (for example, the Y direction), or is flush with the surface of the well region 3 close to the substrate 1 in the first direction perpendicular to the substrate 1 (for example, the Y direction); that is, the breakdown protection layer 5 is located below the well region 3 in the first direction perpendicular to the substrate 1 (for example, the Y direction). In this way, the breakdown protection layer 5 in the embodiment of the present application can reduce the gate leakage current without affecting the on-off of the P well, and effectively disperse the electric field at the bottom of the trench and reduce the peak electric field, thereby improving the breakdown voltage of the semiconductor device and ensuring the withstand voltage performance of the semiconductor device with the trench gate structure 6.

[0106] In step S600 , a gate structure 6 is formed on a side of the breakdown protection layer 5 facing away from the substrate 1 ; the gate structure 6 is embedded in the gate trench G.

[0107] In some embodiments, step S600 includes the following steps S610 to S630.

[0108] In step S610, refer to Fig.12 , a gate dielectric material layer 621 is formed at least on the sidewall of the gate trench G and the surface of the substrate 1 .

[0109] By way of example, the formation process of the gate dielectric material layer 621 includes but is not limited to a deposition process and the like.

[0110] For example, the material of the gate dielectric material layer 621 includes but is not limited to an insulating material; the material of the gate dielectric layer 62 may be, for example, an oxide, such as silicon dioxide (SiO 2 ).

[0111] In step S620, refer to Fig.12 A gate conductive material layer 611 is formed at least on the surface of the gate dielectric material layer 621 and the surface of the breakdown protection material layer 51 on the side away from the epitaxial layer 2 in the direction perpendicular to the substrate 1 ; at least a portion of the gate conductive material layer 611 is embedded in the gate trench G.

[0112] By way of example, the formation process of the gate conductive material layer 611 includes but is not limited to a deposition process and the like.

[0113] By way of example, the material of the gate conductive material layer 611 includes, but is not limited to, polysilicon (Poly).

[0114] In step S630, refer to Fig.13 , grind the gate dielectric material layer 621 and the gate conductive material layer 611 so that the portion of the gate dielectric material layer 621 retained in the gate trench G corresponds to the gate dielectric layer 62, and the portion of the gate conductive material layer 611 retained in the gate trench G corresponds to the gate conductive layer 61, so as to form a gate structure 6.

[0115] For example, the polishing process of the gate dielectric material layer 621 and the gate conductive material layer 611 includes but is not limited to a chemical mechanical polishing (Chemical Mechanical Polishing, for short) process.

[0116] By way of example, a surface of the gate structure 6 facing away from the substrate 1 in a first direction (eg, Y direction) perpendicular to the substrate 1 is flush with the surface of the substrate 1 .

[0117] In step S700, refer to Figure 1 A drain structure 7 is formed on a side of the substrate 1 away from the gate structure 6 in a first direction (eg, Y direction) perpendicular to the substrate 1 .

[0118] By way of example, the material of the drain structure 7 includes, but is not limited to, a conductive material; the material of the drain structure 7 may be, for example, a conductive metal.

[0119] By way of example, the process for forming the drain structure 7 includes, but is not limited to, an electroplating process.

[0120] It should be noted that the drain structure 7 is formed on a side of the substrate 4 that is away from the epitaxial layer 2 in a direction perpendicular to the base 1 .

[0121] In the description of this specification, the description with reference to the terms "some embodiments", "some examples", "exemplarily", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0122] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0123] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application.

Claims

1. A semiconductor structure, characterized in that: include: substrate; The substrate includes an epitaxial layer and a well region located on one side of the epitaxial layer; A gate trench, located on a side of the substrate having the well region; The gate trench at least penetrates the well region and extends into the epitaxial layer in a direction perpendicular to the substrate; A breakdown protection layer, located at the bottom of the gate trench; A gate structure, located on a side of the breakdown protection layer away from the substrate and embedded in the gate trench; The drain structure is located at a side of the substrate that is away from the gate structure in a direction perpendicular to the substrate.

2. The semiconductor structure according to claim 1, characterized in that: The surface of the breakdown protection layer facing away from the epitaxial layer in a direction perpendicular to the substrate is lower than the surface of the well region close to the epitaxial layer in a direction perpendicular to the substrate, or is flush with the surface of the well region close to the substrate in a direction perpendicular to the substrate.

3. The semiconductor structure according to claim 1, characterized in that: The semiconductor structure further comprises: The source region is located in the well region on both sides of the gate trench in a direction parallel to the substrate.

4. The semiconductor structure according to claim 1, characterized in that: The substrate further comprises: A substrate, located on a side of the epitaxial layer away from the well region in a direction perpendicular to the base; The drain structure is located on a side of the substrate that is away from the epitaxial layer in a direction perpendicular to the base.

5. The semiconductor structure according to claim 1, characterized in that: The gate structure comprises: A gate dielectric layer, at least located on a sidewall of the gate trench; The gate conductive layer covers the gate dielectric layer and the breakdown protection layer and fills the gate trench.

6. The semiconductor structure according to claim 1, characterized in that The material of the breakdown protection layer includes insulating material.

7. A method for manufacturing a semiconductor structure, characterized in that: include: providing a substrate; The substrate includes an epitaxial layer; forming a gate trench in the epitaxial layer; The gate trench extends in a direction perpendicular to the substrate; forming a breakdown protection material layer in the gate trench; forming well regions on both sides of the breakdown protection material layer in a direction parallel to the substrate; Etching the breakdown protection material layer so that the breakdown protection material layer retained at the bottom of the gate trench correspondingly constitutes a breakdown protection layer; A gate structure is formed on a side of the breakdown protection layer away from the substrate; the gate structure is embedded in the gate trench; A drain structure is formed on a side of the substrate that is away from the gate structure in a direction perpendicular to the substrate.

8. The method for manufacturing a semiconductor structure according to claim 7, characterized in that: After forming the well regions on both sides of the breakdown protection material layer in a direction parallel to the substrate, the method for manufacturing the semiconductor structure further includes: A source region is formed in the well region on both sides of the gate trench in a direction parallel to the substrate.

9. The method for manufacturing a semiconductor structure according to claim 7, characterized in that: The providing of a substrate comprises: providing a substrate; forming an epitaxial layer on one side of the substrate; Wherein, the drain structure is formed on a side of the substrate away from the epitaxial layer in a direction perpendicular to the base.

10. The method for manufacturing a semiconductor structure according to claim 7, characterized in that: The gate structure is formed on a side of the breakdown protection layer away from the substrate, comprising: forming a gate dielectric material layer at least on the sidewalls of the gate trench and the surface of the substrate; A gate conductive material layer is formed at least on the surface of the gate dielectric material layer and on the surface of the breakdown protection material layer which is away from the epitaxial layer in a direction perpendicular to the substrate; at least a portion of the gate conductive material layer is embedded in the gate trench; The gate dielectric material layer and the gate conductive material layer are ground so that the portion of the gate dielectric material layer remaining in the gate trench corresponds to a gate dielectric layer, and the portion of the gate conductive material layer remaining in the gate trench corresponds to a gate conductive layer, so as to form the gate structure.

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