Semiconductor structure and forming method thereof

Abstract

The invention provides a semiconductor structure and a forming method thereof, and the method comprises the steps: providing a substrate which is provided with a first device region and a second device region; a first epitaxial structure layer and a second epitaxial structure layer are formed on the substrate, the first epitaxial structure layer is located on the substrate of the first device region, and the second epitaxial structure layer is located on the substrate of the second device region; a first gate structure and a second gate structure are formed on the substrate, the first gate structure surrounds and covers the side wall of the first epitaxial structure layer, and the second gate structure surrounds and covers the side wall of the second epitaxial structure layer. By adopting the technical scheme, the control capability of the gate structure can be improved, and the electrical performance of the semiconductor structure is further improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] Complementary Metal Oxide Semiconductor (CMOS) is one of the most important components in modern electronic technology. It has the characteristics of high integration, low power consumption and strong compatibility. It is widely used in computers, communications, consumer electronics, automotive electronics, industrial control, medical equipment and other fields.

[0003] CMOS improves integration and processing speed by supporting smaller manufacturing processes, bringing better energy efficiency and cost-effectiveness. However, as the size of devices continues to shrink, the size of the gate structure becomes smaller and smaller, the conductive channel under the gate structure becomes shorter and shorter, and the control ability of the gate structure decreases. Summary of the invention

[0004] In view of this, the present invention provides a semiconductor structure and a method for forming the same, which can improve the control capability of the gate structure and further improve the electrical performance of the semiconductor structure.

[0005] The present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate having a first device region and a second device region; forming a first epitaxial structure layer and a second epitaxial structure layer on the substrate, the first epitaxial structure layer being located on the substrate in the first device region, and the second epitaxial structure layer being located on the substrate in the second device region; and forming a first gate structure and a second gate structure on the substrate respectively, the first gate structure surrounding and covering the sidewalls of the first epitaxial structure layer, and the second gate structure surrounding and covering the sidewalls of the second epitaxial structure layer.

[0006] The present invention also provides a semiconductor structure, comprising: a substrate, the substrate having a first device region and a second device region; a first epitaxial structure layer, located on the substrate in the first device region; a second epitaxial structure layer, located on the substrate in the second device region; a first gate structure, the first gate structure surrounding and covering the side walls of the first epitaxial structure layer; and a second gate structure, the second gate structure surrounding and covering the side walls of the second epitaxial structure layer.

[0007] Compared with the prior art, the technical solution of the present invention has the following advantages: In the method for forming a semiconductor structure provided by the present invention, a first epitaxial structure layer is formed on the substrate of the first device region, and a second epitaxial structure layer is formed on the substrate of the second device region, which reduces the size of the first epitaxial structure layer and the second epitaxial structure layer and has better doping density and uniformity, so that when at least one layer of the first epitaxial layer and at least one layer of the second epitaxial layer are used as channel layers, the influence of the short channel effect can be reduced, and the first gate structure surrounds and covers the side wall of the first epitaxial structure layer, increasing the contact area between the first gate structure and the first epitaxial structure layer, and the second gate structure surrounds and covers the side wall of the second epitaxial structure layer, increasing the contact area between the second gate structure and the second epitaxial structure layer, so that the first gate structure and the second gate structure have stronger control capabilities, thereby being able to improve the electrical performance of the semiconductor structure.

[0008] In the semiconductor structure provided by the present invention, the first epitaxial structure layer is located on the substrate of the first device region, and the second epitaxial structure layer is located on the substrate of the second device region, which reduces the size of the first epitaxial structure layer and the second epitaxial structure layer and has better doping density and uniformity, so that when at least one layer of the first epitaxial layer and at least one layer of the second epitaxial layer are used as channel layers, the influence of the short channel effect can be reduced, and the first gate structure surrounds and covers the side wall of the first epitaxial structure layer, increasing the contact area between the first gate structure and the first epitaxial structure layer, and the second gate structure surrounds and covers the side wall of the second epitaxial structure layer, increasing the contact area between the second gate structure and the second epitaxial structure layer, so that the first gate structure and the second gate structure have stronger control capabilities, thereby being able to improve the electrical performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figures 1 to 17 A schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention is shown. DETAILED DESCRIPTION

[0010] As described in the background art, as the size of devices continues to shrink, the size of the gate structure becomes smaller and smaller, the conductive channel under the gate structure becomes shorter and shorter, and the control ability of the gate structure decreases.

[0011] In one application scenario, in order to reduce the impact of the short channel effect, semiconductor processes have gradually begun to shift from planar MOSFETs to three-dimensional transistors with higher integration, such as all-around gate transistors (GAA).

[0012] However, as the process node is further reduced, due to the limitations of photolithography machines and etching processes, the size of the conductive channel cannot meet the process requirements, and blindly reducing the channel size will produce a short channel effect, affecting device quality.

[0013] In order to solve the above technical problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate having a first device region and a second device region; forming a first epitaxial structure layer and a second epitaxial structure layer on the substrate, the first epitaxial structure layer being located on the substrate in the first device region, and the second epitaxial structure layer being located on the substrate in the second device region; forming a first gate structure and a second gate structure on the substrate respectively, the first gate structure surrounding and covering the sidewalls of the first epitaxial structure layer, and the second gate structure surrounding and covering the sidewalls of the second epitaxial structure layer.

[0014] By adopting the method for forming a semiconductor structure provided by the present invention, a first epitaxial structure layer is formed on the substrate of the first device region, and a second epitaxial structure layer is formed on the substrate of the second device region. By laying out along the normal direction of the substrate, the sizes of the first epitaxial structure layer and the second epitaxial structure layer are reduced, and the doping density and uniformity are better, so that when at least one layer of the first epitaxial layer and at least one layer of the second epitaxial layer are used as channel layers, the influence of the short channel effect can be reduced, and the first gate structure surrounds and covers the side wall of the first epitaxial structure layer, thereby increasing the contact area between the first gate structure and the first epitaxial structure layer, and the second gate structure surrounds and covers the side wall of the second epitaxial structure layer, thereby increasing the contact area between the second gate structure and the second epitaxial structure layer, so that the first gate structure and the second gate structure have stronger control capabilities, thereby being able to improve the electrical performance of the semiconductor structure.

[0015] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and understandable, the present invention is described below with reference to the accompanying drawings.

[0016] Figures 1 to 17 1 is a schematic diagram of the structure corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention, wherein: Fig.17 is a schematic diagram of a top view of a semiconductor structure of the present invention, Figures 1 to 16 correspond Fig.17 A cross-sectional view along A-A1 in FIG.

[0017] See also Figure 1 , providing a substrate 100, wherein the substrate 100 may have a first device region I and a second device region II.

[0018] The substrate 100 may provide a process operation basis for a formation process of a semiconductor structure, wherein the semiconductor structure may include a CMOS transistor.

[0019] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as silicon on insulator substrate or germanium on insulator substrate. The material of the substrate may be a material suitable for process requirements or easy to integrate.

[0020] The semiconductor substrate may also be a silicon-on-insulator structure, such as silicon-on-insulator (SOI), or a germanium-on-insulator structure, such as germanium-on-insulator; the semiconductor substrate may also include an alloy semiconductor structure, such as GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP or a combination thereof; the semiconductor substrate may also be a lightly doped substrate or a substrate on which an epitaxial layer is grown.

[0021] In this embodiment, the first device region I of the substrate 100 is used to form a first type transistor, and the second device region II of the substrate 100 is used to form a second type transistor.

[0022] In a specific embodiment, the first device region I is used to form an NMOS transistor, and the second device region II is used to form a PMOS transistor; or, the first device region I is used to form a PMOS transistor, and the second device region II is used to form an NMOS transistor.

[0023] In this embodiment, an example is given for illustrative description by taking the formation of an NMOS transistor in the first device region I and the formation of a PMOS transistor in the second device region II as an example.

[0024] See next Figure 1 In the step of providing the substrate 100, the substrate 100 further has an isolation region III, and the isolation region III is located between the first device region I and the second device region II.

[0025] In subsequent steps, an isolation structure 140 may be formed in the isolation region III (see Fig.10 ).

[0026] See also Figures 2 to 7 A first epitaxial structure layer 132 and a second epitaxial structure layer 134 are formed on the substrate 100, wherein the first epitaxial structure layer 132 is located on the substrate 100 in the first device region I, and the second epitaxial structure layer 134 is located on the substrate 100 in the second device region II.

[0027] The first epitaxial structure layer 132 may be used as a source, a drain, and a channel layer in the first type transistor.

[0028] In addition, the first epitaxial structure layer 132 is arranged along the normal direction of the substrate 100, which can reduce the size of the epitaxial layer and is not limited by the lithography machine. Moreover, the source, drain, and channel layer are all located above the substrate 100, which can reduce the short channel effect.

[0029] The second epitaxial structure layer 134 may serve as a source, a drain, and a channel layer in the second type transistor.

[0030] In addition, the second epitaxial structure layer 134 is arranged along the normal direction of the substrate 100, which can reduce the size of the epitaxial layer and is not limited by the lithography machine. Moreover, the source, drain, and channel layer are all located above the substrate 100, which can reduce the short channel effect.

[0031] In this embodiment, the steps of forming the first epitaxial structure layer 132 and the second epitaxial structure layer 134 on the substrate 100 may include: See also Figures 2 to 6 A first initial epitaxial structure layer 116 and a second initial epitaxial structure layer 130 are formed on the substrate 100 , and sidewalls of the first initial epitaxial structure layer 116 and the second initial epitaxial structure layer 130 are in contact with each other.

[0032] The first initial epitaxial structure layer 116 is used to form a first epitaxial structure layer 132 .

[0033] The second initial epitaxial structure layer 130 is used to form a second epitaxial structure layer 134 .

[0034] In this embodiment, for the first initial epitaxial structure layer 116 and the second initial epitaxial structure layer 130 that are in contact with each other, the doping types of the corresponding epitaxial layers are different.

[0035] For example, if the epitaxial layer in the first initial epitaxial structure layer 116 is doped with n-type ions, the epitaxial layer in the second initial epitaxial structure layer 130 is doped with p-type ions.

[0036] In this embodiment, after the first initial epitaxial structure layer 116 is formed, the second initial epitaxial structure layer 130 is formed.

[0037] Accordingly, see Figures 2 to 6 , the forming method may include: See also Figure 2 and Figure 3 , a first blocking layer 104 is formed on the substrate 100 in the second device area II, and the substrate 100 in the first device area I is exposed.

[0038] In other words, the first blocking layer 104 exposes a region for forming the first initial epitaxial structure layer 116 .

[0039] In this embodiment, the first shielding layer 104 is formed by chemical vapor deposition. The film layer formed by chemical vapor deposition is thin and uniform, and has a dense structure, which is beneficial to improving the covering ability of the first shielding layer 104.

[0040] In this embodiment, the material of the first shielding layer 104 is silicon nitride.

[0041] See next Figure 2 Before forming the first blocking layer 104 , a first covering layer 102 is formed, and the first covering layer 102 covers the substrate 100 of the first device region I.

[0042] By forming the first covering layer 102 , the first blocking layer 104 can be prevented from being formed on the substrate 100 in the first device region I.

[0043] In this embodiment, the first cover layer 102 needs to be removed later, so the first cover layer 102 uses a material that is easy to remove. To this end, in this embodiment, the material of the first cover layer 102 includes photoresist, amorphous carbon, an organic dielectric layer material, a bottom anti-reflection coating material, a dielectric anti-reflection layer material, a deep ultraviolet light absorbing silicon oxide material, or a silicon-containing anti-reflection coating material.

[0044] More specifically, before forming the multi-layer first initial epitaxial layer, the first capping layer 102 is removed.

[0045] In this embodiment, a cleaning process is used to remove the first covering layer 102 .

[0046] See also Figure 4 , a plurality of first initial epitaxial layers are formed on the substrate 100 of the first device region I (as a non-limiting example, in this embodiment, the number of the first initial epitaxial layers is at least 3, for example, the plurality of first initial epitaxial layers includes a first first initial epitaxial layer 106A, a second first initial epitaxial layer 110A and a third first initial epitaxial layer 114A).

[0047] Each first initial epitaxial layer provides a process basis for the formation of film layers such as channel layers and source-drain doping layers. In other words, the first initial epitaxial layer can be used as a film layer structure with different or same functions in the semiconductor structure.

[0048] In this embodiment, each first initial epitaxial layer is formed by an epitaxial process, and a doping treatment is performed during the epitaxial growth process.

[0049] In other words, when forming any first initial epitaxial layer, the doping operation is performed while the epitaxial process is performed. On the one hand, the process parameters of the epitaxial process are controllable, and the first initial epitaxial layers with different thicknesses can be formed, thereby reducing the thickness of part or all of the first initial epitaxial layers; on the other hand, the epitaxial process and the doping operation are performed simultaneously, and the first initial epitaxial layer formed by epitaxial growth has better doping density and uniformity, and the uniformity of doping concentration at different positions of the same first initial epitaxial layer is improved, which is conducive to reducing the short channel effect.

[0050] In this embodiment, when the epitaxial process is used to form each first initial epitaxial layer, in any two adjacent first initial epitaxial layers, the upper first initial epitaxial layer uses the top surface of the lower first initial epitaxial layer as the growth basis, and the bottom first initial epitaxial layer uses the top surface of the substrate as the growth basis.

[0051] In other words, the top surface of the substrate 100 serves as the initial growth basis for the entire semiconductor structure. The first first initial epitaxial layer 106A takes the top surface of the substrate 100 as the growth basis, and the subsequently formed second first initial epitaxial layer 108A takes the top surface of the first first initial epitaxial layer 106A as the growth basis.

[0052] In this solution, the surface of the substrate 100 is relatively flat, so that the surface of the first initial epitaxial layer 106A is flat. On this basis, the surface of any epitaxial layer is relatively flat, which reduces the resistance of the interface between the first initial epitaxial layer 106A and the substrate 100, and the resistance of the interface between adjacent epitaxial layers, thereby improving the electrical performance of the semiconductor structure.

[0053] In this embodiment, the epitaxial process may include an atomic layer deposition process or a molecular beam epitaxy process.

[0054] In this embodiment, for any first initial epitaxial layer, the formation step may include: forming multiple sub-first initial epitaxial layers in sequence, and performing doping treatment in the step of forming any sub-first initial epitaxial layer, wherein in the step of each first initial epitaxial layer, the doping type and doping concentration are the same to further improve the doping uniformity of the first initial epitaxial layer.

[0055] In this embodiment, each first initial epitaxial layer has its own doping type, so that the doping type between adjacent first initial epitaxial layers can be controlled. Among the three first initial epitaxial layers, the doping type of the middle epitaxial layer is different from the doping type of the upper and lower epitaxial layers. In this way, an epitaxial structure with a conductive channel can be formed by using the three epitaxial layers with the above-mentioned doping characteristics to enhance the control capability of the gate structure.

[0056] In this embodiment, the doping concentration of the first initial epitaxial layer directly affects parameters such as the conductivity and carrier mobility of the semiconductor structure. Therefore, the doping concentration of each first initial epitaxial layer can be set based on actual needs, so that each first initial epitaxial layer has its own doping concentration, that is, different first initial epitaxial layers have the same or different doping concentrations.

[0057] In practical applications, the inventors further discovered that, under the influence of temperature, there is a diffusion phenomenon between adjacent first initial epitaxial layers, and the higher the temperature, the more serious the diffusion phenomenon. Driven by the diffusion effect, the doping ions between adjacent first initial epitaxial layers will transfer, which will change the characteristics of part or all of the first initial epitaxial layers, significantly reduce the performance of the semiconductor structure, or the semiconductor structure cannot play its intended role.

[0058] As an example, if the doping concentrations of adjacent first initial epitaxial layers are different, the doping concentration of the first initial epitaxial layer with a higher doping concentration may decrease, while the doping concentration of the first initial epitaxial layer with a lower doping concentration may increase, due to the diffusion phenomenon.

[0059] As another example, if the doping types of adjacent first initial epitaxial layers are different, the doping types of the two first initial epitaxial layers may be made consistent due to the diffusion phenomenon, and the semiconductor structure may fail.

[0060] In this embodiment, the first initial epitaxial layer and the second initial epitaxial layer are formed in a relatively low temperature environment.

[0061] In some embodiments, the formation temperature of each first initial epitaxial layer is between 600 degrees Celsius and 800 degrees Celsius, for example, 650 degrees Celsius, 700 degrees Celsius, and 750 degrees Celsius.

[0062] That is, the formation temperature of any epitaxial layer is not higher than 800 degrees Celsius, so that when forming the second layer and the subsequent first epitaxial layer, the diffusion phenomenon is reduced or avoided, so that each epitaxial layer maintains its own characteristics and improves the performance of the semiconductor structure.

[0063] In this embodiment, the formation parameters of each first initial epitaxial layer may also include: a pressure of 70 Torr to 90 Torr, a flow rate of Purge MainH2 of 3200 sccm to 3800 sccm, a flow rate of Purge SlitH2 of 80 sccm to 120 sccm, a flow rate of silicon source gas of 120 sccm to 180 sccm, and at least one of an epitaxial rate of 200 angstroms / minute to 300 angstroms / minute.

[0064] In other words, by changing the formation temperature of the first initial epitaxial layer, at least one of the aforementioned parameters is adaptively adjusted, so that the silicon source gas used in the epitaxial process is adapted to the current temperature, and by reducing the epitaxial rate per unit time, the thickness uniformity of the same epitaxial layer can be improved, and the formation quality of the epitaxial layer can be improved. That is, when the generation temperature is reduced, the epitaxial rate is also reduced.

[0065] In this embodiment, the number of the first initial epitaxial layers is at least 3. By making the number of epitaxial layers greater than or equal to 3, at least a source, a drain, and a channel layer located between the source and the drain can be formed to facilitate current flow.

[0066] In this embodiment, when the number of epitaxial layers is greater than or equal to 3, the method for forming the semiconductor structure in this solution can meet the following requirements: The first initial epitaxial layer 106A is used to form a first source-drain doped layer.

[0067] The first source-drain doped layer can be used as a source or a drain of a field effect transistor. When the field effect transistor is working, the first source-drain doped layer can be used to provide a carrier source.

[0068] In this embodiment, when an NMOS transistor is formed, the first first initial epitaxial layer 106A may include an epitaxial layer doped with N-type ions, and the material of the epitaxial layer may be Si or SiC; when a PMOS transistor is formed, the first first initial epitaxial layer 106A may include an epitaxial layer doped with P-type ions, and the material of the epitaxial layer may be Si or SiGe.

[0069] In a specific embodiment, the material of the first initial epitaxial layer 106A may be Si.

[0070] The second first initial epitaxial layer 110A is used to form a first channel layer.

[0071] The first channel layer is used to provide a flow region for a carrier source.

[0072] In this embodiment, when an NMOS transistor is formed, the first channel layer may include an epitaxial layer doped with P-type ions, and the material of the second first initial epitaxial layer 110A may be Si or SiGe; when a PMOS transistor is formed, the first channel layer may include an epitaxial layer doped with N-type ions, and the material of the second first initial epitaxial layer 110A may be Si or SiC.

[0073] In a specific embodiment, the material of the second first initial epitaxial layer 110A may be Si.

[0074] The third first initial epitaxial layer 114A is used to form a second source-drain doped layer.

[0075] The second source-drain doped layer can be used as a source or a drain of a field effect transistor. When the field effect transistor is working, the second source-drain doped layer can be used to provide a carrier source.

[0076] In this embodiment, when an NMOS transistor is formed, the third first initial epitaxial layer 114A may include an epitaxial layer doped with N-type ions, and the material of the third first initial epitaxial layer 114A may be Si or SiC; when a PMOS transistor is formed, the third first initial epitaxial layer 114A may include an epitaxial layer doped with P-type ions, and the material of the third first initial epitaxial layer 114A is Si or SiGe.

[0077] In a specific embodiment, the material of the third first initial epitaxial layer 114A may be Si.

[0078] It should be pointed out that, first, when the number of first initial epitaxial layers is greater (for example, greater than 3), there are adjacent first initial epitaxial layers that play the same role, for example, two consecutive first initial epitaxial layers serve as source and drain doping layers; second, the roles of the first first initial epitaxial layer, the second first initial epitaxial layer, and the third first initial epitaxial layer listed in the above example are only for schematic illustration, which is used to indicate that there are three consecutive epitaxial layers that can serve as the basis for the generation of the source, the drain, and the channel layer between the source and the drain in the semiconductor structure, and it should not be understood as a limitation on the present invention.

[0079] In this embodiment, the first source-drain doped layer is one of the source and the drain, and the second source-drain doped layer is the other of the source and the drain.

[0080] In other words, one of the first source-drain doped layer and the second source-drain doped layer serves as a source, and the other serves as a drain.

[0081] For example, the first source-drain doped layer is used as the drain electrode, and the second source-drain doped layer is used as the source electrode. For another example, the first source-drain doped layer is used as the drain electrode, and the second source-drain doped layer is used as the source electrode.

[0082] In this embodiment, the doping type of the first source-drain doping layer is different from the doping type of the channel layer.

[0083] In a specific embodiment, the doping type of the first source-drain doping layer is N-type, and the doping type of the channel layer is P-type.

[0084] In a specific embodiment, the doping type of the first source-drain doping layer is P-type, and the doping type of the channel layer is N-type.

[0085] In this embodiment, the doping type of the second source-drain doping layer is different from the doping type of the channel layer.

[0086] In a specific embodiment, the doping type of the second source-drain doping layer is N-type, and the doping type of the channel layer is P-type.

[0087] In a specific embodiment, the doping type of the second source-drain doping layer is P-type, and the doping type of the channel layer is N-type.

[0088] It should be pointed out that, first, this scheme does not limit the doping types of the first source-drain doping layer, the second source-drain doping layer and the channel layer, as long as the doping types of the first source-drain doping layer and the channel layer are different, and the doping types of the second source-drain doping layer and the channel layer are different; second, in this scheme, when the doping type is N-type, the doping ions may include: P, As or Sb; when the doping type is P-type, the doping ions may include: B, Ga or In.

[0089] In this embodiment, the first source-drain doped layer and the second source-drain doped layer have the same doping type, and are different from the first channel layer, so that when a voltage is applied to the gate structure, the carrier (electron or hole) concentration in the first channel layer region will increase significantly, so that the region adjacent to the channel layer and the gate structure is inverted to form a conductive channel. When a voltage is applied between the first source-drain doped layer and the second source-drain doped layer, the carriers begin to move along the conductive channel under the action of the electric field to form a current.

[0090] In this embodiment, the doping concentration of the first source-drain doping layer is greater than the doping concentration of the first channel layer. Under the same electric field strength, the first source-drain doping layer with a higher doping concentration can provide more carriers and has a stronger current conduction capability.

[0091] In some embodiments, the doping concentration of the first source-drain doping layer is 10 to 100 times the doping concentration of the first channel layer.

[0092] By making the doping concentration of the first source-drain doping layer 10 to 100 times the doping concentration of the first channel layer, the selection range of the doping concentration of the first source-drain doping layer is broadened, and based on the doping concentration of the channel layer, a first source-drain doping layer adapted to the doping concentration of the channel layer can be formed.

[0093] In a specific embodiment, the doping concentration of the first source-drain doping layer can be 1E 14 atom / cm 3 To 1E 15 atom / cm 3 The doping concentration of the first channel layer can be 1E 12 atom / cm 3 To 1E13 atom / cm 3 .

[0094] In this embodiment, the doping concentration of the second source-drain doping layer is greater than the doping concentration of the first channel layer. Under the same electric field strength, the second source-drain doping layer with a higher doping concentration can provide more carriers and has a stronger current conduction capability.

[0095] In some embodiments, the doping concentration of the second source-drain doping layer is 10 to 100 times the doping concentration of the first channel layer.

[0096] By making the doping concentration of the second source-drain doping layer 10 to 100 times the doping concentration of the first channel layer, the selection range of the doping concentration of the second source-drain doping layer is broadened, and a second source-drain doping layer that matches the doping concentration of the channel layer can be formed based on the doping concentration of the channel layer.

[0097] In a specific embodiment, the doping concentration of the second source-drain doping layer can be 1E 14 atom / cm 3 To 1E 15 atom / cm 3 The doping concentration of the first channel layer can be 1E 12 atom / cm 3 To 1E 13 atom / cm 3 .

[0098] In this embodiment, the thickness of the first channel layer will directly affect the conductivity, current driving capability and switching speed of the semiconductor structure. For example, when the thickness of the first channel layer is thin, the migration time of carriers in the channel layer can be reduced, thereby improving the conductivity.

[0099] In this solution, the first channel layer is directly in contact with the first source-drain doping layer and the second source-drain doping layer, the short channel effect is not obvious, and the thickness range of the first channel layer is relatively wide, so it can be set based on process requirements to cope with different process nodes.

[0100] In a specific embodiment, the thickness of the channel layer is 10 nanometers to 50 nanometers, so that a process tool of a large technology node can be used to produce a channel layer equivalent to a smaller technology node, thereby reducing the requirements for the process tool.

[0101] It should be noted that the thickness of the channel layer described in the above example is only an example, and in the actual manufacturing process, the thickness of the channel layer can be appropriately reduced or increased. For example, the thickness of the channel layer can be 2 nanometers, 7 nanometers, etc.

[0102] In other words, the present solution adopts an epitaxial process, and the thickness of the first channel layer is controllable. The thickness of the first channel layer can meet the process requirements by setting the parameters of the epitaxial process according to the requirements of the semiconductor structure to be manufactured.

[0103] In this embodiment, the first source-drain doping layer or the second source-drain doping layer plays a role in providing carriers, and its impact on the performance of the semiconductor structure is smaller than the impact of the channel layer on the performance of the semiconductor structure. The thickness of the first source-drain doping layer or the second source-drain doping layer can be greater than the thickness of the channel layer.

[0104] In addition, a thicker first source-drain doped layer or a thicker second source-drain doped layer can generally reduce the contact resistance between the first source-drain doped layer and the channel layer, thereby increasing the carrier injection efficiency and improving the conductivity of the device.

[0105] In a specific embodiment, the thickness of the first source-drain doping layer may be 500 angstroms to 1000 angstroms.

[0106] In a specific embodiment, the thickness of the second source-drain doping layer may be 500 angstroms to 1000 angstroms.

[0107] See also Figure 4 and Figure 5 , remove the first blocking layer 104 located in the second device area II to expose the substrate 100 in the second device area II.

[0108] By removing the first blocking layer 104 , the substrate 100 in the second device region II can be exposed, so as to form the second epitaxial structure layer 134 .

[0109] In this embodiment, before removing the first shielding layer 104, see Figure 4 The formation method further includes: forming a second blocking layer 118A, wherein the second blocking layer 118A covers surfaces of the first blocking layer 104 and the first initial epitaxial structure layer 116 .

[0110] By forming the second blocking layer 118A, it is possible to avoid damage to the surface of the first initial epitaxial structure layer 116 in the subsequent step of removing the first blocking layer 104 , thereby improving the formation quality of the first initial epitaxial structure layer 116 .

[0111] In this embodiment, the formation method, materials and other parameters of the second shielding layer 118A may refer to the description of the first shielding layer 104 .

[0112] In some embodiments, after forming the second blocking layer 118A, a second capping layer 118B is further formed on the second blocking layer 118A, and the second capping layer 118B exposes the surface of the second blocking layer 118A located on the second device region II.

[0113] In this embodiment, the formation method, materials and other parameters of the second covering layer 118B may refer to the description of the first covering layer 102 .

[0114] In the step of removing the first blocking layer 104 , the second blocking layer 118A above the first blocking layer 104 is also removed, so as to completely expose the surface of the substrate 100 in the second device region II.

[0115] It should be noted that, since the second blocking layer 118A on the first initial epitaxial structure layer 116 is covered by the second cover layer 118B, when the first blocking layer 104 is removed, the second blocking layer 118A covered by the second cover layer 118B is retained. Therefore, after the second initial epitaxial structure layer 130 is formed, the second blocking layer 118A on the first initial epitaxial structure layer 116 is also removed.

[0116] See also Figure 6 , a plurality of second initial epitaxial layers are formed on the substrate 100 of the second device region II (as a non-limiting example, in this embodiment, the number of the second initial epitaxial layers is at least 3, and the plurality of second initial epitaxial layers may include a first second initial epitaxial layer 120A, a second second initial epitaxial layer 124A and a third second initial epitaxial layer 128A).

[0117] The second initial epitaxial layer provides a process basis for the formation of film layers such as a channel layer and a source-drain doping layer. In other words, the second initial epitaxial layer can be used as a film layer structure with different or same functions in a semiconductor structure.

[0118] In this embodiment, each second initial epitaxial layer is formed by an epitaxial process, and a doping process is performed during the epitaxial growth process, wherein each second initial epitaxial layer has its own doping type and doping concentration.

[0119] For more descriptions on forming each second initial epitaxial layer by using an epitaxial process, please refer to the contents about the first initial epitaxial layer in the aforementioned example.

[0120] In this embodiment, the formation temperature of each second initial epitaxial layer is between 600 degrees Celsius and 800 degrees Celsius.

[0121] Furthermore, the formation parameters of each second initial epitaxial layer also include: a pressure of 70 Torr to 90 Torr, a flow rate of Purge MainH2 of 3200 sccm to 3800 sccm, a flow rate of Purge SlitH2 of 80 sccm to 120 sccm, a flow rate of silicon source gas of 120 sccm to 180 sccm, and at least one of an epitaxial rate of 200 angstroms / minute to 300 angstroms / minute.

[0122] In other words, by changing the formation temperature of the second initial epitaxial layer, at least one of the aforementioned parameters is adaptively adjusted, so that the silicon source gas used in the epitaxial process is adapted to the current temperature, and by reducing the epitaxial rate per unit time, the thickness uniformity of the same epitaxial layer can be improved, and the formation quality of the epitaxial layer can be improved. That is, when the generation temperature is reduced, the epitaxial rate is also reduced.

[0123] In this embodiment, the number of the second initial epitaxial layers is at least 3. By making the number of epitaxial layers greater than or equal to 3, at least a source, a drain, and a channel layer located between the source and the drain can be formed to facilitate current flow.

[0124] In this embodiment, when the number of epitaxial layers is greater than or equal to 3, the method for forming the semiconductor structure in this solution can meet the following requirements: The first second initial epitaxial layer 120A is used to form a third source-drain doped layer.

[0125] The second second initial epitaxial layer 124A is used to form a second channel layer.

[0126] The third second initial epitaxial layer 128A is used to form a fourth source-drain doped layer.

[0127] In this embodiment, the thickness of the third source-drain doping layer is 500 angstroms to 1000 angstroms; the doping concentration of the third source-drain doping layer is 1E 14 atom / cm 3 To 1E 15 atom / cm 3 .

[0128] The thickness of the fourth source-drain doping layer is 500 angstroms to 1000 angstroms; the doping concentration of the fourth source-drain doping layer is 1E 14 atom / cm 3 To 1E 15 atom / cm 3 .

[0129] The thickness of the second channel layer is 10 nanometers to 50 nanometers; the doping concentration of the second channel layer is 1E 12 atom / cm 3 To 1E 13 atom / cm 3 .

[0130] For a more detailed description of the third source-drain doping layer, the second channel layer, and the fourth source-drain doping layer, reference may be made to the aforementioned description of the first initial epitaxial structure layer 116 .

[0131] In some embodiments, the first initial epitaxial structure layer 116 and the second initial epitaxial structure layer 130 differ only in that the types of doping ions in the contacting epitaxial layers are different.

[0132] See also Figure 7 , the first initial epitaxial structure layer 116 and the second initial epitaxial structure layer 130 are patterned respectively, and the remaining portion of the first initial epitaxial structure layer 116 is used as the first epitaxial structure layer 132, and the remaining portion of the second initial epitaxial structure layer 130 is used as the second epitaxial structure layer 134.

[0133] In this embodiment, after patterning, the film layer of the contact portion of the first initial epitaxial structure layer 116 and the second initial epitaxial structure layer 130 is removed at the same time, so that there is a gap between the first epitaxial structure layer 132 and the second epitaxial structure layer 134, thereby facilitating the formation of an insulating structure in the subsequent process, so that the devices on the first device area I and the devices on the second device area II are independent of each other.

[0134] In this embodiment, by performing a patterning process, the first first initial epitaxial layer 106A is used as the first first epitaxial layer 106 , the second first initial epitaxial layer 110A is used as the second first epitaxial layer 110 , and the third first initial epitaxial layer 114A is used as the third first epitaxial layer 114 .

[0135] By performing the patterning process, the first second initial epitaxial layer 120A is used as the first second epitaxial layer 120 , the second second initial epitaxial layer 124A is used as the second second epitaxial layer 124 , and the third second initial epitaxial layer 128A is used as the third second epitaxial layer 128 .

[0136] In this embodiment, see Figures 4 to 7 In the step of forming each first initial epitaxial layer by an epitaxial process, a first initial barrier layer is formed between two adjacent first initial epitaxial layers.

[0137] As an optional example, a first initial barrier layer 108A is formed between the first first initial epitaxial layer 106A and the second first initial epitaxial layer 110A, and a first initial barrier layer 112A is formed between the second first initial epitaxial layer 110A and the third first initial epitaxial layer 114A.

[0138] Accordingly, when the patterning process is performed, a portion of the first initial barrier layer is also removed to form the first barrier layer.

[0139] As an optional example, when performing the patterning process, a portion of the first preliminary barrier layer 108A is removed to form the first barrier layer 108 ; and a portion of the first preliminary barrier layer 112A is removed to form the first barrier layer 112 .

[0140] By forming a first barrier layer between any adjacent first epitaxial layers, dopants in each first epitaxial layer can be effectively prevented from diffusing into the epitaxial layer serving as the channel layer during a high-temperature process, which can suppress the short channel effect and thus improve the stability and performance of the device.

[0141] In this embodiment, when the first device region I is used to form an NMOS transistor, the material of the first barrier layer is SiC. In some other embodiments, when the first device region I is used to form a PMOS transistor, the material of the first barrier layer is SiGe.

[0142] In this embodiment, see Figures 4 to 7 In the step of forming each second initial epitaxial layer by an epitaxial process, a second initial barrier layer is formed between two adjacent second initial epitaxial layers.

[0143] As an optional example, a second initial barrier layer 122A is formed between the first second initial epitaxial layer 120A and the second second initial epitaxial layer 124A, and a second initial barrier layer 126A is formed between the second second initial epitaxial layer 124A and the third second initial epitaxial layer 128A.

[0144] Correspondingly, when performing the patterning process, a portion of the second initial barrier layer is also removed to form a second barrier layer.

[0145] As an optional example, when performing the patterning process, a portion of the second preliminary barrier layer 122A is removed to form the second barrier layer 122 ; and a portion of the second preliminary barrier layer 126A is removed to form the second barrier layer 126 .

[0146] By forming a second barrier layer between any adjacent second epitaxial layers, the dopants in each second epitaxial layer can be effectively prevented from diffusing into the epitaxial layer serving as the channel layer during the high-temperature process, which can suppress the short channel effect and thus improve the stability and performance of the device.

[0147] In this embodiment, when the second device region II is used to form a PMOS transistor, the material of the second barrier layer is SiGe. In some other embodiments, when the second device region II is used to form an NMOS transistor, the material of the second barrier layer is SiC.

[0148] In other words, the first barrier layer and the second barrier layer are made of different materials and have opposite doping types.

[0149] It should be noted that the above example is described by first forming the first initial epitaxial structure layer and then forming the second initial epitaxial structure layer. In some other embodiments, the first initial epitaxial structure layer is formed after the second initial epitaxial structure layer is formed. The specific formation process can be referred to in Figures 2 to 7 The description is different in that: the second initial epitaxial structure layer is formed first, and then the first initial epitaxial structure layer is formed.

[0150] See also Figures 8 to 14 A first gate structure 148 and a second gate structure 144 are respectively formed on the substrate 100 , wherein the first gate structure 148 surrounds and covers the sidewall of the first epitaxial structure layer 132 , and the second gate structure 144 surrounds and covers the sidewall of the second epitaxial structure layer 134 .

[0151] By making the first gate structure 148 surround and cover the sidewall of the first epitaxial structure layer 132, the contact area between the first gate structure 148 and the first epitaxial structure layer 132 is increased, so that when one of the first epitaxial layers is used as a channel layer, the control capability of the first gate structure 148 is improved.

[0152] When the device is operating, the first gate structure 148 is used to control the opening and closing of the conductive channel.

[0153] In this embodiment, the first gate structure 148 is a metal gate structure, and the first gate structure 148 may include a gate dielectric layer (not shown) and a gate electrode layer (not shown) located on the gate dielectric layer.

[0154] The gate electrode layer is used as an external electrode for electrically connecting the gate structure to an external circuit.

[0155] The material of the gate electrode layer includes one or more of titanium nitride (TiN), tantalum nitride (TaN), tantalum (Ta), titanium (Ti), titanium aluminide (TiAl), tungsten (W), aluminum (Al), titanium silicon nitride (TiSiN) and titanium aluminum carbide (TiAlC).

[0156] In this embodiment, the gate electrode layer includes one or both of a work function layer and an electrode layer.

[0157] In this embodiment, the work function layer is used to adjust the threshold voltage of the transistor. For example, when forming an NMOS transistor, the work function layer is an N-type work function layer, and the material of the N-type work function layer includes one or more of titanium aluminide and aluminum titanium carbide; when forming a PMOS transistor, the work function layer is a P-type work function layer, and the material of the P-type work function layer includes one or more of titanium nitride, tantalum nitride, and silicon titanium nitride.

[0158] The electrode layer is used to electrically connect to an external circuit. The material of the electrode layer is a conductive material, including one or more of tungsten and aluminum. In this embodiment, the material of the electrode layer is tungsten.

[0159] The gate dielectric layer is used to achieve electrical isolation between the gate electrode layer and the conductive channel.

[0160] In this embodiment, the material of the gate dielectric layer includes one or more of hafnium oxide (HfO2), zirconium oxide (ZrO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), aluminum oxide (Al2O3), silicon oxide (SiO2) and lanthanum oxide (La2O3).

[0161] In this embodiment, the gate dielectric layer includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer is a high-k dielectric material. The material of the high-k gate dielectric layer can be selected from zirconium oxide (ZrO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO) or aluminum oxide (Al2O3). In other embodiments, the gate dielectric layer may also include a gate oxide layer and a high-k gate dielectric layer located on the gate oxide layer, or the gate dielectric layer may only include a gate oxide layer.

[0162] By making the second gate structure 144 surround and cover the sidewall of the second epitaxial structure layer 134 , the contact area between the second gate structure 144 and the second epitaxial structure layer 134 is increased, so that when one of the second epitaxial layers is used as a channel layer, the control capability of the second gate structure 144 is improved.

[0163] For more description about the second gate structure 144 , reference may be made to the aforementioned redundant description about the first gate structure 148 .

[0164] In this embodiment, the steps of forming the first gate structure 148 and the second gate structure 144 on the substrate 100 may include: See also Figures 7 to 9 , a dummy gate structure 138 is formed on the substrate 100 , and the dummy gate structure 138 surrounds and covers the sidewalls of the first epitaxial structure layer 132 and the second epitaxial structure layer 134 .

[0165] In other words, the dummy gate structure 138 occupies the space on both sides of the first epitaxial structure layer 132 and the second epitaxial structure layer 134 , so as to pre-occupy the space position for the subsequent formation of the first gate structure 148 and the second gate structure 144 .

[0166] In this embodiment, the dummy gate structure 138 is a polysilicon gate structure or an amorphous silicon gate structure.

[0167] In this embodiment, the steps for forming the dummy gate structure 138 are as follows: forming a dummy gate material layer (not shown) on the substrate 100, wherein the dummy gate material layer covers the side walls and surfaces of the first epitaxial structure layer 132 and the second epitaxial structure layer 134, and fills the space on both sides of the first epitaxial structure layer 132 and the second epitaxial structure layer 134; removing the dummy gate material layer above the top of the first epitaxial structure layer 132 through a planarization process (for example, chemical mechanical polishing (CMP)), and using the remaining part of the dummy gate material layer as the dummy gate structure 138.

[0168] In this embodiment, before forming the dummy gate structure 138 , the forming method further includes: forming a gate oxide layer 136 , wherein the gate oxide layer 136 covers the sidewalls and the bottom of the first epitaxial structure layer 132 and the second epitaxial structure layer 134 .

[0169] In this embodiment, the gate oxide layer 136 may be formed by using atomic layer deposition and planarization processes.

[0170] In this embodiment, the material of the gate oxide layer 136 includes: silicon oxide or a high-k material.

[0171] Accordingly, the dummy gate structure 138 may also cover the sidewall and bottom of the gate oxide layer 136 .

[0172] See also Figures 10 to 14 , remove the dummy gate structure 138 on the side wall of the first epitaxial structure layer 132 to form a first gate opening (not shown in the figure), and form the first gate structure 148 in the first gate opening; remove the dummy gate structure 138 on the side wall of the second epitaxial structure layer 134 to form a second gate opening (not shown in the figure), and form the second gate structure 144 in the second gate opening.

[0173] In this embodiment, after the second gate structure 144 is formed, the dummy gate structure 138 on the sidewall 140 of the first epitaxial structure layer is removed.

[0174] Accordingly, the forming method may include: See also Fig.11 , a third blocking layer 142 is formed on the substrate 100 , and the third blocking layer 142 exposes the dummy gate structure 138 on the sidewall of the second epitaxial structure layer 134 .

[0175] In other words, the other regions are covered by the third shielding layer 142 .

[0176] In this embodiment, the material of the third shielding layer 142 is tantalum nitride. As one of the materials for forming the second gate structure 144, by making the material of the third shielding layer 142 tantalum nitride, when forming the second gate structure 144, there is no need to remove the third shielding layer 142 separately, which can save at least one process step.

[0177] See also Fig.12 , removing the exposed dummy gate structure 138 to form the second gate opening; and forming the second gate structure 144 in the second gate opening.

[0178] In this embodiment, after the second gate opening is formed, a second gate material layer filling the second gate opening is formed on the third blocking layer 142; through a planarization process (for example, chemical mechanical polishing (CMP)), the second gate material layer and the third blocking layer 142 above the top of the second epitaxial structure layer 134 are removed, and the second gate material layer retained in the second gate opening is used as the second gate structure 144.

[0179] See also Fig.13 , a fourth blocking layer 146 is formed on the substrate 100 , and the fourth blocking layer 146 exposes the dummy gate structure 138 on the sidewall of the first epitaxial structure layer 132 .

[0180] In other words, the other regions are covered by the fourth shielding layer 146 .

[0181] In this embodiment, the material of the fourth shielding layer 146 is tantalum nitride. As one of the materials for forming the first gate structure 148, by making the material of the fourth shielding layer 146 tantalum nitride, when forming the first gate structure 148, there is no need to remove the fourth shielding layer 146 separately, which can save at least one process step.

[0182] See also Fig.14 , removing the exposed dummy gate structure to form the first gate opening; and forming the first gate structure 148 in the first gate opening.

[0183] In this embodiment, after the first gate opening is formed, a first gate material layer filling the first gate opening is formed on the fourth blocking layer 146; through a planarization process (for example, chemical mechanical polishing (CMP)), the first gate material layer and the fourth blocking layer 146 above the top of the first epitaxial structure layer 132 are removed, and the fourth blocking layer 146 retained in the first gate opening is used as the first gate structure 148.

[0184] In this embodiment, see Fig. 9 and Fig.10After forming the dummy gate structure 138 on the substrate 100 and before forming the first gate structure 148 and / or the second gate structure 144, the formation method also includes: removing the dummy gate structure on the isolation region III to form a dummy gate opening K, and forming an isolation structure 140 in the dummy gate opening K.

[0185] When forming the dummy gate opening K, a portion of the substrate 100 is also removed. In other words, the bottom of the dummy gate opening K is located inside the substrate 100 .

[0186] In this embodiment, the isolation structure 140 is used to achieve isolation between adjacent devices. For example, the isolation structure 140 achieves isolation between adjacent transistors, such as isolation between NMOS and PMOS.

[0187] In the present embodiment, the material of the isolation structure 140 is an insulating material, for example, one or more of silicon oxide, silicon oxynitride, silicon nitride, silicon carbide, silicon carbonitride, and silicon boron carbide nitride.

[0188] In one embodiment, the material of the isolation structure 140 is silicon oxide.

[0189] It should be noted that the above example is described by first forming the second gate structure and then forming the first gate structure. In some other embodiments, the second gate structure is formed after the first gate structure is formed. The specific formation process can be found in Figures 7 to 14 Description.

[0190] In this embodiment, after forming the first gate structure and the second gate structure, a conductive structure may be further formed to lead out the first gate structure, the second gate structure, and corresponding film layers in the first epitaxial structure layer and the second epitaxial structure layer.

[0191] Specifically, for each first epitaxial layer in part or all of the first epitaxial structure layers, at least one first conductive structure is formed, and each first conductive structure is electrically connected to the corresponding first epitaxial layer.

[0192] In this embodiment, along the normal direction of the substrate surface, multiple first epitaxial layers are stacked and arranged, and when forming the first conductive structure, there is a situation where the first conductive structure is electrically connected to at least two first epitaxial layers. In this case, during the process of forming the first conductive structure, the first conductive structure needs to be electrically insulated from the epitaxial layers that are not electrically connected, so as to avoid a short circuit problem caused by the electrical connection between the first conductive structure and at least two epitaxial layers.

[0193] The first conductive structure can realize electrical connection between the first epitaxial layer and other interconnect structures or external circuits.

[0194] To facilitate understanding of the formation process of the first conductive structure in this solution, see Figures 15 to 17 , briefly explained with an example.

[0195] See also Figures 15 to 17 , the step of forming at least one first conductive structure 156 includes: A first trench G11 is formed, wherein the first trench G11 at least exposes a portion of the sidewall of the first epitaxial layer electrically connected to the first conductive structure 156 (in this embodiment, the first conductive structure 156 is electrically connected to the third first epitaxial layer 114 ).

[0196] In this embodiment, the step of forming the first groove G11 may include: forming an interlayer dielectric layer 150 on the substrate 100; removing a portion of the interlayer dielectric layer 150 to expose the surface of the top first epitaxial layer (in this embodiment, the top first epitaxial layer is the third first epitaxial layer 114); removing a portion of the thickness of the third first epitaxial layer 114 to form the first groove G11.

[0197] The first trench G11 is at least formed by the sidewall and the bottom of the third first epitaxial layer 114 , and optionally, also includes the sidewall of the interlayer dielectric layer 150 .

[0198] In this embodiment, the interlayer dielectric layer 150 is used to achieve electrical isolation between the first conductive structure, the second conductive structure, the third conductive structure and the fourth conductive structure, and is also used to achieve electrical isolation between adjacent devices.

[0199] In this embodiment, the material of the interlayer dielectric layer 150 is an insulating material, for example, the material of the interlayer dielectric layer 150 is silicon oxide. In other embodiments, the material of the interlayer dielectric layer may also be other dielectric materials such as silicon nitride or silicon oxynitride.

[0200] A first insulating layer 152 is formed on the sidewalls of the first trench G11 .

[0201] By forming the first insulating layer 152 , only the bottom of the first trench G11 is exposed, so that the first conductive plug 154 formed subsequently is only electrically connected to the third first epitaxial layer 114 , thereby reducing the probability of short circuit.

[0202] In this embodiment, the step of forming the first insulating layer 152 includes: forming a first insulating material layer in the first trench G11 ; removing the insulating material layer at the bottom of the first trench G11 , and using the remaining first insulating material layer as the first insulating layer 152 .

[0203] In a specific implementation, a conformal covering process is used to form the first insulating material layer, and an etch-back process is used to remove the insulating material layer at the bottom of the first trench G11.

[0204] In the present embodiment, the material of the first insulating layer 152 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide or silicon carbon nitride oxide, boron nitride and boron carbon nitride.

[0205] A first conductive plug 154 is formed at least in the remaining space of the first trench G11 . The first conductive plug 154 is electrically connected to the first epitaxial layer (eg, the third first epitaxial layer 114 ). The first conductive plug 154 and the first insulating layer 152 serve as the first conductive structure 156 .

[0206] In other words, the sidewall of the third first epitaxial layer 114 is covered by the first insulating layer 152 , and the first conductive plug 154 contacts the top surface of the third first epitaxial layer 114 to lead out the third first epitaxial layer 114 .

[0207] In this embodiment, the depth of the first conductive plug 154 in the third-layer first epitaxial layer 114 is 1 / 2 to 2 / 3 of the thickness of the third-layer first epitaxial layer 114. On the one hand, by ensuring that the depth of the first conductive plug 154 in the third-layer first epitaxial layer 114 does not exceed 2 / 3 of the thickness of the third-layer first epitaxial layer 114, the isolation between the first conductive plug 154 and the underlying device is improved and the difficulty of formation is reduced. On the other hand, by ensuring that the depth of the first conductive plug 154 in the third-layer first epitaxial layer 114 is not less than 1 / 2 of the thickness of the third-layer first epitaxial layer 114, the distance between the bottom of the first conductive plug 154 and the top of the third-layer first epitaxial layer 114 is moderate, and the first conductive plug 154 is only electrically connected to the third-layer first epitaxial layer 114.

[0208] In this embodiment, the material of the first conductive plug 154 includes materials with good conductive properties such as cobalt, copper, aluminum or tungsten.

[0209] It should be noted that when the epitaxial layer is the topmost epitaxial layer, the first conductive structure 156 can be directly formed in the first trench G11 .

[0210] Similarly, the description of forming the first conductive structure 162 electrically connected to the second-layer first epitaxial layer 110 can refer to the aforementioned example, except that the first trench G12 is at least composed of the sidewalls of the third-layer first epitaxial layer 114, the sidewalls and bottom of the second-layer first epitaxial layer 110, and optionally, also includes the sidewalls of the interlayer dielectric layer 150.

[0211] In other words, the bottom of the first trench G12 is located in the second first epitaxial layer 110 .

[0212] Accordingly, the first conductive structure 162 is composed of the first insulating structure 158 and the first conductive plug 160 .

[0213] It should be noted that when the first barrier layer 112 is formed, when the first trench G12 is formed, the first trench G12 also penetrates the first barrier layer 112 .

[0214] Similarly, the description of forming the first conductive structure 168 electrically connected to the first first epitaxial layer 106 can refer to the aforementioned example, except that the first trench G13 is at least composed of the sidewalls of the third first epitaxial layer 114, the sidewalls of the second first epitaxial layer 110, and the sidewalls and bottom of the first first epitaxial layer 106, and optionally, also includes the sidewalls of the interlayer dielectric layer 150.

[0215] In other words, the bottom of the first trench G13 is located in the first first epitaxial layer 106 .

[0216] Accordingly, the first conductive structure 168 is composed of the first insulating structure 164 and the first conductive plug 166 .

[0217] It should be noted that when the first barrier layers 108 and 112 are formed, when the first trench G13 is formed, the first trench G13 also penetrates the first barrier layers 108 and 112 .

[0218] In this embodiment, for each second epitaxial layer in part or all of the second epitaxial structure layers, at least one second conductive structure is formed, and each second conductive structure is electrically connected to the corresponding second epitaxial layer.

[0219] In this embodiment, multiple second epitaxial layers are stacked along the normal direction of the substrate surface, and when forming the second conductive structure, there is a situation where the second conductive structure is electrically connected to at least two second epitaxial layers. In this case, during the process of forming the second conductive structure, the second conductive structure needs to be electrically insulated from the epitaxial layers that are not electrically connected, so as to avoid a short circuit problem caused by the electrical connection between the second conductive structure and at least two epitaxial layers.

[0220] The second conductive structure can realize electrical connection between the second epitaxial layer and other interconnect structures or external circuits.

[0221] As an example, see Figures 15 to 17 , the step of forming at least one second conductive structure 174 may include: A second trench G21 is formed, wherein the second trench G21 at least exposes a portion of the sidewall of the top second epitaxial layer electrically connected to the second conductive structure 174 (in this embodiment, the second conductive structure 174 is electrically connected to the third second epitaxial layer 128 ).

[0222] In this embodiment, the step of forming the second groove G21 may include: forming an interlayer dielectric layer 150 on the substrate 100; removing a portion of the interlayer dielectric layer 150 to expose the surface of the top second epitaxial layer (in this embodiment, the top second epitaxial layer is the third second epitaxial layer 128); removing a portion of the thickness of the third second epitaxial layer 128 to form the second groove G21.

[0223] The second trench G21 is at least formed by the sidewall and the bottom of the third second epitaxial layer 128 , and optionally, also includes the sidewall of the interlayer dielectric layer 150 .

[0224] A second insulating layer 170 is formed on the sidewalls of the second trench G21 .

[0225] By forming the second insulating layer 170 , only the bottom of the second trench G21 is exposed, so that the second conductive plug 172 formed subsequently is only electrically connected to the third second epitaxial layer 128 , thereby reducing the probability of short circuit.

[0226] In this embodiment, the step of forming the second insulating layer 170 includes: forming a second insulating material layer in the second trench G11 ; removing the insulating material layer at the bottom of the second trench G21 , and using the remaining second insulating material layer as the second insulating layer 170 .

[0227] In a specific implementation, a conformal covering process is used to form the second insulating material layer, and an etch-back process is used to remove the insulating material layer at the bottom of the second trench G21.

[0228] In the present embodiment, the material of the second insulating layer 170 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide or silicon carbon nitride oxide, boron nitride and boron carbon nitride.

[0229] A second conductive plug 172 is formed at least in the remaining space of the second trench G21 . The second conductive plug 172 is electrically connected to the second epitaxial layer (eg, the third second epitaxial layer 128 ). The second conductive plug 172 and the second insulating layer 170 serve as the second conductive structure 174 .

[0230] In other words, the sidewall of the second trench G21 is covered by the second insulating layer 170 , and the second conductive plug 172 contacts the surface of the third second epitaxial layer 128 to lead out the third second epitaxial layer 128 .

[0231] In this embodiment, the material of the second conductive plug 172 includes materials with good conductive properties such as cobalt, copper, aluminum or tungsten.

[0232] It should be noted that when the epitaxial layer is the topmost epitaxial layer, the first conductive structure 174 can be directly formed in the second trench G21 .

[0233] Similarly, the description of forming the second conductive structure 180 electrically connected to the second second epitaxial layer 124 can refer to the above example, except that: The second trench G22 is at least formed by the sidewalls of the third second epitaxial layer 128, the sidewalls and bottom of the second second epitaxial layer 124, and optionally, also includes the sidewalls of the interlayer dielectric layer 150. In other words, the bottom of the second trench G22 is located in the second second epitaxial layer 124.

[0234] Accordingly, the second conductive structure 180 is composed of the second insulating structure 176 and the second conductive plug 178 .

[0235] It should be noted that when the second barrier layer 126 is formed, when the second trench G22 is formed, the second trench G22 also penetrates the second barrier layer 126 .

[0236] Similarly, the description of forming a second conductive structure 186 electrically connected to the first second epitaxial layer 120 can refer to the aforementioned example, except that the second trench G23 is at least composed of the side walls of the third second epitaxial layer 128, the side walls of the second second epitaxial layer 124, and the side walls and bottom of the first second epitaxial layer 120, and optionally, also includes the side walls of the interlayer dielectric layer 150.

[0237] In other words, the bottom of the second trench G23 is located in the first second epitaxial layer 120 .

[0238] Accordingly, the second conductive structure 186 is composed of the second insulating structure 182 and the second conductive plug 184 .

[0239] It should be noted that when the second barrier layers 126 and 122 are formed, when the second trench G23 is formed, the second trench G23 also penetrates the second barrier layers 126 and 122 .

[0240] In this embodiment, a third conductive structure 188 is formed, and the third conductive structure 188 is electrically connected to the first gate structure 148 .

[0241] In the present embodiment, the third conductive structure 188 is formed by forming a third trench G3 , and forming a third conductive structure 188 electrically connected to the first gate structure 148 in the third trench G3 .

[0242] A fourth conductive structure 190 is formed, and the fourth conductive structure 190 is electrically connected to the second gate structure 144 .

[0243] In this embodiment, the fourth conductive structure 190 is formed by forming a fourth trench G4 , and forming the fourth conductive structure 190 electrically connected to the second gate structure 144 in the fourth trench G4 .

[0244] It should be noted that Figures 15 to 17 The process of the first conductive structure shown is merely an example and is not to be construed as limiting the present invention.

[0245] It should also be noted that in this solution, the reason for leading out the epitaxial layer as the channel layer through the conductive structure is that, on the one hand, when the epitaxial layer is used as the channel layer, it does not contact the substrate, so the substrate cannot serve as a discharge channel for the channel layer; on the other hand, the distance between the conductive structures used to lead out the three epitaxial layers is relatively close, and there is a problem of charge accumulation in the channel layer. In summary, by providing a conductive structure electrically connected to the channel layer, the charge in the channel layer can be extracted and the leakage current can be reduced.

[0246] In addition, the conductive structure connected to the channel layer can be used as a ground terminal to provide a reference value for the entire semiconductor structure.

[0247] In a specific application, for example, a first conductive structure electrically connected to one of the epitaxial layers may be formed first, and then a first conductive structure electrically connected to other epitaxial layers may be formed; for another example, the steps of forming a trench and an insulating layer may be performed first, and then a first conductive plug may be formed simultaneously or in steps; for another example, the step of forming a trench may be performed first, and then a step of forming an insulating layer may be performed, and finally a first conductive plug may be formed simultaneously or in steps.

[0248] In other words, in this solution, a variety of different methods can be used to form the first conductive structure electrically connected to the epitaxial layer.

[0249] In one embodiment, the steps of forming the trench and the insulating layer are performed step by step, and then the first conductive plug is formed simultaneously.

[0250] It should be noted that, first, in the scheme of forming the trenches in steps, when forming the first trench, only the area for forming the first trench is exposed, and the other areas are in a covered state; second, when the number of epitaxial layers is other values, it can be seen that Figures 15 to 17 According to the illustrated process, a first conductive structure is formed.

[0251] It should be noted that the above describes multiple embodiment schemes provided by the embodiments of the present disclosure. The various optional methods introduced in each embodiment scheme can be combined and cross-referenced with each other without conflict, thereby extending a variety of possible embodiment schemes, which can all be considered as embodiment schemes disclosed and disclosed by the present disclosure.

[0252] The present invention also provides a semiconductor structure. Fig.16 and Fig.17 The semiconductor structure includes: a substrate 100, wherein the substrate 100 has a first device region I and a second device region II; a first epitaxial structure layer 132, located on the substrate 100 in the first device region I; a second epitaxial structure layer 134, located on the substrate 100 in the second device region II; a first gate structure 148, wherein the first gate structure 148 surrounds and covers the sidewalls of the first epitaxial structure layer 132; and a second gate structure 144, wherein the second gate structure 144 surrounds and covers the sidewalls of the second epitaxial structure layer 134.

[0253] By adopting the above-mentioned semiconductor structure, on the one hand, the setting of the first epitaxial structure layer and the second epitaxial structure layer reduces the size of each epitaxial layer and has better doping density and uniformity, so that when at least one layer of the first epitaxial layer and at least one layer of the second epitaxial layer are used as channel layers, the influence of the short channel effect can be reduced.

[0254] On the other hand, the first gate structure surrounds and covers the side wall of the first epitaxial structure layer, thereby increasing the contact area between the first gate structure and the first epitaxial structure layer, and the second gate structure surrounds and covers the side wall of the second epitaxial structure layer, thereby increasing the contact area between the second gate structure and the second epitaxial structure layer, so that the first gate structure and the second gate structure have stronger control capabilities, thereby being able to improve the electrical performance of the semiconductor structure.

[0255] The substrate 100 may provide a process operation basis for a formation process of a semiconductor structure, wherein the semiconductor structure may include a CMOS transistor.

[0256] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as silicon on insulator substrate or germanium on insulator substrate. The material of the substrate may be a material suitable for process requirements or easy to integrate.

[0257] The semiconductor substrate may also be a silicon-on-insulator structure, such as silicon-on-insulator (SOI), or a germanium-on-insulator structure, such as germanium-on-insulator; the semiconductor substrate may also include an alloy semiconductor structure, such as GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP or a combination thereof; the semiconductor substrate may also be a lightly doped substrate or a substrate on which an epitaxial layer is grown.

[0258] In this embodiment, the first device region I of the substrate 100 is used to form a first type transistor, and the second device region II of the substrate 100 is used to form a second type transistor.

[0259] In a specific embodiment, the first device region I is used to form an NMOS transistor, and the second device region II is used to form a PMOS transistor; or, the first device region I is used to form a PMOS transistor, and the second device region II is used to form an NMOS transistor.

[0260] In this embodiment, an example is given for illustrative description by taking the formation of an NMOS transistor in the first device region I and the formation of a PMOS transistor in the second device region II as an example.

[0261] The first epitaxial structure layer 132 may be used as a source, a drain, and a channel layer in the first type transistor.

[0262] In addition, the first epitaxial structure layer 132 is arranged along the normal direction of the substrate 100, which can reduce the size of the epitaxial layer and is not limited by the lithography machine. Moreover, the source, drain, and channel layer are all located above the substrate 100, which can reduce the short channel effect.

[0263] In this embodiment, the number of the first epitaxial layers in the first epitaxial structure layer 132 is at least three.

[0264] As a specific embodiment, the first epitaxial structure layer 132 may include a first layer of first epitaxial layers 106 sequentially stacked along a substrate normal direction, wherein the first layer of first epitaxial layers 106 is used to form a first source-drain doping layer.

[0265] The first source-drain doped layer can be used as a source or a drain of a field effect transistor. When the field effect transistor is working, the first source-drain doped layer can be used to provide a carrier source.

[0266] In this embodiment, when an NMOS transistor is formed, the first first epitaxial layer 106 may include an epitaxial layer doped with N-type ions, and the material of the epitaxial layer may be Si or SiC; when a PMOS transistor is formed, the first first epitaxial layer 106 may include an epitaxial layer doped with P-type ions, and the material of the epitaxial layer may be Si or SiGe.

[0267] In a specific embodiment, the material of the first epitaxial layer 106 may be Si.

[0268] The second first epitaxial layer 110 is used to form a first channel layer.

[0269] The first channel layer is used to provide a flow region for a carrier source.

[0270] In this embodiment, when an NMOS transistor is formed, the first channel layer may include an epitaxial layer doped with P-type ions, and the material of the second first epitaxial layer 110 may be Si or SiGe; when a PMOS transistor is formed, the first channel layer may include an epitaxial layer doped with N-type ions, and the material of the second first epitaxial layer 110 may be Si or SiC.

[0271] In a specific embodiment, the material of the second first epitaxial layer 110 may be Si.

[0272] The third first epitaxial layer 114 is used to form a second source-drain doped layer.

[0273] The second source-drain doped layer can be used as a source or a drain of a field effect transistor. When the field effect transistor is working, the second source-drain doped layer can be used to provide a carrier source.

[0274] In this embodiment, when an NMOS transistor is formed, the third first epitaxial layer 114 may include an epitaxial layer doped with N-type ions, and the material of the third first epitaxial layer 114 may be Si or SiC; when a PMOS transistor is formed, the third first epitaxial layer 114 may include an epitaxial layer doped with P-type ions, and the material of the third first epitaxial layer 114 is Si or SiGe.

[0275] In a specific embodiment, the material of the third first epitaxial layer 114 may be Si.

[0276] It should be pointed out that, first, when the number of first epitaxial layers is greater (for example, greater than 3), there are adjacent first epitaxial layers that play the same role, for example, two consecutive first epitaxial layers serve as source and drain doping layers; second, the roles of the first first epitaxial layer, the second first epitaxial layer and the third first epitaxial layer listed in the above example are only for illustrative purposes, which are used to indicate that there are three consecutive epitaxial layers that can serve as the basis for the generation of the source, the drain, and the channel layer between the source and the drain in the semiconductor structure, and should not be understood as a limitation on the present invention.

[0277] In this embodiment, the first source-drain doped layer is one of the source and the drain, and the second source-drain doped layer is the other of the source and the drain.

[0278] In other words, one of the first source-drain doped layer and the second source-drain doped layer serves as a source, and the other serves as a drain.

[0279] In this embodiment, the doping type of the first source-drain doping layer is different from the doping type of the channel layer.

[0280] In a specific embodiment, the doping type of the first source-drain doping layer is N-type, and the doping type of the channel layer is P-type.

[0281] In a specific embodiment, the doping type of the first source-drain doping layer is P-type, and the doping type of the channel layer is N-type.

[0282] In this embodiment, the doping type of the second source-drain doping layer is different from the doping type of the channel layer.

[0283] In a specific embodiment, the doping type of the second source-drain doping layer is N-type, and the doping type of the channel layer is P-type.

[0284] In a specific embodiment, the doping type of the second source-drain doping layer is P-type, and the doping type of the channel layer is N-type.

[0285] It should be pointed out that, first, this scheme does not limit the doping types of the first source-drain doping layer, the second source-drain doping layer and the channel layer, as long as the doping types of the first source-drain doping layer and the channel layer are different, and the doping types of the second source-drain doping layer and the channel layer are different; second, in this scheme, when the doping type is N-type, the doping ions may include: P, As or Sb; when the doping type is P-type, the doping ions may include: B, Ga or In.

[0286] In this embodiment, the first source-drain doped layer and the second source-drain doped layer have the same doping type, and are different from the first channel layer, so that when a voltage is applied to the gate structure, the carrier (electron or hole) concentration in the first channel layer region will increase significantly, so that the region adjacent to the channel layer and the gate structure is inverted to form a conductive channel. When a voltage is applied between the first source-drain doped layer and the second source-drain doped layer, the carriers begin to move along the conductive channel under the action of the electric field to form a current.

[0287] In this embodiment, the doping concentration of the first source-drain doping layer is greater than the doping concentration of the first channel layer. Under the same electric field strength, the first source-drain doping layer with a higher doping concentration can provide more carriers and has a stronger current conduction capability.

[0288] In some embodiments, the doping concentration of the first source-drain doping layer is 10 to 100 times the doping concentration of the first channel layer.

[0289] By making the doping concentration of the first source-drain doping layer 10 to 100 times the doping concentration of the first channel layer, the selection range of the doping concentration of the first source-drain doping layer is broadened, and based on the doping concentration of the channel layer, a first source-drain doping layer adapted to the doping concentration of the channel layer can be formed.

[0290] In a specific embodiment, the doping concentration of the first source-drain doping layer can be 1E14 atom / cm 3 To 1E 15 atom / cm 3 The doping concentration of the first channel layer can be 1E 12 atom / cm 3 To 1E 13 atom / cm 3 .

[0291] In this embodiment, the doping concentration of the second source-drain doping layer is greater than the doping concentration of the first channel layer. Under the same electric field strength, the second source-drain doping layer with a higher doping concentration can provide more carriers and has a stronger current conduction capability.

[0292] In some embodiments, the doping concentration of the second source-drain doping layer is 10 to 100 times the doping concentration of the first channel layer.

[0293] By making the doping concentration of the second source-drain doping layer 10 to 100 times the doping concentration of the first channel layer, the selection range of the doping concentration of the second source-drain doping layer is broadened, and a second source-drain doping layer that matches the doping concentration of the channel layer can be formed based on the doping concentration of the channel layer.

[0294] In a specific embodiment, the doping concentration of the second source-drain doping layer can be 1E 14 atom / cm 3 To 1E 15 atom / cm 3 The doping concentration of the first channel layer can be 1E 12 atom / cm 3 To 1E 13 atom / cm 3 .

[0295] In this embodiment, the thickness of the first channel layer will directly affect the conductivity, current driving capability and switching speed of the semiconductor structure. For example, when the thickness of the first channel layer is thin, the migration time of carriers in the channel layer can be reduced, thereby improving the conductivity.

[0296] In this solution, the first channel layer is directly in contact with the first source-drain doping layer and the second source-drain doping layer, the short channel effect is not obvious, and the thickness range of the first channel layer is relatively wide, so it can be set based on process requirements to cope with different process nodes.

[0297] In a specific embodiment, the thickness of the first channel layer is 10 nanometers to 50 nanometers, so that a process tool of a large technology node can be used to produce a channel layer equivalent to a smaller technology node, thereby reducing the requirements for the process tool.

[0298] It should be noted that the thickness of the channel layer described in the above example is only an example, and in the actual manufacturing process, the thickness of the channel layer can be appropriately reduced or increased. For example, the thickness of the channel layer can be 2 nanometers, 7 nanometers, etc.

[0299] In other words, the present solution adopts an epitaxial process, and the thickness of the first channel layer is controllable. The thickness of the first channel layer can meet the process requirements by setting the parameters of the epitaxial process according to the requirements of the semiconductor structure to be manufactured.

[0300] In this embodiment, the first source-drain doping layer or the second source-drain doping layer plays a role in providing carriers, and its impact on the performance of the semiconductor structure is smaller than the impact of the channel layer on the performance of the semiconductor structure. The thickness of the first source-drain doping layer or the second source-drain doping layer can be greater than the thickness of the channel layer.

[0301] In addition, a thicker first source-drain doped layer or a thicker second source-drain doped layer can generally reduce the contact resistance between the first source-drain doped layer and the channel layer, thereby increasing the carrier injection efficiency and improving the conductivity of the device.

[0302] In a specific embodiment, the thickness of the first source-drain doping layer may be 500 angstroms to 1000 angstroms.

[0303] In a specific embodiment, the thickness of the second source-drain doping layer may be 500 angstroms to 1000 angstroms.

[0304] In this embodiment, the semiconductor structure further includes: a first barrier layer located between any adjacent first epitaxial layers in the first epitaxial structure layer.

[0305] As an optional example, the first barrier layer 108 is located between the first first epitaxial layer 106 and the second first epitaxial layer 110 ; the first barrier layer 112 is located between the second first epitaxial layer 110 and the third first epitaxial layer 114 .

[0306] By forming a first barrier layer between any adjacent first epitaxial layers, dopants in each first epitaxial layer can be effectively prevented from diffusing into the epitaxial layer serving as the channel layer during a high-temperature process, which can suppress the short channel effect and thus improve the stability and performance of the device.

[0307] The second epitaxial structure layer 134 may serve as a source, a drain, and a channel layer in the second type transistor.

[0308] In addition, the second epitaxial structure layer 134 is arranged along the normal direction of the substrate 100, which can reduce the size of the epitaxial layer and is not limited by the lithography machine. Moreover, the source, drain, and channel layer are all located above the substrate 100, which can reduce the short channel effect.

[0309] In this embodiment, the number of the second epitaxial layers in the second epitaxial structure layer 134 is at least three.

[0310] As a specific embodiment, the second epitaxial structure layer 134 may include a first second epitaxial layer 120 stacked in sequence along the normal direction of the substrate, wherein the first first epitaxial layer 106 is used to form a third source-drain doped layer; a second second epitaxial layer 124, wherein the second second epitaxial layer 124 is used to form a second source-drain doped layer; and a third second epitaxial layer 128, wherein the third second epitaxial layer 128 is used to form a fourth source-drain doped layer.

[0311] In this embodiment, the first source-drain doped layer is one of the source and the drain, and the second source-drain doped layer is the other of the source and the drain.

[0312] In this embodiment, the thickness of the third source-drain doping layer is 500 angstroms to 1000 angstroms; the doping concentration of the third source-drain doping layer is 1E 14 atom / cm 3 To 1E 15 atom / cm 3 .

[0313] The thickness of the fourth source-drain doping layer is 500 angstroms to 1000 angstroms; the doping concentration of the fourth source-drain doping layer is 1E 14 atom / cm 3 To 1E 15 atom / cm 3 .

[0314] The thickness of the second channel layer is 10 nanometers to 50 nanometers; the doping concentration of the second channel layer is 1E 12 atom / cm 3 To 1E 13 atom / cm 3 .

[0315] For a more detailed description of the third source-drain doping layer, the second channel layer, and the fourth source-drain doping layer, reference may be made to the aforementioned description of the first epitaxial structure layer 132 .

[0316] In this embodiment, the semiconductor structure further includes: a second barrier layer located between any adjacent second epitaxial layers in the second epitaxial structure layer.

[0317] As an optional example, the second barrier layer 122 is located between the first second epitaxial layer 120 and the second second epitaxial layer 124 ; the second barrier layer 126 is located between the second second epitaxial layer 124 and the third second epitaxial layer 128 .

[0318] By forming a second barrier layer between any adjacent second epitaxial layers, the dopants in each second epitaxial layer can be effectively prevented from diffusing into the epitaxial layer serving as the channel layer during the high-temperature process, which can suppress the short channel effect and thus improve the stability and performance of the device.

[0319] When the device is in operation, the first gate structure 148 is used to control the opening and closing of the first conductive channel.

[0320] In this embodiment, the first gate structure 148 is a metal gate structure, and the first gate structure 148 may include a gate dielectric layer (not shown) and a gate electrode layer (not shown) located on the gate dielectric layer.

[0321] The gate electrode layer is used as an external electrode for electrically connecting the gate structure to an external circuit.

[0322] The material of the gate electrode layer includes one or more of titanium nitride (TiN), tantalum nitride (TaN), tantalum (Ta), titanium (Ti), titanium aluminide (TiAl), tungsten (W), aluminum (Al), titanium silicon nitride (TiSiN) and titanium aluminum carbide (TiAlC).

[0323] In this embodiment, the gate electrode layer includes one or both of a work function layer and an electrode layer.

[0324] In this embodiment, the work function layer is used to adjust the threshold voltage of the transistor. For example, when forming an NMOS transistor, the work function layer is an N-type work function layer, and the material of the N-type work function layer includes one or more of titanium aluminide and aluminum titanium carbide; when forming a PMOS transistor, the work function layer is a P-type work function layer, and the material of the P-type work function layer includes one or more of titanium nitride, tantalum nitride, and silicon titanium nitride.

[0325] The electrode layer is used to electrically connect to an external circuit. The material of the electrode layer is a conductive material, including one or more of tungsten and aluminum. In this embodiment, the material of the electrode layer is tungsten.

[0326] The gate dielectric layer is used to achieve electrical isolation between the gate electrode layer and the conductive channel.

[0327] In this embodiment, the material of the gate dielectric layer includes one or more of hafnium oxide (HfO2), zirconium oxide (ZrO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), aluminum oxide (Al2O3), silicon oxide (SiO2) and lanthanum oxide (La2O3).

[0328] In this embodiment, the gate dielectric layer includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer is a high-k dielectric material. The material of the high-k gate dielectric layer can be selected from zirconium oxide (ZrO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO) or aluminum oxide (Al2O3). In other embodiments, the gate dielectric layer may also include a gate oxide layer and a high-k gate dielectric layer located on the gate oxide layer, or the gate dielectric layer may only include a gate oxide layer.

[0329] When the device is working, the second gate structure 144 is used to control the opening and closing of the first conductive channel.

[0330] For more description about the second gate structure 144 , reference may be made to the aforementioned redundant description about the first gate structure 148 .

[0331] In this embodiment, the semiconductor structure may further include: a gate oxide layer 136 , wherein the gate oxide layer 136 covers the sidewalls and surfaces of the first epitaxial structure layer 132 and the second epitaxial structure layer 134 .

[0332] Accordingly, the first gate structure 148 and the second gate structure 144 may also cover the sidewall and the bottom of the gate oxide layer 136 .

[0333] The gate oxide layer serves as an insulating layer to isolate the first gate structure 148, the second gate structure 144 and the semi-substrate 100, thereby preventing leakage between the first gate structure 148 and the first channel and current leakage between the second gate structure 144 and the second channel, thereby improving voltage control characteristics.

[0334] In this embodiment, the substrate 100 further has an isolation region III, and the isolation region III is located between the first device region I and the second device region II.

[0335] Correspondingly, the semiconductor structure further includes: an isolation structure 140 , which is located on the substrate 100 in the isolation region III and contacts the sidewalls of the first gate structure 148 and the second gate structure 144 .

[0336] The isolation structure 140 is used to achieve isolation between adjacent devices. For example, the isolation structure 140 achieves isolation between adjacent transistors, such as isolation between NMOS and PMOS.

[0337] In the present embodiment, the material of the isolation structure 140 is an insulating material, for example, one or more of silicon oxide, silicon oxynitride, silicon nitride, silicon carbide, silicon carbonitride, and silicon boron carbide nitride.

[0338] In one embodiment, the material of the isolation structure 140 is silicon oxide.

[0339] In this embodiment, the bottom of the isolation structure 140 is located inside the substrate 100 .

[0340] In this embodiment, the semiconductor structure may further include: at least one first conductive structure electrically connected to the corresponding first epitaxial layer.

[0341] As an optional example, the semiconductor structure may include: a first conductive structure 156 electrically connected to the third first epitaxial layer 114 .

[0342] In this embodiment, the first conductive structure 156 includes: a first insulating layer 152, covering a portion of the side walls of the third first epitaxial layer 114 and exposing the surface of the third first epitaxial layer 114; a first conductive plug 154, covering the side walls of the first insulating layer 152 and contacting the surface of the third first epitaxial layer 114.

[0343] In the present embodiment, the material of the first insulating layer 152 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide or silicon carbon nitride oxide, boron nitride and boron carbon nitride.

[0344] The material of the first conductive plug 154 includes cobalt, copper, aluminum, tungsten or other materials with good conductive properties.

[0345] The first conductive structure 162 is electrically connected to the second first epitaxial layer 110 .

[0346] In this embodiment, the first conductive structure 162 may include: a first insulating structure 158, covering the side walls of the third first epitaxial layer 114 and part of the side walls of the second first epitaxial layer 110, and exposing the surface of the second first epitaxial layer 110; a first conductive plug 160, covering the side walls of the first insulating structure 158 and contacting the surface of the second first epitaxial layer 110.

[0347] The first conductive structure 168 is electrically connected to the first first epitaxial layer 106 .

[0348] In this embodiment, the first conductive structure 168 may include: a first insulating structure 164, covering the side walls of the third first epitaxial layer 114, the side walls of the second first epitaxial layer 110, and a portion of the first first epitaxial layer 106, and exposing the surface of the first first epitaxial layer 106; a first conductive plug 166, covering the side walls of the first insulating structure 164 and contacting the surface of the first first epitaxial layer 106.

[0349] In this embodiment, the semiconductor structure may further include: at least one second conductive structure electrically connected to the corresponding second epitaxial layer.

[0350] As an optional example, the semiconductor structure may include: a second conductive structure 174 electrically connected to the third second epitaxial layer 128 .

[0351] In this embodiment, the second conductive structure 174 includes: a second insulating layer 170, covering a portion of the side walls of the third second epitaxial layer 128 and exposing the surface of the third second epitaxial layer 128; a second conductive plug 172, covering the side walls of the second insulating layer 170 and contacting the surface of the third second epitaxial layer 128.

[0352] In the present embodiment, the material of the second insulating layer 170 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide or silicon carbon nitride oxide, boron nitride and boron carbon nitride.

[0353] The material of the second conductive plug 172 includes materials with good conductive properties such as cobalt, copper, aluminum or tungsten.

[0354] The second conductive structure 180 is electrically connected to the second second epitaxial layer 124 .

[0355] In this embodiment, the second conductive structure 180 may include: a second insulating structure 176, covering the side walls of the third second epitaxial layer 128, part of the side walls of the second second epitaxial layer 124, and exposing the surface of the second second epitaxial layer 124; a second conductive plug 178, covering the side walls of the second insulating structure 176 and contacting the surface of the second second epitaxial layer 124.

[0356] The second conductive structure 186 is electrically connected to the first second epitaxial layer 120 .

[0357] In this embodiment, the second conductive structure 186 may include: a second insulating structure 182, covering the side walls of the third second epitaxial layer 128, the side walls of the second second epitaxial layer 124, and part of the side walls of the first second epitaxial layer 120, and exposing the surface of the first second epitaxial layer 120; a second conductive plug 184, covering the side walls of the second insulating structure 182 and contacting the surface of the first second epitaxial layer 120.

[0358] The third conductive structure 188 is electrically connected to the first gate structure 148 .

[0359] The fourth conductive structure 190 is electrically connected to the second gate structure 144 .

[0360] In this embodiment, the semiconductor structure may further include: an interlayer dielectric layer 150 located on the topmost epitaxial layer and covering the side walls of the first conductive structure, the second conductive structure, the third conductive structure and the fourth conductive structure.

[0361] The interlayer dielectric layer 150 is used to achieve electrical isolation between the first conductive structure, the second conductive structure, the third conductive structure, and the fourth conductive structure, and is also used to achieve electrical isolation between adjacent devices.

[0362] In this embodiment, the material of the interlayer dielectric layer 150 is an insulating material, for example, the material of the interlayer dielectric layer 150 is silicon oxide. In other embodiments, the material of the interlayer dielectric layer may also be other dielectric materials such as silicon nitride or silicon oxynitride.

[0363] It should be noted that the semiconductor structure described in this embodiment can be formed by the formation method described in the previous embodiment, or by other formation methods. For the specific description of the semiconductor structure described in this embodiment, reference can be made to the corresponding description in the previous embodiment, and this embodiment will not be repeated here.

[0364] Although the present specification is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate having a first device region and a second device region; forming a first epitaxial structure layer and a second epitaxial structure layer on the substrate, wherein the first epitaxial structure layer is located on the substrate in the first device region, and the second epitaxial structure layer is located on the substrate in the second device region; A first gate structure and a second gate structure are respectively formed on the substrate, wherein the first gate structure surrounds and covers the sidewall of the first epitaxial structure layer, and the second gate structure surrounds and covers the sidewall of the second epitaxial structure layer.

2. The method for forming a semiconductor structure according to claim 1, wherein: The step of forming a first epitaxial structure layer and a second epitaxial structure layer on the substrate comprises: Forming a first initial epitaxial structure layer and a second initial epitaxial structure layer on the substrate, wherein side walls of the first initial epitaxial structure layer and the second initial epitaxial structure layer are in contact with each other; The first initial epitaxial structure layer and the second initial epitaxial structure layer are patterned respectively, and the remaining portion of the first initial epitaxial structure layer is used as the first epitaxial structure layer, and the remaining portion of the second initial epitaxial structure layer is used as the second epitaxial structure layer, and the first epitaxial structure layer and the second epitaxial structure layer are spaced apart.

3. The method for forming a semiconductor structure according to claim 2, wherein: After forming the first initial epitaxial structure layer, forming the second initial epitaxial structure layer; Alternatively, after forming the second initial epitaxial structure layer, the first initial epitaxial structure layer is formed.

4. The method for forming a semiconductor structure according to claim 3, characterized in that: After forming the first initial epitaxial structure layer, forming the second initial epitaxial structure layer, the forming method includes: forming a first blocking layer on the substrate of the second device area to expose the substrate of the first device area; forming a plurality of first initial epitaxial layers on the substrate in the first device region; removing the first shielding layer located in the second device area to expose the substrate in the second device area; A plurality of second initial epitaxial layers are formed on the substrate of the second device region.

5. The method for forming a semiconductor structure according to claim 4, characterized in that: Before forming the first shielding layer, forming a first covering layer, wherein the first covering layer covers the substrate of the first device region; Before forming the multi-layer first initial epitaxial layer, the first covering layer is removed; Before removing the first shielding layer, the forming method further includes: forming a second shielding layer, wherein the second shielding layer covers the surface of the first shielding layer and the first epitaxial structure layer; In the step of removing the first shielding layer, a second shielding layer above the first shielding layer is also removed; After forming the second initial epitaxial layer, the second shielding layer on the first epitaxial structure layer is removed.

6. The method for forming a semiconductor structure according to claim 2, wherein: Forming each first initial epitaxial layer by an epitaxial process, and performing doping treatment during the epitaxial growth process, wherein each first initial epitaxial layer has its own doping type and doping concentration; Each second initial epitaxial layer is formed by an epitaxial process, and a doping treatment is performed during the epitaxial growth process, wherein each second initial epitaxial layer has its own doping type and doping concentration.

7. The method for forming a semiconductor structure according to claim 6, wherein: The formation temperature of each first initial epitaxial layer is between 600 degrees Celsius and 800 degrees Celsius; The formation temperature of each second initial epitaxial layer is between 600 degrees Celsius and 800 degrees Celsius.

8. The method for forming a semiconductor structure according to claim 7, wherein: The formation parameters of each first initial epitaxial layer and / or the formation parameters of each second initial epitaxial layer also include: a pressure of 70 Torr to 90 Torr, a flow rate of PurgeMainH2 of 3200 sccm to 3800 sccm, a flow rate of Purge SlitH2 of 80 sccm to 120 sccm, a flow rate of silicon source gas of 120 sccm to 180 sccm, and at least one of an epitaxial rate of 200 angstroms / minute to 300 angstroms / minute.

9. The method for forming a semiconductor structure according to claim 6, wherein: The number of the first initial epitaxial layers is at least 3, and at least one or more of the following conditions are satisfied: a first first initial epitaxial layer, the first first initial epitaxial layer is used to form a first source-drain doped layer; a second first initial epitaxial layer, the second first initial epitaxial layer is used to form a first channel layer; a third first initial epitaxial layer, the third first initial epitaxial layer forms a second source-drain doped layer; the first source-drain doped layer is one of the source or the drain, and the second source-drain doped layer is the other of the source or the drain; The number of second initial epitaxial layers is at least 3, and at least one or more of the following conditions are satisfied: a first layer of second initial epitaxial layer, the first layer of second initial epitaxial layer is used to form a third source-drain doped layer; a second layer of second initial epitaxial layer, the second layer of second initial epitaxial layer is used to form a second channel layer; a third layer of second initial epitaxial layer, the third layer of second initial epitaxial layer forms a fourth source-drain doped layer; the third source-drain doped layer is one of the source or the drain, and the fourth source-drain doped layer is the other of the source or the drain.

10. The method for forming a semiconductor structure according to claim 6, wherein: In the step of forming each first initial epitaxial layer by an epitaxial process, a first initial barrier layer is formed between two adjacent first initial epitaxial layers; when performing the patterning process, a portion of the first initial barrier layer is also removed to form a first barrier layer; In the step of forming each second initial epitaxial layer by epitaxial process, a second initial barrier layer is formed between two adjacent second initial epitaxial layers; when performing patterning, a part of the second initial barrier layer is also removed to form a second barrier layer.

11. The method for forming a semiconductor structure according to claim 1, wherein: The steps of forming a first gate structure and a second gate structure on the substrate respectively include: forming a dummy gate structure on the substrate, wherein the dummy gate structure surrounds and covers the sidewalls of the first epitaxial structure layer and the second epitaxial structure layer; Removing the dummy gate structure on the sidewall of the first epitaxial structure layer to form a first gate opening, and forming the first gate structure in the first gate opening; The dummy gate structure on the sidewall of the second epitaxial structure layer is removed to form a second gate opening, and the second gate structure is formed in the second gate opening.

12. The method for forming a semiconductor structure according to claim 11, characterized in that: After forming the first gate structure, removing the dummy gate structure on the sidewall of the second epitaxial structure layer; Alternatively, after forming the second gate structure, the dummy gate structure on the side wall of the first epitaxial structure layer is removed.

13. The method for forming a semiconductor structure according to claim 12, wherein: After forming the second gate structure, when removing the dummy gate structure on the sidewall of the first epitaxial structure layer, the forming method includes: forming a third blocking layer on the substrate, wherein the third blocking layer exposes the dummy gate structure on the sidewall of the second epitaxial structure layer; removing the exposed dummy gate structure to form the second gate opening; forming the second gate structure in the second gate opening; forming a fourth blocking layer on the substrate, wherein the fourth blocking layer exposes the dummy gate structure on the sidewall of the first epitaxial structure layer; removing the exposed dummy gate structure to form the first gate opening; The first gate structure is formed in the first gate opening.

14. The method for forming a semiconductor structure according to claim 1, wherein: In the step of providing the substrate, the substrate further comprises an isolation region, wherein the isolation region is located between the first device region and the second device region; After forming the dummy gate structure on the substrate and before forming the first gate structure and / or the second gate structure, the forming method further includes: removing the dummy gate structure on the isolation region to form a dummy gate opening, and forming an isolation structure in the dummy gate opening.

15. The method for forming a semiconductor structure according to claim 1, wherein: The present forming method also includes: For each first epitaxial layer in part or all of the first epitaxial structure layers, at least one first conductive structure is formed, and each first conductive structure is electrically connected to the corresponding first epitaxial layer; For each second epitaxial layer in part or all of the second epitaxial structure layers, at least one second conductive structure is formed, and each second conductive structure is electrically connected to the corresponding second epitaxial layer. forming a third conductive structure, wherein the third conductive structure is electrically connected to the first gate structure; A fourth conductive structure is formed, wherein the fourth conductive structure is electrically connected to the second gate structure.

16. The method for forming a semiconductor structure according to claim 15, characterized in that: The step of forming at least one first conductive structure comprises: forming a first trench, wherein the first trench at least exposes a portion of a sidewall of a first epitaxial layer electrically connected to the first conductive structure; forming a first insulating layer on the sidewall of the first trench; forming a first conductive plug at least in a remaining space of the first trench, wherein the first conductive plug is electrically connected to the first epitaxial layer, and the first conductive plug and the first insulating layer serve as the first conductive structure; The step of forming at least one second conductive structure includes: forming a second trench, wherein the second trench at least exposes a portion of the side wall of the second epitaxial layer electrically connected to the second conductive structure; forming a second insulating layer on the side wall of the second trench; and forming a second conductive plug at least in the remaining space of the second trench, wherein the second conductive plug is electrically connected to the second epitaxial layer, and the second conductive plug and the second insulating layer serve as the second conductive structure.

17. A semiconductor structure, characterized in that: include: A substrate having a first device region and a second device region; A first epitaxial structure layer, located on the substrate of the first device region; A second epitaxial structure layer, located on the substrate of the second device region; A first gate structure, wherein the first gate structure surrounds and covers a sidewall of the first epitaxial structure layer; A second gate structure surrounds and covers a side wall of the second epitaxial structure layer.

18. The semiconductor structure according to claim 17, characterized in that: The number of first epitaxial layers in the first epitaxial structure layer is at least 3, and at least one or more of the following conditions are satisfied: a first layer of first epitaxial layer, the first layer of first epitaxial layer is used to form a first source-drain doped layer; a second layer of first epitaxial layer, the second layer of first epitaxial layer is used to form a first channel layer; a third layer of first epitaxial layer, the third layer of first epitaxial layer is used to form a second source-drain doped layer; the first source-drain doped layer is one of the source or the drain, and the second source-drain doped layer is the other of the source or the drain; The number of second epitaxial layers in the second epitaxial structure layer is at least 3, and at least one or more of the following conditions are satisfied: a first layer of second epitaxial layer, the first layer of second epitaxial layer is used to form a third source-drain doped layer; a second layer of second epitaxial layer, the second layer of second epitaxial layer is used to form a second channel layer; a third layer of second epitaxial layer, the third layer of second epitaxial layer is used to form a fourth source-drain doped layer; the third source-drain doped layer is one of the source or the drain, and the fourth source-drain doped layer is the other of the source or the drain.

19. The semiconductor structure according to claim 18, characterized in that Satisfy at least one or more of the following: A first barrier layer, located between any adjacent first epitaxial layers in the first epitaxial structure layer; A second barrier layer is located between any adjacent first epitaxial layers in the second epitaxial structure layer; The substrate further has an isolation region, and the isolation region is located between the first device region and the second device region. The semiconductor structure further includes: an isolation structure, which is located on the substrate of the isolation region and contacts the sidewalls of the first gate structure and the second gate structure; at least one first conductive structure electrically connected to the corresponding first epitaxial layer; at least one second conductive structure electrically connected to the corresponding second epitaxial layer; a third conductive structure electrically connected to the first gate structure; A fourth conductive structure is electrically connected to the second gate structure.

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