Preparation method of semiconductor structure and semiconductor structure
By forming a groove-shaped base layer at the position to be interconnected in the semiconductor structure and forming an interconnected electrode column thereon, the problem of insufficient mechanical strength of the interconnected electrode column is solved, and the reliability of the interconnected process is improved.
Patent Information
- Application Number
- CN202510117354.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-24
- Publication Date
- 2025-05-16
AI Technical Summary
In the interconnection process of semiconductor structures, the size of the interconnection electrode column becomes smaller and the mechanical strength becomes worse, resulting in fracture and reliability problems.
By forming a bottom layer at the position to be interconnected on the chip, the bottom layer covers the side walls of the position to be interconnected and its interlocking photoresist layer are grooved, forming an interconnected electrode column, and at least part of its structure is located in the groove. When removing the photoresist layer, the side walls of the grooves provide reinforcement protection to the interconnected electrode columns to avoid breakage and tilt.
The uniformity of the height of the interconnected electrode columns is improved, the reliability of the semiconductor structure in the interconnected process is enhanced, and the fracture and inclination of the electrode columns are avoided.
Smart Images
Figure CN120018603A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for preparing a semiconductor structure and a semiconductor structure. Background Art
[0002] With the development of semiconductor technology, infrared detectors are developing towards miniaturization, and the spacing between adjacent pixels in infrared detectors is getting smaller and smaller, going through 30 microns, 20 microns, 15 microns, 12 microns, 10 microns, 7.5 microns and 5 microns. As the spacing between adjacent pixels becomes smaller, the size of the interconnected electrode column in the infrared detector will also become smaller. When the spacing between adjacent pixels is less than 10 microns, the bottom area of the interconnected electrode column is significantly reduced due to the surface space of each chip in the infrared detector. At this time, in order to achieve the interconnection effect of each chip, the interconnected electrode column must reach a certain height, so it is necessary to prepare a thin and tall interconnected electrode column.
[0003] However, since the material commonly used for the interconnect electrode columns is indium, which is a soft metal, when the interconnect electrode columns become thinner and taller, the mechanical strength of the interconnect electrode columns will deteriorate, causing some interconnect electrode columns to break during the process, affecting the reliability of subsequent interconnect processes. Summary of the invention
[0004] The purpose of the present invention is to at least provide a method for preparing a semiconductor structure and a semiconductor structure, which can at least solve the problem of poor reliability of the semiconductor structure during an interconnection process.
[0005] In order to solve the above technical problems, the present invention provides a method for preparing a semiconductor structure, comprising: providing a chip; forming a photoresist layer on the surface of the chip to expose the position of the chip to be interconnected; using the photoresist layer as a mask, forming a base layer at the position of the chip to be interconnected, the base layer covering the position to be interconnected and the side wall of the adjacent photoresist layer in the shape of a groove; forming an interconnection electrode column on the groove of the base layer, at least part of the structure of the interconnection electrode column is located in the groove; removing the photoresist layer.
[0006] The method for preparing a semiconductor structure provided by the present invention has a groove-shaped side wall of a base layer covering a position to be interconnected and an adjacent photoresist layer. After an interconnection electrode column is formed on the groove of the base layer, at least part of the structure of the interconnection electrode column is located in the groove. In the process of removing the photoresist layer, the side wall of the groove reinforces and protects at least part of the structure of the interconnection electrode column, and can better disperse the traction force of the photoresist layer on the interconnection electrode column, thereby avoiding the interconnection electrode column from breaking or tilting, improving the uniformity of the height of the interconnection electrode column, and further improving the reliability of the semiconductor structure during the interconnection process.
[0007] In addition, the process of forming a base layer at the position to be interconnected of the chip includes a magnetron sputtering process; wherein the step of forming the base layer includes: using a rotating member to drive the chip and the photoresist layer to rotate circumferentially around the central axis of the chip; at the same time, metal particles are sputtered toward the position to be interconnected and the side wall of the adjacent photoresist layer. The metal particles can be evenly sputtered to the side wall of the position to be interconnected and the adjacent photoresist layer, so that the thickness of the formed base layer is more uniform.
[0008] In addition, the metal particles are sputtered toward the position to be interconnected and the side wall of the adjacent photoresist layer, including: the metal particles are sputtered toward the position to be interconnected and the side wall of the photoresist layer from the side of the position to be interconnected facing the chip, in a direction deviated from the central axis and with a first deviation angle of less than 90 degrees. It is ensured that the metal particles can be attached to both the position to be interconnected of the chip and the side wall of the photoresist layer, so that the bottom layer covers the side wall of the position to be interconnected and the adjacent photoresist layer in a groove shape.
[0009] In addition, when the ratio of the depth to the width of the opening of the photoresist layer exposing the position to be interconnected of the chip is 2, the first deviation angle is 8 to 14 degrees, which can simultaneously take into account the requirements of preventing the interconnection electrode column from breaking or tilting and the high reliability of the semiconductor structure during the interconnection process.
[0010] In addition, in the process of forming the bottom layer at the position to be interconnected at the chip, the bottom layer is formed on the surface of the photoresist layer on the side away from the chip, and the bottom layer on the surface of the photoresist layer is connected to the bottom layer on the side wall of the photoresist layer; before forming the interconnected electrode column on the groove of the bottom layer, it also includes: removing the bottom layer at the connection. In the process of subsequent removal of the photoresist layer, the bottom layer on the side wall of the photoresist layer is prevented from being pulled by the bottom layer on the surface of the photoresist layer, and the side wall of the groove-shaped bottom layer is prevented from being deformed and broken, and the side wall of the groove is further enhanced to reinforce and protect at least part of the structure of the subsequent formation of the interconnected electrode column; secondly, removing the bottom layer at the connection makes it more convenient to remove the photoresist layer by a stripping process in the subsequent process.
[0011] In addition, the process of removing the bottom layer at the connection includes an ion beam etching process; wherein the step of removing the bottom layer at the connection includes: using a rotating member to drive the chip, the photoresist layer and the bottom layer to rotate circumferentially around the central axis of the chip; at the same time, the ion source emits and controls the ion beam to irradiate the bottom layer at the connection. The ion beam can be evenly irradiated to the bottom layer at the connection to etch the bottom layer at the connection, thereby improving the accuracy of the etching process.
[0012] In addition, the ion source emits and controls the ion beam to irradiate the bottom layer at the connection, including: irradiating the ion beam from the side of the chip to be interconnected, in a direction deviating from the central axis and with a second deviation angle of less than 90 degrees, toward the bottom layer at the connection. The probability of the ion beam irradiating the bottom layer at the connection can be increased, the etching effect of the bottom layer at the connection can be enhanced, and the bottom layer on the side wall of the photoresist layer can be prevented from being pulled by the bottom layer 300 on the surface of the photoresist layer in the subsequent removal of the photoresist layer.
[0013] In addition, when the ratio of the depth to the width of the opening of the photoresist layer exposing the position to be interconnected of the chip is 2, the second deviation angle is 40 to 50 degrees. This can take into account the requirements of good effect of removing the bottom layer at the connection and good effect of the side wall of the groove reinforcing and protecting at least part of the structure of the interconnection electrode column formed subsequently.
[0014] In addition, the method further includes: before forming a bottom layer at the position of the chip to be interconnected, a tray is arranged on the side of the chip away from the photoresist layer; in the step of using a rotating member to drive the chip and the photoresist layer to rotate circumferentially around the central axis of the chip, the rotating member is connected to the tray, and the rotating member drives the tray, the chip and the photoresist layer to rotate circumferentially around the central axis of the chip. The tray is arranged on the side of the chip away from the photoresist layer, and the rotating member is connected to the tray to avoid direct contact between the rotating member and the chip, thereby avoiding damage to the chip surface during rotation.
[0015] The present invention also provides a semiconductor structure, comprising: a chip; a base layer, located at a position to be interconnected on the chip; the base layer covers the position to be interconnected and is in a groove shape; an interconnection electrode column, located on the groove of the base layer, and at least part of the structure of the interconnection electrode column is located in the groove. In the semiconductor structure provided by the present invention, the side wall of the groove plays a role in reinforcing and protecting at least part of the structure of the interconnection electrode column, avoiding the interconnection electrode column from breaking or tilting, improving the uniformity of the height of the interconnection electrode column, and thus improving the reliability of the semiconductor structure during the interconnection process. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] One or more embodiments are exemplarily described by pictures in the corresponding drawings, and these exemplified descriptions do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings represent similar elements, and unless otherwise stated, the figures in the drawings do not constitute proportional limitations.
[0017] Figures 1 to 3 A schematic diagram of a structure in a semiconductor structure preparation process in the related art;
[0018] Figure 4 It is a structural schematic diagram of a semiconductor structure in the related art;
[0019] Figure 5 A schematic diagram of a process for preparing a semiconductor structure provided by an embodiment of the present invention;
[0020] Figures 6 to 12 A schematic structural diagram of a conductor structure during preparation according to an embodiment of the present invention. DETAILED DESCRIPTION
[0021] Combined with reference Figures 1 to 3 A method for preparing a semiconductor structure is provided in the related art, comprising: providing a chip 1; forming a photoresist layer 2 on the surface of the chip 1 to expose the position 1a of the chip 1 to be interconnected (refer to Figure 1 ); using the photoresist layer 2 as a mask, forming a base layer 3 covering the position to be interconnected at the position to be interconnected of the chip 1, and forming a base layer 3 on the surface of the photoresist layer 2 on the side away from the chip 1; and forming an interconnection electrode column 4 on the base layer 3 (reference Figure 2 ); remove the photoresist layer 2, and at the same time remove the base layer 3 and the interconnecting electrode column 4 on the surface of the photoresist layer 2 (reference Figure 3 ). Figure 3 The surface of the middle interconnect electrode column 4 facing away from the chip 1 is broken and becomes uneven.
[0022] Specifically, refer to Figure 4 The process of forming the bottom layer 3 covering the interconnection position 1a of the chip 1 includes a magnetron sputtering process; the step of forming the bottom layer 3 covering the interconnection position 1a of the chip 1 includes: fixing the surface of the chip 1 facing away from the photoresist layer 2 on the tray 5, and using the rotating member 6 to drive the chip 1 and the photoresist layer 2 to rotate circumferentially around the central axis of the chip 1; at the same time, sputtering the metal particles 7 from the side facing the interconnection position 1a of the chip 1 along the surface perpendicular to the chip 1. In the process of forming the bottom layer 3 in the above manner, the metal particles 7 are attached to the interconnection position 1a and the surface of the photoresist layer 2 facing away from the chip 1, while no metal particles 7 are attached to the side wall of the photoresist layer 2. The process of removing the photoresist layer 2 usually adopts a stripping process. Since the material usually used for the interconnection electrode column 4 is indium, which is a soft metal, during the stripping process, the photoresist layer 2 exerts a certain traction force on the interconnection electrode column 4, causing part of the interconnection electrode column 4 to break, resulting in an uneven surface on the side of the interconnection electrode column 4 facing away from the chip 1, which will affect the reliability of the subsequent semiconductor structure during the interconnection process.
[0023] Therefore, a method for preparing a semiconductor structure and a semiconductor structure are provided to solve the above problems.
[0024] In order to make the purpose, technical scheme and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, it can be understood by those skilled in the art that in the embodiments of the present invention, many technical details are provided to enable readers to better understand the present invention. However, even without these technical details and various changes and modifications based on the following embodiments, the technical scheme claimed in the present invention can be implemented.
[0025] refer to Figure 5 An embodiment of the present invention provides a method for preparing a semiconductor structure, comprising:
[0026] Step S1: providing a chip;
[0027] Step S2: forming a photoresist layer on the surface of the chip to expose the locations of the chip to be interconnected;
[0028] Step S3: using the photoresist layer as a mask, forming a base layer at the position to be interconnected on the chip, wherein the base layer covers the position to be interconnected and the side wall of the adjacent photoresist layer in a groove shape;
[0029] Step S4: forming an interconnected electrode column on the groove of the base layer, wherein at least a part of the structure of the interconnected electrode column is located in the groove;
[0030] Step S5: removing the photoresist layer.
[0031] In this embodiment, since the side walls of the base layer covering the position to be interconnected and the adjacent photoresist layer are in the shape of a groove, after the interconnection electrode column is formed on the groove of the base layer, at least part of the structure of the interconnection electrode column is located in the groove; in the process of removing the photoresist layer, the side walls of the groove reinforce and protect at least part of the structure of the interconnection electrode column, and can better disperse the traction force of the photoresist layer on the interconnection electrode column, thereby avoiding the interconnection electrode column from breaking or tilting, improving the uniformity of the height of the interconnection electrode column, and thereby improving the reliability of the semiconductor structure during the interconnection process.
[0032] In step S1, the chip includes a detection chip or a readout circuit chip. It can be known that the semiconductor structure in this embodiment is a part of an infrared detector. In other embodiments, the chip includes chips with other functions.
[0033] In step S2, refer to Figure 6 A photoresist layer 200 is formed on the surface of the chip 100 to expose the locations 110 of the chip 100 to be interconnected.
[0034] In one embodiment, the step of forming a photoresist layer 200 on the surface of the chip 100 to expose the position 110 of the chip 100 to be interconnected includes: forming an initial photoresist layer (not shown) on the surface of one side of the position of the chip 100 to be interconnected; sequentially exposing and developing the initial photoresist layer to form a photoresist layer 200 on the surface of the chip 100 to expose the position 110 of the chip 100 to be interconnected.
[0035] In step S3, in one embodiment, reference is made to Figure 7 The process of forming the bottom layer 300 at the interconnection position 110 of the chip 100 includes a magnetron sputtering process; wherein the step of forming the bottom layer 300 includes: using a rotating member 400 to drive the chip 100 and the photoresist layer 200 to rotate circumferentially around the central axis of the chip 100; at the same time, the metal particles 600 are sputtered toward the side wall direction of the interconnection position 110 and the adjacent photoresist layer 200. The metal particles 600 can be evenly sputtered to the side wall of the interconnection position 110 and the adjacent photoresist layer 200, so that the thickness of the formed bottom layer 300 is more uniform.
[0036] It should be noted that when the rotating member 400 is used to drive the chip 100 and the photoresist layer 200 to rotate circumferentially around the central axis of the chip 100, the rotating axis of the rotating member 400 is coaxial with the rotating axis of the chip 100 and the photoresist layer 200, and both are the central axis of the chip 100. The effect of forming a more uniform thickness of the base layer 300 is enhanced.
[0037] In other embodiments, the process of forming a base layer at the location of the chip to be interconnected includes other coating processes.
[0038] In one embodiment, the metal particles 600 are sputtered toward the position to be interconnected 110 and the side wall of the adjacent photoresist layer 200, including: the metal particles 600 are sputtered toward the position to be interconnected 110 and the side wall of the photoresist layer 200 from the side of the position to be interconnected 110 facing the chip 100, in a direction deviated from the central axis and with a first deviation angle A of less than 90 degrees. It is ensured that the metal particles 600 can be attached to both the position to be interconnected 110 of the chip 100 and the side wall of the photoresist layer 200, so that the bottom layer 300 covers the side wall of the position to be interconnected 110 and the adjacent photoresist layer 200 in a groove shape.
[0039] In one embodiment, the method for preparing the semiconductor structure further includes: before forming the bottom layer 300 at the interconnection position 110 of the chip 100, setting a tray 500 on the side of the chip 100 away from the photoresist layer 200; Figure 7In the step of using the rotating member 400 to drive the chip 100 and the photoresist layer 200 to rotate circumferentially around the central axis of the chip 100, the rotating member 400 is connected to the tray 500, and the rotating member 400 drives the tray 500, the chip 100 and the photoresist layer 200 to rotate circumferentially around the central axis of the chip 100. The tray 500 is arranged on the side of the chip 100 away from the photoresist layer 300, and the rotating member 400 is connected to the tray 500 to avoid the rotating member 400 directly contacting the chip 100, thereby avoiding damage to the surface of the chip 100 during the rotation process.
[0040] It can be known that in the step of sputtering the metal particles 600 from the side of the position to be interconnected 110 facing the chip 100, in a direction deviating from the central axis and with a first deviation angle A of less than 90 degrees toward the position to be interconnected 110 and the side wall of the photoresist layer 200, the step can be achieved by controlling the rotating member 400, the chip 100, the tray 500 and the photoresist layer 200 to rotate and tilt together, or by controlling the metal particles 600 to rotate and tilt together, or by controlling the rotating member 400, the chip 100, the tray 500 and the photoresist layer 200 to rotate and tilt together while controlling the metal particles to rotate and tilt. It is sufficient to ensure that the metal particles 600 are sputtered from the side of the position to be interconnected facing the chip 100, in a direction deviating from the central axis of the chip 100 and with a first deviation angle A of less than 90 degrees toward the position to be interconnected 110 and the side wall of the photoresist layer 200.
[0041] Figure 7 The rotating member 400, the chip 100, the tray 500 and the photoresist layer 200 are controlled to rotate together and then tilt as an illustration. Figure 7 The solid line used to represent the first deviation angle A is the central axis of the chip 100 , and the dotted line used to represent the first deviation angle A is the metal particle 600 .
[0042] In one embodiment, when the ratio of the depth to the width of the opening of the photoresist layer 200 exposing the interconnection position 110 of the chip 100 is 2, the first deviation angle A is 8 to 14 degrees, for example, 8, 9, 10, 11, 12, 13 or 14 degrees. If the first deviation angle A is less than 8 degrees, the probability of the metal particles 600 adhering to the sidewall of the photoresist layer 200 is small, the effect of the bottom layer 300 covering the sidewall of the photoresist layer 200 adjacent to the interconnection position 110 is small, and the effect of preventing the interconnection electrode column from breaking or tilting is weak; if the first deviation angle A is greater than 14 degrees, the probability of the metal particles 600 adhering to the interconnection position 110 is small, the effect of the bottom layer 300 covering the interconnection position 110 is small, and the effect of improving the reliability of the semiconductor structure during the interconnection process is weakened. Therefore, when the ratio of the depth to the width of the opening of the photoresist layer 200 exposing the interconnection position 110 of the chip 100 is 2, the first deviation angle A is 8 to 14 degrees, which can simultaneously take into account the requirements of preventing the interconnection electrode column from breaking or tilting and the high reliability of the semiconductor structure during the interconnection process. It should be noted that the size of the first deviation angle is not limited to this.
[0043] refer to Figure 7 and Figure 8 , when the ratio of the depth to the width of the opening of the photoresist layer 200 exposing the interconnection position 110 of the chip 100 is 2, the magnitude of the first deviation angle A is 14 degrees as an example. Figure 8 , Figure 8 for Figure 7 In the local schematic diagram, when at least metal particles 600 are sputtered to 1 / 2 of the width of the opening, the metal particles 600 and the side walls of the photoresist layer 200 and the interconnection position 110 of the chip 100 form a right triangle OEF. According to the trigonometric function, tan angle OEF=OF:EF=0.25, that is, the angle between the metal particles 600 and the side walls of the photoresist layer 200 is arctan0.25. The angle OEF is calculated to be 14 degrees. According to the parallel theorem, it can be known that the first deviation angle A is equal to the angle OEF.
[0044] It should be noted that, when the ratio of the depth to the width of the opening of the chip 100 exposed by the photoresist layer 200 at the interconnection position 110 changes, the size of the first deviation angle A will change accordingly, and the size of the first deviation angle A can be calculated and adjusted according to the actual ratio of the depth to the width of the opening of the chip 100 exposed by the photoresist layer 200 at the interconnection position 110. In other embodiments, the ratio of the depth to the width of the opening of the chip exposed by the photoresist layer at the interconnection position is other values, and the size of the first deviation angle is in other ranges.
[0045] Continue to refer Figure 7In step S3, that is, in the process of forming the bottom layer 300 at the interconnection position 110 of the chip 100, the bottom layer 300 is formed on the surface of the photoresist layer 200 on the side away from the chip 100, and the bottom layer 300 on the surface of the photoresist layer 200 is connected to the bottom layer 300 on the side wall of the photoresist layer 200; before forming the interconnection electrode column on the groove of the bottom layer 300, combined with the reference Fig. 9 and Fig.10 , and further includes: removing the bottom layer 300 at the connection. In the process of removing the photoresist layer 200 in the future, the bottom layer 300 on the side wall of the photoresist layer 200 is prevented from being pulled by the bottom layer 300 on the surface of the photoresist layer 200, and the side wall of the groove-shaped bottom layer 300 is prevented from being deformed and cracked, and the side wall of the groove is further enhanced to strengthen and protect at least part of the structure of the interconnected electrode column formed in the future; secondly, removing the bottom layer 300 at the connection makes it more convenient to remove the photoresist layer 200 in the future by using a stripping process.
[0046] In one embodiment, reference Fig. 9 The process of removing the bottom layer 300 at the connection includes an ion beam etching process; wherein, the step of removing the bottom layer 300 at the connection includes: using a rotating member 400 to drive the chip 100, the photoresist layer 200 and the bottom layer 300 to rotate circumferentially around the central axis of the chip 100; at the same time, the ion source emits and controls the ion beam 800 to irradiate the bottom layer 300 at the connection. The ion beam 800 can be uniformly irradiated to the bottom layer 300 at the connection to etch the bottom layer 300 at the connection, thereby improving the accuracy of the etching process.
[0047] It should be noted that when the rotating member 400 is used to drive the chip 100, the photoresist layer 200 and the bottom layer 300 to rotate circumferentially around the central axis of the chip 100, the rotating axis of the rotating member 400 is coaxial with the rotating axes of the chip 100, the photoresist layer 200 and the bottom layer 300, that is, they are all the central axis of the chip 100. The bottom layer 300 at the connection is removed more uniformly by etching and the etching accuracy is improved.
[0048] In other embodiments, the process of removing the bottom layer at the connection includes other etching processes.
[0049] In one embodiment, the ion source emits and controls the ion beam 800 to irradiate the bottom layer 300 at the connection, including: irradiating the ion beam 800 from the side of the to-be-connected position 110 facing the chip 100, in a direction deviating from the central axis and with a second deviation angle B of less than 90 degrees, toward the bottom layer 300 at the connection. The probability of the ion beam 800 irradiating the bottom layer 300 at the connection can be increased, the etching effect on the bottom layer 300 at the connection can be enhanced, and the bottom layer 300 on the side wall of the photoresist layer 200 can be prevented from being pulled by the bottom layer 300 on the surface of the photoresist layer 200 in the subsequent removal of the photoresist layer 200.
[0050] In one embodiment, the method for preparing a semiconductor structure further includes: before removing the bottom layer 300 at the connection, setting a tray 500 on the side of the chip 100 away from the photoresist layer 200; Fig. 9 In the step of using the rotating member 400 to drive the chip 100, the photoresist layer 200 and the bottom layer 300 to rotate circumferentially around the central axis of the chip 100, the rotating member 400 is connected to the tray 500, and the rotating member 400 drives the tray 500, the chip 100, the photoresist layer 200 and the bottom layer 300 to rotate circumferentially around the central axis of the chip 100. The tray 500 is arranged on the side of the chip 100 away from the photoresist layer 300, and the rotating member 400 is connected to the tray 500 to avoid the rotating member 400 directly contacting the chip 100, thereby avoiding damage to the surface of the chip 100 during the rotation process.
[0051] It can be known that in the step of irradiating the ion beam 800 from the side of the position 110 to be interconnected facing the chip 100, in a direction deviating from the central axis and with a second deviation angle B of less than 90 degrees toward the coating layer 300 at the connection, the ion beam 800 can be controlled to rotate and tilt together, or the ion beam 800 can be controlled to rotate and tilt together, or the ion beam 800 can be controlled to rotate and tilt while the ion beam is controlled to rotate and tilt at the same time. It is sufficient to ensure that the ion beam 800 is irradiated from the side of the position to be interconnected facing the chip 100, in a direction deviating from the central axis and with a second deviation angle B of less than 90 degrees toward the coating layer at the connection.
[0052] Fig. 9 In the figure, the rotating member 400, the chip 100, the tray 500, the photoresist layer 200 and the base layer 300 are controlled to rotate together and then tilted as an illustration. Fig. 9 The solid line used to represent the second deviation angle B is the central axis of the chip 100 , and the dotted line used to represent the second deviation angle B is the ion beam 800 .
[0053] In one embodiment, when the ratio of the depth to the width of the opening of the photoresist layer 200 exposing the interconnection position 110 of the chip 100 is 2, the second deviation angle B is 40 to 50 degrees, for example, 40, 42, 44, 45, 46, 48 or 50 degrees. If the second deviation angle B is less than 40 degrees, the probability of the ion beam 800 irradiating the bottom layer 300 on the side wall of the photoresist layer 200 is relatively high, resulting in more etching of the bottom layer 300 on the side wall of the photoresist layer 200, and the side wall of the groove has a poor effect of reinforcing and protecting at least part of the structure of the interconnection electrode column formed subsequently; if the second deviation angle B is greater than 50 degrees, the range of the ion beam 800 irradiating the bottom layer 300 at the connection is narrowed, and the effect of removing the bottom layer 300 at the connection is weakened. Therefore, when the ratio of the depth to the width of the opening of the photoresist layer 200 exposing the interconnection position 110 of the chip 100 is 2, the second deviation angle B is 40 to 50 degrees, which can take into account the effect of removing the bottom layer 300 at the connection and the side wall of the groove reinforcing and protecting at least part of the structure of the interconnection electrode column formed subsequently. It should be noted that the size of the second deviation angle is not limited to this.
[0054] refer to Fig. 9 and Fig.10 , when the ratio of the depth to the width of the opening of the photoresist layer 200 exposing the interconnection position 110 of the chip 100 is 2, the magnitude of the first deviation angle B is 45 degrees as an example. Fig.10 , Fig.10 for Fig. 9 A local schematic diagram in FIG. When at least the ion beam 800 irradiates to 1 / 2 of the depth of the opening, the line connecting the ion beam 800 and the two points on the side wall and the opening surface of the photoresist layer 200 forms a right triangle GTF. According to trigonometric functions, tan angle GTF = GF: GT = 1, that is, the angle between the ion beam 800 and the side wall of the photoresist layer 200 is arctan1. It is calculated that the angle GTF is 45 degrees. According to the parallel theorem, it can be known that the second deviation angle B is equal to the angle GTF. It can be known that the bottom layer 300 between the two points GT is the bottom layer 300 of the joint removed in this application.
[0055] It should be noted that, when the ratio of the depth to the width of the opening of the chip 100 exposed by the photoresist layer 200 at the position to be interconnected 110 changes, the size of the second deviation angle B will change accordingly, and the size of the second deviation angle B can be calculated and adjusted according to the actual ratio of the depth to the width of the opening of the chip 100 exposed by the photoresist layer 200 at the position to be interconnected 110. In other embodiments, the ratio of the depth to the width of the opening of the chip exposed by the photoresist layer at the position to be interconnected is other values, and the size of the second deviation angle is in other ranges.
[0056] In step S4, refer to Fig.11 , an interconnection electrode column 310 is formed on the groove of the base layer 300, and at least a part of the structure of the interconnection electrode column 310 is located in the groove.
[0057] In one embodiment, the process of forming the interconnected electrode pillars 310 includes a deposition process.
[0058] In one embodiment, the material of the interconnect electrode pillars 310 includes, but is not limited to, indium.
[0059] In step S5, refer to Fig.12 , remove the photoresist layer 200 to obtain a semiconductor structure.
[0060] In one embodiment, when the photoresist layer 200 is removed, the base layer 300 and the interconnection electrode pillars 310 on the side of the photoresist layer 200 facing away from the chip 100 are removed.
[0061] Another embodiment of the present invention further provides a semiconductor structure, referring to Fig.12 , comprising: a chip 100; a base layer 300, located at the position to be interconnected of the chip 100; the base layer 300 covers the position to be interconnected and is in the shape of a groove; an interconnection electrode column 310, located on the groove of the base layer 300, and at least part of the structure of the interconnection electrode column 310 is located in the groove. In the semiconductor structure provided by the present invention, the side wall of the groove plays a role in reinforcing and protecting at least part of the structure of the interconnection electrode column 310, preventing the interconnection electrode column 310 from breaking or tilting, improving the uniformity of the height of the interconnection electrode column, and thus improving the reliability of the semiconductor structure during the interconnection process.
[0062] In this embodiment, the semiconductor structure is used as a part of the infrared detector, wherein the chip is a detection chip and / or a readout circuit chip, and based on the description of the semiconductor structure of the present invention, the signal transmission capability of the infrared detector is improved.
[0063] In other embodiments, the semiconductor structure is a part of other semiconductor devices, which is not limited here.
[0064] It should be understood that the expressions "mechanism", "device", "component" and the like used in this application are only a method for distinguishing different components, elements, parts, portions or assemblies at different levels. However, if other words can achieve the same purpose, the word can be replaced by other expressions.
[0065] Those skilled in the art can understand that the above-mentioned embodiments are specific examples for realizing the present invention, and in practical applications, the technical features of the above-mentioned embodiments can be arbitrarily combined. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification, and various changes can be made in form and details without departing from the spirit and scope of the present invention.
Claims
1. A method for preparing a semiconductor structure, characterized in that: include: Provide chips; Forming a photoresist layer on the surface of the chip to expose the positions of the chip to be interconnected; Using the photoresist layer as a mask, a primer layer is formed at the position to be interconnected on the chip, wherein the primer layer covers the position to be interconnected and the side wall of the adjacent photoresist layer in a groove shape; forming an interconnected electrode column on the groove of the base layer, wherein at least a portion of the structure of the interconnected electrode column is located in the groove; The photoresist layer is removed.
2. The method for preparing a semiconductor structure according to claim 1, characterized in that: The process of forming a bottom layer at the position to be interconnected of the chip includes a magnetron sputtering process; The step of forming the bottom layer includes: using a rotating member to drive the chip and the photoresist layer to rotate circumferentially around the central axis of the chip; at the same time, metal particles are sputtered toward the position to be interconnected and the side wall of the adjacent photoresist layer.
3. The method for preparing a semiconductor structure according to claim 2, characterized in that: The metal particles are sputtered toward the position to be interconnected and the side wall of the adjacent photoresist layer, including: The metal particles are sputtered from a side facing the position to be interconnected of the chip, in a direction deviating from the central axis and with a first deviation angle of less than 90 degrees, toward the position to be interconnected and the side wall of the photoresist layer.
4. The method for preparing a semiconductor structure according to claim 3, characterized in that: When the ratio of the depth to the width of the opening of the photoresist layer that exposes the position of the chip to be interconnected is 2, the magnitude of the first deviation angle is 8 degrees to 14 degrees.
5. The method for preparing a semiconductor structure according to claim 1, characterized in that: In the process of forming the primer layer at the position to be interconnected of the chip, the primer layer is formed on the surface of the photoresist layer on the side away from the chip, and the primer layer on the surface of the photoresist layer is connected to the primer layer on the side wall of the photoresist layer; Before forming the interconnected electrode column on the groove of the primer layer, the method further includes: removing the primer layer at the connection.
6. The method for preparing a semiconductor structure according to claim 5, characterized in that: The process of removing the primer layer at the connection includes an ion beam etching process; Among them, the step of removing the coating layer at the connection includes: using a rotating part to drive the chip, the photoresist layer and the coating layer to rotate circumferentially around the central axis of the chip; at the same time, an ion source emits and controls an ion beam to irradiate the coating layer at the connection.
7. The method for preparing a semiconductor structure according to claim 6, characterized in that: The ion source emits and controls an ion beam to irradiate the primer layer at the connection, including: The ion beam is irradiated toward the base layer at the connection from a side facing the position to be interconnected of the chip in a direction deviated from the central axis and with a second deviation angle of less than 90 degrees.
8. The method for preparing a semiconductor structure according to claim 7, characterized in that: When the ratio of the depth to the width of the opening of the photoresist layer that exposes the position of the chip to be interconnected is 2, the magnitude of the second deviation angle is 40 degrees to 50 degrees.
9. The method for preparing a semiconductor structure according to claim 2 or 6, characterized in that: Also includes: Before forming a base layer at the position to be interconnected of the chip, a tray is arranged on a side of the chip away from the photoresist layer; In the step of using a rotating member to drive the chip and the photoresist layer to rotate circumferentially around the central axis of the chip, the rotating member is connected to the tray, and the rotating member drives the tray, the chip and the photoresist layer to rotate circumferentially around the central axis of the chip.
10. A semiconductor structure, characterized in that: include: chip; A bottom layer, located at a position of the chip to be interconnected; The bottom layer covers the position to be interconnected and is in a groove shape; The interconnected electrode column is located on the groove of the base layer, and at least a part of the structure of the interconnected electrode column is located in the groove.