A pixel structure and sensor of a linear image sensor

Abstract

The present invention relates to the technical field of CMOS image sensors, and specifically provides a linear image sensor pixel structure and a sensor. The pixel structure includes a partially clamped photodiode with multiple levels of clamping voltages and a high-resistance polysilicon transfer gate. Through the processing technology, the partially clamped photodiode forms multiple levels of gradient clamping voltages when depleted, thereby forming a longitudinal potential difference and a uniform electric field to help the charges quickly transfer from the upper and lower sides to the vicinity of the transfer gate longitudinally. Then, different voltages are applied to both ends of the polysilicon transfer gate, and a transverse gate voltage difference is formed on this polysilicon transfer gate, so that the buried channel forms a potential distribution that increases from the far end to the output end when depleted. The linear scan image sensor pixel structure of the present invention realizes the rapid transfer of photo-generated charges in a large-sized photodiode. Even when the pixel has large longitudinal and transverse dimensions, it can still effectively accelerate the transmission of electrons, significantly reduce the readout time, and avoid the trailing phenomenon.

Description

Technical Field

[0001] The present invention belongs to the technical field of CMOS image sensors, and particularly relates to a linear image sensor pixel structure and a sensor. Background Art

[0002] According to the arrangement mode of the pixel matrix, image sensors can generally be divided into two types: area image sensors and linear image sensors. A linear image sensor obtains information about the color, shape, size or distance of an object by scanning the object row by row, and is usually used in automatic optical inspection machines, sorting machines and other electronic imaging devices. Generally, the horizontal resolution of a line-scan image sensor determines the detection accuracy, while the longitudinal dimension determines the effective photosensitive area. Generally, the larger the single-column area of the pixels, the higher the sensitivity of the image sensor. Therefore, it is beneficial to increase the stability of detection and the accuracy of detecting weak signals. On the other hand, the longer the longitudinal dimension, the longer the time for the charges in the photodiode to transfer from the far end to the output end, thus affecting the detection speed.

[0003] The technical document "Resistive gate type CCD linear image sensor with electronic shutter function" published on the website of Hamamatsu Photonics K.K. describes a high-speed charge transfer method and structure for a longitudinally large-sized photodiode under the CCD (Charge Coupled Device) process. As Figure 1 shown, the photosensitive device of this CCD consists of a resistive gate (REG) and a photodiode (PD). The resistive gate completely covers the photodiode, and two electrodes, namely REGH and REGL, are provided at both ends. In addition, this structure includes a storage gate (STG), a transfer gate (TG) and a two-phase CCD structure (P1H / P2H) for reading out pixel signals. When the photo-generated charges start to transfer, REGH is raised to a high voltage. At this time, the voltage difference between REGH and REGL forms a potential difference inside the diode to accelerate the charge transfer in the horizontal direction. When the electrons transfer to the storage gate, the transfer gate and the two-phase CCD are operated in sequence to transfer the charges to the shift register for signal reading.

[0004] Although the above solution can improve the detection speed, its use of CCD technology and readout structure design make the CCD technology have a relatively high production cost compared to CIS technology, with backward process nodes and high power consumption, which is not conducive to the large-scale integration of logic circuits and analog circuits in the image sensor architecture. In addition, in the design of the above solution, the transfer gate needs to completely cover the photodiode, resulting in an overly large polysilicon gate area, requiring the row logic circuit to provide a very high driving ability, thus causing high power consumption problems. At the same time, an overly large local polysilicon density will cause problems such as uneven etching and low yield in production. Summary of the Invention

[0005] In view of this, the present invention aims to provide a linear image sensor pixel structure and sensor based on CMOS technology, which can prompt the photo-generated electrons generated at different positions of the photodiode to quickly transfer to the output end through gate voltage design, and at the same time solve the drawback of the overly large polysilicon transfer gate area in the existing design.

[0006] To achieve the above object, the technical solution of the present invention is realized as follows:

[0007] On the one hand, the present invention provides a linear image sensor pixel structure, including: a partially clamped photodiode, a polysilicon transfer gate disposed on the surface of the partially clamped photodiode, and a buried channel disposed under the polysilicon transfer gate;

[0008] Among them, the partially clamped photodiode forms a multi-level gradient clamping voltage during depletion, which is used to longitudinally transfer charges to the corresponding buried channel under the polysilicon transfer gate;

[0009] The polysilicon transfer gate has an M end far from the output end of the partially clamped photodiode and an N end close to the output end of the partially clamped photodiode in the transverse direction, and voltages are applied to the N end and the M end;

[0010] When the voltage applied to the N end is greater than that of the M end, a gate voltage uniformly distributed in the transverse direction is formed on the polysilicon transfer gate; the gate voltage causes the buried channel to form a potential distribution increasing from the far end to the output end during depletion.

[0011] Preferably, its manufacturing process is CMOS.

[0012] Preferably, the clamping region of the partially clamped photodiode includes a p-type epitaxial layer, a p-type clamping layer, and an n-type well layer.

[0013] Preferably, the polysilicon transfer gate is disposed in the longitudinal central region of the partially clamped photodiode.

[0014] Preferably, the partially clamped photodiode forms a multi-level clamping potential distribution with low levels on both longitudinal sides and a high level in the center by adjusting the doping process in the clamping region.

[0015] Preferably, n-type doping with different concentrations and different area differences is implanted in the clamping region of the partial clamping photodiode to form a multi-level clamping potential distribution with low values on both longitudinal sides and a high value in the center.

[0016] Preferably, according to a transverse continuous trapezoidal pattern, n-type and / or p-type implantation is carried out in the clamping region of the partial clamping photodiode to form a multi-level clamping potential distribution with low values on both longitudinal sides and a high value in the center.

[0017] Preferably, a p-type silicon surface barrier layer and an n-type buried channel are formed by ion implantation below the polysilicon transfer gate, and the silicon surface barrier layer is used to reduce the dark current.

[0018] Preferably, it includes a non-clamping state mode and a clamping state mode, where:

[0019] In the non-clamping state mode, when the electronic shutter is opened, a low voltage is applied to the M terminal and a high voltage is applied to the N terminal. When the buried channel is depleted, a clamping voltage difference that increases from the far end of the output terminal to the output terminal is formed to promote the drift of charges along the polysilicon transfer gate towards the output terminal.

[0020] In the clamping state mode, when the electronic shutter is opened, low voltages are applied to both M and N simultaneously to suppress the dark current. At the moment when the electronic shutter is closed, a low voltage is applied to the M terminal and a high voltage is applied to the N terminal. When the buried channel is depleted, a clamping voltage difference that increases from the far end of the output terminal to the output terminal is formed to promote the drift of charges along the polysilicon transfer gate towards the output terminal.

[0021] On the other hand, the present invention provides a sensor that adopts a linear array image sensor pixel structure.

[0022] Compared with the prior art, the present invention can achieve the following beneficial effects:

[0023] The line-scan image sensor pixel structure of the present invention is applicable to the CMOS process, avoiding the disadvantages of the traditional CCD process, such as high production cost, backward process nodes, and high power consumption. Through the combined design of a high-resistance polysilicon transfer gate (RTG) and a partial clamping photodiode (PPPD), the present invention realizes the rapid transfer of photo-generated charges in a large-sized photodiode, avoids the design of completely covering the photodiode with a traditional transfer gate, significantly reduces the area of the polysilicon transfer gate, and avoids the disadvantages caused by a large-area polysilicon transfer gate. When the longitudinal and transverse dimensions of the pixel are relatively large, it can still effectively accelerate the transmission of electrons, significantly reduce the readout time, avoid the trailing phenomenon, and at the same time reduce the residence time of charges in the photodiode, improving the detection accuracy and stability. This design not only improves the detection speed of the image sensor but also reduces the power consumption by optimizing the charge transmission path, meeting the design goal of high speed and low power consumption.

[0024] By designing a p-type silicon surface barrier layer and an n-type buried channel under the polysilicon transfer gate, the present invention effectively isolates the direct contact between charges and the silicon surface, reducing the generation of dark current. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The drawings constituting a part of the present invention are used to provide a further understanding of the present invention. The schematic embodiments and descriptions thereof are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0026] Figure 1 is a schematic diagram of an existing CCD photosensitive device according to the background art;

[0027] Figure 2 is a top view of the pixel structure of a linear image sensor according to an embodiment of the present invention;

[0028] Figure 3 is a schematic diagram of a partial clamping region of a clamping photodiode formed by a doping process according to an embodiment of the present invention;

[0029] Figure 4 is a schematic diagram of a multi-level clamping potential formed by a doping process according to an embodiment of the present invention;

[0030] Figure 5 is a schematic diagram of a partial clamping region of a clamping photodiode formed by a trapezoidal injection according to an embodiment of the present invention;

[0031] Figure 6 is a schematic diagram of a multi-level clamping potential formed by a trapezoidal injection according to an embodiment of the present invention;

[0032] Figure 7 is a schematic diagram of the influence of different gate voltages on the clamping potential when the buried channel is depleted according to an embodiment of the present invention;

[0033] Figure 8 is a schematic diagram of the potential distribution from the M end to the N end according to an embodiment of the present invention;

[0034] Figure 9 is a structural design diagram for suppressing dark current according to an embodiment of the present invention;

[0035] Figure 10 is a timing diagram of the non-clamping state mode according to an embodiment of the present invention;

[0036] Figure 11 is a timing diagram of the clamping state mode according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0037] In order to make the purpose, technical solutions and advantages of the present invention clearer and more understandable, the following further elaborates on the present invention in combination with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and do not constitute a limitation to the present invention. Similar elements in different embodiments are labeled with related similar element numbers. In the following embodiments, many detailed descriptions are provided to enable a better understanding of the present invention. However, those skilled in the art can easily recognize that some of the features can be omitted in different situations, or can be replaced by other elements, materials, or methods. In some cases, some operations related to the present invention are not shown or described in the specification to avoid overwhelming the core part of the present invention with excessive descriptions. For those skilled in the art, it is not necessary to describe these related operations in detail, and they can fully understand the related operations based on the descriptions in the specification and the general technical knowledge in the art.

[0038] It should be noted that, without conflict, the embodiments and features in the embodiments of the present invention can be combined with each other to form various implementation manners. At the same time, the steps or actions in the method description can also be reordered or adjusted in an obvious manner by those skilled in the art. Therefore, the various sequences in the specification and the drawings are only for clearly describing a certain embodiment and do not mean that they are the necessary sequences, unless it is stated that a certain sequence must be followed.

[0039] In the description of the present invention, it should be understood that the orientation or positional relationships indicated by the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc. are based on the orientation or positional relationships shown in the accompanying drawings. These are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to the present invention. In addition, the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first", "second", etc. may explicitly or implicitly include one or more of such features. In the description of the present invention, unless otherwise stated, the meaning of "a plurality" is two or more.

[0040] In the description of the present invention, it should be noted that unless otherwise clearly specified and defined, the terms "installation", "connection", and "coupling" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood through specific situations.

[0041] The present invention will be described in detail below with reference to the accompanying drawings and in conjunction with embodiments.

[0042] Please refer to Figure 2 , in an embodiment of the present invention, a linear array image sensor pixel structure based on CMOS technology is provided to solve problems such as the too large size of the transfer gate in the existing pixel structure and the slow transfer speed of photo-generated electrons in the diode. The specific pixel structure includes: a partially pinned photodiode (PPPD), a high-resistance polysilicon transfer gate (RTG), and a buried channel, wherein the high-resistance polysilicon transfer gate is disposed in the longitudinal central region on the upper surface of the partially pinned photodiode. Usually, the sizes of the partially pinned photodiode regions on both longitudinal sides of the high-resistance polysilicon transfer gate are equal.

[0043] The partially pinned photodiode has relatively large lateral and longitudinal dimensions. As a photosensitive element, it is responsible for converting the incident light signal into photo-generated charges. To improve the charge transfer rate, through specific layout design and process flow, a multi-stage longitudinal gradient clamping voltage is formed when the partially pinned photodiode is depleted. The clamping region of the partially pinned photodiode includes a p-type epitaxial layer, a p-type clamping layer, and an n-type well layer. By injecting n-type and / or p-type dopants with different concentrations and different area differences multiple times in the clamping region, a stepped clamping voltage is formed inside the partially pinned photodiode at different positions due to different doping concentrations or areas, thereby realizing a stepped potential distribution. Specifically, a multi-stage clamping potential distribution with low potential on both longitudinal sides and high potential in the center is formed, that is, the potential gradually increases from both longitudinal sides close to the polysilicon transfer gate. This potential distribution enables charges to quickly move along the potential gradient inside the photodiode towards the transfer gate direction, promoting the rapid transfer of charges from the upper and lower sides to the corresponding buried channel under the polysilicon transfer gate in the longitudinal direction, and accelerating the charge transfer efficiency.

[0044] To realize a multi-stage clamping potential distribution with low potential on both longitudinal sides and high potential in the center within the clamping region of the partially pinned photodiode, the following several process design methods are shown in the embodiments of the present invention:

[0045] First, please refer to Figure 3, which shows a design for forming a multi-level clamping potential by adjusting the doping process. Specifically, the partial clamping photodiode is partitioned longitudinally (i.e., the up and down direction in the figure), and different concentrations of n-type doping are designed to be injected within the clamping region, so that the total concentration of n-type doping achieves a symmetric distribution with a high concentration in the longitudinal central region and a low concentration in the two side regions of the partial clamping photodiode. Such a design will form a symmetric stepped clamping voltage at different positions due to different doping concentrations, thereby achieving a stepped potential distribution as shown in Figure 4 , where RTGH and RTGL respectively represent the high voltage and low voltage applied across the polysilicon transfer gate.

[0046] The second one, please refer to Figure 5 , which shows a design for forming a multi-level clamping potential by a trapezoidal injection process. Specifically, along the transverse direction (i.e., the left and right direction in the figure), a plurality of consecutive isosceles trapezoidal patterns are designed within the partial clamping photodiode regions on both sides of the polysilicon transfer gate. According to the transverse continuous trapezoidal pattern, n-type or / and p-type injection is performed within the clamping region of the partial clamping photodiode, forming a multi-level gradient clamping potential distribution with low levels on both longitudinal sides and a high level in the center as shown in Figure 6 .

[0047] The above processes can all achieve the partial clamping photodiode with multi-level clamping voltage required by the embodiments of the present invention, and are all compatible with the CMOS process, which can avoid the complex process steps of traditional CCDs, not only reducing the production cost, but also improving the process scalability and yield.

[0048] Compared with the large-area polysilicon transfer gate of the traditional covering diode, the high-resistance polysilicon transfer gate of the present invention reduces the gate area and the power of the driving circuit through optimized structural design. In order to improve the rapid lateral transfer of charges in the buried channel under the high-resistance polysilicon transfer gate, different voltages are applied to the transverse two ends (M end and N end) of the polysilicon transfer gate in the embodiments of the present invention. Among them, the M end is far from the output terminal (PU, Pick-up Terminal) of the partial clamping photodiode, and the N end is close to the output terminal of the partial clamping photodiode. In order to promote the transfer of charges to the output terminal, a low voltage RTGL is applied to the M end, and a high voltage RTGH is applied to the N end, and RTGH > RTGL. Due to the voltage difference between the M end and the N end, at this time, the voltage difference between RTGH and RTGL will be evenly distributed on the high-resistance polysilicon transfer gate, and a gate voltage evenly distributed along the transverse direction is formed on the polysilicon transfer gate. Please refer to Figure 7 , at different gate voltages, the clamping voltage when the buried channel under the high-resistance polysilicon transfer gate is depleted will also change due to the gate voltage. Therefore, a stepped potential distribution as shown in Figure 8The potential distribution increasing from the far end to the output end of the output terminal (i.e., in the direction from M to N) as shown. Under this potential, a uniform electric field is formed, and the charges converged in the buried channel through the longitudinal multi-stage gradient clamping voltage will be further quickly transferred to the output end by drift. In terms of the readout method, the pixel structure of the linear image sensor provided in the embodiment of the present invention is compatible with a capacitive feedback cross-group amplifier circuit or a source follower.

[0049] As a preferred embodiment, please refer to Figure 9 , to suppress the dark current, the implantation process of the buried channel under the high-resistance polysilicon transfer gate can also be adjusted. Specifically, ion implantation is performed on the p-type layer and n-type layer under the high-resistance polysilicon transfer gate to form a p-type silicon surface barrier layer and an n-type buried channel. Among them, the p-type silicon surface barrier layer can isolate the charges in the buried channel from the silicon surface of the high-resistance polysilicon transfer gate, thereby reducing the dark current.

[0050] According to different application requirements and operating conditions, the voltages applied to the M end and N end can be adjusted so that the signal acquisition and readout methods of the pixel structure can use two methods:

[0051] The first non-clamped state mode, please refer to Figure 10 , when the electronic shutter (ES) is opened, the M end and N end of the polysilicon transfer gate are respectively connected to fixed potentials RTGL and RTGH, where RTGH>RTGL. Due to the resistance characteristics of the high-resistance polysilicon transfer gate, a uniform potential distribution from RTGL to RTGH will be formed on the polysilicon transfer gate. This potential difference generates a corresponding clamping voltage difference in the buried channel under the polysilicon transfer gate. The clamping voltage difference in this buried channel forms an electric field, which promotes the charges converged in the area near the polysilicon transfer gate to quickly drift laterally to the output end. This design significantly speeds up the charge transfer speed and reduces the readout time. The non-clamped state mode is suitable for application scenarios with short exposure times. In this mode, the charges can be quickly transferred to the output end, thereby achieving high-speed readout. However, a potential problem with this mode is that if the potential on the polysilicon transfer gate is higher than the clamping voltage of the buried channel below it, it may cause an increase in dark current. Therefore, the non-clamped state mode is more suitable for short-exposure applications with low requirements for dark current. In applications that require long exposure and low dark current, the clamped state mode can be adopted.

[0052] The second clamped state mode, please refer to Figure 11, when the electronic shutter is opened, both the M terminal and the N terminal of the polysilicon transfer gate are connected to the fixed potential RTGL, which is set to a low potential RTGL at the same time. At this time, the polysilicon transfer gate is completely in the inversion state, and a large number of holes will accumulate in the area near the silicon surface, thereby effectively suppressing the generation of dark current during the exposure time. At the moment when the electronic shutter is closed, when the electronic shutter is opened in the non-clamped state mode, the M terminal and the N terminal of the polysilicon transfer gate are respectively connected to the fixed potential RTGL and RTGH. At this time, as in the non-clamped state mode, a clamping voltage difference increasing from the far end of the output terminal to the output terminal is formed through the buried channel when depleted. Under the action of the clamping voltage difference, electrons quickly drift to the output terminal, thereby achieving the goal of high-efficiency and high-quality reading.

[0053] The sensor prepared by using the above linear image sensor pixel structure can significantly improve the target detection accuracy of the sensor, while reducing the readout time and avoiding the trailing phenomenon.

[0054] In summary, the above description is only the preferred embodiments of this specification and is not intended to limit the protection scope of this specification. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of this specification shall be included within the protection scope of this specification.

[0055] The system, device, module or unit illustrated by the above one or more embodiments can be specifically implemented by a computer chip or entity, or by a product with certain functions. A typical implementation device is a computer. Specifically, the computer can be, for example, a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or any combination of these devices.

[0056] It should also be noted that the term "including", "comprising" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. Without further limitations, the element defined by the statement "including one..." does not exclude the existence of another identical element in the process, method, commodity or device including the said element.

[0057] Each embodiment in this specification is described in a progressive manner. The same or similar parts among the embodiments can be referred to each other, and the key points of each embodiment are the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can refer to the partial description of the method embodiment.

[0058] The foregoing describes specific embodiments of the present specification. Other embodiments are within the scope of the appended claims. In some cases, the acts or steps recited in the claims may be performed in a different order than in the embodiments and still achieve the desired result. Additionally, the processes depicted in the figures do not necessarily require the particular order or sequential order shown to achieve the desired result. In certain embodiments, multitasking and parallel processing are also possible or may be advantageous.

Claims

1. A pixel structure of a linear image sensor, characterized in that, Comprising: A partial-clamping photodiode, a polysilicon transfer gate disposed on the surface of the partial-clamping photodiode, and a buried channel disposed under the polysilicon transfer gate; Wherein, the partial-clamping photodiode forms a multi-level gradient clamping voltage during depletion, for longitudinally transferring charges to the corresponding buried channel under the polysilicon transfer gate; The polysilicon transfer gate has an M end away from the output end of the partial-clamping photodiode and an N end close to the output end of the partial-clamping photodiode in the transverse direction, and voltages are applied to the N end and the M end; When the voltage applied to the N end is greater than that of the M end, a gate voltage uniformly distributed in the transverse direction is formed on the polysilicon transfer gate; the gate voltage causes the buried channel to form a potential distribution increasing from the distal end of the output end to the output end during depletion; Including a non-clamping state mode and a clamping state mode, wherein: In the non-clamping state mode, when the electronic shutter is opened, a low voltage is applied to the M end, a high voltage is applied to the N end, and a clamping voltage difference increasing from the distal end of the output end to the output end formed by the buried channel during depletion promotes the drift of charges along the polysilicon transfer gate towards the output end; In the clamping state mode, when the electronic shutter is opened, low voltages are simultaneously applied to the M end and the N end for suppressing dark current; at the moment when the electronic shutter is closed, a low voltage is applied to the M end, a high voltage is applied to the N end, and a clamping voltage difference increasing from the distal end of the output end to the output end formed by the buried channel during depletion promotes the drift of charges along the polysilicon transfer gate towards the output end.

2. The pixel structure of the linear image sensor according to claim 1, characterized in that, Its manufacturing process is CMOS.

3. The pixel structure of the linear image sensor according to claim 1, wherein The clamping region of the partial-clamping photodiode includes a p-type epitaxial layer, a p-type clamping layer, and an n-type well layer.

4. The pixel structure of the linear image sensor according to claim 3, wherein The polysilicon transfer gate is disposed in the longitudinal central region of the partial-clamping photodiode.

5. The pixel structure of the linear image sensor according to claim 4, wherein The partial-clamping photodiode forms a multi-level clamping potential distribution with low values on both longitudinal sides and a high value in the center in the clamping region by adjusting the doping process.

6. The pixel structure of the linear image sensor according to claim 4, characterized in that, By injecting n-type dopants with different concentrations and different area differences in the clamping region of the partial-clamping photodiode, a multi-level clamping potential distribution with low values on both longitudinal sides and a high value in the center is formed.

7. The pixel structure of the linear image sensor according to claim 6, wherein According to a transverse continuous trapezoidal pattern, n-type and / or p-type implantation is performed in the clamping region of the partial-clamping photodiode to form a multi-level clamping potential distribution with low values on both longitudinal sides and a high value in the center.

8. The pixel structure of the linear image sensor according to claim 1 or 7, characterized in that, A p-type silicon surface barrier layer and the n-type buried channel are formed under the polysilicon transfer gate by ion implantation process, and the silicon surface barrier layer is used to reduce dark current.

9. A sensor, characterized in that, Adopt the linear image sensor pixel structure according to any one of claims 1 to 8.

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