Light emitting diode, display device, and method of manufacturing display device

Abstract

The invention relates to a light emitting diode, a display device and a method of manufacturing the display device. The light emitting diode includes: a first electrode portion; a second electrode portion disposed on the first electrode portion; and a semiconductor junction structure disposed between the first electrode portion and the second electrode portion. The semiconductor junction structure may include a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, an optical layer, and an active layer. Any one of the optical layer and the active layer may be disposed between the first semiconductor layer and the second semiconductor layer, and the other one of the optical layer and the active layer may be disposed between the second semiconductor layer and the third semiconductor layer. The optical layer may include a porous layer and a non-porous layer disposed on the porous layer, and a first width of the porous layer may be greater than a second width of the non-porous layer in a direction perpendicular to the thickness direction.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0158097 filed in the Korean Intellectual Property Office on November 15, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a light emitting diode including a semiconductor layer, a display device including the light emitting diode having excellent light efficiency, and a method of manufacturing the display device. Background Art

[0004] The electronic device for providing an image to a user may be a smart phone, a laptop computer, a navigation system, and a smart TV, and includes a display device for displaying an image. For example, the electronic device may be an augmented reality (AR) device, a virtual reality (VR) device, a video projection device, etc. The electronic device may include a micro display device. The micro display device may include a complementary metal oxide semiconductor (CMOS) chip and a light emitting diode disposed on the CMOS chip and displaying a high brightness image. The micro display device may operate at low power. The display technology of the display device including a light emitting diode has been advanced due to the development of display quality.

[0005] It should be understood that this background technology section is intended, in part, to provide a useful background for understanding the technology. However, this background technology section may also include views, concepts or understandings of parts that were not understood by a person skilled in the relevant art before the corresponding effective filing date of the subject matter disclosed herein. Summary of the invention

[0006] The embodiment provides a light emitting diode having excellent light efficiency.

[0007] Embodiments also provide a display device having excellent display quality.

[0008] Embodiments also provide a method of manufacturing a display device.

[0009] However, the embodiments of the present disclosure are not limited to those described herein. The above and other embodiments will become more apparent to those skilled in the art to which the present disclosure belongs by referring to the detailed description of the present disclosure given below.

[0010] An embodiment of the present disclosure provides a light-emitting diode, which includes: a first electrode portion; a second electrode portion, disposed on the first electrode portion; and a semiconductor junction structure, disposed between the first electrode portion and the second electrode portion. The semiconductor junction structure includes: a first semiconductor layer; a second semiconductor layer, disposed on the first semiconductor layer; a third semiconductor layer, disposed on the second semiconductor layer; an optical layer; and an active layer, which is spaced apart from the optical layer in the thickness direction. Any one of the optical layer and the active layer is disposed between the first semiconductor layer and the second semiconductor layer, and the other of the optical layer and the active layer is disposed between the second semiconductor layer and the third semiconductor layer. The optical layer includes a porous layer and a non-porous layer disposed on the porous layer. In a direction perpendicular to the thickness direction, the first width of the porous layer is greater than the second width of the non-porous layer.

[0011] In an embodiment, the first refractive index of the porous layer may be less than the second refractive index of the non-porous layer.

[0012] In an embodiment, the porous layer and the non-porous layer may each include the same semiconductor material as any two of the first to third semiconductor layers.

[0013] In an embodiment, the optical layer may include at least one of gallium nitride (GaN), indium gallium nitride (InGaN), and aluminum gallium nitride (AlGaN).

[0014] In an embodiment, the thickness of the porous layer may satisfy the following equation 1, and the thickness of the non-porous layer may satisfy the following equation 2:

[0015] [Equation 1]

[0016] T 1 =λ 0 / 4n 1

[0017] [Equation 2]

[0018] T 2 =λ 0 / 4n 2

[0019] In equation 1, n 1 is the refractive index of the porous layer, and T 1 is the thickness of the porous layer, in Equation 2, n 2 is the refractive index of the nonporous layer, and T 2 is the thickness of the non-porous layer, and in Equations 1 and 2, λ 0 is the wavelength of light emitted from the active layer.

[0020] In an embodiment, the thickness of the non-porous layer may be about 2 μm thicker than the thickness of the porous layer. 0+1 times, where m 0 Is an integer of 0 or greater.

[0021] In an embodiment, the optical layer may be disposed between the second semiconductor layer and the third semiconductor layer. The active layer may be disposed between the first semiconductor layer and the second semiconductor layer. Each of the second semiconductor layer and the third semiconductor layer may include an N-type semiconductor layer. The first semiconductor layer may include a P-type semiconductor layer.

[0022] In an embodiment, the optical layer may be disposed between the first semiconductor layer and the second semiconductor layer. The active layer may be disposed between the second semiconductor layer and the third semiconductor layer. Each of the first semiconductor layer and the second semiconductor layer may include an N-type semiconductor layer. The third semiconductor layer may include a P-type semiconductor layer.

[0023] In an embodiment of the present disclosure, a display device includes: a complementary metal oxide semiconductor (CMOS) wafer; and a plurality of light emitting diodes disposed on the CMOS wafer. Each of the light emitting diodes includes: a first electrode portion; a second electrode portion disposed on the first electrode portion; and a semiconductor junction structure disposed between the first electrode portion and the second electrode portion. The semiconductor junction structure includes: a first semiconductor layer; a second semiconductor layer disposed on the first semiconductor layer; a third semiconductor layer disposed on the second semiconductor layer; an optical layer; and an active layer spaced apart from the optical layer in the thickness direction. Any one of the optical layer and the active layer is disposed between the first semiconductor layer and the second semiconductor layer, and the other of the optical layer and the active layer is disposed between the second semiconductor layer and the third semiconductor layer. The optical layer includes a porous layer and a non-porous layer disposed on the porous layer. In a direction perpendicular to the thickness direction, the first width of the porous layer is greater than the second width of the non-porous layer.

[0024] In an embodiment, the first refractive index of the porous layer may be less than the second refractive index of the non-porous layer.

[0025] In an embodiment, any two of the porous layer, the non-porous layer, and the first to third semiconductor layers may include the same material.

[0026] In an embodiment, the optical layer may include at least one of gallium nitride (GaN), indium nitride (InN), and indium gallium nitride (InGaN).

[0027] In an embodiment, the display device may further include: a side surface reflection layer disposed on a side surface of the first electrode portion, a side surface of the semiconductor junction structure, a side surface of the second electrode portion, and an upper surface of the second electrode portion. The side surface reflection layer may include at least one of gold (Au), copper (Cu), silver (Ag), titanium (Ti), and aluminum (Al).

[0028] In an embodiment, the display device may further include: a side surface insulating layer disposed on a side surface of the first electrode portion, a side surface of the semiconductor junction structure, a side surface of the second electrode portion, and an upper surface of the second electrode portion. The side surface reflective layer may be disposed on an outer side of the side surface insulating layer.

[0029] In an embodiment, on the side surface of the semiconductor junction structure, an extension direction of the side surface insulating layer may be inclined with respect to the thickness direction.

[0030] In an implementation, an opening exposing a partial region of the upper surface of the second electrode part may be formed through each of the side surface reflective layer and the side surface insulating layer.

[0031] In an embodiment, the plurality of light emitting diodes may include: a first light emitting diode including a second electrode portion; and a second light emitting diode including a second electrode portion. The display device may further include a common electrode configured to electrically connect the second electrode portion of the first light emitting diode and the second electrode portion of the second light emitting diode. The common electrode may contact the partial area through the opening.

[0032] In an implementation, the display device may further include a plurality of lenses disposed on the plurality of light emitting diodes and corresponding to the plurality of light emitting diodes, respectively.

[0033] In an embodiment of the present disclosure, a method for manufacturing a display device includes: preparing a CMOS wafer having a first silicon substrate and a conductive layer disposed on the first silicon substrate; preparing a semiconductor substrate having an initial semiconductor junction structure and a second silicon substrate disposed on the initial semiconductor junction structure; connecting the CMOS wafer and the semiconductor substrate; dry etching the initial semiconductor junction structure to form a semiconductor junction structure; forming a second electrode portion; and forming a first electrode portion. The second electrode portion is formed while the semiconductor junction structure is formed or after the semiconductor junction structure is formed. The semiconductor junction structure includes: a first semiconductor layer; a second semiconductor layer formed on the first semiconductor layer; a third semiconductor layer formed on the second semiconductor layer; an optical layer; and an active layer spaced apart from the optical layer in a thickness direction. Any one of the optical layer and the active layer is formed between the first semiconductor layer and the second semiconductor layer, and the other of the optical layer and the active layer is formed between the second semiconductor layer and the third semiconductor layer. The optical layer includes a porous layer and a non-porous layer disposed on the porous layer. After dry etching the initial semiconductor junction structure, the porous layer and the non-porous layer are formed by electrochemical etching.

[0034] In an embodiment, a first width of the porous layer may be greater than a second width of the non-porous layer in a direction perpendicular to the thickness direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Further understanding of embodiments according to the present disclosure will become more apparent by describing in detail elements of the present disclosure with reference to the accompanying drawings, in which:

[0036] Figure 1 is a schematic perspective view of a display device according to an embodiment;

[0037] Figure 2 is a schematic cross-sectional view of a display device according to an embodiment;

[0038] Figure 3 is a schematic plan view of a display device according to an embodiment;

[0039] Figure 4 is a schematic plan view of a display device according to an embodiment;

[0040] Figure 5 yes Figure 3 A schematic enlarged plan view of region AA';

[0041] Figure 6 is shown corresponding to Figure 5 A schematic cross-sectional view of a portion taken along line II';

[0042] Figure 7 yes Figure 6 A schematic enlarged cross-sectional view of region YY';

[0043] Figure 8 yes Figure 6 A schematic enlarged cross-sectional view of a region ZZ';

[0044] Fig. 9 yes Figure 6 A schematic enlarged cross-sectional view of region XX';

[0045] Fig. 10A is a diagram schematically showing a light emitting diode according to an embodiment;

[0046] Fig. 10B is a diagram schematically showing a light emitting diode according to an embodiment;

[0047] Fig.11 is a schematic cross-sectional view showing a portion of a light emitting diode according to an embodiment;

[0048] Fig.12 is a schematic cross-sectional view showing a portion of a light emitting diode according to an embodiment;

[0049] Fig.13 is a diagram schematically showing brightness according to thickness;

[0050] Fig.14is a flowchart schematically illustrating a method of manufacturing a display device according to an embodiment;

[0051] Fig.15 is a diagram schematically showing a manufacturing step of a display device according to an embodiment;

[0052] Fig.16 is a diagram schematically showing a manufacturing step of a display device according to an embodiment;

[0053] Fig.17 is a diagram schematically showing a manufacturing step of a display device according to an embodiment;

[0054] Fig.18 is a diagram schematically showing a manufacturing step of a display device according to an embodiment;

[0055] Fig.19 is a diagram schematically showing a manufacturing step of a display device according to an embodiment;

[0056] Fig. 20 is a diagram schematically showing a manufacturing step of a display device according to an embodiment;

[0057] Fig.21 is a diagram schematically showing a manufacturing step of a display device according to an embodiment;

[0058] Fig. 22 is a diagram schematically showing a manufacturing step of a display device according to an embodiment;

[0059] Fig.23 is a diagram schematically showing a manufacturing step of a display device according to an embodiment;

[0060] Fig.24 is a diagram schematically showing a manufacturing step of a display device according to an embodiment;

[0061] Fig.25 is a diagram schematically showing a manufacturing step of a display device according to an embodiment;

[0062] Fig.26 is a diagram schematically showing a manufacturing step of a display device according to an embodiment;

[0063] Fig. 27 is a diagram schematically showing a manufacturing step of a display device according to an embodiment;

[0064] Fig.28 is a diagram schematically showing a manufacturing step of a display device according to an embodiment; and

[0065] Fig.292 is a diagram schematically showing a manufacturing step of a display device according to an embodiment. DETAILED DESCRIPTION

[0066] In the following description, for the purpose of explanation, many specific details are set forth to provide a thorough understanding of various embodiments or implementations of the present disclosure. As used herein, "embodiment" and "implementation" are interchangeable words, which are non-limiting examples of the devices or methods disclosed herein. However, it is apparent that various embodiments can be practiced without these specific details or with one or more equivalent arrangements. Here, various embodiments do not have to be exclusive or limit the present disclosure. For example, the specific shape, configuration and characteristics of an embodiment can be used or implemented in another embodiment.

[0067] When an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, it may be directly disposed on, directly connected to, or directly coupled to the other element or layer, or there may be intervening elements or layers. However, when an element or layer is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. For this purpose, the term "connected" may refer to a physical connection, an electrical connection, and / or a fluid connection with or without intervening elements.

[0068] Unless otherwise specified, the described embodiments should be understood to provide features of the present disclosure. Therefore, unless otherwise specified, the features, components, modules, layers, films, panels, regions and / or aspects, etc. (hereinafter, individually or collectively referred to as "elements") of various embodiments may be combined, separated, interchanged and / or rearranged in other ways without departing from the present disclosure.

[0069] The use of cross hatching and / or shading in the drawings is generally provided to clarify the boundaries between adjacent elements. Thus, unless specified, the presence or absence of cross hatching or shading does not convey or indicate any preference or requirement for a particular material, material property, size, ratio, commonality between the elements shown, and / or any other characteristic, attribute, property, etc. of the elements. In addition, in the drawings, the size and relative size of the elements may be exaggerated for the purpose of clarity and / or description. When the embodiment may be implemented differently, a specific process sequence may be performed differently from the described sequence. For example, two processes described in succession may be performed substantially simultaneously or in an order opposite to the described sequence. In addition, the same reference numerals represent the same elements.

[0070] Although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Therefore, without departing from the teachings of the present disclosure, the first element discussed below may be referred to as the second element.

[0071] The terms used herein are for the purpose of describing particular embodiments and are not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0072] For the purpose of description, spatial relative terms such as "below", "below", "under", "down", "above", "up", "above", "higher", "side" (e.g., as in "sidewall"), etc. may be used herein, and thereby describe the relationship of one element to another element (or elements) as shown in the drawings. In addition to the orientation depicted in the drawings, spatial relative terms are intended to include different orientations of the device in use, operation and / or manufacture. For example, if the device in the drawings is flipped, the elements described as being "below" or "below" other elements or features will then be oriented "above" the other elements or features. Therefore, the term "below" can include both above and below orientations. In addition, the device can be oriented otherwise (e.g., rotated 90 degrees or in other orientations), and therefore, the spatial relative descriptors used herein should be interpreted accordingly.

[0073] Furthermore, when used in this specification, the terms “comprises,” “comprising,” “includes” and / or “including” specify the presence of stated features, integers, steps, operations, elements, components and / or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0074] As used herein, "about" or "approximately" is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, in view of the measurements in question and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0075] For the purpose of the present disclosure, the phrase "at least one of A and B" may be interpreted as only A, only B, or any combination of A and B. In addition, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z.

[0076] Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. It will also be understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and should not be interpreted in an idealized or overly formal sense unless clearly defined as such herein.

[0077] Various embodiments are described herein with reference to cross-sectional views and / or exploded views as schematic diagrams of embodiments and / or intermediate structures. Therefore, variations in the shapes in the figures, such as due to manufacturing techniques and / or tolerances, should be expected. Therefore, the embodiments disclosed herein should not necessarily be interpreted as being limited to the specific illustrated regional shapes, but should include deviations in shapes such as those caused by manufacturing. In this way, the regions shown in the drawings may be schematic in nature, and the shapes of these regions may not reflect the actual shapes of the regions of the device, and are therefore not necessarily intended to be limiting.

[0078] As is customary in the art, some embodiments are described and shown in the accompanying drawings for functional blocks, units and / or modules. It will be understood by those skilled in the art that these blocks, units and / or modules are physically implemented by electrical circuits (or optical circuits) such as logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, wiring connectors, etc., which can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. In the case where blocks, units and / or modules are implemented by microprocessors or other similar hardware, they can be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and they can be selectively driven by firmware and / or software. It is also conceivable that each block, unit and / or module can be implemented by dedicated hardware, or can be implemented as a combination of dedicated hardware for performing some functions and processors (e.g., one or more programmed microprocessors and associated circuits) for performing other functions. In addition, without departing from the scope of the present disclosure, each block, unit and / or module of some embodiments can be physically separated into two or more interactive and discrete blocks, units and / or modules. Furthermore, the blocks, units and / or modules of some embodiments may be physically combined into more complex blocks, units and / or modules without departing from the scope of the present disclosure.

[0079] Hereinafter, embodiments of the present disclosure are described with reference to the accompanying drawings. Figure 1 is a schematic perspective view of a display device DD according to an embodiment.

[0080] refer to Figure 1 , the display device DD may have a rectangular shape including a long side parallel to the first direction axis DR1 and a short side parallel to the second direction axis DR2 intersecting (or crossing) the first direction axis DR1. However, the embodiments of the present disclosure are not limited thereto, and the display device DD may have various shapes, such as a circular shape or other polygonal shapes.

[0081] The display device DD according to the embodiment can be activated in response to an electrical signal. For example, the display device DD can receive an electrical signal and display an image. The display device DD can be a television, a monitor, a billboard, a tablet computer, a car navigation unit, a personal computer, a laptop computer, a personal digital assistant, a game console, a smart phone, a camera, an augmented reality (AR) device, a virtual reality (VR) device, a video projection device, etc. For example, the display device DD can be applied to an augmented reality (AR) device (for example, included in an augmented reality (AR) device). However, the present disclosure is not limited thereto, and the display device DD can also be applied to other devices (for example, included in other devices).

[0082] The display device DD may display a video (or an image) through a display surface DS. The display surface DS may be parallel to a plane defined by the first direction axis DR1 and the second direction axis DR2.

[0083] The display surface DS may include a display area DA and a non-display area NDA adjacent to the display area DA. The display device DD may display an image through the display area DA. The non-display area NDA may surround the display area DA. However, the present disclosure is not limited thereto, and the non-display area NDA may also be disposed adjacent to only one side of the display area DA. In other embodiments, the non-display area NDA may also be omitted.

[0084] The pixels PX may be arranged in the display area DA. The pixels PX may be arranged in a matrix. The pixels PX may each include a pixel circuit and a light emitting diode. For example, the pixels PX may generate light of the same color. In other embodiments, the pixels PX may include pixel groups that generate light of different colors.

[0085] exist Figure 1In the following drawings, a first direction axis (or first direction) DR1, a second direction axis (or second direction) DR2, and a third direction axis (or third direction) DR3 may be shown. In the present specification, the directions indicated by the first direction axis DR1, the second direction axis DR2, and the third direction axis DR3 are relative concepts and may therefore be changed to other directions. For example, the directions indicated by the first direction axis DR1, the second direction axis DR2, and the third direction axis DR3 may be described as a first direction to a third direction, and may be represented by the same reference symbol or label. In the present specification, the first direction axis DR1 and the second direction axis DR2 may intersect at a certain angle (or intersect at right angles), and the third direction axis DR3 may be a normal direction relative to a plane defined by the first direction axis DR1 and the second direction axis DR2.

[0086] The thickness direction of the display device DD may be parallel to the third directional axis DR3, which is the normal direction relative to the plane defined by the first directional axis DR1 and the second directional axis DR2. In the present specification, the front surface (or upper surface) and the rear surface (or lower surface) of each of the components constituting the display device DD may be defined based on the third directional axis DR3. For example, the front surface and the rear surface of the display device DD may be perpendicular to the third directional axis DR3. The front surface (or upper surface, upper side) may be adjacent to the display surface DS (or in a direction close to the display surface DS), and the rear surface (or lower surface, lower side) may be spaced apart from the display surface DS (or in a direction away from the display surface DS). In the present specification, "on a plane" refers to a surface parallel to the plane defined by the first directional axis DR1 and the second directional axis DR2, and "on a cross section" refers to a surface parallel to the third directional axis DR3.

[0087] Figure 2 is a schematic cross-sectional view schematically showing a display device DD according to an embodiment. Figure 2 The display device DD may include a circuit element layer 10 and a light emitting element layer 20. The display device DD may further include a lens layer 30.

[0088] The circuit element layer 10 may include a pixel circuit. The pixel circuit may control the light emitting diode LED (eg, reference Figure 6 ) operation. A detailed description of the pixel circuit is provided below. The pixel circuit may include at least one transistor. The circuit element layer 10 may include a complementary metal oxide semiconductor (CMOS) wafer. The CMOS wafer may include an nMOSFET (NMOS) and a pMOSFET (PMOS) electrically connected to each other in a complementary relationship. The pixel areas may be regularly arranged in the CMOS wafer, and a pixel circuit may be provided for each pixel area.

[0089] The light emitting element layer 20 may include a light emitting diode LED (eg, a reference Figure 6 ). The light emitting diode LED may be an electrically driven light emitting diode. For example, the light emitting diode LED may be a compound semiconductor and include at least one of gallium (Ga), phosphorus (P) and arsenic (As) as a main semiconductor material. When a forward current is applied to the PN junction structure, electrons and holes may recombine at the junction surface (e.g., the interface of the PN junction) and generate light of a wavelength (e.g., a specific or selectable wavelength) corresponding to the energy band gap. The following provides a light emitting diode LED (e.g., reference Figure 6 ) in detail.

[0090] The lens layer 30 may be disposed on the light emitting element layer 20 and may include a lens. The lens may correspond to a light emitting diode. The lens may converge light emitted from the light emitting diode. For example, the lens may include various types of lenses such as a multi-channel lens, a convex lens, a concave lens, a spherical lens, an aspherical lens, a single lens, a compound lens, a standard lens, a narrow-angle lens, a wide-angle lens, a fixed focus lens, a variable focus lens, etc. However, the present disclosure is not limited thereto.

[0091] Figure 3 1 is a schematic plan view showing a common electrode CME disposed in a display area DA and a non-display area NDA of a display device DD. The display area DA and the non-display area NDA of the display device DD may also be similarly applied to the reference Figure 2 The circuit element layer 10 is described as a CMOS wafer. Figure 2 ) can be described as a CMOS wafer 10 (e.g., referring to Figure 2 ) and are denoted by the same reference numerals.

[0092] The common electrode CME may cover at least the display area DA. The common electrode CME may transmit a power voltage applied from the outside to the entire area of ​​the display area DA. Hereinafter, the display area DA may be described as a first area DA and denoted by the same reference symbol.

[0093] The non-display area NDA may be divided into a plurality of areas. The non-display area NDA may include a second area NDA1 and a third area NDA2. The second area NDA1 may be disposed outside the first area DA, and a dummy light emitting diode (not shown) may be disposed in the second area NDA1. For example, the second area NDA1 may be adjacent to the first area DA (e.g., surrounding the first area DA). However, the embodiments of the present disclosure are not limited thereto. The dummy light emitting diode and the light emitting diode in the first area DA may have the same stacking structure. However, the dummy light emitting diode may not be electrically connected to the common electrode CME and may not work (or emit light).

[0094] In the case where light-emitting diodes (e.g., light-emitting diodes and dummy light-emitting diodes in the first area DA) are formed in an area (e.g., a specific or optional area) by the same process, the outer area (e.g., the area in which the dummy light-emitting diodes are formed) and the inner area (e.g., the first area DA) may be formed using different process conditions. For example, the thickness of the deposition component may be different, or the etching rate may be different. Therefore, a poor light-emitting diode may be formed in the outer area. Therefore, the light-emitting diode formed outside (e.g., a poor light-emitting diode) may be used as a dummy light-emitting diode and may not be a valid light-emitting diode (e.g., the light-emitting diode in the first area DA). However, the present disclosure is not limited thereto, and the dummy light-emitting diode and the second area NDA1 may be omitted.

[0095] The third area NDA2 may include an inner area NDA21 (hereinafter, a 3-1st area) and an outer area NDA22 (hereinafter, a 3-2nd area) distinguished according to whether the common electrode CME is set. For example, the common electrode CME may be set in the 3-1st area NDA21, and may not be set in the 3-2nd area NDA22. The 3-1st area NDA21 may be set to be closer to the first area DA than the 3-2nd area NDA22. The 3-2nd area NDA22 may be separated from the first area DA, and the 3-1st area NDA21 may be set between the first area DA and the 3-2nd area NDA22.

[0096] The common electrode CME may be disposed in the 3-1st region NDA21, and the light emitting diode or the dummy light emitting diode may not be disposed in the 3-1st region NDA21. For example, the 3-1st region NDA21 may be adjacent to the second region NDA1 (e.g., surrounding the second region NDA1). However, the embodiments of the present disclosure are not limited thereto. The range of the 3-1st region NDA21 may be determined by the edge of the common electrode CME.

[0097] The common electrode CME may not be disposed in the 3-2 region NDA22. For example, the 3-2 region NDA22 may be adjacent to the 3-1 region NDA21 (for example, surrounding the 3-1 region NDA21). However, the embodiments of the present disclosure are not limited thereto. The driving circuit may be disposed in the CMOS wafer 10 (for example, referring to Figure 2 ) in the 3-2 area NDA22 of the CMOS wafer 10. For example, the scan driver may be disposed in each of the left area and the right area on the first direction (or the first direction axis) DR1 of the 3-2 area NDA22, and the first area DA may be disposed between the left area and the right area on the first direction DR1 of the 3-2 area NDA22. The data driver may be disposed in a partial area of ​​the 3-2 area NDA22 on the lower side disposed on the second direction (or the second direction axis) DR2 of the first area DA. An analog circuit such as a power circuit may also be disposed in the partial area of ​​the 3-2 area NDA22. The scan driver, the data driver, and the analog circuit may be embedded in the CMOS wafer 10. For example, the scan driver, the data driver, and the analog circuit may include transistors. The pixel circuit and the transistors of the scan driver, the data driver, and the analog circuit may be formed in the same method.

[0098] A pad area PDA in which the pad electrode PD is disposed may be disposed on one side (eg, lower side) of the 3-2 area NDA 22. The pad area PDA may correspond to a partial area of ​​the 3-2 area NDA 22. A circuit board may be electrically connected to the pad area PDA. Figure 3 Only four pad electrodes PD receiving the power voltage applied to the common electrode CME are shown. However, the present disclosure is not limited thereto, and more pad electrodes may be provided in the pad area PDA. The pad electrodes not shown may receive a data image signal or a control signal from the outside and provide the received signal to the data driver.

[0099] The voltage transmission electrode VTE may be disposed in the 3-2 area NDA22. Figure 3 , the four voltage transmission electrodes VTE may correspond to (e.g., be electrically connected to) the four pad electrodes PD. The voltage transmission electrode VTE may extend from the common electrode CME toward the pad area PDA. The voltage transmission electrode VTE and the common electrode CME may be formed by the same process and have the same stacking structure and integrated form. The voltage transmission electrode VTE and the common electrode CME may be different parts of the electrode formed by the same process.

[0100] Figure 4is a schematic plan view showing the arrangement relationship of the common electrode CME, the voltage transmission electrode VTE, and the auxiliary electrode SE. The auxiliary electrode SE may overlap each of the common electrode CME and the voltage transmission electrode VTE. In the thickness direction (e.g., the third directional axis or the third direction) DR3, the auxiliary electrode SE may be disposed below the common electrode CME and the voltage transmission electrode VTE. In the thickness direction DR3, the auxiliary electrode SE may be disposed in a groove disposed below the common electrode CME and the voltage transmission electrode VTE. A detailed description of a cross section of the arrangement relationship of the auxiliary electrode SE, the common electrode CME, and the voltage transmission electrode VTE is provided below.

[0101] In this specification, a component overlapping another component means overlapping. The component overlapping another component is not limited to components having the same area and the same shape, and also includes components having different areas and / or shapes from each other.

[0102] The auxiliary electrodes SE may include first auxiliary electrodes SE1 extending in a first direction (or first direction axis) DR1 and second auxiliary electrodes SE2 extending in a second direction (or second direction axis) DR2. The first auxiliary electrodes SE1 may be arranged in the second direction DR2, and the second auxiliary electrodes SE2 may be arranged in the first direction DR1.

[0103] A portion of the auxiliary electrode SE may overlap with the common electrode CME and may be electrically connected to (e.g., completely connected to) the common electrode CME. Thus, a voltage drop in the common electrode CME may be reduced. Another portion of the auxiliary electrode SE may overlap with the voltage transmission electrode VTE and another portion may be electrically connected to (e.g., completely connected to) the voltage transmission electrode VTE. Thus, the pad electrode PD (e.g., reference electrode PD) may be reduced. Figure 3 ) and the common electrode CME. The auxiliary electrode SE (eg, the auxiliary electrode SE in the display area DA and the non-display area NDA) may be formed by the same process regardless of the area and may have an integrated form.

[0104] Figure 5 It is shown Figure 3 Schematic enlarged plan view of area AA' of the first area DA in FIG. Figure 6 It is shown along Figure 5 A schematic cross-sectional view of a portion taken along line II'.

[0105] refer to Figure 5The auxiliary electrode SE may include a first auxiliary electrode SE1 and a second auxiliary electrode SE2. The first auxiliary electrode SE1 and the second auxiliary electrode SE2 may intersect (or cross) each other. The first auxiliary electrodes SE1 may be disposed in the first trenches TC1, respectively, and the second auxiliary electrodes SE2 may be disposed in the second trenches TC2, respectively.

[0106] The first area DA (for example, reference Figure 3 ) may include a unit area UA and a boundary area BA between the unit areas UA. The unit areas UA may each be an inner area (or boundary area) defined by adjacent first trenches TC1 in the first trenches TC1 and adjacent second trenches TC2 in the second trenches TC2. The first trenches TC1 and the second trenches TC2 are located in the boundary area BA.

[0107] refer to Figure 5 , the light emitting diode LED and the lens LS may be disposed in the unit area UA. For example, each of the light emitting diodes LED and each of the lenses LS may be disposed in each of the unit areas UA. The first opening COP1 may be defined in the unit area UA. For example, each of the first openings COP1 may be disposed in each of the unit areas UA.

[0108] Through the first opening COP1, Figure 6 The common electrode CME and Figure 6 The light emitting diodes LED in the light emitting diodes LED may be electrically connected to each other. The first openings COP1 may be respectively defined inside corresponding lenses LS in the lenses LS. The lenses LS may be respectively disposed on the sides of corresponding light emitting diodes LED in the light emitting diodes LED.

[0109] Figure 6 It can be schematically shown Figure 2 A cross-sectional view of the configuration of the display device DD in FIG. Figure 2 ) may include a CMOS wafer 10, a light emitting element layer 20 and a lens layer 30 stacked in sequence.

[0110] The CMOS wafer 10 may include a silicon substrate 101. A source / drain region 111 may be defined in the silicon substrate 101. The source / drain region 111 may each be a region doped with a dopant. Depending on the flow of a signal, the source / drain region 111 may be a source of a transistor or a drain of a transistor. A pair of source / drain regions 111 and a gate 121 may define a transistor. A detailed description of a pair of source / drain regions 111 is provided below.

[0111] Shallow trench isolation (STI) regions 115 may be further defined in the silicon substrate 101. The STI regions 115 may isolate transistors and prevent leakage current. The arrangement of the STI regions 115 may vary depending on the design of the pixel circuit.

[0112] The gate 121 may be disposed on the silicon substrate 101. The gate 121 may include a metal. The gates 121 may each correspond to a pair of source / drain regions 111. The first insulating layer 123 may be disposed on the silicon substrate 101. The first insulating layer 123 may include a single layer or multiple layers. For example, the first insulating layer 123 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide. However, the present disclosure is not limited thereto.

[0113] The CMOS wafer 10 may include a first contact electrode 125. The first contact electrode 125 may be electrically connected to the source / drain region 111 through a first contact hole CH1 defined in the first insulating layer 123. The first contact electrode 125 and the upper surface of the first insulating layer 123 may define the same flat surface (or flattened surface). The first contact electrode 125 may be formed by a damascene method. The first contact electrode 125 may include a metal such as copper, tungsten, an alloy thereof, etc. However, the present disclosure is not limited thereto.

[0114] The second insulating layer 130 may be disposed on the first insulating layer 123. A second contact hole CH2 exposing the first contact electrode 125 may be defined in the second insulating layer 130. The second insulating layer 130 may include a single layer or multiple layers. For example, the second insulating layer 130 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide. However, the present disclosure is not limited thereto.

[0115] The second contact electrode 135 may be disposed in the second contact hole CH2. The upper surfaces of the second contact electrode 135 and the second insulating layer 130 may define the same flat surface (or flattened surface). The second contact electrode 135 may include a metal structure 135-1 and a barrier layer 135-2. The metal structure 135-1 may be disposed in the second contact hole CH2. The barrier layer 135-2 may be disposed between the side surface of the metal structure 135-1 and the inner side surface of the second contact hole CH2, and between the lower surface of the metal structure 135-1 and the upper surface of the first contact electrode 125. For example, the barrier layer 135-2 may extend from the upper surface of the first contact electrode 125 to the side surface of the metal structure 135-1. The upper surface of the first contact electrode 125 may be exposed through the second contact hole CH2.

[0116] The metal structure 135-1 may include a metal such as copper, tungsten, an alloy thereof, etc. However, the present disclosure is not limited thereto. The barrier layer 135-2 may have conductivity. The barrier layer 135-2 may increase the bonding force of the second contact electrode 135 to the second insulating layer 130 and the first contact electrode 125. For example, the barrier layer 135-2 may increase the bonding force between the second contact electrode 135 and the second insulating layer 130 and the bonding force between the second contact electrode 135 and the first contact electrode 125. Therefore, the barrier layer 135-2 may prevent the metal atoms of the metal structure 135-1 from diffusing to the second insulating layer 130.

[0117] The barrier layer 135-2 may include a barrier metal layer and a barrier metal nitride layer. The barrier metal nitride layer may be disposed closer to the second insulating layer 130 than the barrier metal layer. The barrier metal layer may increase the bonding force, and the barrier metal nitride layer may prevent the metal atoms included in the metal structure 135-1 from diffusing (e.g., diffusing toward the second insulating layer 130). The barrier metal may include titanium, tantalum, or an alloy thereof. The barrier layer 135-2 may include a titanium nitride layer and a titanium layer, or may include a tantalum nitride layer and a tantalum layer. However, the present disclosure is not limited thereto.

[0118] The second contact electrode 135 may include a tungsten structure, a titanium layer adjacent to the side surface and the lower surface of the tungsten structure (e.g., surrounding the side surface and the lower surface of the tungsten structure), and a titanium nitride layer adjacent to the titanium layer (e.g., surrounding the titanium layer). The second contact electrode 135 may include a copper structure, a tantalum layer adjacent to the side surface and the lower surface of the copper structure (e.g., surrounding the side surface and the lower surface of the copper structure), and a tantalum nitride layer adjacent to the tantalum layer (e.g., surrounding the tantalum layer).

[0119] Figure 7 1 is a schematic enlarged cross-sectional view showing a region YY′ which is a contact region between the second contact electrode 135 and the first electrode portion ES1. Figure 7 As shown in , the upper surface of the second contact electrode 135 may be concave. The concave upper surface of the second contact electrode 135 may be in contact with the first electrode portion ES1. A detailed description of the first electrode portion ES1 is provided below. The second contact electrode 135 may be formed by a damascene method. In a chemical mechanical polishing (CMP) process of the damascene method, the polishing degree of the second insulating layer 130 may be greater than the polishing degree of the second contact electrode 135. Therefore, a dishing phenomenon may occur in the second contact electrode 135.

[0120] Reference again Figure 6 , the light emitting diode LED may be disposed on the second insulating layer 130 . Figure 6The light emitting diodes LED shown in can generate light of the same wavelength range. In other embodiments, the light emitting diodes LED can generate light of different wavelength ranges from each other. For example, Figure 5 One of the four light emitting diodes LED shown in the figure can generate red light, another light emitting diode LED can generate green light, and another light emitting diode LED can generate blue light. The remaining light emitting diodes LED can generate one of red light, green light, blue light and white light. For example, the four light emitting diodes LED can generate red light, green light, blue light and white light (or other light) respectively.

[0121] refer to Figure 6 The light emitting diode LED may include a first electrode portion ES1, a second electrode portion ES2 disposed on the first electrode portion ES1, and a semiconductor junction structure SJS disposed between the first electrode portion ES1 and the second electrode portion ES2. The light emitting diode LED according to the embodiment may include a porous layer RL (for example, referring to Fig.11 ) and nonporous layer NRL (e.g., ref. Fig.11 ). A detailed description of the porous layer RL and the non-porous layer NRL is provided below. Therefore, the light emitting diode LED can have excellent light efficiency without increasing the thickness. For example, the brightness of the light emitting diode LED can be increased, and the display device DD (for example, reference Figure 1 ) can be reduced in thickness. According to the embodiment, the display device DD including the light emitting diode LED can provide excellent display efficiency and display quality.

[0122] The first electrode portion ES1 may be in contact with the second contact electrode 135. In the first direction (or first direction axis) DR1, the first electrode portion ES1 may have a width (or diameter) greater than a width (or diameter) of each of the semiconductor junction structure SJS and the second electrode portion ES2. The semiconductor junction structure SJS and the second electrode portion ES2 may be disposed inside the first electrode portion ES1. In other embodiments, the first electrode portion ES1, the semiconductor junction structure SJS, and the second electrode portion ES2 may have the same width (or diameter).

[0123] Hereinafter, the first electrode portion ES1 may be an anode, and the second electrode portion ES2 may be a cathode. However, embodiments of the present disclosure are not limited thereto. In other embodiments, the first electrode portion ES1 may be a cathode, and the second electrode portion ES2 may be an anode.

[0124] The light emitting element layer 20 may include a first side surface insulating layer SI1 disposed adjacent to a side surface of the light emitting diode LED. The first side surface insulating layer SI1 may be adjacent to (e.g., surround) the light emitting diode LED except for the first opening COP1 and the lower surface of the first electrode portion ES1. For example, the first opening COP1 may pass through the first side surface insulating layer SI1.

[0125] The first side surface insulating layer SI1 may prevent the light emitting diode LED and the side surface reflective layer SRL from contacting each other. For example, the light emitting diode LED may be electrically insulated from the side surface reflective layer SRL by the first side surface insulating layer SI1. For example, the first side surface insulating layer SI1 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, zirconium oxide, hafnium oxide, and titanium oxide. However, the present disclosure is not limited thereto.

[0126] The side surface reflection layer SRL may be disposed on the outer side of the first side surface insulating layer SI1. The side surface reflection layer SRL may reflect light generated from the light emitting diode LED and improve light efficiency. Therefore, the light generated by the light emitting diode LED may be emitted through the first opening COP1. The side surface reflection layer SRL may include at least one of gold (Au), copper (Cu), silver (Ag), titanium (Ti), and aluminum (Al). However, the present disclosure is not limited thereto.

[0127] For example, a plurality of side surface reflection layers SRL may be disposed on the outer side of the first side surface insulation layer SI1. For the light emitting diode LED, the side surface reflection layers SRL may be disposed to be spaced apart from each other. The side surface reflection layers SRL may be separated and spaced apart from each other in the boundary area BA. For example, the boundary area BA may be disposed between adjacent side surface reflection layers SRL in the side surface reflection layer SRL. However, the embodiments of the present disclosure are not limited thereto, and the side surface reflection layer SRL may have an integrated form. In the case where the side surface reflection layer SRL has an integrated form, the side surface reflection layer SRL may be Figure 3 The first area DA has an integrated form.

[0128] The light emitting element layer 20 may further include a second side surface insulating layer SI2 disposed on the inner side of the first side surface insulating layer SI1. The second side surface insulating layer SI2 may protect a partial area of ​​the side surface of the light emitting diode LED during the manufacturing process of the light emitting diode LED. The second side surface insulating layer SI2 may include a single layer or multiple layers. The second side surface insulating layer SI2 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, zirconium oxide, hafnium oxide, and titanium oxide. However, the present disclosure is not limited thereto.

[0129] The first opening COP1 may correspond to a light emitting region of the light emitting diode LED. The first opening COP1 may correspond to a path electrically connecting the second electrode portion ES2 to the common electrode CME. For example, the second electrode portion ES2 may be electrically connected to the common electrode CME through the first opening COP1.

[0130] The planarization layer 140 may be disposed on the second insulating layer 130. The planarization layer 140 may overlap the unit area UA and the boundary area BA, and may be disposed on the plurality of light emitting diodes LED. The planarization layer 140 may fill an area where the light emitting diode LED is not disposed. The planarization layer 140 may include an organic material.

[0131] The planarization layer 140 may be in contact with the side surface reflection layer SRL. A second opening COP2 overlapping the first opening COP1 may be provided in the planarization layer 140. For example, the second opening COP2 may pass through the planarization layer 140. The second opening COP2 may be aligned with the first opening COP1. The first opening COP1 and the second opening COP2 may be formed by processes different from each other. The second opening COP2 may be formed in an area larger than that of the first opening COP1.

[0132] However, the present disclosure is not limited thereto. The planarization layer 140 may not be disposed on the upper side of the second electrode portion ES2. The upper surface of the planarization layer 140 and the upper surface of the side surface reflective layer SRL may define the same flat surface. The second opening COP2 may also be omitted.

[0133] Grooves TC1 and TC2 (eg, see Figure 5 ) may be defined on the planarization layer 140. Figure 6 In the embodiment, the second trench TC2 is disposed in the boundary area BA between the adjacent unit areas UA in the unit area UA. The second auxiliary electrode SE2 may be disposed in the second trench TC2. The first auxiliary electrode SE1 (eg, referring to Figure 5 ) and the second auxiliary electrode SE2 may be formed by the same process and may have the same structure.

[0134] The second auxiliary electrode SE2 may be formed by a damascene method. The upper surface of the second auxiliary electrode SE2 may be concave. The second auxiliary electrode SE2 may include a metal structure SE2-1 disposed in the second trench TC2 and a barrier layer SE2-2 disposed between the metal structure SE2-1 and the second trench TC2. The metal structure SE2-1 may include a metal, such as copper, tungsten or an alloy thereof. The metal structure SE2-1 and the barrier layer SE2-2 may have conductivity. The barrier layer SE2-2 may increase the bonding force of the second auxiliary electrode SE2 to the planarization layer 140 and prevent the metal atoms of the metal structure SE2-1 from diffusing into the planarization layer 140.

[0135] The barrier layer SE2-2 may include a barrier metal layer and a barrier metal nitride layer. The barrier metal nitride layer may be disposed closer to the planarization layer 140 than the barrier metal layer. For example, the barrier metal nitride layer may be in contact with the planarization layer 140, and the barrier metal layer may be in contact with the metal structure SE2-1. The barrier metal layer may include titanium, tantalum, or an alloy thereof. The barrier metal nitride layer may include a titanium nitride layer or a tantalum nitride layer.

[0136] The common electrode CME may be disposed on the planarization layer 140. The common electrode CME may overlap the unit area UA and the boundary area BA. The common electrode CME may include a transparent conductive material that emits light generated from the light emitting diode LED. The common electrode CME may include a transparent conductive oxide including at least one of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), zinc tin oxide (ZTO), and indium gallium zinc oxide (IGZO). However, the present disclosure is not limited thereto.

[0137] The common electrode CME may be electrically connected to the second electrode portion ES2 of the light emitting diode LED through the first opening COP1 and the second opening COP2. The common electrode CME may contact a partial area AP of each of the second electrode portions ES2 through the first opening COP1 and the second opening COP2. A partial area AP of the second electrode portion ES2 may be exposed by the first opening COP1 and the second opening COP2.

[0138] A power voltage may be applied through the common electrode CME and transmitted to the light emitting diode LED. Figure 6 A common electrode CME electrically connected to two light emitting diodes LED is schematically shown. Any one of the two light emitting diodes LED may be defined as a first light emitting diode LED, and the other of the two light emitting diodes LED may be defined as a second light emitting diode LED.

[0139] The common electrode CME may be in contact with the upper surface of the second auxiliary electrode SE2. Since the upper surface of each of the second auxiliary electrodes SE2 is in contact with the common electrode CME along the length direction of the second trench TC2 (e.g., the second direction DR2), the common electrode CME and the second auxiliary electrode SE2 may ensure a sufficient contact area. For example, the contact area between the common electrode CME and the second auxiliary electrode SE2 may be increased by the second trench TC2.

[0140] The third insulating layer 150 may be disposed on the common electrode CME. The third insulating layer 150 may protect the common electrode CME. The third insulating layer 150 may be separated from the display area DA and the non-display area NDA (eg, reference Figure 3) overlaps, and protects the voltage transmission electrode VTE (eg, reference Figure 3 and Figure 4 ). The third insulating layer 150 may include an organic material or an inorganic material.

[0141] The lens LS may be disposed on the third insulating layer 150 . Figure 6 Two lenses LS corresponding to the first light emitting diode LED and the second light emitting diode LED are shown. The lens LS can collect light emitted from the light emitting diode LED. The lens LS may include an organic material and may have a domelike shape (e.g., a hemispherical shape). For example, in the first direction (or first direction axis) DR1, the diameter of each of the lenses LS may be less than or equal to about 1 μm.

[0142] Figure 8 is shown as Figure 6 A schematic enlarged cross-sectional view of a region ZZ' of the contact region between the third insulating layer 150 and the lens LS in FIG. Figure 6 and Figure 8 In the embodiment, the third insulating layer 150 may include a concave region 150-C. The step may be formed at a position corresponding to Figure 6 The step may be transferred to the common electrode CME and / or the third insulating layer 150 in the region of the first opening COP1 in FIG. 1. Depending on the material and / or thickness of the third insulating layer 150, the step may also be omitted.

[0143] Fig. 9 It is shown Figure 6 A schematic enlarged cross-sectional view of region XX'. Fig. 9 , the side surface SJS_SF of the semiconductor junction structure SJS may be inclined. For example, the side surface SJS_SF of the semiconductor junction structure SJS may be inclined relative to the silicon substrate 101 (eg, reference Figure 6 ) is inclined at a certain angle. The side surface SJS_SF of the semiconductor junction structure SJS may not be parallel to the thickness direction (e.g., the third direction or the third direction axis) DR3. The side surface SJS_SF of the semiconductor junction structure SJS may not be perpendicular to the upper surface ES1_UF of the first electrode portion ES1. In the method of manufacturing a display device according to an embodiment, the semiconductor junction structure SJS may be formed by a dry etching process and may include a side surface SJS_SF that is not parallel to the thickness direction DR3. A detailed description of the method of manufacturing a display device according to an embodiment is provided below.

[0144] The side surface ES2_SF of the second electrode portion ES2 may be substantially parallel to the thickness direction DR3. Substantially parallel includes not only parallel without error but also parallel with a difference within a process error range.

[0145] The second side surface insulating layer SI2 may contact the side surface SJS_SF of the semiconductor junction structure SJS and the side surface ES2_SF of the second electrode portion ES2. In the second side surface insulating layer SI2, the extension direction of the portion in contact with the side surface SJS_SF of the semiconductor junction structure SJS may be inclined relative to the thickness direction DR3. In the second side surface insulating layer SI2, the extension direction of the portion in contact with the side surface ES2_SF of the second electrode portion ES2 may be substantially parallel to the thickness direction DR3. The second side surface insulating layer SI2 may also be disposed on a partial region of the upper surface ES2_UF of the second electrode portion ES2. The second side surface insulating layer SI2 may also be disposed on a region of the upper surface ES1_UF of the first electrode portion ES1 where the semiconductor junction structure SJS is not disposed. For example, the second side surface insulating layer SI2 may be formed along a contour formed by at least a portion of the first electrode portion ES1, the semiconductor junction structure SJS, and the second electrode portion ES2. In the second side surface insulating layer SI2, a first sub-opening S2_OH exposing a partial region AP of the upper surface ES2_UF of the second electrode portion ES2 may be defined.

[0146] The first side surface insulating layer SI1 may be spaced apart from the side surface SJS_SF of the semiconductor junction structure SJS, the side surface ES2_SF of the second electrode portion ES2, and the upper surface ES2_UF of the second electrode portion ES2. The second side surface insulating layer SI2 may be disposed between the first side surface insulating layer SI1 and the side surface SJS_SF of the semiconductor junction structure SJS, the side surface ES2_SF of the second electrode portion ES2, and the upper surface ES2_UF of the second electrode portion ES2. The first side surface insulating layer SI1 may be disposed on the side surface ES1_SF of the first electrode portion ES1, the side surface SJS_SF of the semiconductor junction structure SJS, the side surface ES2_SF of the second electrode portion ES2, and the upper surface ES2_UF of the second electrode portion ES2. For example, the first side surface insulating layer SI1 may extend sequentially from the side surface ES1_SF of the first electrode portion ES1 toward the upper surface ES2_UF of the second electrode portion ES2 through the side surface SJS_SF of the semiconductor junction structure SJS and the side surface ES2_SF of the second electrode portion ES2. The first side surface insulating layer SI1 may also be disposed on the upper surface ES1_UF of the first electrode portion ES1. On the side surface SJS_SF of the semiconductor junction structure SJS, the extension direction of the first side surface insulating layer SI1 may be inclined relative to the thickness direction DR3. For example, in the first side surface insulating layer SI1, the extension direction of the portion disposed on the side surface SJS_SF of the semiconductor junction structure SJS may be inclined relative to the thickness direction DR3. For example, the first side surface insulating layer SI1 may be disposed along a contour formed by the second side surface insulating layer SI2 and the first electrode portion ES1. In the first side surface insulating layer SI1, a second sub-opening S1_OH exposing a partial area AP of the upper surface ES2_UF of the second electrode portion ES2 may be defined.

[0147] The side surface reflection layer SRL may be spaced apart from the first electrode portion ES1 and the semiconductor junction structure SJS. The first side surface insulating layer SI1 may be disposed between the side surface reflection layer SRL and the first electrode portion ES1. The side surface reflection layer SRL may be disposed on the side surface ES1_SF of the first electrode portion ES1, the side surface SJS_SF of the semiconductor junction structure SJS, the side surface ES2_SF of the second electrode portion ES2, and the upper surface ES2_UF of the second electrode portion ES2. For example, the side surface reflection layer SRL may extend sequentially from the side surface ES1_SF of the first electrode portion ES1 toward the upper surface ES2_UF of the second electrode portion ES2 through the side surface SJS_SF of the semiconductor junction structure SJS and the side surface ES2_SF of the second electrode portion ES2. The extension direction of the side surface reflection layer SRL may be inclined relative to the thickness direction DR3. For example, in the side surface reflection layer SRL, the extension direction of the portion disposed on the side surface SJS_SF of the semiconductor junction structure SJS may be inclined relative to the thickness direction DR3. For example, the side surface reflective layer SRL may be disposed along the outline of the first side surface insulating layer SI1. In the side surface reflective layer SRL, a third sub-opening R_OH exposing a partial area AP of the upper surface ES2_UF of the second electrode portion ES2 may be defined.

[0148] The first sub-opening S2_OH of the second side surface insulating layer SI2, the second sub-opening S1_OH of the first side surface insulating layer SI1, and the third sub-opening R_OH of the side surface reflective layer SRL may form a first opening COP1. The inner side surface of the second side surface insulating layer SI2 defining the first sub-opening S2_OH, the inner side surface of the first side surface insulating layer SI1 defining the second sub-opening S1_OH, and the inner side surface of the side surface reflective layer SRL defining the third sub-opening R_OH may be parallel to each other. The common electrode CME may contact the partial area AP of the upper surface ES2_UF of the second electrode portion ES2 through the first opening COP1.

[0149] The planarization layer 140 may be disposed on the side surface ES1_SF of the first electrode portion ES1 and on the side surface SJS_SF of the semiconductor junction structure SJS. For example, the planarization layer 140 may be disposed on the side surface reflective layer SRL along a contour formed by the side surface ES1_SF of the first electrode portion ES1 and the side surface SJS_SF of the semiconductor junction structure SJS. A portion of the planarization layer 140 may correspond to the side surface ES2_SF of the second electrode portion ES2, and another portion may be disposed on the second electrode portion ES2 and overlap the side surface reflective layer SRL.

[0150] Fig. 10A and Fig. 10B It is schematically shown Figure 6FIG. 1 is a diagram of a light emitting diode LED in FIG. The light emitting diode LED may include a first electrode portion ES1, a semiconductor junction structure SJS, and a second electrode portion ES2.

[0151] refer to Fig. 10A and Fig. 10B , the light emitting diode LED may have a column shape. The light emitting diode LED may have a size ranging from nanometer scale to micrometer scale. The light emitting diode LED may have a diameter (or width) and / or length ranging from nanometer scale to micrometer scale. The diameter (or width) may refer to the diameter (or width) in a direction perpendicular to the thickness direction (e.g., the third direction or the third direction axis) DR3, and the length may refer to the length in the thickness direction DR3. However, the size of the light emitting diode LED is not limited thereto, and the size of the light emitting diode LED may vary according to the design conditions of different devices using the light emitting device (which uses the light emitting diode LED) as a light source.

[0152] For example, in the light emitting diode LED, the semiconductor junction structure SJS may have a truncated cone shape. In an embodiment, the semiconductor junction structure SJS may include a first semiconductor layer SC1, a second semiconductor layer SC2 disposed on the first semiconductor layer SC1, a third semiconductor layer SC3 disposed on the second semiconductor layer SC2, an optical layer OPL, and an active layer ACT. In the method for manufacturing a display device according to an embodiment, the semiconductor junction structure SJS of the light emitting diode LED may be formed by a dry etching process and may be manufactured in a truncated cone shape. A detailed description of the method for manufacturing a display device according to the present embodiment is provided below. In the semiconductor junction structure SJS having a truncated cone shape, the diameters of the first semiconductor layer SC1, the second semiconductor layer SC2, and the third semiconductor layer SC3, the optical layer OPL, and the active layer ACT may be different from each other. The diameter may refer to the average width in a direction perpendicular to the thickness direction DR3.

[0153] The optical layer OPL and the active layer ACT may be spaced apart from each other in the thickness direction DR3. Any one of the optical layer OPL and the active layer ACT may be disposed between the first and second semiconductor layers SC1 and SC2, and the other of the optical layer OPL and the active layer ACT may be disposed between the second and third semiconductor layers SC2 and SC3.

[0154] The first semiconductor layer SC1, the second semiconductor layer SC2, and the third semiconductor layer SC3 may each include an N-type semiconductor layer or a P-type semiconductor layer. For example, any one of the first semiconductor layer SC1, the second semiconductor layer SC2, and the third semiconductor layer SC3 may be a P-type semiconductor layer, and the other two of the first semiconductor layer SC1, the second semiconductor layer SC2, and the third semiconductor layer SC3 may be N-type semiconductor layers. For example, the N-type semiconductor layer may include at least one semiconductor material of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may be doped with a first conductive dopant, such as silicon (Si), germanium (Ge), or tin (Sn). The P-type semiconductor layer may include at least one semiconductor material of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may be doped with a second conductive dopant, such as magnesium (Mg), zinc (Zn), calcium (Ca), or barium (Ba). However, this is an example, and the materials constituting the N-type semiconductor layer and the P-type semiconductor layer are not limited thereto.

[0155] refer to Fig. 10A The optical layer OPL may be disposed between the second semiconductor layer SC2 and the third semiconductor layer SC3, and the active layer ACT may be disposed between the first semiconductor layer SC1 and the second semiconductor layer SC2. The second semiconductor layer SC2 and the third semiconductor layer SC3 may each include an N-type semiconductor layer, and the first semiconductor layer SC1 may include a P-type semiconductor layer.

[0156] The second semiconductor layer SC2 and the third semiconductor layer SC3, which are spaced apart from each other and between which the optical layer OPL is disposed, may include an N-type semiconductor layer. The second semiconductor layer SC2 and the third semiconductor layer SC3 may have different dopant concentrations. For example, the dopant concentration doped to the second semiconductor layer SC2 may be greater than the dopant concentration doped to the third semiconductor layer SC3. In other embodiments, the second semiconductor layer SC2 and the third semiconductor layer SC3 may be doped with the same dopant concentration.

[0157] refer to Fig. 10B , the optical layer OPL may be disposed between the first semiconductor layer SC1 and the second semiconductor layer SC2, and the active layer ACT may be disposed between the second semiconductor layer SC2 and the third semiconductor layer SC3. The first semiconductor layer SC1 and the second semiconductor layer SC2 may each include an N-type semiconductor layer, and the third semiconductor layer SC3 may include a P-type semiconductor layer. The first semiconductor layer SC1 and the second semiconductor layer SC2, which are spaced apart from each other and between which the optical layer OPL is disposed, may include an N-type semiconductor layer. The dopant concentrations in the first semiconductor layer SC1 and the second semiconductor layer SC2 may be different from each other.

[0158] The active layer ACT may be formed as a single quantum well structure or a multi-quantum well structure. Electrons and holes may be recombined with each other in the active layer ACT, and emit light in response to an electrical signal applied through the P-type semiconductor layer and the N-type semiconductor layer. The active layer ACT may emit light having a wavelength ranging from about 400 nm to about 900 nm, and a double heterostructure may be used.

[0159] For example, the active layer ACT may have a structure in which a semiconductor material having a large energy band gap and a semiconductor material having a small energy band gap are alternately stacked with each other. The active layer ACT may also include semiconductor materials of Group III to Group V selected according to the wavelength range of the emitted light. In this specification, "group" refers to a group in the IUPAC periodic table.

[0160] Although not shown in the drawings, the light emitting diode LED may further include a cladding layer. The cladding layer may be disposed above the active layer ACT and / or below the active layer ACT. The cladding layer may include AlGaN or InAlGaN. The light emitting diode LED may further include a tensile strain barrier reduction (TSBR) layer disposed above the active layer ACT and / or below the active layer ACT. The TSBR layer may be a strain relief layer disposed between semiconductor layers having different lattice structures and used as a buffer for reducing the lattice constant difference. The TSBR layer may be formed of a P-type semiconductor layer such as p-GaInP, p-AlInP, and p-AlGaInP. However, the embodiments of the present disclosure are not limited thereto.

[0161] The optical layer OPL may be disposed between the N-type semiconductor layers. Fig.11 is a schematic cross-sectional view showing the optical layer OPL. Fig.11 , the optical layer OPL may include a porous layer RL and a non-porous layer NRL disposed on the porous layer RL.

[0162] The number of porous layers RL and the number of non-porous layers NRL may be n. n is an integer of 1 or more. The number of porous layers RL and the number of non-porous layers NRL may be the same. When n is an integer of 2 or more, the porous layers RL and the non-porous layers NRL may be alternately arranged. For example, n may be 10, and Fig.11 The nth porous layer RL shown in n The tenth porous layer may be the nth non-porous layer NRL n It may be a tenth non-porous layer. However, this is an example, and the number of porous layers RL and the number of non-porous layers NRL are not limited to any one embodiment of the present disclosure.

[0163] The porous layer RL may include a first porous layer RL 1 To the nth porous layer RL n The non-porous layer NRL may include a first non-porous layer NRL1 To the nth non-porous layer NRL n .

[0164] In a semiconductor junction structure SJS having a truncated cone shape (e.g., reference Fig. 10A and Fig. 10B ), the first width (eg, the first first width, the second first width, ..., or the nth first width) RW of the porous layer RL 1 , RW 2 , ..., or RW n The second widths NW and NW of the non-porous layer NRL may be respectively greater than the second widths (eg, the first second width, ..., the n-1th second width, or the nth second width) NW. 1 、…、NW n-1 or NW n The first width (eg, the first first width, the second first width, ..., or the nth first width) RW of the porous layer RL 1 , RW 2 , ..., or RW n The second widths NW of the non-porous layer NRL disposed above the porous layer RL may be respectively greater than the second widths (eg, the first second width, . . . , the n-1th second width, or the nth second width) NW. 1 、…、NW n-1 or NW n . The nth porous layer RL n The nth first width RW n Can be larger than the nth nonporous layer NRL n The nth second width NW n . The nth porous layer RL n The nth first width RW n Can be smaller than the n-1th non-porous layer NRL n-1 The n-1th second width NW n-1 . The n-1th non-porous layer NRL n-1 It can be set in the nth porous layer RL n under.

[0165] The first porous layer RL 1 The first width RW 1 It can be larger than the first non-porous layer NRL 1 The first and second widths NW 1 The second porous layer RL 2 The second first width RW 2 It can be smaller than the first nonporous layer NRL 1 The first and second widths NW 1 In the thickness direction (eg, the third direction or the third directional axis) DR3, the first non-porous layer NRL 1 It can be arranged in the first porous layer RL1 above, and disposed on the second porous layer RL 2 under.

[0166] In the thickness direction DR3, the width may decrease from the lower side to the upper side of the optical layer OPL. The second width (e.g., the first second width, ..., the n-1th second width, or the nth second width) NW of the non-porous layer NRL disposed on the upper side in the thickness direction DR3 1 、…、NW n-1 or NW n In contrast, a first width (eg, a first first width, a second first width, . . . , or an nth first width) RW of the porous layer RL disposed on the lower side in the thickness direction DR3 is 1 , RW 2 , ..., or RW n Can be relatively large.

[0167] The porous layer RL and the non-porous layer NRL may include a III-N group (e.g., nitrogen atom) semiconductor compound, and may be doped with a first conductive dopant, such as silicon (Si), germanium (Ge), or tin (Sn). For example, the porous layer RL and the non-porous layer NRL may each include at least one semiconductor material of gallium nitride (GaN), indium gallium nitride (InGaN), and aluminum gallium nitride (AlGaN), and may be doped with a first conductive dopant, such as silicon (Si), germanium (Ge), or tin (Sn).

[0168] The porous layer RL and the non-porous layer NRL may each include a first semiconductor layer SC1, a second semiconductor layer SC2, and a third semiconductor layer SC3 (eg, referring to Fig. 10A and Fig. 10B ) are the same semiconductor material as any two of the semiconductor materials of the porous layer RL and the non-porous layer NRL. The porous layer RL and the non-porous layer NRL may each include the same semiconductor material as the first semiconductor layer SC1, the second semiconductor layer SC2, and the third semiconductor layer SC3 (for example, reference Fig. 10A and Fig. 10B ) in the N-type semiconductor layer. The optical layer OPL composed of the porous layer RL and the non-porous layer NRL may be inserted into the N-type semiconductor layer. However, this is an example, and embodiments of the present disclosure are not limited thereto.

[0169] The dopant of the porous layer RL and the dopant of the non-porous layer NRL may be different from each other in doping concentration. The concentration of the dopant doped to the porous layer RL may be relatively greater than the concentration of the dopant doped to the non-porous layer NRL. In the method of manufacturing a display device according to an embodiment, the optical layer OPL may be formed by an electrochemical (EC) etching process. A detailed description of the method of manufacturing a display device is provided below. By an electrochemical etching process, an optical layer OPL including a porous layer RL and a non-porous layer NRL may be formed. In the case of performing the electrochemical etching process, a porous structure may be formed at a portion of the optical layer OPL having a relatively high doping concentration to form the porous layer RL, and a porous structure may not be formed at another portion of the optical layer OPL having a relatively low doping concentration to form the non-porous layer NRL. For example, the porous layer RL and the non-porous layer NRL may be formed by an electrochemical etching process, and the porous layer RL may have a greater concentration than the non-porous layer NRL. Since a porous structure is formed, point defects may be reduced, and the light emitting diode LED (for example, reference 1) may be prevented from being damaged. Figure 6 ) leakage current and can improve the light emitting diode LED (for example, reference Figure 6 )'s light efficiency.

[0170] Porous layer (eg, first porous layer, second porous layer, ..., or nth porous layer) RL 1 RL 2 , ..., or RL n The thickness (eg, the first thickness, the second thickness, ..., or the nth thickness) RH 1 RH 2 , ..., or RH n The following equation 1 can be satisfied. Nonporous layer NRL 1 、…、NRL n-1 or NRL n The thickness (eg, the first thickness, ..., the n-1th thickness, or the nth thickness) NH 1 ,…,NH n-1 or NH n The following equation 2 may be satisfied.

[0171] [Equation 1]

[0172] T 1 =λ 0 / 4n 1

[0173] [Equation 2]

[0174] T 2 =λ 0 / 4n 2

[0175] In equation 1, n 1may be the refractive index of the porous layer RL, and T 1 It may be a porous layer (eg, a first porous layer, a second porous layer, ..., or an nth porous layer) RL 1 RL 2 , ..., or RL n The thickness (eg, the first thickness, the second thickness, ..., or the nth thickness) RH 1 RH 2 , ..., or RH n In equation 2, n 2 may be the refractive index of the nonporous layer NRL, and T 2 Can be non-porous layer NRL 1 、…、NRL n-1 or NRL n The thickness (eg, the first thickness, ..., the n-1th thickness, or the nth thickness) NH 1 ,…,NH n-1 or NH n In Equation 1 and Equation 2, λ 0 It can be from the active layer ACT (for example, reference Fig. 10A or Fig. 10B )The wavelength of the light emitted.

[0176] Non-porous layer NRL 1 、…、NRL n-1 or NRL n The thickness (eg, the first thickness, ..., the n-1th thickness, or the nth thickness) NH 1 ,…,NH n-1 or NH n It may be a porous layer (eg, a first porous layer, a second porous layer, ..., or an nth porous layer) RL 1 RL 2 , ..., or RL n The thickness (eg, the first thickness, the second thickness, ..., or the nth thickness) RH 1 RH 2 , ..., or RH n About 2m 0 +1 times (where m 0 is an integer of 0 or greater). For example, in m 0 When the non-porous layer NRL is 0 1 、…、NRL n-1 or NRL n The thickness (eg, the first thickness, ..., the n-1th thickness, or the nth thickness) NH 1 ,…,NH n-1 or NH n and a porous layer (eg, a first porous layer, a second porous layer, ..., or an nth porous layer) RL1 RL 2 , ..., or RL n The thickness (eg, the first thickness, the second thickness, ..., or the nth thickness) RH 1 RH 2 , ..., or RH n In other embodiments, in m 0 When the non-porous layer NRL is 1 1 、…、NRL n-1 or NRL n The thickness (eg, the first thickness, ..., the n-1th thickness, or the nth thickness) NH 1 ,…,NH n-1 or NH n It may be a porous layer (eg, a first porous layer, a second porous layer, ..., or an nth porous layer) RL 1 RL 2 , ..., or RL n The thickness (eg, the first thickness, the second thickness, ..., or the nth thickness) RH 1 RH 2 , ..., or RH n About three times.

[0177] The thickness of the optical layer OPL may be in the range of about 600 nm to about 1200 nm, and the thickness of the optical layer OPL is about 100 nm to about 150 nm. 1 To the nth porous layer RL n The first thickness RH 1 To nth thickness RH n With the first non-porous layer NRL 1 , ..., n-1th non-porous layer NRL n-1 and the nth nonporous layer NRL n The first thickness NH 1 、...、n-1th thickness NH n-1 and the nth thickness NH n A light emitting diode LED (eg, reference Figure 6 ) can exhibit excellent light efficiency without increasing the display device DD (e.g., reference Figure 1 ) thickness.

[0178] The optical layer OPL may include layers having different refractive indices. The first refractive index of the porous layer RL may be smaller than the second refractive index of the non-porous layer NRL. 1 , ..., and the nth porous layer RL n ) and a non-porous layer NRL (eg, a first non-porous layer NRL 1, ..., and the nth nonporous layer NRL n ) are alternately arranged, so the optical layer OPL can have a structure in which layers with a relatively small refractive index and layers with a relatively large refractive index are alternately arranged.

[0179] The optical layer OPL may be a reflector configured to reflect light. The optical layer OPL may be a distributed Bragg reflector (DBR). The optical layer OPL may have a reflectivity (e.g., a predetermined or selectable reflectivity). For example, the reflectivity of the optical layer OPL may be close to that of a metal. For example, the reflectivity of the optical layer OPL with respect to light in the visible light wavelength range may be in the range of about 80% to about 95%. In the case where the number of porous layers RL and the number of non-porous layers NRL are increased, the reflectivity may be increased.

[0180] Light emitted from the active layer ACT may be provided to the optical layer OPL. Therefore, since the refractive indices between the porous layer RL and the non-porous layer NRL included in the optical layer OPL are different from each other, reflection of light provided from the active layer ACT may occur at the interface between the porous layer RL and the non-porous layer NRL. The porous layer RL (e.g., the first porous layer RL) 1 , ..., and the nth porous layer RL n ) and a non-porous layer NRL (eg, a first non-porous layer NRL 1 , ..., and the nth nonporous layer NRL n ) can be arranged alternately with each other in the optical layer OPL, and there can be multiple interfaces between adjacent layers in the porous layer RL and the non-porous layer NRL. Constructive interference of reflected light can be generated at the interface, and optical loss can be prevented. Therefore, a light emitting diode LED (for example, reference 1) including an optical layer OPL composed of a porous layer RL and a non-porous layer NRL Figure 6 ) can show excellent light efficiency. Including light emitting diodes LED (for example, reference Figure 6 ) of a display device DD (eg, reference Figure 1 ) can provide excellent display quality.

[0181] For a display device applicable to an augmented reality device (e.g., included in an augmented reality device), directional light emission may be required. In other embodiments, the display device of the augmented reality device may include a light emitting diode having a resonant structure, and the manufacture of the resonant structure may include depositing a reflective layer on the upper / lower side of the light emitting diode. Therefore, the light efficiency may be reduced due to high-order resonance caused by the increased thickness of the light emitting diode.

[0182] In the case where a micro-light emitting diode disposed on a silicon substrate does not include an optical layer consisting of a porous layer and a non-porous layer, only high-order resonances of about the 8th order or higher may be possible. In the case of high-order resonances, the effect of improving light efficiency by resonance may be reduced, and a relatively long cavity length may be required. The cavity length may be parallel to the thickness direction of the light emitting diode, and a long cavity length may increase the thickness of the light emitting diode. In other embodiments, the light emitting diode may have a first transparent conductive oxide layer COL (e.g., reference numeral 20) extending from the first electrode portion ES1. Fig.12 ) to the third semiconductor layer SC3 (eg, reference Fig. 10A ) The following provides a detailed description of the first transparent conductive oxide layer COL of the first electrode portion ES1.

[0183] In other embodiments, for low-order resonance having a relatively low order, the thickness of the N-type semiconductor layer may be reduced. However, in the case where the thickness of the N-type semiconductor layer is reduced, process variation of the N-type semiconductor layer formed by an etching process may increase.

[0184] However, in the embodiment of the present disclosure, the light emitting diode LED may include an optical layer OPL composed of a porous layer RL and a non-porous layer NRL. Therefore, the light emitting diode LED may include a first transparent conductive oxide layer COL (eg, reference numeral 206) formed from the first electrode portion ES1. Fig.12 ) to the second semiconductor layer SC2 (eg, reference Fig. 10A ) in the range of cavity length. For example, the cavity length of the light emitting diode LED of the embodiment of the present disclosure can be increased by the optical layer OPL composed of the porous layer RL and the non-porous layer NRL without increasing the thickness. A detailed description of the first transparent conductive oxide layer COL of the first electrode portion ES1 is provided below. Therefore, the light emitting diode LED according to the embodiment can have the characteristic that low-order resonance is possible. The light emitting diode LED according to the embodiment can exhibit excellent light efficiency without increasing the thickness.

[0185] Fig.12 It is shown Figure 6 A schematic cross-sectional view of a first electrode portion ES1 in FIG. Fig.12, the first electrode portion ES1 may include a reflective layer RFL and a transparent conductive oxide layer COL (hereinafter, referred to as a first transparent conductive oxide layer) disposed on the reflective layer RFL. The first electrode portion ES1 may further include a first barrier layer BRL1 disposed between the reflective layer RFL and the first transparent conductive oxide layer COL, a second barrier layer BRL2 disposed under the reflective layer RFL, and a metal layer ML disposed under the second barrier layer BRL2. However, the present disclosure is not limited thereto, and the first electrode portion ES1 may further include an additional functional layer disposed under the metal layer ML, such as a third barrier layer.

[0186] The reflective layer RFL may be disposed toward the semiconductor junction structure SJS (e.g., reference Fig. 10A and Fig. 10B ) direction from the active layer ACT (eg, reference Fig. 10A and Fig. 10B ) generated by the reflective layer. The reflective layer RFL may include at least one of gold (Au), copper (Cu), silver (Ag), titanium (Ti), and aluminum (Al). However, the present disclosure is not limited thereto. For example, the reflective layer RFL may have a reflectivity of about 90% for light in the visible light wavelength range.

[0187] In the case where the first electrode portion ES1 is an anode, the first transparent conductive oxide layer COL may inject holes into the semiconductor junction structure SJS. The first transparent conductive oxide layer COL may have a high work function that is favorable for hole injection, and may transmit light reflected on the reflective layer RFL. The first transparent conductive oxide layer COL may include at least one of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), zinc tin oxide (ZTO), and indium gallium zinc oxide (IGZO). However, the present disclosure is not limited thereto.

[0188] The metal layer ML may correspond to a layer formed by bonding the CMOS wafer 10 (eg, reference numeral 20 ) during a display device manufacturing process. Fig.16 ) and a semiconductor substrate SUB-S (eg, reference Fig.16 The metal layer ML can be formed by placing the CMOS wafer 10 (for example, reference Fig.16 ) is bonded to a semiconductor substrate SUB-S (eg, reference Fig.16 ) is formed by a metal layer of . The metal layer ML may include a single layer or multiple layers. The metal layer ML may include at least one metal layer. The at least one metal layer may include at least one of gold (Au), copper (Cu), silver (Ag), tin (Sn), titanium (Ti), zirconium (Zr) and tantalum (Ta). For example, the at least one metal layer may include an alloy of two metals thereof. However, the present disclosure is not limited thereto.

[0189] The first barrier layer BRL1 and the second barrier layer BRL2 may each include a barrier metal layer and a barrier metal nitride layer. The barrier metal layer may improve the adhesive strength between adjacent layers, and the barrier metal nitride layer may prevent atoms from diffusing between adjacent layers.

[0190] The first barrier layer BRL1 may include a single layer or multiple layers. For example, the first barrier layer BRL1 may include a barrier metal nitride layer including titanium nitride and a barrier metal layer including titanium and disposed on each of the upper and lower sides of the barrier metal nitride layer. The titanium nitride layer may prevent the movement of metal atoms. Therefore, electromigration may be prevented from occurring between adjacent layers.

[0191] The second barrier layer BRL2 may include a single layer or multiple layers. For example, the second barrier layer BRL2 may include a barrier metal nitride layer including titanium nitride. For example, the titanium nitride layer may block the movement of atoms between the first transparent conductive oxide layer COL and the reflective layer RFL. Therefore, it is possible to prevent the formation of voids on the first transparent conductive oxide layer COL or prevent oxidation of the reflective layer RFL.

[0192] Reference again Fig. 10A and Fig. 10B , the second electrode portion ES2 may include a transparent conductive oxide layer (hereinafter referred to as a second transparent conductive oxide layer). The second transparent conductive oxide layer may include at least one of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), zinc tin oxide (ZTO), and indium gallium zinc oxide (IGZO). However, the present disclosure is not limited thereto. The second transparent conductive oxide layer may correspond to a protective layer in a light emitting diode (LED) manufacturing process, and may inject electrons into the semiconductor junction structure SJS.

[0193] The second electrode portion ES2 may further include an electrode metal layer disposed between the second transparent conductive oxide layer and the semiconductor junction structure SJS. The electrode metal layer may include a metal having a work function lower than that of the second transparent conductive oxide layer. The electrode metal layer may improve the electron injection quality of the second electrode portion ES2. The electrode metal layer may include at least one of aluminum (Al), titanium (Ti), indium (In), gold (Au), silver (Ag), nickel (Ni), and copper (Cu). For example, the electrode metal layer may include an oxide thereof or an alloy thereof. However, the present disclosure is not limited thereto.

[0194] Fig.13 is a diagram schematically showing relative values ​​of luminance according to thickness of a functional layer in a light emitting diode including a functional layer for injecting holes. Fig.13 The figures in show the simulation results.

[0195] refer to Fig.13, the brightness can be increased as the thickness of the functional layer is reduced. The brightness can be improved in low-order resonance. Therefore, the light emitting diode according to the embodiment may include an optical layer composed of a porous layer and a non-porous layer, and the light emitting diode may have excellent light efficiency without increasing thickness.

[0196] The display device according to the embodiment may be manufactured by the method of manufacturing the display device according to the embodiment. Fig.14 is a flowchart schematically illustrating a method of manufacturing a display device according to an embodiment. Figures 15 to 29 is a diagram schematically showing a manufacturing step of a display device according to an embodiment. Figures 14 to 29 Description, omitting references Figures 1 to 13 Detailed description of the same constituent elements described.

[0197] refer to Fig.14 According to an embodiment, a method for manufacturing a display device may include: preparing a CMOS wafer including a first silicon substrate and a conductive layer disposed on the first silicon substrate (S100); preparing a semiconductor substrate including an initial semiconductor junction structure and a second silicon substrate disposed on the initial semiconductor junction structure (S200); connecting the CMOS wafer and the semiconductor substrate (S300); dry etching the initial semiconductor junction structure to form a semiconductor junction structure (S400); forming a second electrode portion (S500); and forming a first electrode portion (S600).

[0198] refer to Fig.15 CMOS wafer 10 may include a first silicon substrate 101, a first insulating layer 123, and a second insulating layer 130 sequentially stacked. A first conductive layer CL1 may be disposed on CMOS wafer 10. For ease of description, in addition to the second contact electrode 135 disposed in the second contact hole CH2, Fig.15 CMOS chip in 10 Figure 6 The CMOS wafer 10 in FIG. 1 is more simply shown. Therefore, detailed description of the same constituent elements is omitted.

[0199] For example, the first conductive layer CL1 may be formed by a deposition process, and the type of the deposition process is not limited thereto. The first conductive layer CL1 may include at least one metal layer. The first conductive layer CL1 may include Fig.12 The metal layer ML shown in FIG.

[0200] refer to Fig.16 , the semiconductor substrate SUB-S may be provided on the CMOS wafer 10. The semiconductor substrate SUB-S may be aligned with the CMOS wafer 10.

[0201] The semiconductor substrate SUB-S may include a second silicon substrate 201, a buffer layer 202 disposed under the second silicon substrate 201, a semiconductor junction layer 203 disposed under the buffer layer 202, and a second conductive layer CL2 disposed under the semiconductor junction layer 203. The buffer layer 202 may be an epitaxial layer grown from the second silicon substrate 201.

[0202] The semiconductor junction layer 203 may include an initial semiconductor junction structure P-SJS. The semiconductor junction structure SJS (eg, Fig. 10A and Fig. 10B ) may be formed by an initial semiconductor junction structure P-SJS. In the semiconductor junction layer 203, an initial third semiconductor layer P-SC3 (eg, referring to Fig.18 ) may be thicker than the semiconductor junction structure SJS (eg, Fig. 10A and Fig. 10B ) in the third semiconductor layer SC3 (for example, reference Fig. 10A and Fig. 10B ) thickness. In the grinding process, the initial third semiconductor layer P-SC3 (eg, reference Fig.18 A detailed description of the grinding process is provided below.

[0203] The second conductive layer CL2 may include a transparent conductive oxide layer, a reflective layer disposed under the transparent conductive oxide layer, and at least one metal layer disposed under the reflective layer. The second conductive layer CL2 may include a first transparent conductive oxide layer COL (eg, Fig.12 ), the reflective layer RFL (for example, reference Fig.12 ) and the metal layer ML (eg, reference Fig.12 ). The second conductive layer CL2 may further include a first barrier layer BRL1 and a second barrier layer BRL2 (eg, referring to Fig.12 ) at least one of ).

[0204] refer to Fig.17 , the CMOS wafer 10 and the semiconductor substrate SUB-S may be coupled to each other. The second conductive layer CL2 may be bonded to the first conductive layer CL1 through a high temperature and high pressure process. The second conductive layer CL2 may be bonded to the first conductive layer CL1. Thus, an initial first electrode portion P-ES1 may be formed. Fig.18 In the embodiment, the preliminary first electrode portion P-ES1 may be a single layer. However, the present disclosure is not limited thereto, and the preliminary first electrode portion P-ES1 may have a plurality of layers.

[0205] After the second conductive layer CL2 is bonded to the first conductive layer CL1, a portion of the semiconductor junction layer 203 may be removed. The portion of the semiconductor junction layer 203 may be removed by a grinding process of the semiconductor. In the grinding process, the second silicon substrate 201 and the buffer layer 202 may be removed (e.g., completely removed), and a portion of the semiconductor junction layer 203 may be removed.

[0206] refer to Fig.18 The initial semiconductor junction structure P-SJS may include an initial first semiconductor layer P-SC1, an initial active layer P-ACT, an initial second semiconductor layer P-SC2, an initial optical layer P-OPL, and an initial third semiconductor layer P-SC3, which are sequentially stacked. Fig. 10A The light emitting diode LED shown in FIG. Fig.18 The initial semiconductor junction structure P-SJS shown in is formed.

[0207] However, the present disclosure is not limited thereto, and the initial optical layer P-OPL may be disposed between the initial first semiconductor layer P-SC1 and the initial second semiconductor layer P-SC2, and the initial active layer P-ACT may be disposed between the initial second semiconductor layer P-SC2 and the initial third semiconductor layer P-SC3. Fig. 10B The light emitting diode LED shown in .

[0208] The initial optical layer P-OPL may include an initial porous layer P-RL and an initial non-porous layer P-NRL. For example, the initial optical layer P-OPL may include a plurality of initial porous layers P-RL and a plurality of initial non-porous layers P-NRL. The initial porous layers P-RL and the initial non-porous layers P-NRL may be alternately arranged with each other. The concentration of the dopant doped to the initial porous layer P-RL may be greater than the concentration of the dopant doped to the initial non-porous layer P-NRL. Due to the higher concentration of the dopant, the speed of the electrochemical etching process may become higher. Therefore, in the electrochemical etching process, the initial porous layer P-RL may be formed into a porous layer RL having a porous structure (for example, refer to Fig.19 ), and the initial non-porous layer P-NRL may be formed as a non-porous layer NRL having no porous structure (e.g., reference Fig.19 ). A detailed description of the electrochemical etching process is provided below.

[0209] The semiconductor junction structure SJS can be formed by dry etching of the initial semiconductor junction structure P-SJS. Fig.18 and Fig.19The first semiconductor layer SC1 may be formed of an initial first semiconductor layer P-SC1, the second semiconductor layer SC2 may be formed of an initial second semiconductor layer P-SC2, and the third semiconductor layer SC3 may be formed of an initial third semiconductor layer P-SC3. The active layer ACT may be formed of an initial active layer P-ACT.

[0210] After performing the dry etching process of the initial semiconductor junction structure P-SJS, an electrochemical etching process may be performed on the initial optical layer P-OPL. Thus, the optical layer OPL may be formed. The electrochemical etching process may be performed on the side surface of the initial optical layer P-OPL on which the dry etching process has been performed. The electrochemical etching process is performed on the initial optical layer P-OPL including the side surface exposed by the dry etching process. For example, in the case of performing the electrochemical etching process, potassium hydroxide (KOH) or nitric acid (HNO 3 However, the embodiments of the present disclosure are not limited thereto.

[0211] The semiconductor junction structure SJS formed by the dry etching process may have a width that decreases from the lower side to the upper side. The width may refer to a width in a direction (e.g., a first direction or a first direction axis) DR1 perpendicular to the thickness direction (e.g., a third direction or a third direction axis) DR3. Therefore, in the optical layer OPL, the porous layer (e.g., the first porous layer RL) disposed on the lower side may be 1 , the second porous layer RL 2 , ..., or the nth porous layer RL n )RL (e.g., reference Fig.11 ) (eg, a first first width, a second first width, ..., or an nth first width) RW 1 , RW 2 , ..., or RW n (For example, see Fig.11 ) may be larger than the non-porous layer disposed on the upper side (eg, the first non-porous layer NRL 1 , ..., n-1th non-porous layer NRL n-1 or nth nonporous layer NRL n )NRL (e.g., reference Fig.11 ) (eg, the first second width, ..., the n-1th second width, or the nth second width) NW 1 、…、NW n-1 or NW n (For example, see Fig.11 ). For example, the first nonporous layer NRL 1 To the nth non-porous layer NRL n Each of the above may be disposed in the first porous layer RL 1 To the nth porous layer RL nOn each of them.

[0212] The second electrode portion ES2 may be formed on the semiconductor junction structure SJS. After the semiconductor junction structure SJS is formed, the second electrode portion ES2 may be formed. In other embodiments, the formation of the second electrode portion ES2 and the formation of the semiconductor junction structure SJS may be performed in the same process. For example, an initial second electrode portion may be formed on an initial semiconductor junction structure P-SJS, and the second electrode portion ES2 may be formed from the initial second electrode portion in the process of forming the semiconductor junction structure SJS from the initial semiconductor junction structure P-SJS. Fig. 20 In the embodiment, the semiconductor junction structure SJS may be a single layer. However, the present disclosure is not limited thereto, and the semiconductor junction structure SJS may have a plurality of layers.

[0213] refer to Fig. 20 , an initial second side surface insulating layer P-SI2 may be formed on the CMOS wafer 10. The initial second side surface insulating layer P-SI2 may be formed by a deposition process of an inorganic material. The initial second side surface insulating layer P-SI2 may be disposed on the initial first electrode portion P-ES1 and surround the side surface of the semiconductor junction structure SJS and the side surface of the second electrode portion ES2. The initial second side surface insulating layer P-SI2 may be disposed on the upper surface of the second electrode portion ES2.

[0214] exist Fig.21 In the initial second side surface insulating layer P-SI2 (for example, reference Fig. 20 ) and the initial first electrode portion P-ES1 (eg, reference Fig. 20 ) can be patterned. Thus, a light emitting diode LED can be formed. Figure 6 The second side surface insulating layer SI2 shown in FIG. 1 may be formed of a preliminary second side surface insulating layer P-SI2, and Figure 6 The first electrode portion ES1 shown in FIG. 1 may be formed by the initial first electrode portion P-ES1. In other embodiments, in the case where the initial second side surface insulating layer P-SI2 is omitted, the second side surface insulating layer SI2 may not be formed (for example, referring to FIG. 1 ). Figure 6 ).

[0215] refer to Fig. 22 , an initial first side surface insulating layer P-SI1 may be formed on the CMOS wafer 10. An initial side surface reflective layer P-SRL may be formed on the initial first side surface insulating layer P-SI1.

[0216] The initial first side surface insulating layer P-SI1 may be formed by a deposition process of an inorganic material. The initial first side surface insulating layer P-SI1 may be disposed on the second side surface insulating layer SI2 and cover the side surface of the first electrode portion ES1. The initial first side surface insulating layer P-SI1 may be disposed on a partial area of ​​the upper surface of the CMOS wafer 10.

[0217] The initial side surface reflection layer P-SRL may be formed by depositing a metal. For example, the initial side surface reflection layer P-SRL may be formed by depositing at least one of gold (Au), copper (Cu), silver (Ag), titanium (Ti), and aluminum (Al). However, the present disclosure is not limited thereto. The initial side surface reflection layer P-SRL may be provided, and the initial first side surface insulation layer P-SI1 may be covered by the initial side surface reflection layer P-SRL.

[0218] refer to Fig. 22 and Fig.23 , the initial first side surface insulating layer P-SI1 may be patterned, and the first side surface insulating layer SI1 may be formed. The initial side surface reflective layer P-SRL may be patterned, and the side surface reflective layer SRL may be formed. A first opening COP1 may be formed through the second side surface insulating layer SI2, the first side surface insulating layer SI1, and the side surface reflective layer SRL. For example, the second side surface insulating layer SI2, the first side surface insulating layer SI1, and the side surface reflective layer SRL may be wet etched to form the first opening COP1. In the wet etching process for forming the first opening COP1, the second transparent conductive oxide layer of the second electrode portion ES2 may protect the semiconductor junction structure SJS disposed thereunder from the etchant. For example, the second transparent conductive oxide layer of the second electrode portion ES2 may be an etching stop layer for wet etching.

[0219] refer to Fig.24 , a planarization layer 140 in which the second trench TC2 is defined may be formed. The planarization layer 140 formed of an organic material may be formed on the CMOS wafer 10 by an inkjet process or a coating process. The second trench TC2 may be formed in the planarization layer 140 by a photolithography process. Although not shown in the drawings, in the case of forming the second trench TC2, a planarization layer 140 may also be formed together Figure 5 The first trench TC1 is shown in FIG.

[0220] refer to Fig.25 , a second auxiliary electrode SE2 may be formed in the second trench TC2. Although not shown in the drawings, when the second auxiliary electrode SE2 is formed, a second auxiliary electrode SE2 may be formed together. Figure 5 The first auxiliary electrode SE1 is shown in FIG.

[0221] The second auxiliary electrode SE2 may be formed by a damascene method. After the barrier layer is thinly formed on the planarization layer 140 by the first deposition process, the metal layer may have a thickness greater than the barrier layer by the second deposition process. The barrier layer and the metal layer (e.g., a portion of the barrier layer and a portion of the metal layer) disposed on the planarization layer 140 may be removed by a CMP process. Therefore, the second auxiliary electrode SE2 including the barrier layer SE2-2 and the metal structure SE2-1 may be disposed only within the second trench TC2.

[0222] like Fig.26 As shown in , the second opening COP2 may be formed in the planarization layer 140. The second opening COP2 may correspond to the first opening COP1, and a partial region of the second electrode portion ES2 may be exposed to the outside. The second openings COP2 may each have a diameter greater than that of each of the first openings COP1. However, embodiments of the present disclosure are not limited thereto.

[0223] refer to Fig. 27 , a common electrode CME may be formed on the planarization layer 140. A transparent conductive oxide layer may be formed and patterned on the planarization layer 140 to form the common electrode CME. Although not shown in the drawings, the voltage transmission electrode VTE (eg, reference Figure 3 and Figure 4 ) may have a shape integral with the common electrode CME. For example, the voltage transmission electrode VTE and the common electrode CME may be formed simultaneously through the same process.

[0224] The common electrode CME and the voltage transmission electrode VTE in an integral shape may be formed by a photolithography process. The common electrode CME may be electrically connected to the light emitting diode LED through the first opening COP1 and the second opening COP2.

[0225] refer to Fig.28 , a third insulating layer 150 covering the common electrode CME may be formed on the planarization layer 140. Fig.29 , a lens LS may be formed on the third insulating layer 150. The lens LS may overlap the light emitting diode LED. The organic layer may be patterned by a photolithography process, and the lens LS may be formed. In other embodiments, the organic material may be provided by an inkjet process and dried to form the lens LS.

[0226] The method for manufacturing a display device according to an embodiment may include forming a semiconductor junction structure by a dry etching process. The display device according to an embodiment may be manufactured by the method for manufacturing a display device according to an embodiment, and includes a light emitting diode. In an embodiment, the light emitting diode may include a semiconductor junction structure, and the semiconductor junction structure may include an optical layer disposed between adjacent semiconductor layers in the semiconductor layer. The optical layer may include a porous layer and a non-porous layer disposed on the porous layer, and the first width of the porous layer in a direction perpendicular to the thickness direction may be greater than the second width of the non-porous layer. In the case where the light emitting diode may include a porous layer and a non-porous layer, the light emitting diode may have a low-order resonance without increasing the thickness. Therefore, the light emitting diode according to the embodiment may exhibit excellent light efficiency, and the display device according to the embodiment may provide excellent display quality.

[0227] The light emitting diode according to the embodiment may include a semiconductor junction structure having a porous layer and a non-porous layer, and exhibit excellent light efficiency.

[0228] The display device according to the embodiment can be manufactured by the method of manufacturing the display device according to the embodiment, the method including forming a semiconductor junction structure. Therefore, the display device can have excellent display efficiency.

[0229] The above description is an example of the technical features of the present disclosure, and those skilled in the art to which the present disclosure belongs will be able to make various modifications and changes.Therefore, the embodiments of the present disclosure described above can be implemented individually or in combination with each other.

[0230] Therefore, the embodiments disclosed in the present disclosure are not intended to limit the technical spirit of the present disclosure, but to describe the technical spirit of the present disclosure, and the scope of the technical spirit of the present disclosure is not limited by these embodiments. The protection scope of the present disclosure should be interpreted by the attached claims, and it should be interpreted that all technical spirits within the equivalent scope are included in the scope of the present disclosure.

Claims

1. Light emitting diodes, including: a first electrode portion; a second electrode portion, disposed on the first electrode portion; as well as A semiconductor junction structure is provided between the first electrode portion and the second electrode portion, wherein: The semiconductor junction structure comprises: a first semiconductor layer; A second semiconductor layer, disposed on the first semiconductor layer; A third semiconductor layer, disposed on the second semiconductor layer; an optical layer; and an active layer, spaced apart from the optical layer in a thickness direction, Any one of the optical layer and the active layer is disposed between the first semiconductor layer and the second semiconductor layer, The other of the optical layer and the active layer is disposed between the second semiconductor layer and the third semiconductor layer, The optical layer comprises: a porous layer; and a non-porous layer disposed on the porous layer, and In a direction perpendicular to the thickness direction, a first width of the porous layer is greater than a second width of the non-porous layer.

2. The light emitting diode according to claim 1, wherein: The first refractive index of the porous layer is less than the second refractive index of the non-porous layer.

3. The light emitting diode according to claim 1, wherein: The porous layer and the non-porous layer each include the same semiconductor material as any two of the first to third semiconductor layers.

4. The light emitting diode according to claim 1, wherein: The optical layer includes at least one of gallium nitride, indium gallium nitride, and aluminum gallium nitride.

5. The light emitting diode according to claim 1, wherein: The thickness of the porous layer satisfies the following equation 1, and the thickness of the non-porous layer satisfies the following equation 2: [Equation 1] T1=λ0 / 4n1 [Equation 2] T2=λ0 / 4n2 Wherein, in Equation 1, n1 is the refractive index of the porous layer, and T1 is the thickness of the porous layer, In Equation 2, n2 is the refractive index of the non-porous layer, and T2 is the thickness of the non-porous layer, and In Equation 1 and Equation 2, λ0 is the wavelength of light emitted from the active layer.

6. The light emitting diode according to claim 1, wherein: The thickness of the non-porous layer is 2m0+1 times the thickness of the porous layer, where m0 is an integer of 0 or more.

7. Display equipment, including: Complementary metal oxide semiconductor wafer; as well as A plurality of light emitting diodes are arranged on the complementary metal oxide semiconductor wafer, wherein: Each of the plurality of light emitting diodes is a light emitting diode according to any one of claims 1 to 6.

8. The display device according to claim 7, further comprising: a side surface reflection layer, disposed on a side surface of the first electrode portion, a side surface of the semiconductor junction structure, a side surface of the second electrode portion, and an upper surface of the second electrode portion, Wherein, the side surface reflection layer includes at least one of gold, copper, silver, titanium and aluminum.

9. The display device according to claim 8, further comprising: a side surface insulating layer disposed on the side surface of the first electrode portion, the side surface of the semiconductor junction structure, the side surface of the second electrode portion, and the upper surface of the second electrode portion, Wherein, the side surface reflection layer is arranged on the outer side of the side surface insulation layer.

10. The display device according to claim 9, wherein: On the side surface of the semiconductor junction structure, an extension direction of the side surface insulating layer is inclined with respect to the thickness direction.

11. The display device according to claim 9, wherein: An opening exposing a partial region of the upper surface of the second electrode part is formed through each of the side surface reflective layer and the side surface insulating layer.

12. The display device according to claim 11, wherein: The plurality of light emitting diodes include: A first light emitting diode including a second electrode portion; and a second light emitting diode including a second electrode portion, The display device further includes a common electrode configured to electrically connect the second electrode portion of the first light emitting diode and the second electrode portion of the second light emitting diode, and The common electrode contacts the partial region through the opening.

13. The display device according to claim 7, further comprising: A plurality of lenses are disposed on the plurality of light emitting diodes and respectively correspond to the plurality of light emitting diodes.

14. A method for manufacturing a display device, the method comprising: preparing a complementary metal oxide semiconductor wafer, the complementary metal oxide semiconductor wafer comprising a first silicon substrate and a conductive layer disposed on the first silicon substrate; preparing a semiconductor substrate, the semiconductor substrate comprising an initial semiconductor junction structure and a second silicon substrate disposed on the initial semiconductor junction structure; connecting the complementary metal oxide semiconductor wafer and the semiconductor substrate; dry etching the initial semiconductor junction structure to form a semiconductor junction structure; forming a second electrode portion; as well as A first electrode portion is formed, wherein forming the second electrode portion is performed while forming the semiconductor junction structure or after forming the semiconductor junction structure, The semiconductor junction structure comprises: a first semiconductor layer; a second semiconductor layer formed on the first semiconductor layer; a third semiconductor layer formed on the second semiconductor layer; an optical layer; and an active layer, spaced apart from the optical layer in a thickness direction, Any one of the optical layer and the active layer is formed between the first semiconductor layer and the second semiconductor layer, The other of the optical layer and the active layer is formed between the second semiconductor layer and the third semiconductor layer, and The optical layer comprises: a porous layer; and a non-porous layer disposed on the porous layer, and After dry etching the initial semiconductor junction structure, the porous layer and the non-porous layer are formed by electrochemical etching.

15. The method according to claim 14, wherein: In a direction perpendicular to the thickness direction, a first width of the porous layer is greater than a second width of the non-porous layer.

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