High-integration superconducting quantum device flip chip based on NbN film and preparation method thereof

Abstract

The invention discloses a high-integration superconducting quantum device flip chip based on an NbN film and a preparation method of the high-integration superconducting quantum device flip chip based on the NbN film, and the chip is sequentially provided with a lower-layer chip and an upper-layer chip from bottom to top, the lower-layer chip comprises a lower-layer substrate, a first superconducting thin film and a first metal column, and the upper-layer chip comprises an upper-layer substrate, a second superconducting thin film and a second metal column. Wherein a coplanar waveguide transmission line and a first overlay alignment mark are manufactured on the first superconducting film, and a resonator and a second overlay alignment mark are manufactured on the second superconducting film; a flip-chip technology is adopted between the upper-layer chip and the lower-layer chip, and the first metal columns and the second metal columns are connected together by aligning the first overlay alignment marks of the lower-layer chip with the second overlay alignment marks of the upper-layer chip one by one, so that the upper-layer chip and the lower-layer chip are electrically connected. According to the invention, the occupied area of the device is reduced and the integration level is improved.

Description

Technical Field

[0001] The invention relates to superconducting quantum computing, and in particular to a high-integration superconducting quantum device flip chip based on a NbN film and a preparation method thereof. Background Art

[0002] Superconducting quantum computing technology, as a frontier field of quantum information technology, relies on superconducting quantum bits for information processing. Its core advantage lies in the use of quantum mechanics principles to achieve data encoding, storage, operation and reading, thereby providing computing power beyond that of traditional computers. Superconducting quantum computers significantly improve the speed of processing complex problems through the parallel computing power of quantum bits, especially in scenarios that require a large number of parallel operations, such as big data analysis and complex physical simulations. With the in-depth development of quantum computing research, higher requirements are placed on the scalability and integration of quantum systems.

[0003] As superconducting quantum computing technology develops towards larger-scale integration, traditional planar interconnect technology has shown its limitations. In superconducting quantum devices, planar wire bonding technology rapidly expands as the chip area increases with the number of quantum bits, is limited by the limited space inside the refrigerator, and encounters technical difficulties such as mechanical stress, signal crosstalk, and impedance mismatch, all of which have an adverse effect on device performance. In contrast, flip-chip technology, as an efficient packaging solution, effectively reduces the device's footprint by installing one chip upside down on another chip, optimizes the signal path, reduces the impact of parasitic capacitance, and significantly improves the efficiency and speed of signal transmission. This technology makes the connection between chips more compact, which is of great significance for improving the integration and performance of quantum computing devices.

[0004] At present, in superconducting quantum bit circuits, the quantum bit readout circuit, i.e., the superconducting resonator, occupies more than 90% of the circuit area, which limits the size of the quantum bit computing unit and makes it difficult to improve the chip integration. Commonly used Al or Nb films as superconducting materials have a large readout circuit size due to their small dynamic inductance, which further limits the integration. In contrast, niobium nitride (NbN) film, as a superconducting material with high dynamic inductance, high critical temperature and simple composition, shows great application potential in the field of superconducting thin films. The dynamic inductance of thin NbN films can reduce the size of the readout circuit resonator in superconducting quantum circuits and improve the integration of quantum chip devices. The low power consumption characteristics of NbN films help reduce energy loss and extend the quantum coherence time, while its high critical current density enables it to maintain a superconducting state during high-frequency operation, supporting more complex quantum computing tasks. In addition, the preparation technology of NbN films is mature and easy to mass-produce, which makes it possible to commercialize quantum devices, thereby improving the integration of superconducting resonators while also enhancing the performance and efficiency of quantum computing.

[0005] In addition, existing superconducting quantum devices still face some challenges in achieving high integration. When the existing flip-chip technology uses indium pillars to achieve superconducting connections between upper and lower chips, it often requires the growth of an under-bump metallization layer, which not only increases the complexity of device preparation, but may also introduce other uncertainties. Summary of the invention

[0006] The purpose of the present invention is to provide a high-integration superconducting quantum device flip chip based on NbN film and a preparation method thereof.

[0007] The technical solution to achieve the purpose of the present invention is: a high-integration superconducting quantum device flip chip based on NbN film, which is arranged from bottom to top as follows: the lower chip includes a lower substrate, a first superconducting film, and a first metal pillar, and the upper chip includes an upper substrate, a second superconducting film, and a second metal pillar, wherein:

[0008] A coplanar waveguide transmission line is fabricated on the first superconducting film, and a first set of alignment marks are engraved; a resonator is fabricated on the second superconducting film, and a second set of alignment marks are engraved;

[0009] The upper chip and the lower chip are connected by using a flip-chip technology. The first set of alignment marks of the lower chip is aligned with the second set of alignment marks of the upper chip, and the first metal pillar is connected with the second metal pillar, so that the upper and lower chips are electrically connected.

[0010] The resonators of the upper chip are distributed on the upper and lower sides of the coplanar waveguide transmission line, and there is a gap between the upper and lower sides of the coplanar waveguide transmission line. The coupling part of the resonator is facing the coplanar waveguide transmission line of the lower chip and is coupled through the inter-chip capacitance. The signal of the resonator of the upper chip is read out through the coplanar waveguide transmission line of the lower chip.

[0011] Further, the first metal column includes a first small indium column and a first large indium column bar, and the second metal column includes a second small indium column and a second large indium column bar;

[0012] Three first set alignment marks distributed in a triangular relationship are arranged on the lower chip, the first small indium pillars are distributed around the coplanar waveguide transmission line and the first set alignment marks, and the first large indium pillar strip is distributed around the lower chip to surround the first small indium pillar and the coplanar waveguide transmission line;

[0013] The upper chip is provided with three first set engraved alignment marks distributed in a triangular relationship, the second small indium pillars are distributed around the resonator and the second set engraved alignment marks, and the second large indium pillar strips are distributed around the chip to surround the second small indium pillar and the resonator;

[0014] After the three overlay alignment marks of the lower chip are aligned one by one with the three overlay alignment marks of the upper chip, the first small indium column and the first large indium column bar of the lower chip are connected with the second small indium column and the second large indium column bar of the upper chip respectively.

[0015] Furthermore, the material of the first superconducting film is selected from Ta film, Nb film, NbN film, NbTiN and other superconducting films, the second superconducting film is selected from NbN high dynamic inductance film, and the thickness of the first superconducting film and the second superconducting film is 1-60nm.

[0016] Furthermore, the first small indium column, the first large indium column bar, the second small indium column and the second large indium column bar are indium columns with equal height of 4-10μm. The first small indium column and the second small indium column are square columns with a length and width of 5-50μm, and the first large indium column bar and the second large indium column bar are rectangular strips with a width of 100-250μm. The total length of the first large indium column bar 204 and the second large indium column bar 205 is 80-100% of the circumference of the upper chip to ensure that the large indium column bars surround and protect the internal devices in the upper and lower chips of different sizes, while providing stable mechanical support and electrical isolation.

[0017] Furthermore, the coupling part of the superconducting resonator is designed to be a special shape similar to a pentagon, and the coupling part is about twice as wide as the central conductor of the coplanar waveguide.

[0018] A method for preparing a flip chip of a highly integrated superconducting quantum device based on a NbN film, characterized in that it comprises the following steps:

[0019] Step 1, cleaning the substrate, and sputtering the first superconducting film and the second superconducting film respectively by using a magnetron sputtering device;

[0020] Step 2, performing photoresist, photolithography, development, and etching operations on the surface of the sample obtained in step 1 to produce a coplanar waveguide transmission line, a resonator, a first set of alignment marks, and a second set of alignment marks;

[0021] Step 3, the sample obtained in step 2 is stripped and re-skinned, photolithographically processed, and developed to produce patterns of the first metal pillar and the second metal pillar;

[0022] Step 4, performing ion milling on the sample obtained in step 3, evaporating a layer of indium film, and performing debonding and peeling to obtain a sample with metal pillars;

[0023] Step 5, performing photoresist protection and dicing on the sample obtained in step 4 to obtain a plurality of upper chips and lower chips respectively;

[0024] Step 6, using a chip mounter to align and pressure weld the upper chip and the lower chip obtained in step 5, to obtain a highly integrated superconducting quantum device flip chip based on the NbN film.

[0025] Further, in step 1, the substrate is cleaned, and a first superconducting film and a second superconducting film are sputtered respectively by a magnetron sputtering device, wherein:

[0026] N-methyl solvent, acetone and isopropanol were used for ultrasonic cleaning in succession, and the ultrasonic power was set to 10-50W. After the ultrasonic cleaning, the substrate was blown dry and dried with nitrogen. Before the magnetron sputtering device sputtered the superconducting film, the substrate was ion milled and pre-sputtered for more than 30s. The thickness of the first superconducting film and the second superconducting film sputtered by the magnetron sputtering device was 1-60nm.

[0027] Further, in step 2, coating, photolithography, development, and etching operations are performed on the surface of the sample obtained in step 1 to produce a coplanar waveguide transmission line, a resonator, a first set of alignment marks, and a second set of alignment marks, wherein:

[0028] The photolithography adopts laser direct writing maskless photolithography exposure, with a laser direct writing resolution of 0.6μm and the photoresist used is S1813 photoresist.

[0029] Further, in step 3, the sample obtained in step 2 is stripped and re-skinned, photolithographically processed, and developed to produce patterns of the first metal pillar and the second metal pillar, wherein:

[0030] The photoresist used in photolithography is a double-layer photoresist. First, apply a layer of LOR10B photoresist, bake it, and then apply a layer of AZ4620 photoresist at a low speed and bake it.

[0031] The positive photoresist developer is used for development, and the development time is about 2 minutes, so that the bottom of the convex dot pattern forms a positive trapezoid.

[0032] Furthermore, in step 4, the sample obtained in step 3 does not need to be made into an indium pillar under-bump metallization layer, and the indium pillar bump can be directly grown on the NbN film.

[0033] Further, in step 6, the upper chip and the lower chip obtained in step 5 are aligned and pressure-bonded using a chip mounter to obtain a highly integrated superconducting quantum device flip chip based on the NbN film, wherein:

[0034] When the upper and lower chips are pressure-welded, cold welding is used to fit the upper and lower chips together.

[0035] Compared with the prior art, the present invention has the following significant advantages: 1) By utilizing the high dynamic inductance characteristics of the thin NbN film on the sapphire substrate, a resonator of the same frequency can be produced with a smaller footprint. By integrating different functional components (such as coplanar waveguide transmission lines, resonators, etc.) in the upper and lower chips respectively, a highly integrated design is achieved by combining flip-chip technology with a high dynamic inductance film. This method helps to reduce the footprint of the device and improve the integration level.

[0036] 2) Instead of using the technology of under-bump metallization layer, indium pillar bumps are grown directly on the NbN film, which simplifies the preparation process steps and realizes the superconducting connection between the upper and lower chips, reducing the generation of parasitic effects. This method avoids the problem of alloying between the aluminum film and the indium pillar to form a non-superconducting layer, ensuring the stability and reliability of the superconducting connection.

[0037] 3) A combination of small indium pillars and large indium pillar bars is adopted. The small indium pillar adopts a square column design with a side length between 5-50μm. This design helps to reduce the layout resource occupation and the lithography time of laser direct writing (maskless lithography technology) compared with the cylindrical design. The large indium pillar bars (204, 205) are rectangular pillars. The length is selected according to the length and width of the upper and lower chips. The width is between 100-250μm, which is wider than the small indium pillars. It can maintain a certain height under a larger patch bonding force to ensure that there is an appropriate spacing between the two layers of chips during patching. The large indium pillar bars are symmetrically distributed around the device and the small indium pillars, which helps to evenly apply force during patching and prevent tilting after patching. In addition, the large indium pillar bars surround quantum devices such as transmission lines and resonators, which can effectively protect the internal devices while providing stable mechanical support and electrical isolation.

[0038] 4) The part where the superconducting resonator is coupled to the transmission line of the lower chip is designed to be in a special pentagonal shape. The advantage of this design is that it can still ensure the signal transmission between the resonator of the upper chip and the lower transmission line when there is an offset of more than ten microns between the upper and lower chip patches. The pentagonal design can better control the ratio of the width of the coplanar waveguide center conductor and the spacing between the center conductor and the ground, thereby achieving better impedance matching.

[0039] 5) The material selection range of the first superconducting film and the second superconducting film is wide. The first superconducting film can be selected from one of the superconducting films such as Ta film, Nb film, NbN film, NbTiN, etc. according to the needs, and can be freely combined with the second superconducting high dynamic inductance film, providing more design flexibility and optimization space.

[0040] 6) Designing the overlay mark and alignment mark into an integral pattern can not only ensure the accuracy of overlay and alignment, but also reduce the occupied area. Using three non-collinear overlay alignment marks helps to reduce the error that may be caused by a single mark, thereby improving the overall alignment accuracy and improving the yield of the device.

[0041] 7) The low power consumption characteristics of NbN film help to reduce energy loss and extend quantum coherence time, while its high critical current density enables it to remain in a superconducting state during high-frequency operation. By utilizing its high dynamic inductance characteristics and combining it with indium pillar-based flip-chip technology, it helps to integrate highly integrated and superior superconducting quantum devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 This is a schematic diagram of the main structure of the flip chip of the superconducting quantum device of the present invention;

[0043] Figure 2 This is a schematic diagram of the side view of the flip chip structure of a superconducting quantum device;

[0044] Figure 3 Schematic diagram of the flip-chip structure of a highly integrated superconducting quantum device based on NbN film of the present invention, wherein (a) is a schematic diagram of the lower chip structure, and (b) is a schematic diagram of the upper chip structure;

[0045] Figure 4 The present invention is a process flow chart for preparing a flip chip of a superconducting quantum device;

[0046] Figure 5 S for four flip-chip resonators based on NbN films 21 Test result graph. DETAILED DESCRIPTION

[0047] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0048] A high-integration superconducting quantum device flip chip based on NbN film includes an upper chip and a lower chip. From bottom to top, the lower chip includes a lower substrate 101, a first superconducting film 102, and a first metal pillar 105, and the upper chip includes an upper substrate 104, a second superconducting film 103, and a second metal pillar 106.

[0049] The size of the lower chip is larger than that of the upper chip. Specifically, the length and width of the upper chip are smaller than the corresponding sizes of the lower chip. The materials of the lower substrate 101 and the upper substrate 104 are selected from one or more of the following: sapphire, high-resistance silicon, amorphous silicon, preferably sapphire or high-resistance silicon, and most preferably sapphire. The material of the first superconducting film 102 is selected from superconducting films such as Ta film, Nb film, NbN film, NbTiN, etc., and is preferably NbN high dynamic inductance film. The material of the second superconducting film 103 is selected from NbN film, NbTiN or other high dynamic inductance films, and is preferably NbN high dynamic inductance film. The metal pillar 105 is an indium pillar.

[0050] Furthermore, the first metal pillar 105 includes a first small indium pillar 203, a first large indium pillar bar 204, and the second metal pillar 106 includes a second small indium pillar 208 and a second large indium pillar bar 205; the first superconducting film 102 is mainly used to produce a coplanar waveguide transmission line 201, a first overlay alignment mark 202, a first small indium pillar 203, and a first large indium pillar bar 204; the second superconducting film 103 is mainly used to produce a resonator 206, a second overlay alignment mark 207, a second small indium pillar 208, and a second large indium pillar bar 205; the resonator 206 is made of NbN high dynamic inductance thin film material and is prepared by micromachining technology.

[0051] The small indium columns 203 and 208 are square columns, round columns or other shaped columns, preferably square columns; the side lengths of the small indium columns 203 and 208 are 5-50 μm, preferably 20 μm; the widths of the large indium columns 204 and 205 are 100-250 μm, preferably 200 μm, and the total lengths of the first large indium column bar 204 and the second large indium column bar 205 are designed to be approximately equal to the circumference of the upper chip (designed to be 80-100% of the circumference of the upper chip), so as to ensure that in the upper and lower chips of different sizes, the large indium column bars can effectively surround and protect the internal devices, while providing stable mechanical support and Electrical isolation; the resonator 206 can be selected from coplanar waveguide resonators, lumped parameter resonators and other types of resonators, preferably coplanar waveguide resonators; the overlay alignment marks 202, 207 are formed by etching around the large square and leaving a small positive shape in the middle as an alignment mark for overlay, and a cross-like structure is formed with the surrounding etched rectangles as an alignment mark for patching. The upper and lower chips are respectively made with three non-collinear overlay alignment marks 202, 207, which helps to reduce the error that may be caused by a single mark, ensure the accuracy of overlaying indium column bump patterns and the precise alignment of the upper and lower chips during flip-chip patching. The NbN film thickness can show high dynamic inductance characteristics in the range of several nanometers to tens of nanometers, and the corresponding thickness can be selected according to the specific situation. The upper chip and the lower chip are electrically connected by small indium columns 203, 208 and large indium column bars 204, 205 using flip-chip technology, and the superconducting resonator 206 of the upper chip is coupled with the transmission line 201 of the lower chip through inter-chip capacitance. The part where the superconducting resonator 206 is coupled with the transmission line of the lower chip is designed to be a special pentagon-like shape, which is similar to the pentagon at the beginning and end of the coplanar waveguide transmission line 201. The coupling part is about twice as wide as the coplanar waveguide center conductor. The advantage of this design is that when the upper and lower chip patches are offset by more than ten microns, the signal transmission between the resonator of the upper chip and the lower transmission line can still be guaranteed. The design similar to a pentagon can better control the ratio of the width of the coplanar waveguide center conductor and the distance between the center conductor and the ground, thereby achieving better impedance matching and improving the fault tolerance and stability of the device.

[0052] A method for preparing a flip chip of a highly integrated superconducting quantum device based on a NbN film, characterized in that it comprises the following steps:

[0053] Step 1, cleaning the substrate, and sputtering the first superconducting film 102 and the second superconducting film 103 respectively by using a magnetron sputtering device;

[0054] N-methyl solvent, acetone and isopropanol are used for ultrasonic cleaning in succession, and the ultrasonic power is set to 10-50W. After the ultrasonic cleaning, the substrate is blown dry and dried with nitrogen. Before the magnetron sputtering device sputters the superconducting film, the substrate is ion milled and pre-sputtered for more than 30s. The magnetron sputtering device sputters the first superconducting film 102 and the second superconducting film 103 respectively. The thickness of the first superconducting film 102 and the second superconducting film 103 is 1-60nm.

[0055] Step 2, performing photoresist, photolithography, development, and etching operations on the surface of the sample obtained in step 1 to produce a coplanar waveguide transmission line 201, a resonator 206, a first set alignment mark 202, and a second set alignment mark 207;

[0056] The lithography adopts laser direct writing maskless lithography exposure, selects a 20x lens and focuses, selects a 0.6μm laser direct writing resolution, and uses S1813 photoresist.

[0057] Step 3, the sample obtained in step 2 is stripped and re-skinned, photolithographically processed, and developed to produce patterns of the first metal pillar 105 and the second metal pillar 106;

[0058] The photoresist used in photolithography is a double-layer photoresist. First, apply a layer of LOR10B photoresist, bake it, and then apply a layer of AZ4620 photoresist at a low speed and bake it.

[0059] The positive photoresist developer is used for development, and the development time is about 2 minutes, so that the bottom of the convex dot pattern forms a regular trapezoidal shape.

[0060] Step 4, ion milling is performed on the sample obtained in step 3 to evaporate a layer of indium film, and the glue is removed and peeled off to obtain a sample with metal pillars;

[0061] Step 5, performing photoresist protection and dicing on the sample obtained in step 4 to obtain a plurality of upper chips and lower chips respectively;

[0062] Step 6, using a chip mounter to align and pressure weld the upper chip and the lower chip obtained in step 5, to obtain a highly integrated superconducting quantum device flip chip based on the NbN film.

[0063] When the upper and lower chips are pressure-welded, cold welding is used to fit the upper and lower chips together.

[0064] Example 1

[0065] Figure 3 The structure diagram of the upper chip and the lower chip of the flip chip of the highly integrated superconducting quantum device based on NbN film in Example 1 of the present invention is shown. Figure 3 (a) The lower chip pattern includes a coplanar waveguide transmission line 201, a first set alignment mark 202, a first small indium column 203, and a first large indium column strip 204. Figure 3(b) The upper chip pattern includes a resonator 206, a second overlay alignment mark 207, a second small indium column 208, and a second large indium column strip 205. The size of the lower chip is larger than that of the upper chip. Specifically, the length and width of the upper chip are smaller than the corresponding sizes of the lower chip. After etching between the overlay alignment marks 202 and 207, a 20μm×20μm NbN film square is left as an alignment mark during overlay, which forms a cross-like structure with the surrounding four etched 10μm×40μm rectangles as an alignment mark during patching. Three non-collinear overlay alignment marks 202 and 207 are made on the upper and lower chips respectively, which helps to reduce the error that may be caused by a single mark, and can clearly confirm whether the upper and lower chips can be aligned. The small indium pillars 203 and 208 are square pillars with a side size of 20μm. Compared with the cylindrical shape, they are beneficial in reducing the resource size of the layout and reducing the laser direct writing (maskless lithography technology) lithography time. They are distributed in the large indium pillar bars 204 and 205 and are used for electrical connection between the upper and lower chips, mainly to reduce parasitic inductance and capacitance effects, and improve signal integrity and reliability. The large indium column bars 204 and 205 are rectangular columns, and their lengths are selected according to the length and width of the upper and lower chips. The total lengths of the first large indium column bar 204 and the second large indium column bar 205 are designed to be approximately equal to the circumference of the upper chip to ensure that in the upper and lower chips of different sizes, the large indium column bars can effectively surround and protect the internal devices, while providing stable mechanical support and electrical isolation. The width is 200μm, which is smaller than the width of the indium column. Compared with the small indium columns 203 and 208, they can maintain a certain height under a larger patch bonding force, thereby ensuring the spacing height between the two chips during patching. At the same time, they are symmetrically distributed around the device and the small indium columns 203 and 208, which can ensure that the chip is evenly stressed during patching, and to a certain extent prevent tilting after patching. In addition, the large indium column bars 204 and 205 form an enclosure for quantum devices such as transmission lines and resonators, reducing the entry of external pollutants into the chip and reducing the interference of external noise. Resonator 206 is a coplanar waveguide resonator, and the part where the resonator is coupled to the lower transmission line is designed to be a special pentagon-like shape, which is similar to the pentagon at the beginning and end of the coplanar waveguide transmission line 201. The coupling part is about 2 times wider than the coplanar waveguide center conductor. The advantage of this design is that when the upper and lower chip patches are offset by more than ten microns, the signal transmission between the resonator of the upper chip and the lower transmission line can still be guaranteed, and the design similar to a pentagon can better control the ratio of the width of the coplanar waveguide center conductor and the distance between the center conductor and the ground, thereby achieving better impedance matching. The four resonators in the figure are made by reducing the length of four tantalum film resonators with a center frequency distribution of 5-7GHz by about half.

[0066] Figure 4The following is a flow chart of the preparation process of a flip chip of a highly integrated superconducting quantum device based on a NbN film according to the present invention in Example 1. The specific preparation method is as follows:

[0067] Step 1: Clean two sapphire substrates, which are used to make upper chip patterns and lower chip patterns respectively. Soak them in N-methyl solution and use 30W ultrasonic power for ultrasonic cleaning for 5 minutes, then soak them in acetone for ultrasonic cleaning at 30W ultrasonic power for 5 minutes, and soak them in isopropanol for ultrasonic cleaning at 30W ultrasonic power for 10 minutes. After the ultrasonic cleaning, blow dry the substrate with nitrogen and bake it on a drying table at 100℃ for 1 minute.

[0068] Step 2: Thin film growth: 50 nm NbN thin film was grown by sputtering using a magnetron sputtering machine from Texas Instruments. The two sapphire substrates cleaned in step 1 were placed in the sample chamber of the magnetron sputtering machine. The vacuum was reduced to 10 -4 Pa below and sent to the ion milling source until the vacuum drops to 10 -5 Pa, and then ion milling is performed. After ion milling, wait for the vacuum to return to 10 -5 Pa, pre-sputtering was performed for 5 minutes and then formal sputtering was performed for 50 seconds to obtain a sapphire substrate with a 50nm NbN film grown on it. After the sputtering was completed, oxygen was introduced to perform oxidation protection on the NbN film to obtain a first superconducting film 102 and a second superconducting film 103.

[0069] Step 3: Photolithography and development. Place the substrates with NbN thin films grown in step 2 on the coating table, drip S1813 photoresist and coat at an appropriate speed, then place them on the baking table and bake at 120℃ for two minutes. Then place the coated thin film sheets into the laser direct writing system and import the corresponding layouts. There are two layouts, which are composed of multiple Figure 3 (a) shows a layout composed of the lower chip pattern and multiple Figure 3 (b) shows the layout of the lower chip pattern. The two chips correspond to the two layouts. Select the 20x lens and focus, select 0.6μm laser direct writing resolution, and select 120mj / cm 2 The film is exposed with an exposure dose of 10000. After exposure, it is placed in a positive photolithography developer for 30 seconds. During the development process, it should be shaken evenly and quickly to ensure sufficient development, and then blown dry with a nitrogen gun.

[0070] Step 4: Etching and degumming, put the two wafers exposed in step 3 into the RIE etcher, set the flow of CF4 gas, etching power and time, and start the etching program for etching. Put the two etched wafers into N methyl solvent and clean them with low-power ultrasonic for 5 minutes, and then clean the two wafers using the method in step 1.

[0071] Step 5: Photolithography development, place the two wafers in step 4 into the coating machine one after another, coat them with a layer of LOR10B photoresist of about 1.2μm at a speed of 3000 rpm and bake for 3 minutes, then coat them with a layer of AZ4620 photoresist of about 9μm at a speed of 1200 rpm. When coating AZ462 photoresist, the coating speed is controlled at a lower speed in order to obtain a relatively high coating thickness. After coating, bake again for 3 minutes. Put the two wafers after baking into the laser direct writing machine one after another, select the 10x lens and focus, select the laser direct writing resolution of 1μm, and select 700mj / cm 2 The exposure dose is used to find the mark pattern on the film and match it with the overlay pattern, such as Figure 3 As shown, both upper and lower chips have overlay mark patterns 202 and 207. The overlay marks of the layout are matched with the overlay marks of the two chips made in the previous steps. Then, laser direct writing is used to photolithography convex patterns 203, 204, 205, and 208. These convex patterns 203, 204, 205, and 208 are the positions where the indium pillars grow later. The convex patterns 203 and 208 are small indium pillar patterns, and the convex patterns 204 and 205 are large indium pillar strip patterns, which are used to evaporate large indium pillars. Then, positive photoresist developer is used for development for about 2 minutes. A slightly longer time can achieve a slightly overdeveloped effect, so that the bottom of the convex pattern forms a positive trapezoid, which is convenient for the subsequent peeling of the indium pillars, and then blown dry with nitrogen.

[0072] Step 6: Ion milling to evaporate indium. The two wafers developed in step 5 are placed in an ion milling device for ion milling to remove the photoresist and oxide at the position of the bump pattern 203, so that the subsequent indium column can be well bonded with the NbN film. After the ion milling is completed, the wafer is placed in the indium evaporation device to evaporate an indium film of about 6μm. The thermal evaporation current is first slowly adjusted from 0 amperes to 110 amperes. After the indium particles are completely melted, the current is slowly increased to 150A and maintained until the evaporation is completed. The evaporation rate of indium is slowly increased to prevent the indium film from being uneven in height and the bumps from being blocked due to excessive evaporation. During the evaporation process, cooling water is passed through the substrate on which the wafer is placed to prevent the photoresist from being deformed due to excessively high wafer temperature.

[0073] Step 7: Stripping and dicing, put the wafer after indium evaporation in step 6 into N methyl solution and heat it in a water bath for 1 hour, then low-power ultrasound for 60 seconds, continue to heat it in a water bath for 1 hour, then clamp the wafer with tweezers and shake it gently to get the wafer with indium column and circuit, and clean the wafer with acetone and isopropanol solution, and then blow it dry with nitrogen. The peeled wafer is protected by glue, and the two wafers are diced into multiple upper chips and multiple lower chips using DS616 dicing machine.

[0074] Step 8: Flip-chip mounting. De-glue the upper and lower chips after dicing in step 7. Then use the FineTech mounter to align the alignment marks of the upper and lower chips. Adjust the force arm of the mounter to the corresponding force and bond the upper and lower chips. The bonding temperature can be operated at room temperature, that is, cold welding is used for bonding. At the same time, avoid the influence of high temperature on sensitive materials to ensure the stability and reliability of electrical connection.

[0075] In summary, this embodiment reduces the area of ​​the superconducting resonator by utilizing the high dynamic inductance characteristics of the NbN film. Also, thanks to the relatively high hardness of the NbN film and the relatively stable film quality that does not easily react with indium metal, indium column bumps can be made directly on the NbN film without the need for an under-bump metallization layer. The upper and lower chips are then welded together using a flip-chip welding instrument to achieve three-dimensional packaging of superconducting conductive connections.

[0076] Example 2

[0077] This example is used to illustrate the test results of four flip-chip resonators based on NbN films prepared in Example 1.

[0078] The flip-chip sample in Example 1 was placed in a sample box, wired and packaged, and then placed in a refrigerator. When the ambient temperature of the sample box in the refrigerator reached 10 mK, the S of the four superconducting flip-chip resonators based on the NbN film in Example 1 were read using a network analyzer. 21 Parameters, results such as Figure 5 As shown, the frequencies of the four resonators of Example 1 are distributed between 5.3GHz and 7.5GHz. These four resonators are made by reducing the length of four tantalum film resonators with center frequencies distributed between 5-7GHz by more than half. It can be seen that the high dynamic inductance of the 50nm NbN film plays a big role in this, reducing the footprint of the resonator by about half. The higher the NbN film, the greater its dynamic inductance. Using thinner NbN films is conducive to reducing the footprint of superconducting resonators, and indium pillars can be grown directly on NbN films, which is well compatible with the current mainstream superconducting quantum flip-chip technology based on indium pillars.

[0079] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0080] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A highly integrated superconducting quantum device flip chip based on NbN film, characterized in that: From bottom to top, the arrangement is as follows: the lower chip includes a lower substrate (101), a first superconducting film (102), and a first metal pillar (105); the upper chip includes an upper substrate (104), a second superconducting film (103), and a second metal pillar (106), wherein: A coplanar waveguide transmission line (201) and a first set of alignment marks (202) are fabricated on the first superconducting film (102), and a resonator (206) and a second set of alignment marks (207) are fabricated on the second superconducting film (103); The upper chip and the lower chip are connected by using a flip-chip technology, and the first metal pillar (105) and the second metal pillar (106) are connected together by aligning the first set of alignment marks (202) of the lower chip with the second set of alignment marks (207) of the upper chip one by one, so that the upper and lower chips are electrically connected; The resonators (206) of the upper chip are distributed on the upper and lower sides of the coplanar waveguide transmission line (201), and there is a gap between the upper and lower sides of the coplanar waveguide transmission line (201). The resonator coupling part faces the coplanar waveguide transmission line (201) of the lower chip and is coupled through the inter-chip capacitance. The signal of the resonator (206) of the upper chip is read out through the coplanar waveguide transmission line (201) of the lower chip.

2. The highly integrated superconducting quantum device flip chip based on NbN film according to claim 1, characterized in that: The first metal column (105) includes a first small indium column (203) and a first large indium column strip (204), and the second metal column (106) includes a second small indium column (208) and a second large indium column strip (205); Three first engraved alignment marks (202) distributed in a triangular relationship are arranged on the lower chip, first small indium pillars (203) are distributed around the coplanar waveguide transmission line (201) and the first engraved alignment marks (202), and a first large indium pillar strip (204) is distributed around the lower chip to surround the first small indium pillars (203) and the coplanar waveguide transmission line (201); Three first set alignment marks (207) distributed in a triangular relationship are arranged on the upper chip, the second small indium pillars (208) are distributed around the resonator (206) and the second set alignment marks (207), and the second large indium pillar strip (205) is distributed around the upper chip to surround the second small indium pillars (208) and the resonator (206); After the three overlay alignment marks (202) of the lower chip are aligned one by one with the three overlay alignment marks (207) of the upper chip, the first small indium column (203) and the first large indium column bar (204) of the lower chip are connected to the second small indium column (208) and the second large indium column bar (205) of the upper chip respectively.

3. The highly integrated superconducting quantum device flip chip based on NbN film according to claim 1, characterized in that: The material of the first superconducting film (102) is selected from one of Ta film, Nb film, NbN film, NbTiN and the like, and the second superconducting film (103) is selected from NbN high dynamic inductance film. The thickness of the first superconducting film (102) and the second superconducting film (103) is 1-60 nm.

4. The highly integrated superconducting quantum device flip chip based on NbN film according to claim 2, characterized in that: The first small indium column (203), the first large indium column strip (204), the second small indium column (208) and the second large indium column strip (205) are indium columns with equal heights of 4-10 μm. The first small indium column (203) and the second small indium column (208) are square columns with a length and width of 5-50 μm, and the first large indium column strip (204) and the second large indium column strip (205) are rectangular strips with a width of 100-250 μm. The total length of the first large indium column strip (204) and the second large indium column strip (205) is 80-100% of the circumference of the upper chip to ensure that the large indium column strips surround and protect the internal devices in the upper and lower chips of different sizes.

5. The highly integrated superconducting quantum device flip chip based on NbN film according to claim 1, characterized in that: The coupling part of the superconducting resonator (206) is designed to be a special shape similar to a pentagon, and the coupling part is about twice as wide as the central conductor of the coplanar waveguide.

6. A method for preparing a highly integrated superconducting quantum device flip chip based on a NbN film according to any one of claims 1 to 5, characterized in that: The preparation method comprises the following steps: Step 1, cleaning the substrate, and sputtering the first superconducting film (102) and the second superconducting film (103) respectively using a magnetron sputtering device; Step 2, performing photoresist, photolithography, development, and etching operations on the surface of the sample obtained in step 1 to produce a coplanar waveguide transmission line (201), a resonator (206), a first set of alignment marks (202), and a second set of alignment marks (207); Step 3, the sample obtained in step 2 is stripped and re-skinned, photolithographically processed, and developed to produce patterns of the first metal pillar (105) and the second metal pillar (106); Step 4, performing ion milling on the sample obtained in step 3 and evaporating a layer of indium film, and then performing debonding and peeling to obtain a sample with metal pillars; Step 5, performing photoresist protection and dicing on the sample obtained in step 4 to obtain a plurality of upper chips and lower chips respectively; Step 6: Use a chip mounter to align and pressure-weld the upper chip and the lower chip obtained in step 5 to obtain a highly integrated superconducting quantum device flip chip based on the NbN film.

7. The method for preparing a flip chip of a highly integrated superconducting quantum device based on a NbN film according to claim 6, characterized in that: Step 1, cleaning the substrate, and sputtering the first superconducting film (102) and the second superconducting film (103) respectively by using a magnetron sputtering device, wherein: Ultrasonic cleaning is performed using N-methyl solvent, acetone and isopropanol in sequence, with the ultrasonic power set to 10-50W. After the ultrasonic cleaning, the substrate is blown dry and dried with nitrogen. Before the magnetron sputtering device sputters the superconducting film, the substrate is ion milled and pre-sputtered for more than 30 seconds. The thickness of the first superconducting film (102) and the second superconducting film (103) sputtered by the magnetron sputtering device is 1-60nm.

8. The method for preparing a flip chip of a highly integrated superconducting quantum device based on a NbN film according to claim 6, characterized in that: Step 2, performing coating, photolithography, development, and etching operations on the surface of the sample obtained in step 1 to produce a coplanar waveguide transmission line (201), a resonator (206), a first set of alignment marks (202), and a second set of alignment marks (207), wherein: The photolithography adopts laser direct writing maskless photolithography exposure, with a laser direct writing resolution of 0.6μm and the photoresist used is S1813 photoresist.

9. The method for preparing a flip chip of a highly integrated superconducting quantum device based on a NbN film according to claim 6, characterized in that: Step 3, the sample obtained in step 2 is stripped and re-skinned, photolithographically processed, and developed to produce patterns of the first metal pillar (105) and the second metal pillar (106), wherein: The photoresist used in the photolithography is a double-layer photoresist. First, apply a layer of LOR10B photoresist, bake it, and then apply a layer of AZ4620 photoresist at a low speed and bake it. The positive photoresist developer is used for development, and the development time is about 2 minutes, so that the bottom of the column pattern forms a positive trapezoid.

10. The method for preparing a flip chip of a highly integrated superconducting quantum device based on a NbN film according to claim 6, characterized in that: Step 6, using a chip mounter to align and pressure weld the upper chip and the lower chip obtained in step 5, to obtain a highly integrated superconducting quantum device flip chip based on NbN film, wherein: When aligning the upper and lower chips, three non-collinear overlay alignment marks are used for alignment; When the upper and lower chips are pressure-welded, cold welding is used to fit the upper and lower chips together.

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