Analog front-end circuit, working method thereof and gene sequencing chip
Patent Information
- Application Number
- CN202280100885.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2022-12-15
- Publication Date
- 2025-05-16
AI Technical Summary
Existing analog front-end circuits contain multi-stage amplifiers and multiple capacitors, resulting in large sizes and difficulty in miniaturization.
An analog front-end circuit is designed, including a preamplifier, a multiplexing capacitor and a state switching unit. Through the switching of the state switching unit, the amplification and multiplexing stages are performed in each working cycle, and the multiplexing capacitor is directly used as a coupling capacitor. The number of capacitors is reduced and the coupling capacitance between the pre-amplifier and the post-amplifier is avoided.
This reduces the size of the analog front-end circuit, optimizes circuit performance, improves power supply wiring strength, and reduces the area occupied by capacitors.
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Figure CN120019575A_ABST
Abstract
Description
Analog front-end circuit and working method thereof, gene sequencing chip Technical Field
[0001] The present application relates to the field of test and measurement technology, for example, to an analog front-end circuit and a working method thereof, and a gene sequencing chip. Background Art
[0002] Analog front-end circuits can amplify the signal to be measured, so that the amplified signal can be used for analysis and calculation. Analog front-end circuits have important applications in modern test and measurement fields.
[0003] However, the analog front-end circuit in the related art usually includes a multi-stage amplifier and multiple capacitors, which results in a large size of the analog front-end circuit and makes miniaturization difficult.
[0004] Summary of the Invention
[0005] The present application provides an analog front-end circuit and its working method, and a gene sequencing chip to reduce the size of the analog front-end circuit, which is conducive to miniaturization of the analog front-end circuit.
[0006] According to one aspect of the present application, an analog front-end circuit is provided, the analog front-end circuit comprising:
[0007] Pre-amplifier, multiplexing capacitor, state switching unit and post-amplifier;
[0008] The state switching unit is configured to connect the first end of the multiplexed capacitor to the first input end of the pre-stage amplifier and the second end of the multiplexed capacitor to the output end of the pre-stage amplifier in a first state; and to connect the first end of the multiplexed capacitor to a first level and the second end of the multiplexed capacitor to the first input end of the post-stage amplifier in a second state.
[0009] According to another aspect of the present application, a gene sequencing chip is provided, wherein the gene sequencing chip integrates a plurality of the above-mentioned analog front-end circuits;
[0010] The first input terminal of the preamplifier is used for inputting a gene modulation current signal.
[0011] According to another aspect of the present application, a method for operating an analog front-end circuit is provided. The analog front-end circuit is the analog front-end circuit described above, characterized in that the analog front-end circuit includes N integration periods in each operating cycle, where N ≥ 1, and each integration period includes:
[0012] During the amplification phase, the state switching unit is controlled to switch to the first state;
[0013] In the multiplexing stage, the state switching unit is controlled to switch to the second state. BRIEF DESCRIPTION OF THE DRAWINGS
[0014] FIG1 is a schematic diagram of a circuit structure of an analog front-end circuit provided in an embodiment of the present application;
[0015] FIG2 is a circuit schematic diagram of the analog front-end circuit shown in FIG1 in a first working state;
[0016] FIG3 is a circuit schematic diagram of the analog front-end circuit shown in FIG1 in a second working state;
[0017] FIG4 is a schematic diagram of the circuit structure of another analog front-end circuit provided in an embodiment of the present application;
[0018] FIG5 is a circuit schematic diagram of the analog front-end circuit shown in FIG4 in a first working state;
[0019] FIG6 is a circuit schematic diagram of the analog front-end circuit shown in FIG4 in a second working state;
[0020] FIG7 is a timing diagram of an analog front-end circuit provided in an embodiment of the present application;
[0021] FIG8 is a schematic diagram of the structure of a gene sequencing chip provided in an embodiment of the present application;
[0022] FIG9 is a schematic diagram of the structure of a detection unit provided in an embodiment of the present application;
[0023] FIG10 is a flowchart of a working method of an analog front-end circuit provided in an embodiment of the present application. DETAILED DESCRIPTION
[0024] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in a sequence other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.
[0025] FIG1 is a schematic diagram of the circuit structure of an analog front-end circuit provided in an embodiment of the present application. Referring to FIG1 , the analog front-end circuit includes: a preamplifier AMP1, a multiplexing capacitor Cint, a state switching unit 10, and a post-amplifier AMP2. The state switching unit 10 is configured to, in a first state, connect the first end of the multiplexing capacitor Cint to the first input of the preamplifier AMP1 and the second end of the multiplexing capacitor Cint to the output of the preamplifier AMP1. In a second state, the first end of the multiplexing capacitor Cint is connected to a first voltage level VCM1 and the second end of the multiplexing capacitor Cint is connected to the first input of the post-amplifier AMP2.
[0026] For example, the analog front-end circuit can amplify the sensor signal (Sensor) input to its input terminal, so that the amplified signal can be used for information processing. In this embodiment, the analog front-end circuit can be applied to the field of gene sequencing, and the sensor signal (Sensor) can be a gene-modulated current signal. The gene-modulated current signal is a weak current signal that has been converted by a biosensor into information about the type of nucleotide molecules. The magnitude of the current signal represents the type of biological nucleotide molecules. The preamplifier AMP1 is used to perform primary amplification on the sensor signal (Sensor) to generate a first characteristic modulated voltage signal. The post-amplifier AMP2 is used to further amplify the first characteristic modulated voltage signal to generate a second characteristic modulated voltage signal. In this embodiment, the state switching circuit includes two operating states, as shown in Figures 2 and 3. Figure 2 is a circuit schematic diagram of the analog front-end circuit shown in Figure 1 in the first operating state, and Figure 3 is a circuit schematic diagram of the analog front-end circuit shown in Figure 1 in the second operating state. In a first operating state, the two ends of the reuse capacitor Cint are connected to the first input and output ends of the pre-amplifier AMP1, respectively. A first characteristic modulation voltage signal is stored on the reuse capacitor Cint. Subsequently, the state switching circuit is switched to a second state. In this state, one end of the reuse capacitor Cint is connected to the first voltage level VCM1, and the other end is connected to the first input end of the post-amplifier AMP2. Because the voltage across a capacitor cannot change suddenly, the first characteristic modulation voltage signal stored on the reuse capacitor Cint is coupled to the first input end of the post-amplifier AMP2 and amplified by the post-amplifier AMP2 to become a second characteristic modulation voltage signal VO. In other words, by setting the operating state of the state switching unit, a coupling capacitor between the pre-amplifier and the post-amplifier can be eliminated, and the reuse capacitor can be directly reused as the coupling capacitor. Therefore, the analog front-end circuit of this embodiment can be equipped with one less capacitor. Since capacitors occupy a large area in an integrated circuit, this embodiment can significantly reduce the size of the analog front-end circuit.
[0027] The technical solution of this embodiment adopts an analog front-end circuit including a preamplifier, a reused capacitor, a state switching unit and a post-amplifier; the state switching unit is configured to connect the first end of the reused capacitor to the first input end of the preamplifier in a first state and the second end of the reused capacitor to the output end of the preamplifier; in a second state, the first end of the reused capacitor is connected to the first level and the second end of the reused capacitor is connected to the first input end of the post-amplifier. By setting the working state of the state switching unit, it is no longer necessary to set the coupling capacitor between the preamplifier and the post-amplifier, and the reused capacitor can be directly reused as the coupling capacitor. Therefore, the analog front-end circuit of this embodiment can set one less capacitor, and the area occupied by the capacitor in the integrated circuit is large, so this embodiment can greatly reduce the size of the analog front-end circuit. In addition, reducing the number of capacitors can also supplement the area of the operational transconductance amplifier (OTA), optimize and improve circuit performance, and thus improve the power supply wiring strength.
[0028] For example, FIG4 is a schematic diagram of the circuit structure of another analog front-end circuit provided in an embodiment of the present application. Referring to FIG4, the state switching unit includes: a first switch INT1, a second switch SAM1, a third switch INT2, and a fourth switch SAM2; a first end of the first switch INT1 is electrically connected to the first end of the pre-amplifier AMP1, and a second end of the first switch INT1 is electrically connected to the first end of the multiplexing capacitor Cint; a first end of the second switch SAM1 is connected to the first voltage level VCM1, and a second end of the second switch SAM2 is electrically connected to the first end of the multiplexing capacitor Cint; a first end of the third switch INT2 is electrically connected to the second end of the multiplexing capacitor Cint, and a second end of the third switch INT2 is electrically connected to the output end of the pre-amplifier AMP1; a first end of the fourth switch SAM2 is electrically connected to the second end of the multiplexing capacitor Cint, and a second end of the fourth switch SAM2 is electrically connected to the first input end of the post-amplifier AMP2.
[0029] For example, in this embodiment, the state switching unit can be composed of four switches, and the switching of the state of the state switching unit is completed by switching the switch state. Figure 5 is a circuit schematic diagram of the analog front-end circuit shown in Figure 4 in the first working state. Figure 6 is a circuit schematic diagram of the analog front-end circuit shown in Figure 4 in the second working state. Combined with Figures 4 to 6, in the first state, the first switch INT1 and the third switch INT2 are turned on, and the second switch SAM1 and the fourth switch SAM2 are turned off, so that the two ends of the multiplexing capacitor Cint are connected between the first input and output ends of the pre-amplifier AMP1; in the second state, the first switch INT1 and the third switch INT2 are turned off, and the second switch SAM1 and the fourth switch SAM2 are turned on, so that one end of the multiplexing capacitor Cint is connected to the first level VCM1, and the other end is connected to the first input end of the post-amplifier AMP2, thereby coupling the signal stored on the multiplexing capacitor Cint to the first input end of the post-amplifier AMP2.
[0030] For example, the analog front-end circuit may further include a controller for precisely controlling the operating states of the first switch INT1, the second switch SAM1, the third switch INT2, and the fourth switch SAM2. At least one of the first switch INT1, the second switch SAM1, the third switch INT2, and the fourth switch SAM2 may be a complementary field-effect transistor, for example, each of which may be a complementary field-effect transistor. The control terminals of the multiple switches are connected to the controller, which sends control signals to control the states of the multiple switches. The multiple switches may be turned on in response to a low level and turned off in response to a high level, or may be turned on in response to a high level and turned off in response to a low level. Of course, when the analog front-end circuit is integrated into a chip, the chip may include multiple detection units, each of which includes an analog front-end circuit. In this case, only one controller may be provided on the chip, and the analog front-end circuits on the chip may reuse the same controller.
[0031] For example, continuing to refer to Figure 4, the analog front-end circuit also includes: a feedback capacitor Ca, a first reset switch RST1, and a second reset switch RST2; the first end of the feedback capacitor Ca is electrically connected to the first input end of the post-stage amplifier AMP2, the second end of the feedback capacitor Ca is electrically connected to the output end of the post-stage amplifier AMP2, the first end of the first reset switch RST1 is electrically connected to the first input end of the pre-stage amplifier AMP1, and the second end of the first reset switch RST1 is electrically connected to the output end of the pre-stage amplifier AMP1; the first end of the second reset switch RST2 is electrically connected to the first input end of the post-stage amplifier AMP2, and the second end of the second reset switch RST2 is electrically connected to the output end of the post-stage amplifier AMP2. In the above embodiment, the reuse capacitor Cint and the feedback capacitor Ca can both be planar capacitors with a metal-metal structure.
[0032] For example, the first reset switch RST1 can be used to reset the preamplifier; the second reset switch can be used to reset the postamplifier AMP2. During a working cycle of the analog front-end circuit, the preamplifier AMP1 typically needs to sample multiple times, which is then accumulated to the postamplifier, and the final signal output by the postamplifier serves as the sampled signal. As shown in Figure 7, Figure 7 is a timing diagram of an analog front-end circuit provided in an embodiment of the present application. Figure 7 corresponds to Figure 4. In combination with Figure 7 and Figure 4, in this embodiment, multiple switches are turned on at a high level and turned on at a low level as an example for explanation.
[0033] Taking the analog front-end circuit as an example, which integrates four times in each working cycle T, that is, it includes the first integration period T1, the second integration period T2, the third integration period T3 and the fourth integration period T4; each integration period includes the reset stage t1, the amplification stage t2 and the multiplexing stage t3; during the reset stage t1 corresponding to the first integration period in each working cycle T, the second reset switch RST2 is also used to reset the post-stage amplifier AMP2.
[0034] In the reset phase t1, the first reset switch RST1 receives a high-level signal and is turned on, and the first switch INT1 and the second switch SAM1 receive a low-level signal and are turned off. At this time, the pre-amplifier AMP1 is reset; it should be noted that the timing of the third switch INT2 is the same as that of the first reset switch RST1, and the timing of the fourth switch SAM2 is the same as that of the second switch SAM1.
[0035] During amplification phase t2, the first reset switch RST1 and the second reset switch RST2 are both turned off in response to a low level; the first switch INT1 and the third switch INT2 are turned on in response to a high level, and the second switch SAM1 and the fourth switch SAM2 are turned off in response to a low level. At this point, the two ends of the reuse capacitor Cint are connected between the first input and output ends of the preamplifier AMP1. The preamplifier AMP1 is in an integrating amplification state, and the first characteristic modulation voltage signal V1 output by the preamplifier AMP1 is stored on the reuse capacitor Cint.
[0036] During reuse phase t3, both the first reset switch RST1 and the second reset switch RST2 are turned off in response to a low level. The first and third switches INT1 and INT2 are turned off in response to a low level, while the second and fourth switches SAM1 and SAM2 are turned on in response to a high level. At this point, the two ends of the reuse capacitor Cint are connected to the first voltage level VCM1 and the first input terminal of the post-amplifier AMP2, respectively. The first characteristic modulation voltage signal stored on the reuse capacitor Cint is coupled to the post-amplifier, amplified, and outputted.
[0037] Subsequently, in the next integration period, it still includes the reset stage t1, the amplification stage t2 and the multiplexing stage t3. In the reset stage t1, the second reset switch RST2 remains in the off state, that is, at this time the post-amplifier AMP2 is not reset, but data accumulation is performed. After multiple data accumulations, the sensor signal Sensor is amplified from a small signal to a large signal that can be processed.
[0038] For example, referring to FIG4 , the second input terminal of the pre-amplifier AMP1 is connected to the second level VCM2 , and the second input terminal of the post-amplifier AMP2 is connected to the third level VCM3 .
[0039] For example, the first input terminal of the pre-stage amplifier AMP1 can be an inverting input terminal, and the second input terminal can be a non-inverting input terminal; the first input terminal of the post-stage amplifier AMP2 can be an inverting input terminal, and the second input terminal can be a non-inverting input terminal. The second voltage level VCM2 is a DC voltage level, which is used to set the static operating point of the pre-stage amplifier, so that the pre-stage amplifier AMP1 operates in an optimal operating state. The third voltage level VCM3 is a DC voltage level, which is used to set the static operating point of the post-stage amplifier, so that the post-stage amplifier AMP2 operates in an optimal operating state. For example, the first voltage level is multiplexed into the second and third voltage levels. In this case, the analog front-end circuit requires fewer DC signals, and thus fewer signal lines, which is more conducive to reducing the size of the analog front-end circuit.
[0040] The present application also provides a gene sequencing chip, as shown in FIG8 , which is a schematic diagram of the structure of a gene sequencing chip provided in the present application. The gene sequencing chip 20 may be integrated with multiple detection units 201, each detection unit 201 including the analog front-end circuit 2013 provided in the present application; the input end of the analog front-end circuit 2013 (the first input end of the preamplifier) is used to input a gene modulation current signal. Because the gene sequencing chip provided in the present application includes the analog front-end circuit provided in the present application, it also has the same beneficial effects, which will not be described in detail here.
[0041] Figure 9 is a schematic diagram of a detection unit structure provided by an embodiment of the present application. Each detection unit 201 includes a biosensor 2011, a switch selection module 2012, and an analog front-end circuit 2013. Biosensor 2011 is configured to convert biological nucleotide molecule type information into a gene-modulated current signal; switch selection module 2012 is configured to select the gene-modulated current signal, and analog front-end circuit 2013 is configured to amplify the selected gene-modulated current signal so that the amplified signal can be used for information processing. There can be N biosensors, where N ≥ 1.
[0042] The present application also provides a method for operating an analog front-end circuit, as shown in FIG10 . FIG10 is a flow chart of a method for operating an analog front-end circuit according to an embodiment of the present application. The analog front-end circuit includes N integration periods in each operating cycle, where N ≥ 1. Each integration period includes:
[0043] Step S301, amplification stage, controlling the state switching unit to switch to the first state;
[0044] Step S302: in the multiplexing stage, the state switching unit is controlled to switch to the second state.
[0045] For example, when the state switching unit is in a first working state, the two ends of the reuse capacitor are connected to the first input and output ends of the pre-stage amplifier, respectively. At this time, a first characteristic modulation voltage signal is stored on the reuse capacitor. Subsequently, the state switching circuit is switched to a second state. At this time, one end of the reuse capacitor is connected to the first voltage level, and the other end is connected to the first input end of the post-stage amplifier. Due to the principle that the voltage across the capacitor cannot change suddenly, the first characteristic modulation voltage signal stored on the reuse capacitor is coupled to the first input end of the post-stage amplifier and amplified by the post-stage amplifier to become a second characteristic modulation voltage signal. Therefore, the working method of the analog front-end circuit provided in this embodiment can realize the amplification function of the analog front-end circuit with fewer capacitors, and thus this embodiment can greatly reduce the size of the analog front-end circuit.
[0046] For example, each integration cycle includes a reset phase before each amplification phase, during which the first reset switch is turned on. Furthermore, the second reset switch is simultaneously turned on during the reset phase of the first integration phase within each operating cycle. In an analog front-end circuit, the preamplifier typically samples multiple times during a single operating cycle before accumulating the data in the postamplifier, with the final signal output by the postamplifier serving as the sampled signal. Therefore, the postamplifier is reset at the beginning of each operating cycle, and the preamplifier is reset during each integration phase. During each operating cycle, multiple first characteristic modulation voltage signals are accumulated in the postamplifier, where they are amplified to form a large signal suitable for direct data processing.
[0047] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the multiple steps described in this application can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of this application can be achieved. This is not limited herein.
Claims
1. An analog front-end circuit, comprising: Pre-amplifier, multiplexing capacitor, state switching unit and post-amplifier; The state switching unit is configured to connect the first end of the multiplexed capacitor to the first input end of the pre-stage amplifier and the second end of the multiplexed capacitor to the output end of the pre-stage amplifier in a first state; and to connect the first end of the multiplexed capacitor to a first level and the second end of the multiplexed capacitor to the first input end of the post-stage amplifier in a second state.
2. The analog front-end circuit according to claim 1, wherein: The state switching unit includes: a first switch, a second switch, a third switch, and a fourth switch; A first end of the first switch is electrically connected to a first end of the pre-amplifier, and a second end of the first switch is electrically connected to a first end of the multiplexing capacitor; The first end of the second switch is connected to the first electrical level, and the second end of the second switch is electrically connected to the first end of the reuse capacitor; A first end of the third switch is electrically connected to the second end of the multiplexing capacitor, and a second end of the third switch is electrically connected to the output end of the pre-amplifier; The first end of the fourth switch is electrically connected to the second end of the multiplexing capacitor, and the second end of the fourth switch is electrically connected to the first input end of the post-stage amplifier.
3. The analog front-end circuit according to claim 2, further comprising: A controller is configured to control the states of the first switch, the second switch, the third switch, and the fourth switch.
4. The analog front-end circuit according to claim 2, wherein: At least one of the first switch, the second switch, the third switch, and the fourth switch is a complementary field effect transistor.
5. The analog front-end circuit according to claim 1 , further comprising: a feedback capacitor, a first reset switch, and a second reset switch; The first end of the feedback capacitor is electrically connected to the first input end of the post-stage amplifier, and the second end of the second reset switch is electrically connected to the output end of the post-stage amplifier; A first end of the first reset switch is electrically connected to a first input end of the pre-stage amplifier, and a second end of the first reset switch is electrically connected to an output end of the pre-stage amplifier; A first end of the second reset switch is electrically connected to the first input end of the post-stage amplifier, and a second end of the second reset switch is electrically connected to the output end of the post-stage amplifier.
6. The analog front-end circuit according to claim 1, wherein: The second input terminal of the pre-stage amplifier is connected to the second electrical level, and the second input terminal of the post-stage amplifier is connected to the third electrical level.
7. The analog front-end circuit according to claim 6, wherein: The first level is multiplexed into the second level and the third level.
8. A gene sequencing chip, integrating multiple detection units, each detection unit comprising the analog front-end circuit according to any one of claims 1 to 7; The input end of the analog front-end circuit is configured to input a gene modulation current signal.
9. The gene sequencing chip according to claim 8, wherein: Each detection unit further includes a biosensor and a switch selection module; The biosensor is configured to convert biological nucleotide molecule type information into a gene-modulated current signal; The switch selection module is configured to select the gene modulation current signal; The analog front-end circuit is configured to amplify the selected gene modulation current signal.
10. A method for operating an analog front-end circuit, the analog front-end circuit being the analog front-end circuit according to any one of claims 1 to 7, wherein each operating cycle of the analog front-end circuit comprises N integration periods, where N ≥ 1, and each integration period comprises: During the amplification phase, the control state switching unit switches to the first state; In the multiplexing stage, the state switching unit is controlled to switch to the second state.
11. The method according to claim 10, wherein: The analog front-end circuit further includes: a first reset switch and a second reset switch; a first end of the first reset switch is electrically connected to a first input end of a pre-stage amplifier, and a second end of the first reset switch is electrically connected to an output end of the pre-stage amplifier; a first end of the second reset switch is electrically connected to a first input end of a post-stage amplifier, and a second end of the post-stage amplifier is electrically connected to an output end of the post-stage amplifier; The method includes: in each integration period, a reset phase is included before the amplification phase, and the first reset switch is turned on in the reset phase; in the first integration period in each working cycle, the second reset switch is turned on in the reset phase.