Memory device including row decoder circuit

Abstract

A memory device is disclosed. The memory device includes a row decoder connected to a plurality of word lines of each of a plurality of memory blocks. The row decoder includes: a main word line driver circuit commonly connected to the plurality of memory blocks, and configured to generate a first main word line driving signal, a second main word line driving signal, and a sub-word line driving signal based on a row address signal; and a sub-word line driver circuit connected to each of the plurality of memory blocks and configured to activate one word line from among the plurality of word lines using a NOR logic circuit to which the first main word line driving signal, the second main word line driving signal, and the sub-word line driving signal are connected.

Description

[0001] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2023-0161439 filed on November 20, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] The inventive concept relates generally to semiconductor memory devices, and more particularly, to a memory device including a row decoder circuit that can reduce a chip size. Background Art

[0003] Recently, with the multifunctionalization of information and communication devices, memory devices with larger capacity and higher integration are needed. As the size of memory cells is reduced for high integration, the operation circuits and / or wiring structures included in the memory devices for the operation and electrical connection of the memory devices are becoming more complex. There is a demand for memory devices with excellent electrical characteristics at an increased integration. In order to increase the storage capacity and integration of memory devices, vertical channel transistors formed vertically on a semiconductor substrate are being introduced instead of planar channel transistors formed on a semiconductor substrate.

[0004] A memory device (e.g., a dynamic random access memory (DRAM)) includes a plurality of memory cells, each of which includes a vertical channel transistor and a capacitor, and operates in a manner of writing and reading data by using the charge stored in the capacitor. The memory cells are connected to word lines and bit lines. In the DRAM, when a read operation or a refresh operation is performed, a row decoder decodes a row address to select a word line corresponding to the row address, and a high voltage (e.g., Fig. 8A A word line driving voltage of VPP) is applied to a selected word line, and the sense amplifier may sense a voltage level of a bit line corresponding to a column address among bit lines from memory cells connected to the selected word line.

[0005] A DRAM may have a cell on periphery (COP) structure including a cell array structure and a core peripheral circuit structure stacked on each other in a vertical direction. The cell array structure may include a memory cell array including a plurality of memory cells, each of the plurality of memory cells including a vertical channel transistor and a capacitor, and the core peripheral circuit structure may include a peripheral circuit including a row decoder and a sense amplifier. As memory processes shrink, the ratio of an area occupied by a core peripheral circuit region relative to an area occupied by a memory cell array region increases. Therefore, the chip size of a DRAM having a COP structure mainly depends on the area occupied by the core peripheral circuit region.

[0006] In order to reduce the chip size of the DRAM, it is necessary to reduce the area occupied by the core peripheral circuit region. When the area occupied by the row decoder is reduced, it is beneficial to reduce the chip size of the DRAM. Summary of the invention

[0007] As embodied in one or more embodiments of the inventive concept, the inventive concept provides a memory device including a row decoder circuit associated with a plurality of memory cells including vertical channel transistors and configured to reduce a chip size of the memory device.

[0008] According to one aspect of the inventive concept, a memory device is provided, comprising: a plurality of memory blocks including a plurality of word lines; and a row decoder connected to the plurality of word lines of each of the plurality of memory blocks, wherein the row decoder comprises: a main word line driver circuit commonly connected to the plurality of memory blocks and configured to generate a first main word line drive signal, a second main word line drive signal and a sub-word line drive signal based on a row address signal; and a sub-word line driver circuit connected to each of the plurality of memory blocks and configured to activate a word line from among the plurality of word lines using a NOR logic circuit, the first main word line drive signal, the second main word line drive signal and the sub-word line drive signal being connected to the NOR logic circuit.

[0009] According to another aspect of the inventive concept, a memory device is provided, the memory device comprising: a core peripheral circuit structure comprising a first bonding metal pad; and a cell array structure, which is overlapped with the core peripheral circuit structure in a vertical direction above the core peripheral circuit structure and comprises a second bonding metal pad in contact with the first bonding metal pad, wherein the cell array structure comprises a memory cell area, the memory cell area has a plurality of memory blocks, the plurality of memory blocks comprise a plurality of word lines, wherein each of the plurality of word lines respectively contacts the first bonding metal pad and the second bonding metal pad, the core peripheral circuit structure comprises: a row decoder, connected to the plurality of word lines of each of the plurality of memory blocks, and the row decoder comprises: a main word line driver circuit, configured to generate a first main word line drive signal, a second main word line drive signal and a sub-word line drive signal based on a row address signal; and a sub-word line driver circuit, configured to activate a word line from among the plurality of word lines using a NOR logic circuit, the first main word line drive signal, the second main word line drive signal and the sub-word line drive signal being connected to the NOR logic circuit.

[0010] According to another aspect of the inventive concept, a memory device is provided, the memory device comprising: a core peripheral circuit structure, comprising a first bonding metal pad; and a cell array structure, overlapping the core peripheral circuit structure in a vertical direction above the core peripheral circuit and comprising a second bonding metal pad in contact with the first bonding metal pad, wherein the cell array structure comprises a memory cell area, the memory cell area has a plurality of memory blocks, the plurality of memory blocks comprise a plurality of word lines, wherein each of the plurality of word lines contacts the first bonding metal pad and the second bonding metal pad, respectively; the core peripheral circuit structure comprises: a row decoder, connected to the plurality of word lines of each of the plurality of memory blocks; the row decoder comprises: a sub-word line driver circuit, configured to activate a word line from among the plurality of word lines, and the sub-word line driver circuit connected to each of the plurality of word lines is arranged in an area overlapping with the first bonding metal pad in a vertical direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, wherein like reference numerals (when used) designate corresponding elements throughout the several views.

[0012] Figure 1 is a schematic diagram conceptually illustrating at least a portion of an example memory device according to an embodiment.

[0013] Figure 2 It is shown Figure 1 A schematic block diagram of a configuration of a memory device.

[0014] Figure 3 , Figure 4 , Figure 5 and Figure 6 is a schematic diagram showing a structure of a memory device according to an embodiment.

[0015] Figure 7 is a schematic block diagram illustrating a row decoder according to an embodiment.

[0016] Fig. 8A , Figure 8B , Fig.9A and Fig. 9B It is shown Figure 7 Schematic circuit diagram of the main word line driver circuit.

[0017] Fig.10 It is shown Figure 7 Schematic circuit diagram of a sub-word line driver circuit in a row decoder.

[0018] Fig.11 and Fig.12are schematic diagrams illustrating a perspective view and a top view, respectively, of a row decoder architecture in which a row decoder is disposed in a memory device according to an embodiment.

[0019] Fig.13 is a schematic block diagram illustrating an example system of an electronic device including a memory device according to an embodiment. DETAILED DESCRIPTION

[0020] Figure 1 is a schematic diagram conceptually illustrating a memory device 10 according to an embodiment. Figure 2 is a diagram showing a method according to one or more embodiments Figure 1 1 is a schematic block diagram of a configuration of a memory device 10.

[0021] Reference Figure 1 and Figure 2 , the memory device 10 may include a core peripheral circuit 21 and a memory cell array 22 coupled to the core peripheral circuit 21. The core peripheral circuit 21 may include a control logic circuit 24, a voltage generating circuit 27, a sense amplifier 28, a row decoder 25, and a column decoder 26. The core peripheral circuit 21 may also include an address buffer 23, an input / output gating circuit 2090, a data input / output (I / O) circuit 2095, etc. According to an embodiment, the memory device 10 may be a dynamic random access memory (DRAM) including a plurality of memory cells, each memory cell including a vertical channel transistor and a capacitor. Hereinafter, a "memory device" will refer to a DRAM.

[0022] The memory cell array 22 may be connected to the row decoder 25 via word lines WL and to the sense amplifier (SA) 28 via bit lines BL. As may be used herein, the term "connection" (or similar terms such as "contact") is intended to refer to a physical and / or electrical connection between two or more elements, and may include other intermediate elements. As used herein, the term "and / or" includes any and all combinations of one or more associated listed items. The memory cell array 22 may include first to fourth memory arrays (or referred to as first to fourth memory arrays) 2080a, 2080b, 2080c, and 2080d, respectively, but the embodiment is not limited to any particular number of memory arrays. The first to fourth memory bank arrays 2080a, 2080b, 2080c, and 2080d may each include a plurality of word lines WL, a plurality of bit lines BL, and a plurality of memory cells formed at points where the plurality of word lines WL and the plurality of bit lines BL intersect each other, and may be divided into a plurality of memory blocks BLK1 to BLKi (eg, Fig.11 , i is an integer equal to or greater than 2).

[0023] The voltage generating circuit 27 may generate various internal voltages for driving the circuits of the memory device 10. The voltage generating circuit 27 may generate, for example, a high voltage VPP, a negative voltage VBB, an internal power supply voltage, a bit line precharge voltage, a reference voltage, a body bias voltage, etc. by using a power supply voltage (e.g., VDD) applied from the outside of the memory device 10.

[0024] For example, the high voltage VPP may be provided to the row decoder 25, has a voltage level higher than the power supply voltage VDD, and may be used for the main word line drive signal generating circuit ( Fig. 8A and Figure 8B ) and the sub-word line drive signal generating circuit ( Fig.9A and Fig. 9B ) to turn on the N-type metal oxide semiconductor (NMOS) cell transistor connected to the word line WL. The negative voltage VBB may have a negative (-) voltage level lower than the voltage level of the power supply voltage VDD, and may be used to increase the data retention time by increasing the threshold voltage Vth of the NMOS cell transistor. The negative voltage VBB may be applied to the well region in which the NMOS cell transistor is formed, and may generally be referred to as a body bias voltage or a reverse bias voltage. The bit line precharge voltage may be used to equalize the bit line BL with the complementary bit line before the sense amplifier 28 senses the voltage difference between the bit line BL and the complementary bit line. The internal power supply voltage may be provided to the first sensing drive voltage line and the second sensing drive voltage line of the sense amplifier 28. The sense amplifier 28 may sense and amplify the voltage difference between the bit line BL and the complementary bit line according to the first sensing drive voltage line and the second sensing drive voltage line. The reference voltage may be used to compare with the voltage of the signal received from the command / address bus to determine the logic value of the signal received from the memory controller.

[0025] The row decoder 25 may include first to fourth memory bank row decoders 2060a, 2060b, 2060c, and 2060d connected to the first to fourth memory bank arrays 2080a, 2080b, 2080c, and 2080d, respectively, and the column decoder 26 may include first to fourth memory bank column decoders 2070a, 2070b, 2070c, and 2070d connected to the first to fourth memory bank arrays 2080a, 2080b, 2080c, and 2080d, respectively. The sense amplifier 28 may include first to fourth sense amplifiers (SA) 2082a, 2082b, 2082c, and 2082d connected to the first to fourth memory bank arrays 2080a, 2080b, 2080c, and 2080d, respectively.

[0026] The first to fourth memory bank arrays 2080a, 2080b, 2080c and 2080d, the first to fourth memory bank row decoders 2060a, 2060b, 2060c and 2060d, the first to fourth memory bank column decoders 2070a, 2070b, 2070c and 2070d, and the first to fourth sense amplifiers 2082a, 2082b, 2082c and 2082d may respectively constitute the first to fourth memory banks of the memory device 10. The first to fourth bank row decoders 2060a, 2060b, 2060c, and 2060d, the first to fourth bank column decoders 2070a, 2070b, 2070c, and 2070d, and the first to fourth sense amplifiers 2082a, 2082b, 2082c, and 2082d may be referred to as core circuits of the first to fourth banks BANK1 to BANK4, respectively. Although an example of the memory device 10 including four banks is shown in the present embodiment, according to some embodiments, the memory device 10 may include other numbers of banks.

[0027] The address buffer 23 may receive a row address (eg, RA<0:8>, Fig. 8A and 9A ) and the address ADDR of the column address. In addition, the address buffer 23 may receive the memory address and provide the memory address to the memory control logic, provide the received row address RA<0:8> to the row decoder 25, and provide the received column address to the column decoder 26. The memory control logic may generate a memory control signal in response to the memory address. In response to the memory control signal, the memory row decoder corresponding to the memory address from among the first memory row decoder to the fourth memory row decoder 2060a, 2060b, 2060c and 2060d may be activated, and the memory column decoder corresponding to the memory address from among the first memory column decoder to the fourth memory column decoder 2070a, 2070b, 2070c and 2070d may be activated.

[0028] The control logic circuit 24 may control the overall operation of the memory device 10. The control logic circuit 24 may generate a control signal for performing a write operation and / or a read operation of the memory device 10. The control logic circuit 24 may include a mode register for setting a plurality of operation options of the memory device 10 and a command decoder for decoding a command CMD signal received from a memory controller.

[0029] The sense amplifier 28 may sense the data stored in the memory cell and send the sensed data to the data input / output circuit 2095 to output the sensed data to the memory controller through one or more data pads. The data input / output circuit 2095 may receive the data to be written in the memory cell from the memory controller through one or more data pads and send the data to the memory cell array 22. The input / output gating circuit 2090 may output the read data using a data line amplifier that receives and amplifies the data sensed by the sense amplifier 28. The read data may be output to the memory controller through one or more data pads. In addition to the circuit for gating the input / output data DQ, the input / output gating circuit 2090 may include a column selection circuit, an input data mask logic, a read data latch for storing data output from the first memory array to the fourth memory array 2080a, 2080b, 2080c and 2080d, and a write driver for writing data to the first memory array to the fourth memory array 2080a, 2080b, 2080c and 2080d.

[0030] The read data output from one memory array from among the first to fourth memory arrays 2080a, 2080b, 2080c, and 2080d may be sensed by the first to fourth sense amplifiers 2082a, 2082b, 2082c, and 2082d corresponding to the one memory array and stored in the read data latch. The write data to be written to the memory cell array of one of the first to fourth memory arrays 2080a, 2080b, 2080c, and 2080d may be provided from the memory controller to the data input / output circuit 2095. The data provided to the data input / output circuit 2095 may be written to the one memory array through the write driver.

[0031] Figure 3 , Figure 4 , Figure 5 and Figure 6 is a schematic diagram showing a structure of a memory device according to an embodiment. Figure 3 is a perspective view depicting an example arrangement of a cell array structure CAS and a core peripheral circuit structure CPS of the memory device 10 according to one or more embodiments. Figure 4 yes Figure 3 FIG. 1 is a perspective view of a cell array structure CAS of the memory device 10 . Figure 5 is Figure 4 A cross-sectional view taken along the second direction D2 in a perspective view of the memory device 10, and Figure 6 is Figure 41 is a cross-sectional view taken along a first direction D1 in a perspective view of a memory device 10 of FIG. 1. For ease of understanding, terms such as top surface / bottom surface, top / bottom, above / below, etc. are used based on the directions shown in the referenced drawings. Therefore, even the same surface may be referred to as a top surface or a bottom surface depending on the directions shown in the drawings.

[0032] Reference Figure 2 and Figure 3 , the memory device 10 may include a cell array structure CAS and a core peripheral circuit structure CPS that are stacked on each other in a third direction D3. As may be used herein, the term "stacked" (or "overlap" or similar terms) is intended to broadly refer to a first element that intersects at least a portion of a second element in a vertical direction (i.e., the third direction D3), but does not require that the first element and the second element be completely aligned with each other in a horizontal plane (i.e., in the first direction D1 and / or the second direction D2). The cell array structure CAS may include a memory cell array 22. The core peripheral circuit structure CPS may include a core peripheral circuit, which includes an address buffer 23, a control logic circuit 24, a row decoder 25, a column decoder 26, a sense amplifier 28, an input / output gating circuit 2090, and a data input / output circuit 2095. In order to simplify the description, the circuits constituting the row decoder 25 are shown to be arranged in the core peripheral circuit structure CPS. The memory device 10 may have a structure in which the memory cell array 22 is disposed above the core peripheral circuit (i.e., a cell on periphery (COP) structure).

[0033] The cell array structure CAS may include a plurality of memory cells including vertical channel transistors (VCT). In the cell array structure CAS, a plurality of word lines WL may extend in a first direction D1 parallel to an upper surface of the cell array structure CAS, and a plurality of bit lines BL may extend in a second direction D2 parallel to an upper surface of the cell array structure CAS and intersecting the first direction D1. A shielding bit line SBL may be arranged adjacent to the plurality of bit lines BL.

[0034] The core peripheral circuit structure CPS may include a semiconductor substrate, and the core peripheral circuit may be formed by forming semiconductor devices (such as transistors) and patterns for distributing the devices on the semiconductor substrate. After the core peripheral circuit is formed in the core peripheral circuit structure CPS, a cell array structure CAS including a memory cell array 22 may be formed, and patterns (e.g., 3D images) for electrically connecting word lines WL, bit lines BL, and shielding bit lines SBL of the memory cell array 22 to the core peripheral circuit formed in the core peripheral circuit structure CPS may be formed. Figure 5 bonding metal pads 301 and 302).

[0035] Refer to Figure 4 , Figure 5 and Figure 6 , the core peripheral circuit structure CPS may include a lower substrate 310, an interlayer insulating layer 315, a plurality of circuit elements 312a and 312b formed on the lower substrate 310, first metal layers 314a and 314b respectively connected to the plurality of circuit elements 312a and 312b, second metal layers 316a and 316b respectively formed on the first metal layers 314a and 314b, and a bonding metal pad 301 formed on the uppermost metal layer of the core peripheral circuit structure CPS. According to an embodiment, the first metal layers 314a and 314b may include tungsten having a relatively high resistance, the second metal layers 316a and 316b may include copper having a relatively low resistance, and the bonding metal pad 301 may include copper, but the embodiment is not limited thereto. According to another embodiment, the bonding metal pad 301 may include aluminum (Al) or tungsten (W).

[0036] Although only the first metal layers 314a and 314b and the second metal layers 316a and 316b are shown and described in this specification, the inventive concept is not limited thereto, and one or more metal layers may also be formed on the second metal layers 316a and 316b. At least some of the one or more metal layers formed on the second metal layers 316a and 316b may include a material (such as aluminum) having a lower resistance than copper constituting the second metal layers 316a and 316b. An interlayer insulating layer 315 is provided on the lower substrate 310 to cover the plurality of circuit elements 312a and 312b, and the first metal layers 314a and 314b and the second metal layers 316a and 316b may include an insulating material (such as, for example, silicon oxide or silicon nitride). As may be used herein, the term “overlying” (or similar terms) is intended to broadly refer to an element, structure or layer that is directly on or over another element, structure or layer, or an element, structure or layer that is on or over another element, structure or layer and has one or more other intervening elements, structures or layers therebetween.

[0037] The plurality of circuit elements 312a and 312b may be connected to at least one of the circuit elements constituting the peripheral circuit. For convenience of explanation, the first circuit element 312a represents a transistor constituting the row decoder 25, and the second circuit element 312b represents a transistor constituting the control logic circuit 24.

[0038] In the memory device 10, the bit lines BL may be arranged on the upper substrate 320 in the cell array structure CAS, and the bit lines BL extend in the second direction D2 and are spaced apart from each other in the first direction D1. The upper substrate 320 is shown as a component corresponding to the lower substrate 310. According to one or more embodiments, the upper substrate 320 may be referred to as a plate or a conductive plate. The bit lines BL may be spaced apart from each other in the first direction D1 and extend in the second direction D2 intersecting the first direction D1. The active pattern AP may be alternately arranged on each bit line BL in the second direction D2. The active pattern AP may be spaced apart from each other at regular intervals in the first direction D1. In other words, the active pattern AP may be arranged two-dimensionally in the first direction D1 and the second direction D2 intersecting each other. According to some embodiments, a plurality of word lines WL, a plurality of bit lines BL, and a plurality of active patterns AP constitute a plurality of vertical channel transistors.

[0039] The active patterns AP may each have a length in the first direction D1, a width in the second direction D2, and a height in a third direction D3 perpendicular to the upper substrate 320. The active patterns AP may each have a substantially uniform width. The active patterns AP may each have a top surface and a bottom surface facing each other in the third direction D3. For example, the bottom surface of the active pattern AP may contact the bit line BL. The active patterns AP may each include a source region adjacent to the bit line BL, a drain region adjacent to the contact pattern BC, and a channel region between the source region and the drain region. When the memory device 10 operates, the channel region of the active pattern AP may be controlled by the word line WL and the back gate electrode BG. The active pattern AP may include, for example, single crystal silicon (Si) to improve the leakage current characteristics during operation of the memory device 10.

[0040] The back gate electrodes BG may be spaced apart from each other at regular intervals in the second direction D2 on the bit line BL. The back gate electrode BG may extend in the first direction D1 across the bit line BL. The back gate electrodes BG may each be disposed between active patterns AP adjacent to each other in the second direction D2. A first active pattern 191 may be disposed on one side of each back gate electrode BG, and a second active pattern 192 may be disposed on the other side of each back gate electrode BG. The back gate electrode BG may have a height that is smaller than the height of the active pattern AP in the vertical direction (ie, the third direction D3). A negative voltage may be applied to the back gate electrode BG during operation of the memory device 10, and the threshold voltage of the vertical channel transistor may be increased. This means that degradation of the leakage current characteristic due to a lower threshold voltage based on miniaturization of the vertical channel transistor may be prevented or reduced.

[0041] The first insulating pattern 111 may be disposed between active patterns AP adjacent to each other in the second direction D2. The first insulating pattern 111 may extend in parallel with the back gate electrode BG in the first direction D1. A back gate insulating layer 113 may be disposed between each back gate electrode BG and the active pattern AP and between the back gate electrode BG and the first insulating pattern 111. The back gate insulating layer 113 may include a vertical portion covering both sides of the back gate electrode BG and a horizontal portion interconnecting the vertical portions. The horizontal portion of the back gate insulating layer 113 may be closer to the contact pattern BC than the bit line BL and may cover the bottom surface of the back gate electrode BG. The back gate covering pattern 115 may be disposed between the bit line BL and the back gate electrode BG. The back gate covering pattern 115 may include an insulating material, and the bottom surface of the back gate covering pattern 115 may contact the bit line BL. The back gate covering pattern 115 may be disposed between the vertical portions of the back gate insulating layer 113.

[0042] The word lines WL may extend on the bit lines BL in the first direction D1, and may be alternately arranged in the second direction D2. A first word line 181 among the word lines WL may be disposed on one side of the first active pattern 191, and a second word line 182 among the word lines WL may be disposed on the other side of the second active pattern 192. Portions of the first word lines 181 may be disposed between the first active patterns 191 adjacent to each other in the first direction D1, and portions of the second word lines 182 may be disposed between the second active patterns 192 adjacent to each other in the first direction D1.

[0043] The word line WL may be vertically spaced apart from the bit line BL and the contact pattern BC. When viewed in the vertical direction, the word line WL may be located between the bit line BL and the contact pattern BC. The word lines WL adjacent to each other may have side walls facing each other. The word line WL may have a height smaller than the height of the active pattern AP in the vertical direction relative to the upper surface of the upper substrate 320 as a reference layer. The height of the word line WL may be equal to or greater than the height of the back gate electrode BG relative to the upper surface of the upper substrate 320 in the third direction D3.

[0044] The gate insulating layer 160 may be disposed between the word line WL and the active pattern AP. The gate insulating layer 160 may extend in parallel to the word line WL in the first direction D1. The gate insulating layer 160 may cover one side surface of the first active pattern 191 and the other side surface of the second active pattern 192. The gate insulating layer 160 may have a substantially uniform thickness. The second insulating pattern 141 may be disposed between the gate insulating layer 160 and the contact pattern BC. For example, the second insulating pattern 141 may include silicon oxide. The first etch stop layer 131 and the second etch stop layer 133 may be disposed between the active pattern AP and the second insulating pattern 141.

[0045] On the gate insulating layer 160, the word lines WL may be separated from each other by the third insulating pattern 151. The third insulating pattern 151 may extend in the first direction D1 between the word lines WL. The first capping layer 153 may be disposed between the third insulating pattern 151 and the word lines WL. The first capping layer 153 may have a substantially uniform thickness. The third insulating pattern 151 may include a third vertical pattern 151A and a third horizontal pattern 151B.

[0046] The contact patterns BC may penetrate the third etch stop layer 210 and the interlayer insulating layer 220 (i.e., extend into the third etch stop layer 210 and the interlayer insulating layer 220) and be electrically connected to the active patterns AP, respectively. In other words, the contact patterns BC may be electrically connected to the drain regions of the active patterns AP, respectively. The contact patterns BC may each have a lower width greater than an upper width. The contact patterns BC adjacent to each other may be separated from each other by a separation insulating pattern 230. When viewed from above (i.e., in a plan view), the contact patterns BC may each have any of various shapes (such as a circular shape, an elliptical shape, a rectangular shape, a square shape, a diamond shape, a hexagonal shape, etc.). A landing pad (or a bonding pad, a landing pad, or a landing pad) LP may be arranged on the contact patterns BC.

[0047] The separation insulating pattern 230 may be arranged between the pads LP. When viewed from above, the pads LP may be arranged in a matrix form in the first direction D1 and the second direction D2. The top surface of the pad LP may be substantially coplanar with the top surface of the separation insulating pattern 230 in the third direction D3. The fourth etch stop layer 240 may be formed on the separation insulating pattern 230.

[0048] The data storage patterns DSP may be arranged on the pads LP. The data storage patterns DSP may be electrically connected to the active patterns AP, respectively. The data storage patterns DSP may be arranged in a matrix form in the first direction D1 and the second direction D2. The data storage patterns DSP may be completely or partially overlapped with the pads LP. The data storage patterns DSP may contact the entire top surface of the pads LP or a portion of the top surface of the pads LP. An upper insulating layer 260 may be provided on the data storage patterns DSP, and the cell contact plugs PLG may penetrate the upper insulating layer 260 and be electrically connected to the plate electrode 255.

[0049] According to some embodiments, the data storage pattern DSP may be a capacitor and may include a capacitor dielectric layer 253 disposed between a storage electrode 251 and a plate electrode 255. In this case, the storage electrode 251 may be in direct contact with the pad LP, and when viewed from above, the storage electrode 251 may have any of various shapes such as a circular shape, an oval shape, a rectangular shape, a square shape, a diamond shape, a hexagonal shape, etc.

[0050] According to some embodiments, the data storage pattern DSP may be a variable resistance pattern that can be switched between two resistance states by an electric pulse applied to a memory element. For example, the data storage pattern DSP may include a phase change material, a perovskite compound, a transition metal oxide, a magnetic material, a ferromagnetic material, an antiferromagnetic material, etc., whose crystal state changes according to the amount of current, but is not limited thereto. Depending on the material layer constituting the data storage pattern DSP, the memory device 10 may be implemented as a resistive memory such as a phase change RAM (PRAM), a magnetic RAM (MRAM), or a resistive RAM (RRAM).

[0051] In one or more embodiments, the shielding bit line SBL may be disposed between the bit lines BL and below the bit lines BL. The shielding bit line SBL may reduce coupling noise between the bit lines BL adjacent to each other. For example, the shielding bit line SBL may be a shielding structure including a conductive material. The first wire insulating layer 173 may be spaced apart from each other in the first direction D1 and may extend in the second direction D2. The first wire insulating layer 173 may be formed to contact the back-facing sidewalls of the adjacent bit lines BL and be separated from each other in the first direction D1. The second wire insulating layer 325 may be formed to surround the bottom surface and side surfaces of the shielding bit line SBL and fill the space between one or more shielding bit lines SBL. As may be used herein, the term "surrounding" (or similar terms (such as, "encircling")) is intended to broadly refer to an element, structure or layer that surrounds, encapsulates, surrounds or surrounds another element, structure or layer extending on all sides, but a break or gap may also exist. As may be used herein, the term "fill" (or similar terms) is intended to broadly refer to completely filling a defined space (e.g., the space between shielding bit lines SBL) or partially filling a defined space; that is, the defined space need not be completely filled, but may, for example, be partially filled or have gaps or other spaces here and there.

[0052] The via electrode 322 (e.g., a through hole via (THV)) may penetrate the upper substrate 320 (i.e., extend into the upper substrate 320), contact the metal layer 318b, and extend in the third direction D3 to a bonding metal pad 302 formed on the uppermost metal layer of the core peripheral circuit structure CPS. In the present embodiment, only one metal layer 318a or 318b is shown and described. However, the inventive concept is not limited thereto, and at least one additional metal layer may also be formed on the metal layer 318a or 318b. The shielding bit line SBL may be electrically connected to the element 312b of the control logic circuit 24 through the bonding metal pad 302 of the cell array structure CAS and the bonding metal pad 301 of the core peripheral circuit structure CPS. The shielding bit line SBL may be controlled by the control logic circuit 24.

[0053] According to some embodiments, the bonding metal pad 302 of the cell array structure CAS and the bonding metal pad 301 of the core peripheral circuit structure CPS may be connected to each other by an electrical bonding method or a physical bonding method. When the bonding metal pads 301 and 302 include copper (Cu), the bonding method may be a Cu-Cu bonding method. In another example, the bonding metal pads 301 and 302 may include aluminum (Al) or tungsten (W).

[0054] The metal layer 318a of the cell array structure CAS may be electrically or physically connected to each word line WL, and may be in contact with the bonding metal pad 301. The word lines WL may be electrically connected to the element 312a of the row decoder 25 through the bonding metal pad 302 of the cell array structure CAS and the bonding metal pad 301 of the core peripheral circuit structure CPS, respectively. Hereinafter, the components and operation of the row decoder 25 connected to the word lines WL will be described in detail through various embodiments.

[0055] Figure 7 , Fig. 8A , Figure 8B , Fig.9A , Fig. 9B and Fig.10 is a schematic diagram showing a row decoder according to an embodiment. Figure 7 It is shown Figure 1 A block diagram of a row decoder 25 is shown in FIG. Fig. 8A , Figure 8B , Fig.9A and Fig. 9B It is shown Figure 7 A circuit diagram of an example embodiment of a main word line driver circuit 610 is shown. Fig.10 It is shown Figure 7 A circuit diagram of an example embodiment of a sub-word line driver circuit 620 is shown.

[0056] Reference Figure 7 , the row decoder 25 can be used for Figure 2 A selected memory bank (eg, the first memory bank BANK1 ) among the first to fourth memory banks BANK1 to BANK4 selects a word line WL corresponding to the row address RA. Figure 7 The row decoder 25 shown in FIG. Figure 2 The first memory bank row decoder 2060a connected to the first memory bank BANK1 among the first to fourth memory bank row decoders 2060a, 2060b, 2060c, and 2060d.

[0057] In the following embodiments, for ease of explanation, the first to fourth memory banks BANK1, BANK2, BANK3, and BANK4 may each include a row decoder 25, and the row decoder 25 may select at least one of the plurality of memory blocks BLK1 to BLKi by decoding the row address, and select the word line WL of the selected memory block. According to the present embodiment, although each of the plurality of memory blocks BLK1 to BLKi is described as including 512 word lines according to 9 row address RA<0:8> signal configurations, the inventive concept is not limited thereto, and other numbers of word lines and corresponding row addresses may be included. For example, the plurality of memory blocks BLK1 to BLKi may each include 1024 word lines or 2048 word lines according to 10 row address RA<0:9> signal configurations or 11 row address RA<0:10> signal configurations.

[0058] The row decoder 25 may include a main word line driver (MWD) circuit 610 and a sub word line driver (SWD) circuit 620. According to some embodiments, the first to fourth memory banks BANK1, BANK2, BANK3, and BANK4 may each include a plurality of memory blocks BLK1 to BLKi, where i is an integer equal to or greater than 2. The main word line driver circuit 610 may be commonly connected to the memory blocks BLK1 to BLKi, and the sub word line driver circuit 620 may be connected to each of the memory blocks BLK1 to BLKi.

[0059] The main word line driver circuit 610 may include a first main word line drive signal generating circuit (NWE0 DRV) 611 and a second main word line drive signal generating circuit (NWE1 DRV) 612 and a first sub word line drive signal generating circuit (PXID DRV) 613 and a second sub word line drive signal generating circuit (PXIB DRV) 614. The main word line driver circuit 610 may generate a first main word line drive signal NWEIB0<0:7> and a second main word line drive signal NWEIB1<0:7> based on a signal of a most significant bit (MSB) group from among row address RA<0:8> signals. The signal of the MSB group from among row address RA<0:8> signals may be set to RA<3:8> row address. RA<3:8> row address may include RA<6:8> row address corresponding to a more significant bit group (hereinafter referred to as "RA678" row address) and RA<3:5> row address corresponding to a less significant bit group (hereinafter referred to as "RA345" row address).

[0060] According to some embodiments, the first main word line drive signal generating circuit 611 may generate the first main word line drive signal NWEIB0<0:7> by decoding the row address RA678, and the second main word line drive signal generating circuit 612 may generate the second main word line drive signal NWEIB1<0:7> by decoding the row address RA345. Such an example is described: in this example, the main word line driver circuit 610 according to the present embodiment divides the MSB signal RA<3:8> of the row address RA<0:8> signal into two groups (e.g., RA678, RA345) and generates eight first main word line drive signals NWEIB0<0:7> and eight second main word line drive signals NWEIB1<0:7> based on them. According to other embodiments, the main word line driver circuit 610 may change the decoding for generating a plurality of main word line drive signals NWEIBn (n is a natural number) based on the number of bits (e.g., 5, 6, or 7) of the MSB group signal from the row address signal according to the configuration of each of the plurality of first to fourth memory banks BANK1, BANK2, BANK3, and BANK4 (i.e., the number of word lines; for example, 1024, 2048, etc.).

[0061] Reference Fig. 8A , the first main word line drive signal generating circuit 611 may include a first transistor 801 to a fourth transistor 804 connected in series between a line of a high voltage VPP and a line of a ground voltage VSS, include a first inverter 806 and a second inverter 807 connected in series to a connection node 805 of the first transistor 801 and the second transistor 802, and include a fifth transistor 808 connected between the line of the high voltage VPP and the connection node 805 of the first transistor 801 and the second transistor 802. The first transistor 801 to the fourth transistor 804 may constitute a specific type of NAND logic circuit. The first transistor 801 may be configured as a P-type metal oxide semiconductor (PMOS) transistor having a precharge signal PCGB connected to its gate, and the second transistor 802 may be configured as an NMOS transistor having a precharge signal PCGB connected to its gate.

[0062] According to some embodiments, the precharge signal PCGB is provided by the control logic circuit 24 based on the precharge command, and may serve as a signal for activating the row decoder 25. The row decoder 25 may be activated by the logic high level precharge signal PCGB, and the row decoder 25 may be deactivated by the logic low level precharge signal PCGB.

[0063] The third transistor 803 may be configured as an NMOS transistor to which the decoded RA678<0:7> row address signal is set (i.e., connected) to its gate, and the fourth transistor 804 may be configured as an NMOS transistor to which the block selection signal BLK_SELECT is set to its gate. The block selection signal BLK_SELECT may be set to select a memory block from among a plurality of memory blocks BLK1 to BLKi. For example, a logic high first block selection signal may be set to select a first memory block BLK1. The first inverter 806 and the second inverter 807 connected in series to the connection node 805 of the first transistor 801 and the second transistor 802 may output a first main word line drive signal NWEIB0<0:7>. The fifth transistor 808 may include a PMOS transistor whose gate is connected to the output of the first inverter 806, and may be referred to as a keeper transistor that stably maintains the output of the first inverter 806.

[0064] Eight first main word line drive signal generating circuits 611 each of which outputs the first main word line drive signal NWEIB0<0:7> in response to the decoded RA678<0:7> row address signal may be provided. Since the configuration of the decoded RA678<0:7> row address signal has eight cases (i.e., 000, 001, 010, 011, 100, 101, 110, and 111), the first main word line drive signal NWEIB0<0:7> to be activated may also have eight configurations. In other words, NWEIB0<0:7> may be activated according to the decoded RA678<0:7> row address signal. <0> 、NWEIB0 <1> 、NWEIB0 <2> 、NWEIB0 <3> 、NWEIB0 <4> 、NWEIB0 <5> 、NWEIB0 <6> and NWEIB0 <7> The first main word line driving signal NWEIB0<0:7> at a logic low level may have a voltage level of a ground voltage VSS level and may be provided to the sub word line driver circuit 620 connected to each of the memory blocks BLK1 to BLKi.

[0065] Reference Figure 8B, the second main word line drive signal generating circuit 612 may include a first transistor 811 to a fourth transistor 814 connected in series between a line of a high voltage VPP and a line of a ground voltage VSS, include a first inverter 816 and a second inverter 817 connected in series to a connection node 815 of the first transistor 811 and the second transistor 812, and include a fifth transistor 818 connected between the line of the high voltage VPP and the connection node 815 of the first transistor 811 and the second transistor 812. The first transistor 811 to the fourth transistor 814 may constitute a specific type of NAND logic circuit. In addition to the decoded RA345<0:7> row address signal being connected to the gate of the third transistor 813, and the second inverter 817 outputting the second main word line drive signal NWEIB1<0:7>, the second main word line drive signal generating circuit 612 has Fig. 8A The first main word line drive signal generating circuit 611 has the same configuration.

[0066] Eight second main word line drive signal generating circuits 612 each of which outputs the second main word line drive signal NWEIB1<0:7> in response to the decoded RA345<0:7> row address signal may be provided. Since the configuration of the decoded RA345<0:7> row address signal has eight cases (i.e., 000, 001, 010, 011, 100, 101, 110, and 111), the second main word line drive signal NWEIB1<0:7> to be activated may also have eight configurations. In other words, according to the decoded RA345<0:7> row address signal, NWEIB1<0:7> may be activated. <0> 、NWEIB1 <1> 、NWEIB1 <2> 、NWEIB1 <3> 、NWEIB1 <4> 、NWEIB1 <5> 、NWEIB1 <6> and NWEIB1 <7> The second main word line driving signal NWEIB1<0:7> at a logic low level may have a voltage level of a ground voltage VSS level and may be provided to the sub word line driver circuit 620 connected to each of the memory blocks BLK1 to BLKi.

[0067] Figure 7The main word line driver circuit 610 may generate a first sub word line drive signal PXID<0:7> and a second sub word line drive signal PXIB<0:7> based on a signal of a least significant bit (LSB) group from among row address RA<0:8> signals. The signal of the LSB group from among row address RA<0:8> signals may be set to RA<0:2> row address (hereinafter referred to as "RA012"). The main word line driver circuit 610 may include a first sub word line drive signal generating circuit 613 and a second sub word line drive signal generating circuit 614, the first sub word line drive signal generating circuit 613 is used to generate the first sub word line drive signal PXID<0:7> by decoding the RA012 row address, and the second sub word line drive signal generating circuit 614 is used to generate the second sub word line drive signal PXIB<0:7> by decoding the RA012 row address.

[0068] Although an example is described in which the main word line driver circuit 610 according to the present embodiment generates eight first sub word line drive signals PXID<0:7> and eight second sub word line drive signals PXIB<0:7> based on the LSB signal RA<0:2> of the row address RA<0:8> signal, it is merely an example to help understanding and is not intended to limit the inventive concept. According to other embodiments, the main word line driver circuit 610 may change decoding for generating a plurality of sub word line drive signals PXIDj and PXIBk (j and k are natural numbers) based on the number of bits (e.g., 3, 4, or 5) of the LSB group signal from among the row address signal according to the configuration of each of the plurality of memory blocks BLK1 to BLKi (i.e., the number of word lines; e.g., 2048, 4096, etc.).

[0069] Reference Fig.9A, the first sub-word line drive signal generating circuit 613 may include a first transistor 911 to a fourth transistor 914 connected in series between a line of a high voltage VPP and a line of a ground voltage VSS, an inverter 916 connected to a connection node 915 of the first transistor 911 and the second transistor 912, and a fifth transistor 917 connected between the line of the high voltage VPP and the connection node 915 of the first transistor 911 and the second transistor 912. The first transistor 911 to the fourth transistor 914 may constitute a specific type of NAND logic circuit. The first transistor 911 may be configured as a PMOS transistor having a precharge signal PCGB connected to its gate, and the second transistor 912 may be configured as an NMOS transistor having a precharge signal PCGB connected to its gate. The third transistor 913 may be configured as an NMOS transistor having a decoded RA012<0:7> row address signal connected to its gate, and the fourth transistor 914 may be configured as an NMOS transistor having a block select signal BLK_SELECT connected to its gate. The inverter 916 may output the first sub-word line drive signal PXID<0:7>. The fifth transistor 917 may include a PMOS transistor whose gate is connected to the output of the inverter 916 , and may be referred to as a keeper transistor that stably maintains the output of the inverter 916 .

[0070] Eight first sub-word line drive signal generating circuits 613 each of which outputs the first sub-word line drive signal PXID<0:7> in response to the decoded RA012<0:7> row address signal may be provided. Since the configuration of the decoded RA012<0:7> row address signal has eight cases (i.e., 000, 001, 010, 011, 100, 101, 110, and 111), the first sub-word line drive signal PXID<0:7> to be activated may also have eight configurations. In other words, the first sub-word line drive signal PXID<0:7> may be activated according to the decoded RA012<0:7> row address signal. <0> 、PXID0 <1> 、PXID0 <2> 、PXID0 <3> 、PXID0 <4> 、PXID0 <5> 、PXID0 <6> and PXID0 <7> Any one of the first sub word line driving signals PXID<0:7> at a logic high level may have a voltage level of a high voltage VPP and may be provided to the sub word line driver circuit 620 connected to each of the memory blocks BLK1 to BLKi.

[0071] Reference Fig. 9B, the second sub-word line drive signal generating circuit 614 may include first to fourth transistors 921 to 924 connected in series between a line of a high voltage VPP and a line of a ground voltage VSS, include a first inverter 926 and a second inverter 927 connected in series to a connection node 925 of the first transistor 921 and the second transistor 922, and include a fifth transistor 928 connected between the line of the high voltage VPP and the connection node 925 of the first transistor 921 and the second transistor 922. The first to fourth transistors 921 to 924 may constitute a specific type of NAND logic circuit. In addition to the first inverter 926 and the second inverter 927 connected in series to the connection node 925 of the first transistor 921 and the second transistor 922 outputting the second sub-word line drive signal PXIB<0:7>, the second sub-word line drive signal generating circuit 614 has the same Fig.9A The second sub word line driving signal generating circuit 613 has the same configuration. The first sub word line driving signal PXID<0:7> and the second sub word line driving signal PXIB<0:7> may have opposite logic levels to each other (ie, complementary outputs).

[0072] Eight second sub-word line drive signal generating circuits 614 each of which outputs the second sub-word line drive signal PXIB<0:7> in response to the decoded RA012<0:7> row address signal may be provided. Since the decoded RA012<0:7> row address signal has eight configurations (i.e., 000, 001, 010, 011, 100, 101, 110, and 111), the second sub-word line drive signal PXIB<0:7> to be activated may also have eight configurations. In other words, the second sub-word line drive signal PXIB<0:7> may be activated according to the decoded RA012<0:7> row address signal. <0> 、PXIB0 <1> 、PXIB0 <2> 、PXIB0 <3> 、PXIB0 <4> 、PXIB0 <5> 、PXIB0 <6> and PXIB0 <7> Any one of the second sub word line driving signals PXIB<0:7> at a logic low level may have a voltage level of a ground voltage VSS and may be provided to the sub word line driver circuit 620 connected to each of the memory blocks BLK1 to BLKi.

[0073] like Fig.11As shown in , the main word line driver circuit 610 may include eight first main word line drive signal generating circuits 611, eight second main word line drive signal generating circuits 612, eight first sub word line drive signal generating circuits 613, and eight second sub word line drive signal generating circuits 614. The main word line driver circuit 610 may be provided in the peripheral circuit structure CPS, and the first main word line drive signal NWEIB0<0:7> and the second main word line drive signal NWEIB1<0:7> and the first sub word line drive signal PXID<0:7> and the second sub word line drive signal PXIB<0:7> outputted from the main word line driver circuit 610 may be commonly connected to the memory blocks BLK1 to BLKi.

[0074] Reference Fig.10 , the sub word line driver circuit 620 may include first to fifth transistors 1001, 1002, 1003, 1004, and 1006. The first transistor 1001 and the second transistor 1002 may be connected in series between a line of the first sub word line drive signal PXID<0:7> and a connection node 1005 of the second transistor 1002 to the fourth transistor 1004, a first main word line drive signal NWEIB0<0:7> may be connected to a gate of the first transistor 1001, and a second main word line drive signal NWEIB1<0:7> may be connected to a gate of the second transistor 1002. The third transistor 1003 and the fourth transistor 1004 may be connected in parallel between a connection node 1005 of the second transistor 1002 to the fourth transistor 1004 and a line of a negative voltage VBB, a second main word line drive signal NWEIB1<0:7> may be connected to a gate of the third transistor 1003, and a first main word line drive signal NWEIB0<0:7> may be connected to a gate of the fourth transistor 1004. The fifth transistor 1006 may be configured as an NMOS transistor in which a line of a negative voltage VBB is connected to a source of the fifth transistor 1006, a connection node 1005 of the second transistor 1002 to the fourth transistor 1004 is connected to a drain of the fifth transistor 1006, and a second sub word line drive signal PXIB<0:7> is applied to a gate of the fifth transistor 1006. The connection node 1005 of the second transistor 1002 to the fourth transistor 1004 may be connected to a word line WL<0:511> of the memory blocks BLK1 to BLKi. The first transistor 1001 to the fourth transistor 1004 of the sub word line driver circuit 620 may be implemented as a NOR logic circuit.

[0075] The sub-word line driver circuits 620 may be provided in portions of the peripheral circuit structure PCS corresponding to the memory blocks BLK1 to BLKi, respectively. The 512 sub-word line driver circuits 620 may be provided to be connected to the word lines WL<0:511>, respectively, in response to the first main word line drive signal NWEIB0<0:7>, the second main word line drive signal NWEIB1<0:7>, the first sub-word line drive signal PXID<0:7>, and the second sub-word line drive signal PXIB<0:7>. The sub word line driver circuit 620 may select any one of the 512 word lines WL<0:511> in response to the logic low level of the activated first main word line drive signal NWEIB0<0:7>, the logic low level of the activated second main word line drive signal NWEIB1<0:7>, the logic high level of the activated first sub word line drive signal PXID<0:7>, and the logic low level of the activated second sub word line drive signal PXIB<0:7>, and may activate the selected word line to a logic high level. The word line selected from among the word lines WL<0:511> may be activated to the level of the high voltage VPP of the first sub word line drive signal PXID<0:7> of a logic high level.

[0076] Fig.11 and Fig.12 FIG. 1 shows a row decoder architecture in which a row decoder is disposed in a memory device according to one or more embodiments. Fig.11 It is shown that the Figure 2 1 is a perspective view of a first memory block BLK1 and a second memory block BLK2 among a plurality of memory blocks BLK1 to BLKi in first to fourth memory banks BANK1, BANK2, BANK3, and BANK4. Fig.12 1 to 3 word lines WL<0:511> are shown. <0> , WL <1> and WL <2> Each of the associated bonding metal pads 301 and the sub-word line driver circuit 620.

[0077] Combination Figure 7 , Fig. 8A , Figure 8B , Fig.9A , Fig. 9B and Fig.10 Reference Fig.11, the memory device 10 may include a cell array structure CAS and a core peripheral circuit structure CPS stacked on each other in a third direction D3. The cell array structure CAS may include a first memory block BLK1 region and a second memory block BLK2 region. The core peripheral circuit structure CPS may include a main word line driver circuit 610 region commonly connected to the first memory block BLK1 and the second memory block BLK2 and a sub word line driver circuit 620 region connected to each of the first memory block BLK1 and the second memory block BLK2.

[0078] The main word line driver circuit 610 area may include eight first main word line drive signal generating circuits 611 for respectively generating first main word line drive signals NWEIB0<0:7> (expressed as “NWEIB0”), eight second main word line drive signal generating circuits 612 for respectively generating second main word line drive signals NWEIB1<0:7> (expressed as “NWEIB1”), eight first sub-word line drive signal generating circuits 613 for respectively generating first sub-word line drive signals PXID<0:7> (expressed as “PXID”), and eight second sub-word line drive signal generating circuits 614 for respectively generating second sub-word line drive signals PXIB<0:7> (expressed as “PXIB”). The lines of the first main word line driving signal NWEIB0<0:7>, the lines of the second main word line driving signal NWEIB1<0:7>, the lines of the first sub word line driving signal PXID<0:7>, and the lines of the second sub word line driving signal PXIB<0:7> may be set to the sub word line driver circuit 620 area.

[0079] The sub-word line driver circuit 620 region may include 512 sub-word line driver circuits 620 and 512 bonding metal pads 301 respectively connected to the word lines WL<0:511>. The 512 sub-word line driver circuits 620 and the 512 bonding metal pads 301 may be divided into word lines corresponding to the first memory block BLK1 and the second memory block BLK2, respectively. According to an embodiment, the first to third word lines WL <0> , WL <1> and WL <2> may be included in the first memory block BLK1.

[0080] Reference Fig.10 and Fig.12, respectively connected to the first to third word lines WL <0> , WL <1> and WL <2> The sub-word line driver circuit 620 may be arranged in the bonding metal pad 301 area. A sub-word line driver circuit 620 connected to the first word line WL may be provided. <0> The sub-word line driver circuit 620 is connected to the first main word line drive signal NWEIB0 <0> The line and the second main word line drive signal NWEIB1 <0> The first transistor 1001 and the second transistor 1002 of the line are connected in series in the first sub-word line drive signal PXID <0> The line and the first word line WL <0> In addition, a first word line WL may be provided. <0> The sub-word line driver circuit 620 is connected to the second main word line drive signal NWEIB1 <0> line, the first main word line drive signal NWEIB0 <0> The line and second sub-word line drive signal PXIB <0> The third to fifth transistors 1003, 1004 and 1006 of the line are connected in parallel to the first word line WL <0> and a negative voltage VBB. The first word line WL <0> The connection to the bonding metal pad 301 may be through the metal contact 1200 .

[0081] Can be set to connect to the second word line WL <1> The sub-word line driver circuit 620 is connected to the first main word line drive signal NWEIB0 <0> The line and the second main word line drive signal NWEIB1 <0> The first transistor 1001 and the second transistor 1002 of the line are connected in series in the first sub-word line drive signal PXID <1> The line and the second word line WL <1> In addition, a second word line WL may be provided. <1> The sub-word line driver circuit 620 is connected to the second main word line drive signal NWEIB1 <0> line, the first main word line drive signal NWEIB0 <0> The line and second sub-word line drive signal PXIB <1> The third to fifth transistors 1003, 1004 and 1006 of the line are connected in parallel to the second word line WL <1> and a negative voltage VBB. The second word line WL <1> The connection to the bonding metal pad 301 may be through the metal contact 1201 .

[0082] Can be set to connect to the third word line WL <2> The sub-word line driver circuit 620 is connected to the first main word line drive signal NWEIB0 <0> The line and the second main word line drive signal NWEIB1 <0> The first transistor 1001 and the second transistor 1002 of the line are connected in series in the first (sub-word line drive signal PXID <2> The line and the third word line WL <2> In addition, a third word line WL may be provided. <2> The sub-word line driver circuit 620 is connected to the second main word line drive signal NWEIB1 <0> line, the first main word line drive signal NWEIB0 <0> The line and second sub-word line drive signal PXIB <2> The third to fifth transistors 1003, 1004 and 1006 of the line are connected in parallel on the third word line WL <2> and a negative voltage VBB. The third word line WL <2> The connection to the bonding metal pad 301 may be through the metal contact 1202 .

[0083] According to some embodiments, the lines of the first main word line driving signal NWEIB0<0:7>, the lines of the second main word line driving signal NWEIB1<0:7>, the lines of the first sub word line driving signal PXID<0:7>, and the lines of the second sub word line driving signal PXIB<0:7> provided in the main word line driver circuit 610 region may be arranged at regular intervals and extend to the sub word line driver circuit 620 region. In addition, there are lines configured to be connected to the first main word line driving signal NWEIB0<0:7>, the second main word line driving signal NWEIB1<0:7>, and the lines of the first sub word line driving signal PXID<0:7>. <0> The sub word line driver circuit 620 of the NOR logic circuit of the line of the first sub word line drive signal PXID<0:7>, the line of the second sub word line drive signal PXIB<0:7> can be arranged in the bonding metal pad 301 area connected to the word line WL<0:511> respectively. This means that by uniformly arranging the wiring connected to the circuit constituting the row decoder 25, the area occupied by the row decoder 25 can be reduced. Therefore, the chip size of the memory device 10 can be reduced, and the circuit operation delay time (i.e., latency) of the row decoder 25 can be reduced, thereby improving the operation performance of the memory device 10.

[0084] Fig.13 is a schematic block diagram illustrating a system 2000 of an electronic device including a memory device according to one or more embodiments.

[0085] Reference Fig.13, the system 2000 may include a camera 2100, a display 2200, an audio processor 2300, a modem 2400, DRAMs 2500a and 2500b, flash memories 2600a and 2600b, input / output (I / O) devices 2700a and 2700b, and an application processor (AP) 2800. The system 2000 may be implemented as a laptop computer, a mobile phone, a smart phone, a tablet PC, a wearable device, a healthcare device, or an Internet of Things (IoT) device. In addition, the system 2000 may be implemented as a server or a PC.

[0086] The camera 2100 may capture a still image or a video according to the control of the user, and may store the captured image / video data or transmit the captured image / video data to the display 2200. The audio processor 2300 may process the audio data or network content included in the flash memory 2600a and 2600b. The modem 2400 may transmit a modulated signal for wired / wireless data transmission / reception to a receiver, and the modulated signal may be demodulated by the receiver to restore the original signal. The I / O devices 2700a and 2700b may include devices that provide a digital input function and / or a digital output function (e.g., a universal serial bus (USB), a storage device, a digital camera, a secure digital (SD) card, a digital versatile disk (DVD), a network adapter, a touch screen, etc.).

[0087] The AP 2800 may control the overall operation of the system 2000. The AP 2800 may include a controller block 2810, an accelerator block or an accelerator chip 2820, and an interface block 2830. The AP 2800 may control the display 2200 so that a portion of the content stored in the flash memories 2600a and 2600b is displayed on the display 2200. When a user input is received through the I / O devices 2700a and 2700b, the AP 2800 may perform a control operation corresponding to the user input. The AP 2800 may include an accelerator block of a circuit dedicated to the calculation of artificial intelligence (AI) or other data, or may include the accelerator chip 2820 separately from the AP 2800. The DRAM 2500b may be additionally provided in the accelerator block or the accelerator chip 2820. The accelerator block is a functional block specialized in performing specific functions of the AP 2800, and may include a graphics processing unit (GPU) as a functional block specialized in processing graphic data, a neural processing unit (NPU) as a block specialized in AI calculation and inference, and a data processing unit (DPU) as a block specialized in data transmission.

[0088] The system 2000 may include a plurality of DRAMs 2500a and 2500b. The AP 2800 may establish a DRAM interface protocol and communicate with the DRAMs 2500a and 2500b to control the DRAMs 2500a and 2500b by following the Joint Electron Device Engineering Council (JEDEC) standard and the command set by the mode register (MRS), or use company-specific functions such as low voltage / high speed / reliability and cyclic redundancy check (CRC) / error correction code (ECC) functions. For example, the AP 2800 may communicate with the DRAM 2500a through an interface conforming to the JEDEC standard such as LPDDR4 and LPDDR5, and the accelerator block or accelerator chip 2820 may set and use a new DRAM interface protocol to control the DRAM 2500b for the accelerator having a greater bandwidth than the DRAM 2500a.

[0089] although Fig.13 Only DRAM 2500a and 2500b are shown, but the present invention is not limited thereto. As long as the bandwidth, response speed, and voltage conditions of AP 2800 or accelerator chip 2820 are met, any memory (such as phase change random access memory (PRAM), static random access memory (SRAM), magnetic random access memory (MRAM), resistive random access memory (RRAM), ferroelectric random access memory (FRAM), or hybrid RAM) can be used. DRAM 2500a and 2500b have a relatively small latency and bandwidth than I / O devices 2700a and 2700b or flash memory 2600a and 2600b. DRAM 2500a and 2500b are initialized when system 2000 is powered on and OS and application data are loaded therein, and thus DRAM 2500a and 2500b can be used as temporary storage of OS and application data, or can be used as execution space of various software codes.

[0090] In DRAM 2500a and 2500b, four arithmetic operations (i.e., addition, subtraction, multiplication, division), vector calculation, address calculation, or fast Fourier transform (FFT) calculation may be performed. In addition, in DRAM 2500a and 2500b, functions for inference operations may be performed. Here, inference may be performed in a deep learning algorithm using an artificial neural network. The deep learning algorithm may include a training operation for learning a model through various data and an inference operation for recognizing data using the trained model. According to an embodiment, an image captured by a user through camera 2100 is signal processed and stored in DRAM 2500b, and an accelerator block or accelerator chip 2820 may perform AI data calculations for recognizing data using the data stored in DRAM 2500b and the function for inference.

[0091] The system 2000 may include a plurality of storage devices or flash memories 2600a and 2600b having a larger capacity than the DRAM 2500a and 2500b. The accelerator block or accelerator chip 2820 may use the flash memories 2600a and 2600b to perform training operations and AI data calculations. According to an embodiment, the flash memories 2600a and 2600b may include a memory controller 2610 and a flash memory device 2620, and the training operations and inference AI data calculations performed by the AP 2800 and / or the accelerator chip 2820 may be performed more efficiently by using an arithmetic unit included in the memory controller 2610. The flash memories 2600a and 2600b may store images captured by the camera 2100 or data sent over a data network. For example, the flash memories 2600a and 2600b may store augmented reality / virtual reality content, high definition (HD) content, or ultra high definition (UHD) content.

[0092] In system 2000, DRAM 2500a and 2500b may include the above-referenced Figures 1 to 12The memory device described herein may include a peripheral circuit structure formed on a semiconductor substrate and a cell array structure vertically stacked with the peripheral circuit structure on the peripheral circuit structure. The cell array structure may include a plurality of memory blocks in a memory cell region, in which a plurality of vertical channel transistor structures and a plurality of capacitor structures respectively connected to the vertical channel transistor structures are formed. The core peripheral circuit structure may include a row decoder connected to a plurality of word lines of each of the plurality of memory blocks, and the row decoder may include a main word line driver circuit commonly connected to the plurality of memory blocks and a sub-word line driver circuit 620 connected to each of the plurality of memory blocks. The main word line driver circuit may generate a first main word line drive signal based on some signals from the MSB group among the row address signals, generate a second main word line drive signal based on the remaining signals from the MSB group among the row address signals, and generate a first sub-word line drive signal and a second sub-word line drive signal having opposite logic levels based on signals from the LSB group among the row address signals. The sub-word line driver circuit may include a first PMOS transistor and a second PMOS transistor connected in series to a line of each of the first sub-word line drive signals and first to third NMOS transistors connected in parallel to a line of a negative voltage of the memory device, each of the first main word line drive signals may be connected to a gate of the first PMOS transistor, each of the second main word line drive signals may be connected to a gate of the second PMOS transistor, each of the first main word line drive signals may be connected to a gate of the first NMOS transistor, each of the second main word line drive signals may be connected to a gate of the second NMOS transistor, and each of the first sub-word line drive signals may be connected to a gate of the third NMOS transistor. The first PMOS transistor and the second PMOS transistor and the first NMOS transistor and the second NMOS transistor of the sub-word line driver circuit may constitute a NOR logic circuit, and a plurality of word lines may be connected to the second PMOS transistor and connection nodes of the first to third NMOS transistors, respectively. The sub-word line driver circuit may be disposed in a region vertically overlapped with a bonding metal pad, the bonding metal pad being in electrical contact with each of the plurality of word lines. In a memory device, since a row decoder circuit and wirings connected to the row decoder circuit at uniform intervals are arranged in a circuit core peripheral circuit structure, and a sub-word line driver circuit of the row decoder circuit is arranged in a bonding metal pad region, the area occupied by the row driver circuit can be reduced, thereby reducing the chip size of the memory device. In addition, the operation delay time of the row decoder circuit is reduced, thereby improving the operation performance of the memory device.

[0093] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A memory device, comprising: a plurality of memory blocks, each of the plurality of memory blocks comprising a plurality of word lines; as well as a row decoder electrically connected to the plurality of word lines of each of the plurality of memory blocks, Among them, the row decoder includes: a main word line driver circuit commonly electrically connected to the plurality of memory blocks and configured to generate a plurality of first main word line drive signals, a plurality of second main word line drive signals, and a plurality of sub word line drive signals based on a plurality of row address signals; and A sub-word line driver circuit is electrically connected to each of the plurality of memory blocks and is configured to activate one word line from among the plurality of word lines using an NOR logic circuit, the plurality of first main word line drive signals, the plurality of second main word line drive signals, and the plurality of sub-word line drive signals are electrically connected to the NOR logic circuit.

2. The memory device according to claim 1, wherein: The main word line driver circuit includes: A first main word line drive signal generating circuit configured to generate the plurality of first main word line drive signals based on a subset of signals from a more significant bit group among the plurality of row address signals; A second main word line drive signal generating circuit configured to generate the plurality of second main word line drive signals based on remaining signals not included in the subset of signals from more significant bit groups among the plurality of row address signals; and The first sub-word line drive signal generating circuit and the second sub-word line drive signal generating circuit are configured to respectively generate a plurality of first sub-word line drive signals and a plurality of second sub-word line drive signals based on signals from a less significant bit group among the plurality of row address signals, the plurality of first sub-word line drive signals and the plurality of second sub-word line drive signals having logic levels complementary to each other, and wherein the plurality of sub-word line drive signals include the plurality of first sub-word line drive signals and the plurality of second sub-word line drive signals.

3. The memory device according to claim 2, wherein: The sub-word line driver circuit comprises: a first PMOS transistor and a second PMOS transistor connected in series to the lines of the plurality of first sub word line drive signals, wherein each of the plurality of first main word line drive signals is connected to a gate of the first PMOS transistor, and each of the plurality of second main word line drive signals is connected to a gate of the second PMOS transistor; and first to third NMOS transistors are connected in parallel to a line of a negative voltage of the memory device, wherein each of the plurality of first main word line drive signals is connected to a gate of the first NMOS transistor, each of the plurality of second main word line drive signals is connected to a gate of the second NMOS transistor, and each of the plurality of second sub word line drive signals is connected to a gate of the third NMOS transistor, The NOR logic circuit includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor, and The plurality of word lines are respectively connected to connection nodes between the second PMOS transistor and the first to third NMOS transistors.

4. The memory device according to claim 2, wherein: The first main word line drive signal generating circuit includes: a NAND logic circuit configured to decode the subset of signals from the more significant bit group among the multiple row address signals, input each of the decoded multiple row address signals, and output each of the multiple first main word line drive signals, and wherein the NAND logic circuit is configured to be selectively connected to a line of a voltage higher than a power supply voltage and a line of a ground voltage of the memory device.

5. The memory device according to claim 2, wherein: The second main word line drive signal generating circuit includes: a NAND logic circuit configured to decode the remaining signal from the more significant bit group among the multiple row address signals, input each of the decoded multiple row address signals, and output each of the multiple second main word line drive signals, and wherein the NAND logic circuit is configured to be selectively connected to a line of a voltage higher than a power supply voltage and a line of a ground voltage of the memory device.

6. The memory device according to claim 2, wherein: The first sub-word line drive signal generating circuit includes: a NAND logic circuit configured to decode a signal from a less significant bit group among the plurality of row address signals, input each of the decoded plurality of row address signals, and output each of the plurality of first sub-word line drive signals, and wherein the NAND logic circuit is configured to be selectively connected to a line of a voltage higher than a power supply voltage and a line of a ground voltage of the memory device.

7. The memory device according to claim 2, wherein: The second sub-word line drive signal generating circuit includes: a NAND logic circuit configured to decode a signal from a less significant bit group among the plurality of row address signals, input each of the decoded plurality of row address signals, and output each of the plurality of second sub-word line drive signals, and wherein the NAND logic circuit is configured to be selectively connected to a line of a voltage higher than a power supply voltage and a line of a ground voltage of the memory device.

8. A memory device comprising: A core peripheral circuit structure including a first bonding metal pad; as well as a cell array structure at least partially overlapping the core peripheral circuit structure in a vertical direction perpendicular to an upper surface of the core peripheral circuit structure and comprising a second bonding metal pad electrically contacting the first bonding metal pad, The cell array structure includes a memory cell region, the memory cell region includes a plurality of memory blocks, each of the plurality of memory blocks includes a plurality of word lines, wherein each of the plurality of word lines electrically contacts a first bonding metal pad and a second bonding metal pad, respectively. The core peripheral circuit structure includes: a row decoder electrically connected to the plurality of word lines of each of the plurality of memory blocks, The row decoder consists of: a main word line driver circuit configured to generate a plurality of first main word line drive signals, a plurality of second main word line drive signals, and a plurality of sub word line drive signals based on a plurality of row address signals; and The sub-word line driver circuit is configured to activate one word line from among the plurality of word lines using an NOR logic circuit, the plurality of first main word line drive signals, the plurality of second main word line drive signals and the plurality of sub-word line drive signals being electrically connected to the NOR logic circuit.

9. The memory device according to claim 8, wherein: A main word line driver circuit is electrically connected in common to the plurality of memory blocks.

10. The memory device according to claim 8, wherein: The main word line driver circuit includes: A first main word line drive signal generating circuit configured to generate the plurality of first main word line drive signals based on a subset of signals from a more significant bit group among the plurality of row address signals; A second main word line drive signal generating circuit configured to generate the plurality of second main word line drive signals based on remaining signals not included in the subset of signals from more significant bit groups among the plurality of row address signals; and The first sub-word line drive signal generating circuit and the second sub-word line drive signal generating circuit are configured to respectively generate a plurality of first sub-word line drive signals and a plurality of second sub-word line drive signals based on signals from a less significant bit group among the plurality of row address signals, the plurality of first sub-word line drive signals and the plurality of second sub-word line drive signals having logic levels complementary to each other, and wherein the plurality of sub-word line drive signals include the plurality of first sub-word line drive signals and the plurality of second sub-word line drive signals.

11. The memory device according to claim 8, wherein: A sub word line driver circuit is electrically connected to each of the plurality of memory blocks.

12. The memory device according to claim 11, wherein: The sub-word line driver circuit comprises: a first PMOS transistor and a second PMOS transistor connected in series to the lines of the plurality of first sub-word line drive signals, wherein each of the plurality of first main word line drive signals is connected to a gate of the first PMOS transistor, and each of the plurality of second main word line drive signals is connected to a gate of the second PMOS transistor; first to third NMOS transistors are connected in parallel to a line of a negative voltage of the memory device, wherein each of the plurality of first main word line drive signals is connected to a gate of the first NMOS transistor, each of the plurality of second main word line drive signals is connected to a gate of the second NMOS transistor, and each of the plurality of second sub word line drive signals is connected to a gate of the third NMOS transistor, The NOR logic circuit includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor, and The plurality of word lines are respectively connected to connection nodes between the second PMOS transistor and the first to third NMOS transistors.

13. The memory device according to claim 8, wherein: The memory cell region includes a plurality of bit lines extending in a second horizontal direction intersecting the first horizontal direction and parallel to an upper surface of a core peripheral circuit structure, and the memory device further includes a plurality of cell structures including a plurality of vertical channel transistor structures respectively on the plurality of bit lines and a plurality of capacitor structures respectively electrically connected to the plurality of vertical channel transistor structures.

14. The memory device according to claim 13, wherein: The memory cell region includes: a shielding bit line between and below the plurality of bit lines.

15. A memory device comprising: A core peripheral circuit structure including a first bonding metal pad; as well as a cell array structure at least partially overlapping the core peripheral circuit structure in a vertical direction perpendicular to an upper surface of the core peripheral circuit structure and comprising a second bonding metal pad in contact with the first bonding metal pad, The cell array structure includes a memory cell region, the memory cell region includes a plurality of memory blocks, each of the plurality of memory blocks includes a plurality of word lines, wherein each of the plurality of word lines electrically contacts a first bonding metal pad and a second bonding metal pad, respectively. The core peripheral circuit structure includes: a row decoder electrically connected to the plurality of word lines of each of the plurality of memory blocks, The row decoder includes: a sub-word line driver circuit configured to activate one word line from among the plurality of word lines, and The sub word line driver circuit is located in a region at least partially overlapping the first bonding metal pad in a vertical direction.

16. The memory device of claim 15, wherein: The row decoder also includes: a main word line driver circuit commonly connected to the plurality of memory blocks and configured to generate a plurality of first main word line drive signals, a plurality of second main word line drive signals, and a plurality of sub word line drive signals based on a plurality of row address signals, Wherein, the sub-word line driver circuit is electrically connected to each of the plurality of memory blocks and is configured to activate the one word line from among the plurality of word lines based on the plurality of first main word line drive signals, the plurality of second main word line drive signals and the plurality of sub-word line drive signals.

17. The memory device of claim 16, wherein: The main word line driver circuit includes: A first main word line drive signal generating circuit configured to generate the plurality of first main word line drive signals based on a subset of signals from a more significant bit group among the plurality of row address signals; A second main word line drive signal generating circuit configured to generate the plurality of second main word line drive signals based on remaining signals not included in the subset of signals from more significant bit groups among the plurality of row address signals; and The first sub-word line drive signal generating circuit and the second sub-word line drive signal generating circuit are configured to respectively generate a plurality of first sub-word line drive signals and a plurality of second sub-word line drive signals based on signals from a less significant bit group among the plurality of row address signals, the plurality of first sub-word line drive signals and the plurality of second sub-word line drive signals having logic levels complementary to each other, and the plurality of sub-word line drive signals include the plurality of first sub-word line drive signals and the plurality of second sub-word line drive signals.

18. The memory device of claim 17, wherein: The sub-word line driver circuit comprises: a first PMOS transistor and a second PMOS transistor connected in series to the lines of the plurality of first sub word line drive signals, wherein each of the plurality of first main word line drive signals is connected to a gate of the first PMOS transistor, and each of the plurality of second main word line drive signals is connected to a gate of the second PMOS transistor; and first to third NMOS transistors are connected in parallel to a line of a negative voltage of the memory device, wherein each of the plurality of first main word line drive signals is connected to a gate of the first NMOS transistor, each of the plurality of second main word line drive signals is connected to a gate of the second NMOS transistor, and each of the plurality of second sub word line drive signals is connected to a gate of the third NMOS transistor, The NOR logic circuit includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor, and The plurality of word lines are respectively connected to connection nodes between the second PMOS transistor and the first to third NMOS transistors.

19. The memory device of claim 15, wherein: The memory cell region includes a plurality of bit lines extending in a second horizontal direction intersecting the first horizontal direction, and the memory device includes a plurality of cell structures including a plurality of vertical channel transistor structures respectively on the plurality of bit lines and a plurality of capacitor structures respectively electrically connected to the plurality of vertical channel transistor structures.

20. The memory device of claim 19, wherein: The memory cell region includes: a shielding bit line between and below the plurality of bit lines.

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