Packaging substrate and preparation method thereof

Abstract

The invention provides a packaging substrate and a preparation method thereof, and the method comprises the steps: arranging a first circuit layer, a first dielectric layer, a first silicon-based intermediate layer, a second dielectric layer, a second silicon-based intermediate layer and a third circuit layer on each of the two surfaces of a core plate, separating the intermediate dielectric layer in the core plate from a first conductive layer and a second conductive layer on the two surfaces, and removing the first conductive layer and the second conductive layer to obtain two packaging substrate structures, and arranging a solder mask to lead out the first circuit layer and the third circuit layer. According to the invention, the process is carried out on the two surfaces of one core plate at the same time, so that two times of packaging substrates can be formed within the same time, and the preparation efficiency is improved; meanwhile, the dielectric layer with the groove is obtained by an imprinting method, so that the preparation precision and the preparation speed are improved; in addition, the circuit layer on the core board is prepared through a wire embedding process, and the circuit precision is improved; and finally, a vernier structure and a plum blossom hole structure are used as alignment structures, so that the alignment precision and the alignment efficiency are improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor integrated circuit manufacturing, and particularly relates to a packaging substrate and a preparation method thereof. Background Art

[0002] With the development of electronic technology, the semiconductor market demands higher integration. At this time, traditional packaging can no longer meet the requirements, and the development of advanced packaging technology has become the trend of the current era. Most packaging substrates mount chips on the surface for packaging, but the limited surface mounting space can no longer accommodate more chips for surface mounting. Therefore, after embedding a silicon-based intermediate layer in the packaging substrate, the utilization rate of the packaging substrate can be improved, the surface mounting area can be reduced, and the limited surface space can be left for high-performance chips. However, in the prior art, generally only one layer of silicon-based intermediate layer can be integrated, and the preparation efficiency is low.

[0003] At the same time, in the prior art, the subtractive method is usually used to prepare the first circuit layer on the core board, and the achievable line accuracy is limited, making it difficult to meet the requirements of higher integration line accuracy.

[0004] In addition, in the prior art, when embedding a silicon-based intermediate layer in a packaging substrate, it is necessary to make a groove (Cavity) at a position corresponding to the embedded silicon-based intermediate layer, then use a chip mounter to attach the silicon-based intermediate layer in the Cavity, and then perform the lamination of the surface dielectric layer. How to embed more silicon-based intermediate layers in the packaging substrate while maintaining high precision in the mounting of the silicon-based intermediate layer is one of the technical difficulties in realizing this preparation process.

[0005] It should be noted that the above introduction of the technical background is only for the convenience of clearly and completely explaining the technical solutions of the present application and facilitating the understanding of those skilled in the art. It cannot be considered that the above technical solutions are well-known to those skilled in the art just because these solutions are described in the background art part of the present application. Summary of the Invention

[0006] In view of the above disadvantages of the prior art, the purpose of the present invention is to provide a packaging substrate and a preparation method thereof, which are used to solve the problems of low preparation efficiency and poor line accuracy of the silicon-based intermediate layer in the packaging substrate in the prior art.

[0007] To achieve the above object, the present invention provides a preparation method of a packaging substrate, and the preparation method includes:

[0008] Step 1: Provide a core board, the core board includes a first conductive layer, an intermediate dielectric layer and a second conductive layer, the first conductive layer and the second conductive layer are respectively disposed on two opposite surfaces of the intermediate dielectric layer; a first circuit layer including a first circuit pattern, a first groove and a first alignment pattern is disposed on both the first conductive layer and the second conductive layer; align and bond a first silicon-based intermediate layer into the first groove;

[0009] Step 2: Dispose a first dielectric layer on the first silicon-based intermediate layer, the first dielectric layer covers the first silicon-based intermediate layer, the first circuit layer and the surfaces of the exposed first conductive layer and the second conductive layer; dispose a patterned second circuit layer on the first dielectric layer, the second circuit layer includes a second circuit pattern, a second alignment pattern, a second groove circuit pattern and a first via post, the first via post penetrates through the first dielectric layer and forms an effective electrical connection with the first circuit layer and the first silicon-based intermediate layer;

[0010] Step 3: Dispose a second dielectric layer including a second groove on the second circuit layer, the second dielectric layer covers the second circuit layer and the exposed surface of the first dielectric layer, the second groove of the second dielectric layer exposes the second groove circuit pattern; dispose a second silicon-based intermediate layer on the second dielectric layer and align and bond it into the second groove on the second groove circuit pattern;

[0011] Step 4: Dispose a surface dielectric layer, the surface dielectric layer covers the exposed surfaces of the second silicon-based intermediate layer and the second dielectric layer; dispose a third circuit layer on the surface dielectric layer, so that the third circuit layer passes through the surface dielectric layer and forms an effective electrical connection with the second silicon-based intermediate layer and passes through the surface dielectric layer and the second dielectric layer and forms an effective electrical connection with the second circuit layer;

[0012] Step 5: Separate the intermediate dielectric layer from both the first conductive layer and the second conductive layer to obtain a first packaged substrate structure located on the first conductive layer and a second packaged substrate structure located on the second conductive layer; remove the first conductive layer and the second conductive layer respectively to expose the first circuit layer; dispose a patterned solder mask layer on the surfaces of the first circuit layer and the third circuit layer respectively to expose the portions of the first circuit layer and the third circuit layer that need to be electrically connected.

[0013] Optionally, the method for disposing the first circuit pattern in Step 1 includes:

[0014] Dispose a first photosensitive dry film on both the first conductive layer and the second conductive layer, and perform patterned exposure on the positions of the first photosensitive dry film corresponding to the first circuit pattern and the first alignment pattern;

[0015] Develop the exposed first photosensitive dry film to obtain the patterned first photosensitive dry film;

[0016] Set a first circuit layer on the patterned first photosensitive dry film, and the first circuit layer fills the gaps between the patterned first photosensitive dry films;

[0017] Remove the patterned first photosensitive dry film to obtain the first circuit layer including the first circuit pattern, the first groove, and the first alignment pattern.

[0018] Optionally, the method of aligning and bonding the first silicon-based intermediate layer to the first groove in step 1 is:

[0019] Set a chip bonding film under the first silicon-based intermediate layer, and bond and cure the first silicon-based intermediate layer into the first groove through the chip bonding film; or apply glue dots in the first groove, and bond and cure the first silicon-based intermediate layer into the first groove through the conductive glue layer obtained by applying glue dots; or set an anisotropic conductive film under the first silicon-based intermediate layer, and bond and cure the first silicon-based intermediate layer into the first groove through the conductive film.

[0020] And / or the method of aligning and bonding the second silicon-based intermediate layer to the second groove in step 3 is:

[0021] Set a chip bonding film under the second silicon-based intermediate layer, and bond and cure the second silicon-based intermediate layer into the second groove through the chip bonding film; or apply glue dots in the second groove, and bond and cure the second silicon-based intermediate layer into the second groove through the conductive glue layer obtained by applying glue dots; or set an anisotropic conductive film under the second silicon-based intermediate layer, and bond and cure the second silicon-based intermediate layer into the second groove through the conductive film.

[0022] Optionally, the method of setting the second dielectric layer including the second groove in step 3 is:

[0023] Imprint the pattern of the second groove on a dielectric layer through an imprint template, punch out the second dielectric layer at the position corresponding to the imprinted pattern of the second groove, place the second dielectric layer on the second circuit layer, and perform alignment through the second alignment pattern, so that the position corresponding to the pattern of the second groove where the second dielectric layer is punched out is aligned with the second groove circuit pattern of the second circuit layer, and the second dielectric layer including the pattern of the second groove obtained is the second dielectric layer.

[0024] Optionally, the method of preparing the imprint template is:

[0025] Prepare a pattern on the wafer where only the position corresponding to the second groove is removed; pour polydimethylsiloxane on the pattern of the wafer to fill the voids of the wafer, and remove the wafer to form an imprint template where only the position corresponding to the second groove is not removed;

[0026] Or provide a temporary core plate, and set a second photosensitive dry film on the temporary core plate; expose and develop the second photosensitive dry film to obtain a second photosensitive dry film where only the position corresponding to the second groove is removed; electroplate a copper layer on the second photosensitive dry film to fill the voids of the photosensitive dry film; electroplate a nickel layer on the copper layer, and coat a fluorine-containing coating on the nickel layer; remove the second photosensitive dry film; obtain an imprint template where only the copper layer, nickel layer, and fluorine-containing coating exist at the position corresponding to the second groove.

[0027] Optionally, the method for setting the second dielectric layer including the second groove in step 3 is: set a second dielectric layer on the second circuit layer, perform laser ablation on the second dielectric layer for patterning through a substrate circuit pattern file, and obtain a pattern of the second groove on the second dielectric layer, so as to obtain the second dielectric layer including the pattern of the second groove.

[0028] Optionally, the preparation method for setting the patterned second circuit layer in step 2 is:

[0029] Form the first via posts on the first dielectric layer, and the first via posts penetrate through the first dielectric layer to expose part of the first circuit layer and the first silicon-based intermediate layer; cover a third seed layer on the first dielectric layer, and the third seed layer covers the exposed surface of the first via posts; set a fourth photosensitive dry film on the third seed layer; after exposing and developing the fourth photosensitive dry film, obtain the patterned fourth photosensitive dry film; set a fourth conductive layer in the voids between the patterned fourth photosensitive dry films; remove the fourth photosensitive dry film to obtain the patterned fourth conductive layer; flash-etch the third seed layer exposed between the patterned fourth conductive layers to expose the first dielectric layer under the third seed layer, and the obtained patterned third seed layer and the fourth conductive layer together form the second circuit layer;

[0030] And / or the method for setting the third circuit layer in step 4 is:

[0031] A second hole column is provided on the surface dielectric layer, and the second hole column penetrates through the second dielectric layer to expose a part of the second circuit layer; a fourth seed layer is covered on the surfaces of the second hole column and the surface dielectric layer; a third photosensitive dry film is provided on the surface of the first seed layer, and the third photosensitive dry film is subjected to patterned exposure and development to obtain the patterned third photosensitive dry film; a fifth conductive layer is provided on the patterned third photosensitive dry film, and the fifth conductive layer fills the gaps between the patterned third photosensitive dry films; the patterned third photosensitive dry film is removed to obtain the patterned fifth conductive layer, which is the third circuit layer.

[0032] Optionally, the first alignment pattern and / or the second alignment pattern is a plum blossom hole structure formed by n circles surrounding each other, and the centers of the n circles are located on the contour line of the same circle; or the first alignment pattern and / or the second alignment pattern is a vernier structure in which n rectangles with the same length and different widths are arranged along the length direction, and n is an integer greater than or equal to 2.

[0033] Optionally, steps 3 to 4 are repeated multiple times to obtain the packaging substrate including multiple silicon-based intermediate layers.

[0034] The present invention also provides a packaging substrate, which is obtained by using any one of the above preparation methods.

[0035] As described above, the packaging substrate and its preparation method of the present invention have the following beneficial effects:

[0036] By simultaneously providing each layer structure on both surfaces of a core board, the present invention can double the number of packaging substrate structures prepared in the same time, greatly improving the preparation efficiency of the packaging substrate structure and being beneficial to meeting the requirements of mass production applications in the industry;

[0037] By using the embedded trace substrate (ETS) process to provide the first circuit layer, and by first providing a patterned photosensitive layer and then providing a circuit layer in the gaps of the photosensitive layer pattern, the present invention can obtain finer circuits. The conventional line width / line pitch is 15 μm / 15 μm, and the minimum can be 6 μm / 6 μm, which is beneficial to the application of high-integration and miniaturized packaging substrate structures;

[0038] By using an imprint template to perform imprint stamping to obtain the pattern of the second groove, and at the same time, after a second dielectric layer including the second groove is prepared in advance, it can be directly transferred to the device that needs to be provided with the second dielectric layer, with higher preparation efficiency, faster speed of preparing the second groove, and more accurate setting position of the second groove, so as to improve the circuit alignment accuracy, improve the yield of the device, and at the same time meet the requirements of higher-integration circuits;

[0039] The present invention sets a plum blossom hole and a cursor structure as the alignment structure, making the alignment marks more recognizable and easier to identify, so as to improve the accuracy of preparing the circuit. At the same time, the occupied space is relatively small, which is beneficial to adapting to the miniaturized packaging substrate;

[0040] The present invention improves the accuracy of the circuit on the packaging substrate in various ways, so as to adapt to the setting of the silicon-based intermediate layer with higher integration, realize the packaging substrate with a high-density silicon-based intermediate layer, and is beneficial to meeting the market demand of high integration;

[0041] The present invention sets the roughness of the first circuit layer to ensure that the packaging substrate where the silicon-based intermediate layer is located can achieve the performance of high-speed signal transmission;

[0042] The present invention sets the first silicon-based intermediate layer and the second silicon-based intermediate layer through an anisotropic conductive film, so as to realize a good and firm conductive connection between the silicon-based intermediate layer and the second groove, which is beneficial to improving the reliability of the device. Brief Description of the Drawings

[0043] Figure 1 It shows the structural schematic diagram of the core board provided in step 1 of the preparation method of the packaging substrate of the present invention.

[0044] Figure 2 It shows the structural schematic diagram of the patterned exposure of the first photosensitive dry film in an optional example of step 1 of the preparation method of the packaging substrate of the present invention.

[0045] Figure 3 It shows the structural schematic diagram of the developed patterned first photosensitive dry film in an optional example of step 1 of the preparation method of the packaging substrate of the present invention.

[0046] Figure 4 It shows the structural schematic diagram of setting the first circuit layer in an optional example of step 1 of the preparation method of the packaging substrate of the present invention.

[0047] Figure 5 It shows the structural schematic diagram of removing the first photosensitive dry film in an optional example of step 1 of the preparation method of the packaging substrate of the present invention.

[0048] Figure 6 It shows the structural schematic diagram of laminating the first silicon-based intermediate layer in step 1 of the preparation method of the packaging substrate of the present invention.

[0049] Figure 7 It shows the structural schematic diagram of setting the first dielectric layer in step 2 of the preparation method of the packaging substrate of the present invention.

[0050] Figure 8It shows a schematic structural diagram presented when setting the second circuit layer in step 2 of the method for preparing the packaging substrate of the present invention.

[0051] Figure 9 It shows a schematic structural diagram presented when setting the second dielectric layer in an optional example of step 3 of the method for preparing the packaging substrate of the present invention.

[0052] Figure 10 It shows a schematic structural diagram presented by the second dielectric layer provided with a second groove in step 3 of the method for preparing the packaging substrate of the present invention.

[0053] Figure 11 It shows a schematic structural diagram presented when laminating the second silicon-based intermediate layer in step 3 of the method for preparing the packaging substrate of the present invention.

[0054] Figure 12 It shows a schematic structural diagram of the second dielectric layer with a second groove in an optional example of step 3 of the method for preparing the packaging substrate of the present invention.

[0055] Figure 13 It shows a schematic structural diagram presented when setting the surface dielectric layer in step 4 of the method for preparing the packaging substrate of the present invention.

[0056] Figure 14 It shows a schematic structural diagram presented when setting the third circuit layer in step 4 of the method for preparing the packaging substrate of the present invention.

[0057] Figure 15 It shows a schematic structural diagram presented when separating the intermediate dielectric layer in step 5 of the method for preparing the packaging substrate of the present invention.

[0058] Figure 16 It shows a schematic structural diagram presented when removing the first conductive layer and the second conductive layer in step 5 of the method for preparing the packaging substrate of the present invention.

[0059] Figure 17 It shows a schematic structural diagram presented when setting the solder resist layer in step 5 of the method for preparing the packaging substrate of the present invention.

[0060] Figure 18 It shows a schematic structural diagram presented when flipping the first packaging substrate structure in an optional example of step 5 of the method for preparing the packaging substrate of the present invention.

[0061] Explanation of reference numerals

[0062] 10. Core board; 11. Intermediate dielectric layer; 12. First conductive layer; 121. First seed layer; 13. Second conductive layer; 131. Second seed layer; 14. First photosensitive dry film; 141. Non-exposed area; 15. First circuit layer; 151. First circuit pattern; 152. First groove; 153. First alignment pattern; 16. First silicon-based intermediate layer; 161. Chip bonding film; 162. Conductive adhesive layer; 163. Conductive film; 21. First dielectric layer; 22. Second circuit layer; 221. Second circuit pattern; 222. Second alignment pattern; 223. Second groove circuit pattern; 224. First via post; 23. Second dielectric layer; 231. Second groove; 24. Second silicon-based intermediate layer; 25. Surface dielectric layer; 26. Third circuit layer; 261. Second via post; 262. Fifth conductive layer; 263. Fourth seed layer; 27. Solder mask layer. Detailed implementation manners

[0063] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0064] When detailing the embodiments of the present invention, for ease of explanation, the schematic diagrams showing the device structure will be enlarged locally out of the general proportion, and the schematic diagrams are only examples and should not limit the scope of protection of the present invention here. In addition, in actual production, three-dimensional spatial dimensions including length, width, and depth should be included.

[0065] For convenience of description, spatial relationship terms such as "under", "below", "lower than", "beneath", "above", "on" etc. may be used herein to describe the relationship between one element or feature shown in the drawings and other elements or features. It will be understood that these spatial relationship terms are intended to encompass other directions of the device in use or operation in addition to the directions depicted in the drawings.

[0066] In the context of the present application, the structure where the first feature is "above" the second feature may include embodiments where the first and second features are in direct contact, and may also include embodiments where additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0067] It should be noted that the illustrations provided in this embodiment only schematically illustrate the basic concept of the present invention. Therefore, only the components related to the present invention are shown in the illustrations, rather than being drawn according to the number, shape, and size of the components in actual implementation. The types, quantities, and ratios of the components in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0068] The present invention provides a method for preparing a packaging substrate, and the preparation method includes:

[0069] Step 1: Provide a core board, the core board includes a first conductive layer, an intermediate dielectric layer, and a second conductive layer, and the first conductive layer and the second conductive layer are respectively disposed on two opposite surfaces of the intermediate dielectric layer; a first circuit layer including a first circuit pattern, a first groove, and a first alignment pattern is disposed on both the first conductive layer and the second conductive layer; align and bond a first silicon-based intermediate layer into the first groove;

[0070] Step 2: Dispose a first dielectric layer on the first silicon-based intermediate layer, the first dielectric layer covers the first silicon-based intermediate layer, the first circuit layer, and the exposed surfaces of the first conductive layer and the second conductive layer; dispose a patterned second circuit layer on the first dielectric layer, the second circuit layer includes a second circuit pattern, a second alignment pattern, a second groove circuit pattern, and a first via post, and the first via post penetrates through the first dielectric layer and forms an effective electrical connection with the first circuit layer and the first silicon-based intermediate layer;

[0071] Step 3: Dispose a second dielectric layer including a second groove on the second circuit layer, the second dielectric layer covers the second circuit layer and the exposed surface of the first dielectric layer, and the second groove of the second dielectric layer exposes the second groove circuit pattern; dispose a second silicon-based intermediate layer on the second dielectric layer and align and bond it into the second groove on the second groove circuit pattern;

[0072] Step 4: Dispose a surface dielectric layer, the surface dielectric layer covers the exposed surfaces of the second silicon-based intermediate layer and the second dielectric layer; dispose a third circuit layer on the surface dielectric layer, so that the third circuit layer passes through the surface dielectric layer to form an effective electrical connection with the second silicon-based intermediate layer and passes through the surface dielectric layer and the second dielectric layer to form an effective electrical connection with the second circuit layer;

[0073] Step 5: Separate the intermediate dielectric layer from both the first conductive layer and the second conductive layer to obtain a first package substrate structure located on the first conductive layer and a second package substrate structure located on the second conductive layer; Remove the first conductive layer and the second conductive layer respectively to expose the first circuit layer; Dispose patterned solder resist layers on the surfaces of the first circuit layer and the third circuit layer respectively to expose the portions of the first circuit layer and the third circuit layer that need to be electrically connected.

[0074] The preparation method of the package substrate of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the above order does not strictly represent the order of the preparation method of the package substrate protected by the present invention, and those skilled in the art can make changes according to the actual preparation steps.

[0075] First, perform Step 1. As Figure 1 shown, provide a core board 10, the core board 10 includes a first conductive layer 12, an intermediate dielectric layer 11 and a second conductive layer 13, and the first conductive layer 12 and the second conductive layer 13 are respectively disposed on two opposite surfaces of the intermediate dielectric layer 11; As Figures 2 - 5 shown, a first circuit layer 15 including a first circuit pattern 151, a first groove 152 and a first alignment pattern 153 is disposed on both the first conductive layer 12 and the second conductive layer 13; As Figure 6 shown, align and bond the first silicon-based intermediate layer 16 into the first groove 152.

[0076] In the prior art, when preparing a package structure including a silicon-based intermediate layer, the preparation speed is often slow, only one silicon-based intermediate layer can be prepared at a time, and the preparation efficiency is low. When multiple silicon-based intermediate layers need to be provided, it takes a long time and it is difficult to meet the increasing demand for the use of silicon-based intermediate layers.

[0077] The present invention simultaneously disposes each layer structure on two surfaces of a core board 10, so that the number of package substrate structures prepared can be doubled within the same time, greatly improving the preparation efficiency of the package substrate structure and being conducive to meeting the large-scale production applications in the industry.

[0078] In one embodiment, as Figure 1As shown, the first conductive layer 12 and the second conductive layer 13 are respectively disposed on the surface of the intermediate dielectric layer 11 through the first seed layer 121 and the second seed layer 131. Specifically, when the first conductive layer 12, the second conductive layer 13 and the intermediate dielectric layer 11 are separated subsequently, it is achieved through the separation of the first seed layer 121, the second seed layer 131 from the first conductive layer 12, the second conductive layer 13. Ideally, as shown in the figure, the first seed layer 121 and the second seed layer 131 remain completely connected to the intermediate dielectric layer 11. However, in actual situations, the portions of the first seed layer 121 and the second seed layer 131 connected to the first conductive layer 12 and the second conductive layer 13 may be partially adhered to the first conductive layer 12 and the second conductive layer 13.

[0079] In one embodiment, the first conductive layer 12, the second conductive layer 13, the first seed layer 121, and the second seed layer 131 are all copper foil layers (CCL).

[0080] In one embodiment, the dielectric constant of the first dielectric layer 21 is less than 3.6, and the dielectric loss factor is less than 0.004.

[0081] In one embodiment, the roughness of the first circuit layer 15 is less than 5 micrometers.

[0082] The present invention ensures the performance of high-speed signal transmission of the packaging substrate where the silicon-based intermediate layer is located by setting the roughness of the first circuit layer 15.

[0083] In one embodiment, the method for setting the first circuit pattern 151 in step 1 includes:

[0084] As Figure 2 shown, a first photosensitive dry film 14 is disposed on both the first conductive layer 12 and the second conductive layer 13, and the position of the first photosensitive dry film 14 corresponding to the first circuit pattern 151 and the first alignment pattern 153 is pattern-exposed.

[0085] As Figure 3 shown, the exposed first photosensitive dry film 14 is developed to obtain the patterned first photosensitive dry film 14.

[0086] As Figure 4 shown, a first circuit layer 15 is disposed on the patterned first photosensitive dry film 14, and the first circuit layer 15 fills the gaps between the patterned first photosensitive dry film 14.

[0087] As Figure 5 shown, the patterned first photosensitive dry film 14 is removed to obtain the first circuit layer 15 including the first circuit pattern 151, the first groove 152, and the first alignment pattern 153.

[0088] Specifically, as Figure 2 shown, the non-exposed area 141 is the part that is not exposed during the patterned exposure. Since this part is not exposed, an uncured dry film is obtained, which is easily removed by development. The remaining first photosensitive dry film 14 is the cured dry film part.

[0089] In one embodiment, the first alignment pattern 153 is a plum blossom hole structure formed by n circles surrounding each other, and the centers of the n circles are located on the contour line of the same circle; or the first alignment pattern 153 and / or the second alignment pattern 222 is a vernier structure formed by n rectangles with the same length and different widths arranged along the length direction, where n is an integer greater than or equal to 2.

[0090] In one embodiment, as Figure 6 shown, the method of aligning and bonding the first silicon-based intermediate layer 16 to the first groove 152 in step 1 is as follows:

[0091] A chip bonding film 161 is disposed below the first silicon-based intermediate layer 16, and the first silicon-based intermediate layer 16 is bonded and cured to the first groove 152 through the chip bonding film 161; or dispensing is performed in the first groove 152, and the first silicon-based intermediate layer 16 is bonded and cured to the first groove 152 through the conductive adhesive layer 162 obtained by dispensing; or an anisotropic conductive film 163 is disposed below the first silicon-based intermediate layer 16, and the first silicon-based intermediate layer 16 is bonded and cured to the first groove 152 through the conductive film 163.

[0092] In one embodiment, a plurality of the first grooves 152 are arranged at intervals, and the first silicon-based intermediate layer 16 is disposed in each of the first grooves 152.

[0093] Then, step 2 is performed. As Figure 7 shown, a first dielectric layer 21 is disposed on the first silicon-based intermediate layer 16, and the first dielectric layer 21 covers the surfaces of the first silicon-based intermediate layer 16, the first circuit layer 15, and the exposed first conductive layer 12 and second conductive layer 13; as Figure 8 shown, a patterned second circuit layer 22 is disposed on the first dielectric layer 21. The second circuit layer 22 includes a second circuit pattern 221, a second alignment pattern 222, a second groove circuit pattern 223, and a first via pillar 224. The first via pillar 224 penetrates through the first dielectric layer 21 and forms an effective electrical connection with the first circuit layer 15 and the first silicon-based intermediate layer 16.

[0094] In the prior art, the first circuit layer 15 on the core board 10 is usually set by the subtractive method (Tenting), that is, a metal layer is first set, and then the first circuit layer 15 is obtained by patterning etching through a mask layer or a photosensitive layer. The line width / line pitch obtained by this method is too large, usually 40 microns / 40 microns, and the minimum can only be 20 microns / 20 microns, which does not meet the requirements of fine circuits.

[0095] In the present invention, the first circuit layer 15 is set by using the embedded trace substrate (ETS) process. By first setting a patterned photosensitive layer and then setting a circuit layer in the gaps of the photosensitive layer pattern, a circuit with higher fineness can be obtained. The conventional line width / line pitch is 15 microns / 15 microns, and the minimum can be 6 microns / 6 microns, which is beneficial to the application of a highly integrated and miniaturized package substrate structure.

[0096] In one embodiment, the second alignment pattern 222 is a plum blossom hole structure formed by n circles surrounding each other, and the centers of the n circles are located on the contour line of the same circle; or the first alignment pattern 153 and / or the second alignment pattern 222 is a vernier structure formed by n rectangles with the same length and different widths arranged along the length direction, where n is an integer greater than or equal to 2.

[0097] In the prior art, a single circle or square is usually used as the alignment pattern. In a package substrate with higher and higher integration and circuit precision, such a small and indistinguishable alignment pattern is difficult to accurately identify and is easily mistaken for a conductive circuit, thus making it difficult to play the role of alignment.

[0098] In the present invention, by setting the plum blossom hole and the vernier structure as the alignment structure, the alignment mark is more distinguishable and easy to recognize, so as to improve the precision of preparing the circuit. At the same time, the occupied space is relatively small, which is beneficial to the adaptation of the miniaturized package substrate.

[0099] In one embodiment, the first alignment pattern 153 and / or the second alignment pattern 222 may also be a structure formed by arranging or surrounding multiple triangles, polygons or other irregular shapes, which all fall within the protection scope of the present invention.

[0100] In one embodiment, the preparation method of setting the patterned second circuit layer 22 in step 2 is as follows:

[0101] The first via pillar 224 is formed on the first dielectric layer 21, and the first via pillar 224 penetrates through the first dielectric layer 21 to expose a part of the first circuit layer 15 and the first silicon-based intermediate layer 16; a third seed layer is covered on the first dielectric layer 21, and the third seed layer covers the exposed surface of the first via pillar 224; a fourth photosensitive dry film is disposed on the third seed layer; after the fourth photosensitive dry film is exposed and developed, the patterned fourth photosensitive dry film is obtained; a fourth conductive layer is disposed in the gap between the patterned fourth photosensitive dry films; the fourth photosensitive dry film is removed to obtain the patterned fourth conductive layer; the third seed layer exposed between the patterned fourth conductive layers is etched to expose the first dielectric layer 21 under the third seed layer, and the patterned third seed layer and the fourth conductive layer together form the second circuit layer 22.

[0102] Next, step 3 is performed. As Figure 10 shown, a second dielectric layer 23 including a second groove 231 is disposed on the second circuit layer 22. The second dielectric layer 23 covers the second circuit layer 22 and the exposed surface of the first dielectric layer 21, and the second groove 231 of the second dielectric layer 23 exposes the second groove circuit pattern 223; as Figure 11 shown, a second silicon-based intermediate layer 24 is disposed in the second groove 231 of the second dielectric layer 23 that is aligned and attached to the second groove circuit pattern 223.

[0103] In one embodiment, the method of disposing the second dielectric layer 23 including the second groove 231 in step 3 is: as Figure 9 shown, a second dielectric layer 23 is disposed on the second circuit layer 22, and the second dielectric layer 23 is pattern laser ablated through a substrate circuit pattern file. As Figure 10 shown, a pattern of the second groove 231 is obtained on the second dielectric layer 23, and the second dielectric layer 23 including the pattern of the second groove 231 is obtained.

[0104] In one embodiment, the method of disposing the second dielectric layer 23 including the second groove 231 in step 3 is:

[0105] As Figure 12As shown, the pattern of the second groove 231 is imprinted on a dielectric layer through an imprint template. The second dielectric layer 23 at the position corresponding to the imprinted pattern of the second groove 231 is punched out. The second dielectric layer 23 is placed on the second circuit layer 22 and aligned through the second alignment pattern 222, so that the position of the second dielectric layer 23 corresponding to the punched-out pattern of the second groove 231 is aligned with the second groove circuit pattern 223 of the second circuit layer 22, and the second dielectric layer 23 including the pattern of the second groove 231 is obtained as the second dielectric layer 23.

[0106] In the present invention, the pattern of the second groove 231 is obtained through imprinting and punching with an imprint template. At the same time, after the second dielectric layer 23 including the second groove 231 is prepared in advance, it can be directly transferred to the device where the second dielectric layer 23 needs to be set, with higher preparation efficiency, faster speed of preparing the second groove 231, and more accurate setting position of the second groove 231, so that the line alignment can be improved, the yield of the device can be increased, and it is also applicable to the line requirements of higher integration.

[0107] In one embodiment, the method for preparing the imprint template is as follows:

[0108] A pattern in which only the position corresponding to the second groove 231 is removed is prepared on the wafer; polydimethylsiloxane is poured on the pattern of the wafer to fill the voids of the wafer, and the wafer is removed to form an imprint template in which only the position corresponding to the second groove 231 is not removed;

[0109] Or a temporary core plate is provided, and a second photosensitive dry film is provided on the temporary core plate; the second photosensitive dry film is exposed and developed to obtain a second photosensitive dry film in which only the position corresponding to the second groove 231 is removed; a copper layer is electroplated on the second photosensitive dry film to fill the voids of the photosensitive dry film; a nickel layer is electroplated on the copper layer, and a fluorine-containing coating is coated on the nickel layer; the second photosensitive dry film is removed; an imprint template in which only the copper layer, nickel layer, and fluorine-containing coating exist at the position corresponding to the second groove 231 is obtained.

[0110] Specifically, when the imprint template is prepared by the method of pouring PDMS (polydimethylsiloxane) on the wafer, since the size of the wafer is relatively small, only 8 inches (diameter 200 mm) and 12 inches (diameter 300 mm), the cost of batch preparation is relatively high, but the obtained imprint template has high precision and a flat surface; when the imprint template is prepared by the method of electroplating a metal layer on the temporary core plate, the size can reach 410 mm * 510 mm or 500 mm * 510 mm, the size is larger, and the cost of batch preparation is lower, but the precision of the obtained imprint template is worse than that of the wafer. Those skilled in the art can select a suitable method to prepare the imprint template according to the requirements.

[0111] In one embodiment, the thickness of the temporary core board is greater than 1.0 mm.

[0112] Specifically, the accuracy of the second groove 231 obtained by the method of graphically laser ablating the dielectric layer through a substrate circuit pattern (GERBER) file is not as good as that obtained by imprinting with an imprint template, but the imprint template is not required, saving some processes. Those skilled in the art can select a suitable method according to requirements to prepare the second dielectric layer 23 including the second groove 231.

[0113] In one embodiment, as Figure 11 shown, the method of aligning and bonding the second silicon-based intermediate layer 24 to the second groove 231 in step 3 is as follows:

[0114] A chip bonding film 161 is disposed under the second silicon-based intermediate layer 24, and the second silicon-based intermediate layer 24 is bonded and cured into the second groove 231 through the chip bonding film 161; or glue is applied in the second groove 231, and the second silicon-based intermediate layer 24 is bonded and cured into the second groove 231 through the conductive adhesive layer 162 obtained by applying glue; or an anisotropic conductive film 163 is disposed under the second silicon-based intermediate layer 24, and the second silicon-based intermediate layer 24 is bonded and cured into the second groove 231 through the conductive film 163.

[0115] The present invention sets the first silicon-based intermediate layer 16 and the second silicon-based intermediate layer 24 through the anisotropic conductive film 163, so as to achieve a good and firm conductive connection between the silicon-based intermediate layer and the second groove 231, which is beneficial to improving the reliability of the device.

[0116] In one embodiment, a plurality of the second grooves 231 are arranged at intervals, and the second silicon-based intermediate layer 24 is arranged in each of the second grooves 231.

[0117] In one embodiment, the second dielectric layer 23 is an ABF (Ajinomoto build-up film).

[0118] In one embodiment, after the second dielectric layer 23 is provided, the second dielectric layer 23 is pre-cured to change the ABF film from a glassy state to a viscous flow state, and the preliminary curing makes the obtained structure stable.

[0119] In one embodiment, after the second silicon-based intermediate layer 24 is provided, the second dielectric layer 23 is cured to make the overall structure of the second dielectric layer 23 stable and bonded after the second silicon-based intermediate layer 24 is provided.

[0120] Then, step 4 is performed, as Figure 13As shown, a surface dielectric layer 25 is provided, and the surface dielectric layer 25 covers the exposed surfaces of the second silicon-based intermediate layer 24 and the second dielectric layer 23; as Figure 14 As shown, a third circuit layer 26 is provided on the surface dielectric layer 25, so that the third circuit layer 26 passes through the surface dielectric layer 25 to form an effective electrical connection with the second silicon-based intermediate layer 24 and passes through the surface dielectric layer 25 and the second dielectric layer 23 to form an effective electrical connection with the second circuit layer 22.

[0121] In one embodiment, the method for providing the third circuit layer 26 in step 4 is as follows:

[0122] A second via pillar 261 is provided on the surface dielectric layer 25, and the second via pillar 261 passes through the second dielectric layer 23 to expose a part of the second circuit layer 22; a fourth seed layer 263 is covered on the surfaces of the second via pillar 261 and the surface dielectric layer 25; a third photosensitive dry film is provided on the surface of the first seed layer 121, and the third photosensitive dry film is subjected to patterned exposure and development to obtain the patterned third photosensitive dry film; a fifth conductive layer 262 is provided on the patterned third photosensitive dry film, and the fifth conductive layer 262 fills the gaps between the patterned third photosensitive dry films; the patterned third photosensitive dry film is removed to obtain the patterned fifth conductive layer 262, which is the third circuit layer 26.

[0123] In the present invention, the second circuit layer 22 and the third circuit layer 26 are obtained through a semi-additive (SAP, Semi-Additive Processes) process, that is, the first via pillar 224 and the second via pillar 261 are first provided, and then a patterned photosensitive dry film is provided, and the gaps between the photosensitive dry films are filled with a conductive material to obtain a patterned circuit layer. Its conventional line width / line pitch can reach 15 μm / 15 μm, and the minimum can be 8 μm / 8 μm. Therefore, the obtained circuit accuracy is also less than that of the subtractive method, and it can meet the requirements of higher-integration packaging substrates.

[0124] In one embodiment, the third circuit layer 26 also includes a circuit pattern, a via pillar pattern, and an alignment pattern.

[0125] In one embodiment, the first via pillar 224 and / or the second via pillar 261 are formed by laser drilling.

[0126] In one embodiment, after the first via pillar 224 and / or the second via pillar 261 are formed, a desmear process is performed.

[0127] In one embodiment, the third seed layer and / or the fourth seed layer 263 are obtained by chemical copper plating (PTH, Plated-Through Hole).

[0128] In one embodiment, the fourth conductive layer and / or the fifth conductive layer 262 are obtained by electroplating a copper layer.

[0129] In one embodiment, steps 3 to 4 are repeated multiple times to obtain the encapsulation substrate including multiple silicon-based intermediate layers.

[0130] The present invention improves the accuracy of the encapsulation substrate circuit in various ways, so as to adapt to the setting of the silicon-based intermediate layer build-up with higher integration degree, realize the encapsulation substrate with a high-density silicon-based intermediate layer, and is beneficial to meeting the market demand of high integration degree.

[0131] Finally, perform step 5. As Figure 15 shown, separate the intermediate dielectric layer 11 from both the first conductive layer 12 and the second conductive layer 13 to obtain a first encapsulation substrate structure located on the first conductive layer 12 and a second encapsulation substrate structure located on the second conductive layer 13; as Figure 16 shown, remove the first conductive layer 12 and the second conductive layer 13 respectively to expose the first circuit layer 15; as Figure 17 shown, dispose patterned solder resist layers 27 on the surfaces of the first circuit layer 15 and the third circuit layer 26 respectively to expose the portions of the first circuit layer 15 and the third circuit layer 26 that need to be electrically connected.

[0132] In one embodiment, before removing the first conductive layer 12, flip the first encapsulation substrate structure where the first conductive layer 12 is located by 180° to obtain the first encapsulation substrate structure as Figure 18 shown, so that all encapsulation substrate structures are placed in the same direction, which is convenient for subsequent same batch processes. Specifically, here it is considered that the first encapsulation substrate structure is the side away from the placement container, so when flipping the first encapsulation substrate structure, specifically in operation, flip the encapsulation substrate structure on the side away from the container for placing the device.

[0133] In one embodiment, after separating the intermediate dielectric layer 11 from both the first conductive layer 12 and the second conductive layer 13, perform flash etching on the fourth seed layer 263 exposed between the patterned fifth conductive layers 262 to expose a part of the surface dielectric layer 25 under the fourth seed layer 263.

[0134] The present invention also provides an encapsulation substrate, which is obtained by using any one of the above preparation methods.

[0135] In summary, for the encapsulation substrate and its preparation method of the present invention, by simultaneously performing processes on two surfaces of a core board, twice the number of encapsulation substrates can be formed within the same time, improving the preparation efficiency; meanwhile, an imprinting method is used to obtain a dielectric layer with grooves, improving the preparation precision and speed; in addition, a circuit layer on the core board is prepared by a wire embedding process, improving the line precision; finally, a vernier structure and a plum blossom hole structure are used as alignment structures, improving the alignment precision and efficiency.

[0136] Therefore, the present invention effectively overcomes various drawbacks in the prior art and has high industrial utilization value.

[0137] The above embodiments merely illustrate the principles and effects of the present invention and are not used to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A method for preparing a packaging substrate, characterized in that: The preparation method comprises: Step 1: providing a core board, the core board comprising a first conductive layer, an intermediate dielectric layer and a second conductive layer, the first conductive layer and the second conductive layer being respectively arranged on two oppositely arranged surfaces of the intermediate dielectric layer; a first circuit layer comprising a first circuit pattern, a first groove and a first alignment pattern being arranged on both the first conductive layer and the second conductive layer; aligning and laminating the first silicon-based intermediate layer into the first groove; Step 2: a first dielectric layer is provided on the first silicon-based intermediate layer, the first dielectric layer covers the first silicon-based intermediate layer, the first circuit layer and the exposed surfaces of the first conductive layer and the second conductive layer; a patterned second circuit layer is provided on the first dielectric layer, the second circuit layer includes a second circuit pattern, a second alignment pattern, a second groove circuit pattern and a first hole column, the first hole column penetrates the first dielectric layer and forms an effective electrical connection with the first circuit layer and the first silicon-based intermediate layer; Step 3: a second dielectric layer including a second groove is provided on the second circuit layer, the second dielectric layer covers the second circuit layer and the exposed surface of the first dielectric layer, and the second groove of the second dielectric layer reveals the second groove circuit pattern; a second silicon-based intermediate layer is provided on the second dielectric layer and aligned and attached to the second groove on the second groove circuit pattern; Step 4: providing a surface dielectric layer, wherein the surface dielectric layer covers the second silicon-based intermediate layer and the exposed surface of the second dielectric layer; providing a third circuit layer on the surface dielectric layer, so that the third circuit layer passes through the surface dielectric layer to form an effective electrical connection with the second silicon-based intermediate layer and passes through the surface dielectric layer and the second dielectric layer to form an effective electrical connection with the second circuit layer; Step 5: Separate the intermediate dielectric layer from the first conductive layer and the second conductive layer to obtain a first packaging substrate structure located on the first conductive layer and a second packaging substrate structure located on the second conductive layer; remove the first conductive layer and the second conductive layer respectively to expose the first circuit layer; and set a patterned solder resist layer on the surface of the first circuit layer and the third circuit layer respectively to expose the parts of the first circuit layer and the third circuit layer that need to be electrically connected.

2. The method for preparing a packaging substrate according to claim 1, characterized in that: The method for setting the first line pattern in step 1 includes: Disposing a first photosensitive dry film on both the first conductive layer and the second conductive layer, and performing patterned exposure on the first photosensitive dry film at a position corresponding to the first circuit pattern and the first alignment pattern; developing the first photosensitive dry film after exposure to obtain a patterned first photosensitive dry film; Disposing a first circuit layer on the patterned first photosensitive dry film, wherein the first circuit layer fills the gaps between the patterned first photosensitive dry films; The patterned first photosensitive dry film is removed to obtain the first circuit layer including the first circuit pattern, the first groove and the first alignment pattern.

3. The method for preparing a packaging substrate according to claim 1, characterized in that: The method for aligning and bonding the first silicon-based intermediate layer to the first groove in step 1 is: A chip adhesive film is arranged below the first silicon-based intermediate layer, and the first silicon-based intermediate layer is bonded and cured into the first groove through the chip adhesive film; or glue is dispensed in the first groove, and the conductive glue layer obtained by dispensing the first silicon-based intermediate layer is bonded and cured into the first groove; or an anisotropic conductive film is arranged below the first silicon-based intermediate layer, and the first silicon-based intermediate layer is bonded and cured into the first groove through the conductive film; And / or the method of aligning and bonding the second silicon-based intermediate layer to the second groove in step 3 is: A chip adhesive film is arranged below the second silicon-based intermediate layer, and the second silicon-based intermediate layer is bonded and cured into the second groove through the chip adhesive film; or glue is dispensed in the second groove, and the conductive glue layer obtained by glue dispensing the second silicon-based intermediate layer is bonded and cured into the second groove; or an anisotropic conductive film is arranged below the second silicon-based intermediate layer, and the second silicon-based intermediate layer is bonded and cured into the second groove through the conductive film.

4. The method for preparing a packaging substrate according to claim 1, characterized in that: The method of providing the second dielectric layer including the second groove in step 3 is: The pattern of the second groove is embossed on a dielectric layer by a stamping template, and the second dielectric layer at a position corresponding to the embossed pattern of the second groove is punched out, and the second dielectric layer is placed on the second circuit layer. The second alignment pattern is used for alignment, so that the position corresponding to the pattern of the second groove that is punched out of the second dielectric layer is aligned with the second groove circuit pattern of the second circuit layer, and the second dielectric layer including the pattern of the second groove is obtained as the second dielectric layer.

5. The method for preparing a packaging substrate according to claim 1, characterized in that: The method for preparing the imprint template is: preparing a pattern on a wafer in which only a position corresponding to the second groove is removed; pouring polydimethylsiloxane on the pattern of the wafer to fill the gaps of the wafer, removing the wafer, and forming an imprint template that is not removed except at a position corresponding to the second groove; Or provide a temporary core board, set a second photosensitive dry film on the temporary core board; expose and develop the second photosensitive dry film to obtain a second photosensitive dry film with only the position corresponding to the second groove removed; electroplate a copper layer on the second photosensitive dry film to fill the gaps in the photosensitive dry film; electroplate a nickel layer on the copper layer, and coat a fluorine-containing coating on the nickel layer; removing the second photosensitive dry film; An imprint template is obtained in which the copper layer, the nickel layer and the fluorine-containing coating exist only at the position corresponding to the second groove.

6. The method for preparing a packaging substrate according to claim 1, characterized in that: The method for setting the second dielectric layer including the second groove in step 3 is: setting the second dielectric layer on the second circuit layer, performing patterned laser ablation on the second dielectric layer through the substrate circuit graphic file, obtaining the pattern of the second groove on the second dielectric layer, and obtaining the second dielectric layer including the pattern of the second groove.

7. The method for preparing a packaging substrate according to claim 1, characterized in that: The preparation method of setting the patterned second circuit layer in step 2 is: The first hole column is formed on the first dielectric layer, and the first hole column penetrates the first dielectric layer to expose a part of the first circuit layer and the first silicon-based intermediate layer; the third seed layer is covered on the first dielectric layer, and the third seed layer covers the surface exposed by the first hole column; a fourth photosensitive dry film is arranged on the third seed layer; the fourth photosensitive dry film is exposed and developed to obtain a patterned fourth photosensitive dry film; a fourth conductive layer is arranged in the gaps between the patterned fourth photosensitive dry films; Removing the fourth photosensitive dry film to obtain the patterned fourth conductive layer; flash etching the third seed layer exposed between the patterned fourth conductive layers to expose the first dielectric layer under the third seed layer, and the obtained patterned third seed layer and the fourth conductive layer together constitute the second circuit layer; And / or the method for setting the third circuit layer in step 4 is: A second hole column is set on the surface dielectric layer, and the second hole column passes through the second dielectric layer to expose a portion of the second circuit layer; a fourth seed layer is covered on the surface of the second hole column and the surface dielectric layer; a third photosensitive dry film is set on the surface of the first seed layer, and the third photosensitive dry film is patterned exposed and developed to obtain the patterned third photosensitive dry film; a fifth conductive layer is set on the patterned third photosensitive dry film, and the fifth conductive layer fills the gaps between the patterned third photosensitive dry films; the patterned third photosensitive dry film is removed to obtain the patterned fifth conductive layer, which is the third circuit layer.

8. The method for preparing a packaging substrate according to claim 1, characterized in that: The first alignment pattern and / or the second alignment pattern is a plum blossom hole structure formed by n circles, and the centers of the n circles are located on the contour line of the same circle; or the first alignment pattern and / or the second alignment pattern is a cursor structure in which n rectangles of the same length and different widths are arranged along the length direction, and n is an integer greater than or equal to 2.

9. The method for preparing a packaging substrate according to any one of claims 1 to 8, characterized in that: Steps 3 to 4 are repeated multiple times to obtain the packaging substrate including multiple silicon-based intermediate layers.

10. A packaging substrate, characterized in that: The packaging substrate is obtained by the preparation method described in any one of claims 1-9.

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