Circuits and methods for reducing driving loss in GAN switches

Abstract

The embodiment of the invention relates to a circuit and a method for reducing driving loss in a GAN switch. The half-bridge circuit comprises two GaN high electron mobility transistors (HEMTs). The driver circuit generates a high-side driver signal and a low-side driver signal corresponding to the square wave. The driver dead time is a period between the two driver signals are both low. The half-bridge adjustment circuit is coupled between the driver and the half-bridge circuit and generates a modified high-side driver signal and a modified low-side driver signal, the modified high-side driver signal and the modified low-side driver signal each include a transition from a low voltage to an intermediate voltage during a corresponding dead time, and a transition from the intermediate voltage to a high voltage at the end of the corresponding dead time. The half-bridge adjustment circuit drives a gate terminal of the high-side transistor and a gate terminal of the low-side transistor with the modified high-side driver signal and the modified low-side driver signal.

Description

Technical Field

[0001] The present disclosure relates to a half - bridge circuit including a field - effect high - electron - mobility transistor (HEMT) device and a method of driving the HEMT device. Background Art

[0002] HEMT devices are well - known. In an HEMT device, a conducting channel is based on a layer that forms a two - dimensional electron gas (2DEG) with high mobility at a heterojunction (i.e., at the interface between semiconductor materials with different bandgaps). For example, HEMT devices are known to be based on the heterojunction between an aluminum gallium nitride (AlGaN) layer and a gallium nitride (GaN) layer.

[0003] HEMT devices based on an AlGaN / GaN heterojunction or heterostructure offer a wide range of advantages that make them particularly suitable for and widely used in different applications. For example, the high breakdown threshold of HEMT devices is employed for high - performance power switches; the high electron mobility in the conducting channel allows for the obtaining of high - frequency amplifiers; in addition, the high electron concentration in the 2DEG allows for the obtaining of a low ON - state resistance (R ON on). In addition, HEMT devices for radio - frequency (RF) applications generally offer better RF performance than similar silicon LDMOS devices.

[0004] GaN HEMT devices have become a popular solution for high - power - density and efficient solutions due to their very small size, high switching speed, and low ON - state resistance. GaN reverse conduction (third quadrant) is possible in GaN devices, but it exhibits a higher reverse voltage compared to conventional silicon devices. The high value of this negative voltage may generate high losses.

[0005] All topics discussed in the background art section are not necessarily prior art and should not be assumed to be prior art merely because of the discussion in the background art section. Along these lines, unless explicitly stated as prior art, any recognition of problems in the prior art discussed in the background art section or problems associated with such topics should not be considered prior art. Instead, the discussion of any topic in the background art section should be considered part of the inventor's approach to a particular problem, which itself can also be creative. Summary of the Invention

[0006] Embodiments of the present disclosure provide methods and systems for driving a GaN-based HEMT half-bridge circuit. The method includes modifying a deadtime portion of a driver signal applied to transistors of the half-bridge circuit. Specifically, a half-bridge adjustment circuit receives square-wave driver signals for each transistor of the half-bridge such that there is a short deadtime and the square-wave driver signals are offset from each other, and during the deadtime, both driver signals are low. The half-bridge adjustment circuit generates an adjusted driver signal by adjusting the next rising square-wave signal from a low value to an intermediate value after a first portion of the deadtime. Thus, the adjusted driver signal is low during the first portion of the deadtime and at an intermediate value during the second portion of the deadtime. This helps to reduce losses caused by reverse voltage during the deadtime.

[0007] In one embodiment, the method includes: receiving, at a half-bridge adjustment circuit, a first driver signal corresponding to a square wave, and receiving, at the half-bridge adjustment circuit, a second driver signal corresponding to a square wave. A first deadtime is a period between a falling edge of the second driver signal and a rising edge of the first driver signal. The method includes: using the half-bridge adjustment circuit to generate a first modified driver signal corresponding to the first driver signal, the first modified driver signal having a transition from a low voltage to an intermediate voltage during the first deadtime and a transition from the intermediate voltage to a high voltage at the end of the first deadtime. The method includes: using the first modified driver signal to drive a gate terminal of a first transistor of the half-bridge circuit.

[0008] In one embodiment, a device includes a half-bridge circuit. The half-bridge circuit includes a high-side transistor and a low-side transistor, and the low-side transistor is coupled to the high-side transistor at an intermediate node. The device includes a driver configured to generate a high-side driver signal corresponding to a square wave and a low-side driver signal corresponding to a square wave. A first deadtime is a period between a falling edge of the low-side driver signal and a rising edge of the high-side driver signal. The device includes a half-bridge adjustment circuit coupled between the driver and the half-bridge circuit. The half-bridge adjustment circuit is configured to generate a modified high-side driver signal corresponding to the high-side driver signal, the modified high-side driver signal having a transition from a low voltage to an intermediate voltage during the first deadtime and a transition from the intermediate voltage to a high voltage at the end of the first deadtime. The half-bridge adjustment circuit is configured to use the modified high-side driver signal to drive a gate terminal of the high-side transistor of the half-bridge circuit.

[0009] In one embodiment, the method includes: providing a first square wave from a driver to a half-bridge conditioning circuit, the half-bridge conditioning circuit being coupled between the driver and a half-bridge resonant converter that includes a high-side GaN high electron mobility transistor (HEMT) and a low-side GaN HEMT. The first square wave has a high voltage value corresponding to the on-voltage of the HEMT and a low voltage value corresponding to the off-voltage of the HEMT and having a value less than 0V. The method includes: providing a second square wave from the driver to the half-bridge conditioning circuit. The first square wave and the second square wave have opposite phases, the opposite phases providing a dead time during which both the first square wave and the second square wave are low. The method includes: using the half-bridge conditioning circuit to generate a first corrected square wave in which the dead time is divided into a first part and a second part. The first corrected square wave is at the low voltage value during the first part and at an intermediate voltage during the second part. The method includes: applying the first corrected square wave to the gate terminal of the high-side GaN HEMT. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a block diagram of a system 100 according to one embodiment, the system 100 including a half-bridge circuit and a half-bridge conditioning circuit.

[0011] Figure 2A and Figure 2B is a graph of signals illustrating characteristics associated with operating the half-bridge circuit.

[0012] Figure 3A and Figure 3B is a graph of signals illustrating characteristics associated with operating the half-bridge circuit according to one embodiment.

[0013] Figure 4A is a schematic diagram of a half-bridge conditioning circuit according to one embodiment.

[0014] Figures 4B to 4E is according to one embodiment and Figure 4A is a graph associated with the operation of the half-bridge conditioning circuit.

[0015] Figure 5 is a cross-sectional view of a HEMT according to one embodiment.

[0016] Figure 6 is a flowchart of a method for operating a half-bridge circuit according to one embodiment.

[0017] Figure 7 is a flowchart of a method for operating a half-bridge circuit according to one embodiment. DETAILED DESCRIPTION

[0018] In the following description, in order to provide a thorough understanding of the various disclosed embodiments, certain specific details are set forth. However, those skilled in the relevant art will recognize that the embodiments can be practiced without one or more of these specific details, or with other methods, components, materials, etc. In other instances, well-known systems, components, and circuitry associated with integrated circuits have not been shown or described in detail to avoid unnecessarily obscuring the description of the embodiments.

[0019] Unless the context otherwise requires, throughout the specification and the appended claims, the word "comprising" and its variations, such as "comprises" and "comprising," shall be interpreted in an open, inclusive sense, i.e., "including but not limited to." Additionally, unless the context clearly dictates otherwise, the terms "first," "second," and similar sequential indicators shall be construed as interchangeable.

[0020] Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Moreover, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0021] Unless the context clearly dictates otherwise, as used in this specification and the appended claims, the singular forms "a," "an," and "the" include plural referents. It should also be noted that, unless the context clearly dictates otherwise, the term "or" is generally used in its broadest sense, i.e., the meaning of "and / or."

[0022] Figure 1 is a block diagram of a half-bridge system 100 according to one embodiment. The half-bridge system 100 includes a half-bridge circuit 102, a driver 104, and a half-bridge regulation circuit 106. As will be elaborated in more detail below, the half-bridge regulation circuit 106 and the driver 104 cooperate to effectively drive the half-bridge circuit 102 in a power-efficient manner.

[0023] The half-bridge circuit 102 includes a first transistor S1 and a second transistor S2. The first transistor S1 includes a drain terminal coupled to a supply voltage Vbus, a gate terminal coupled to the half-bridge regulation circuit 106, and a source terminal coupled to a half-bridge node HB. The second transistor S2 includes a drain terminal coupled to the half-bridge node HB, a gate terminal coupled to the half-bridge regulation circuit 106, and a source terminal coupled to ground. Thus, the transistors S1 and S2 are coupled together in a half-bridge configuration.

[0024] In one embodiment, transistors S1 and S2 are HEMT devices. In one embodiment, transistors S1 and S2 are GaN-based HEMT devices. The use of GaN HEMT devices provides several benefits. For example, GaN HEMT devices can enable high-frequency operation at high voltages (e.g., 600V or higher between terminals) with low power consumption. More details regarding the structure of the GaN HEMT devices are provided with respect to Figure 5 to provide.

[0025] In one embodiment, driver 104 provides a first square wave signal for driving the gate terminal of transistor S1 and a second square wave signal for driving the gate terminal of transistor S2. It is beneficial to ensure that transistors S1 and S2 never conduct simultaneously. Therefore, driver 104 generates the first and second square waves with opposite phases, and the opposite phases provide a dead time within each half cycle. The dead time corresponds to the period during which both square wave signals are low.

[0026] However, power losses may occur during the dead time period. Specifically, in some scenarios, there is a reverse conduction time associated with each HEMT device of the half-bridge circuit.

[0027] During the reverse conduction time, there may be a reverse voltage value V SD , and the reverse voltage value V SD corresponds to the source voltage minus the drain voltage. The reverse voltage value V SD can be given by the following formula:

[0028] V SD = V gs(th) – V gs(off), ,

[0029] where Vgs(th) is the gate threshold voltage and Vgs(off) is the off voltage applied to the gate terminal of the transistor to turn off the transistor.

[0030] In one embodiment, the gate threshold Vgs(th) is between 1V and 2.6V. The off voltage Vgs(off) can be between -3V and -10V. Other voltages can be used without departing from the scope of the present disclosure. It can be seen that the off voltage Vgs(off) is negative. The negative value of Vgs(off) may be beneficial for faster and more robust turn-off in terms of noise immunity. This may result in V SD reaching a relatively high value. Although GaN HEMT devices have reverse conduction capabilities, the resulting power losses limit the advantages compared to standard MOS technologies. The power loss Preverse during reverse conduction can be given by the following formula:

[0031] P reverse = V SD × I av × Tr × f sw ,

[0032] where Iav is the average reverse conduction current, Tr is the duration of the reverse time, and fsw is the switching frequency.

[0033] In an example of a 250 W half - bridge dwell converter based on GaN, V SD can be 8.6 V, Iav can be 2 A, the reverse time Tr can be 200 ns, and the switching frequency fsw can be 250 kHz. This results in a reverse power loss Preverse of 0.86 W. If the frequency is increased to 1 MHz, the loss becomes 3.44 W.

[0034] Before describing the function of the half - bridge adjustment circuit 106, it is beneficial to discuss the voltages and currents associated with the operation of the half - bridge circuit without the need to adjust the square wave provided by the driver 104 as shown in Figure 2A and Figure 2B .

[0035] Figure 2A Graph 200 includes a first square wave 210 and a second square wave 212, which are respectively applied to the gate terminal of switch S1 and the gate terminal of switch S2 without correction. Each of the square waves 210 and 212 stays between a low value Vgs(off) and a high value Vgs(on). The phase shift of the square waves 210 and 212 is such that there is a dead time between t1 and t2, between t3 and t4, between t5 and t6, and between t7 and t8.

[0036] Graph 202 illustrates the currents 214 and 216 flowing through transistors S1 and S2 respectively. It can be seen from Graph 202 that there is a negative current flowing during the dead time before the next rising edge of the corresponding square wave. For example, during the dead time before the rising edge of the square wave 212 of transistor S2, the current 216 has a negative value corresponding to the reverse conduction current. During the dead time before the rising edge of the square wave 210, the current 214 has a negative value corresponding to the reverse conduction current of transistor S1.

[0037] Graph 204 illustrates the drain voltage 218 and the drain current 216 of transistor S2. During the dead time before the rising edge 212, the drain voltage V SD has a negative value, resulting in a reverse conduction current. Outside of these dead times, the drain voltage 218 has a value of 0 V or a high voltage value HV. Graph 204 also illustratesFigure 2B The enlarged portion 206 in. The portion 206 corresponds to the dead time between times t7 and t8 before the rising edge of the second square wave signal 212.

[0038] In Figure 2B In, graph 206 illustrates the drain voltage of transistor S2. Graph 207 illustrates the power loss Preverse associated with the reverse conduction time of transistor S2. It can be seen that the drain voltage of transistor S2 drops from the high voltage value HV to the negative voltage value V at time T7 2SD . Graph 206 illustrates the threshold V2gs(th) and the turn-off voltage value V2gs(off) of transistor S2. This results in a relatively high power loss during the reverse conduction time.

[0039] Returning to Figure 1 , embodiments of the present disclosure reduce reverse power loss by implementing the half-bridge adjustment circuit 106. Specifically, the driver 104 provides a first square wave and a second square wave to the half-bridge adjustment circuit 106. The half-bridge adjustment circuit 106 generates adjusted driver signals and supplies them to the gate terminals of transistors S1 and S2 to drive transistors S1 and S2.

[0040] In one embodiment, the half-bridge adjustment circuit 106 includes a high-side adjustment circuit 108 that generates a high-side adjusted driver signal based on the first square wave signal and applies the high-side adjusted driver signal to the gate terminal of the high-side transistor S1. The half-bridge adjustment circuit 106 includes a low-side adjustment circuit 110 that generates a low-side adjusted driver signal based on the second square wave signal and applies the low-side adjusted driver signal to the gate terminal of the low-side transistor S2.

[0041] The half-bridge adjustment circuit 106 operates by dividing each dead time dt into a first dead time portion dt1 and a second dead time portion dt2. For the dead time before the rising edge of the first square wave 210, the adjusted high-side driver signal is at a low voltage value during the first dead time portion dt1. However, at the start of the second dead time portion dt2, the adjusted high-side driver signal transitions to an intermediate voltage between the low voltage and the high voltage. Similarly, for the dead time before the rising edge of the second square wave 212, the adjusted high-side driver signal is at a low voltage value during the first dead time portion dt1. However, at the start of the second dead time portion dt2, the adjusted high-side driver signal transitions to an intermediate voltage between the low voltage and the high voltage. As will be elaborated in more detail below, this greatly reduces the reverse conduction power loss.

[0042] For the following discussion regarding the adjusted drive signals, the dead time before the rising edge of the first square wave 210 will be referred to as the first dead time. The dead time before the rising edge of the second square wave 212 will be referred to as the second dead time. Each first dead time has a first dead time portion dt1 and a second dead time portion dt2. Each second dead time has a first dead time portion dt1 and a second dead time portion dt2.

[0043] Figure 3A Including graph 300 which illustrates the high-side adjusted drive signal 310 and the low-side adjusted drive signal 312. There is a first dead time between time t1 and t3 and between time t7 and t8. There is a second dead time between t4 and t6 and between t10 and t12.

[0044] For the first dead time between time t1 and t3, there is a first dead time portion between time t1 and t2. There is a second dead time portion between time t2 and t3. For the first dead time portion dt1, the high-side adjusted drive signal 310 has a low value of -Vgs(off). For the second dead time portion dt2 between time t2 and t3, the high-side adjusted drive signal 310 has an intermediate value. In one example, the intermediate value can be approximately 0V, or slightly less than 0V. The low-side adjusted drive signal 312 is at a low value during the first dead time between time t1 and t3. The signals for other first dead times are the same.

[0045] For the second dead time between time t4 and t6, there is a first dead time portion between time t4 and t5. There is a second dead time portion between time t5 and t6. For the first dead time portion dt1, the low-side adjusted drive signal 312 has a low value of -Vgs(off). For the second dead time portion dt2 between time t5 and t6, the low-side adjusted drive signal 312 has an intermediate value. The high-side adjusted drive signal 310 is at a low value during the second dead time between time t4 and t6. The signals for other second dead times are the same.

[0046] Graph 302 illustrates the drain currents 314 and 316 associated with transistors S1 and S2 when receiving the adjusted drive signals 310 and 312. The overall form of the drain currents 314 and 316 is substantially similar to the overall form of the drain currents 214 and 216. However, as will be elaborated in more detail below, there is reduced power loss during the reverse conduction time.

[0047] The graph 304 illustrates the drain voltage 318 and the drain current 316 of the transistor S2. During the first dead time portion dt1 of the second dead time before the rising edge 312, the drain voltage V SD has a negative value. During the second dead time portion dt2 of the second dead time before the rising edge 312, the drain voltage has a value approximately equal to zero. Outside of these dead times, the drain voltage 218 has a value of 0V or a high voltage value HV. The graph 304 also illustrates Figure 3B an enlarged portion 306. The portion 306 corresponds to the dead time between times t10 and t12 before the rising edge of the low-side adjusted driver signal 312.

[0048] At Figure 3B , the graph 306 illustrates the drain voltage of the transistor S2. The graph 307 illustrates the power loss Preverse associated with the reverse conduction time of the transistor S2. It can be seen that the drain voltage of the transistor S2 drops from the high voltage value HV to the negative voltage value V 2SD at time T10 and remains there within the first dead time portion dt1. When transitioning to the second dead time portion dt2, the drain voltage becomes an intermediate value for the remainder of the second dead time portion dt2. As a result, during the second dead time portion, as can be seen in the graph 307, the power loss is greatly reduced. This is because the magnitude of the source-to-drain voltage has decreased. Since the reverse power loss is a factor of both the average current and the source-to-drain voltage, the reduced source-to-drain voltage results in a reduced power loss. The portion 313 of the graph 307 corresponds to the power loss. The portion 311 illustrates the power consumption savings compared to the scheme shown in Figure 2B .

[0049] Although Figure 3A illustrates that the first dead time portion dt1 is substantially equal to the second dead time portion dt2, in practice, it may be beneficial for the second dead time portion dt2 to be longer than the first dead time portion dt1. This can result in a further reduction in power loss. In one embodiment, the second dead time portion dt2 is twice as long as the first dead time portion dt1. In one embodiment, the second dead time portion dt2 is more than three times as long as the first dead time portion dt1.

[0050] Although Figure 3AIt has been illustrated that the value of the adjusted drive signal has a step at the interface between dt1 and dt2. However, in reality, there can be multiple steps, in which the adjusted drive signal transitions to multiple different intermediate voltage values before becoming high at the end of the dead time. Additionally, the adjusted drive signal can have a linear increase or a non-linear but continuous increase instead of a step. Various waveforms can be used for the adjusted drive signal without departing from the scope of the present disclosure.

[0051] Figure 4A is a schematic diagram of the high-side adjustment circuit 108 of the half-bridge adjustment circuit 106 according to an embodiment. Figure 4A The high-side adjustment circuit 108 is Figure 1 an example of the high-side adjustment circuit 108. The high-side adjustment circuit 108 includes a reverse time generator 120, a first dead-time portion generator 122, a second dead-time portion generator 124, an actuator 126, and a portion 128 corresponding to the high-side transistor S1. Although not shown, the low-side adjustment circuit 106 can have a design substantially similar to that of the high-side adjustment circuit 108.

[0052] The reverse time generator 120 includes a comparator 130 that receives a reference voltage from the non-inverting terminal and a low-side square wave signal from the driver 104 and the inverting terminal. The reverse time generator 120 includes a comparator 132 that receives a high-side square wave signal from the driver 104 and the inverting terminal and a reference voltage from the non-inverting terminal. The reverse time generator 120 includes a NOR (not OR) gate 134 that has a first input coupled to the output of the comparator 130 and a second input coupled to the output of the comparator 132.

[0053] The first dead-time portion generator 122 includes a comparator 136. A resistor R1 is coupled between the output of the NOR gate 134 and the non-inverting input of the comparator 136. A capacitor C1 is coupled between ground and the non-inverting input of the comparator 136. The inverting input of the comparator 136 is coupled to the reference voltage. The resistor R1 and the capacitor C1 correspond to a low-pass RC filter.

[0054] The second dead time portion generator 124 includes an AND gate 138 having a first input coupled to the output of the NOR gate 134. A resistor R3 is coupled between the output of the comparator 136 and the second input of the AND gate 138. A switch S3 is coupled between the second input of the AND gate 138 and ground. A resistor R2 is coupled between the output of the comparator 132 and the control terminal of the switch S3. A second capacitor C2 is coupled between ground and the control terminal of the switch S3. The resistor R2 and the capacitor C2 form an RC filter that controls the switch S3.

[0055] The actuator 126 includes a switch S4 that is coupled between ground and the gate terminal of the transistor S1. The control terminal of the switch S4 is coupled to the output of the AND gate 138 such that the AND gate 138 controls the opening and closing of the switch S4. A resistor R4 is coupled between the output of the comparator 132 and the gate terminal of the transistor S1.

[0056] The function of the high-side regulation circuit 108 can be understood with respect to a graph associated with, as will be described in more detail below, Figures 4B to 4E which is associated with the graph.

[0057] Figure 4B FIG. 400 illustrates a graph according to one embodiment, where graph 400 illustrates square waves 210 and 212 provided by the driver 204 to the reverse time generator 120. The reverse time signal 402 is the output of the NOR gate 134. Thus, when the outputs of the comparators 130 and 132 are low, the output of the NOR gate 134 is high. Thus, when the first and second square waves are low, the reverse time signal 402 is high.

[0058] Figure 4C FIG. 410 illustrates a graph associated with the first dead time portion generator 122 according to one embodiment. Figure 4C Illustrated are the first square wave 210 and the second square wave 212, the reverse time signal 402, and the first dead time portion signal 412. The comparator 136 receives the reverse time signal from the output of the NOR gate 134 via the RC filter of R1 and C1. The first dead time portion signal 412 is delayed by the RC circuit of R1 and C1 compared to the threshold of the comparator 136. The comparator 136 outputs the first dead time portion signal 412. The first dead time portion corresponds to the time between the rising edge of the reverse time signal 402 at time t1 and the rising edge of the first dead time portion signal 412 at time t2.

[0059] Figure 4DFIG. 420 associated with the second dead time portion generator 124 according to one embodiment is illustrated. FIG. 420 illustrates a first square wave signal 210 and a second square wave signal 212, a reverse time signal 402, and a second dead time portion signal 422. The second dead time portion signal 422 is generated as the output of the AND gate 138 and is based on the reverse time signal 402, the first dead time portion signal 412, and the high-side square wave signal via the switch S3. Note that the second dead time portion is high only during the second dead time portion of the dead time before the rising edge of the high-side square wave signal 210. The second dead time portion signal does not go high during the second dead time between time t4 and t5.

[0060] Figure 4E FIG. 430 associated with the actuator 126 of the high-side adjustment circuit 108 according to one embodiment is illustrated. Specifically, the output of the switch S4 is the high-side adjustment signal 310 based on the second dead time portion signal 422. The first dead time portion dt1 is between time t1 and t2. The second dead time portion is between time t2 and t3 when the second dead time portion signal 422 is high. The high-side adjustment signal 310 is at an intermediate value between time t2 and t3.

[0061] The low-side adjustment signal 312 can be generated in substantially the same manner as the high-side adjustment signal 310.

[0062] Figure 5 is a cross-sectional view of an integrated circuit including a GaN HEMT S1 according to some embodiments. The HEMT S1 is an example of the transistor S1. Although the HEMT S2 is not shown, the HEMT S2 can have substantially the same structure as the HEMT S1. Figures 1 to 4E

[0063] According to one embodiment, the integrated circuit includes a substrate 502. The substrate 502 can include a semiconductor material. In one embodiment, the substrate 502 includes silicon. However, the substrate 502 can include other types of semiconductor materials or crystals, such as sapphire, silicon carbide, aluminum nitride. In some embodiments, the substrate 502 can include one or more layers of dielectric material. The substrate 502 can include other materials suitable for forming HEMTs.

[0064] ​According to one embodiment, an integrated circuit includes a stack 504 of layers. The stack 504 of layers is grown epitaxially from a substrate 502. By in-situ adjusting the parameters of the epitaxial growth process, individual layers can be formed. For example, the epitaxial growth process can include flowing one or more gases or other materials into a deposition chamber in which the integrated circuit (which is part of a semiconductor wafer at this stage) is positioned. The temperature, pressure, and materials can be adjusted throughout the epitaxial growth process to form the individual layers of the stack 504. In some cases, when one layer of the stack 504 is complete, a purging process can be performed to remove any excess gases or by-products from the deposition chamber before the next layer begins to grow.

[0065] In one embodiment, the stack 504 includes a layer 506 on the substrate 502. In one embodiment, the layer 506 includes aluminum nitride. The aluminum nitride layer 506 can be formed as a precursor for forming a plurality of gallium nitride layers. Aluminum nitride can be selected as the first layer because, especially when the substrate 502 includes silicon, gallium can damage the substrate 502. Thus, the epitaxial growth process first forms the layer 506 of aluminum nitride so that the layers of gallium nitride can be formed subsequently. Alternatively, other materials can be used for the layer 506 and subsequent layers without departing from the scope of the present disclosure.

[0066] The stack 504 includes a superlattice 508 formed on the layer 506 during the epitaxial growth process. The superlattice 508 is Figure 5 illustrated as a single layer in. However, in practice, the superlattice 508 can include a large number of layers. In an example where the layer 506 is aluminum nitride and subsequent layers of gallium nitride are to be formed, the first layer of the superlattice 508 can include a layer of aluminum gallium nitride with a relatively high percentage of aluminum and a relatively low percentage of gallium to enable epitaxial growth from the layer of aluminum nitride. Subsequent layers of the superlattice 508 include aluminum gallium nitride with an increasing concentration of gallium and a decreasing concentration of aluminum. Finally, the top layer of the superlattice 508 can include gallium nitride without any aluminum. The superlattice 508 can include up to 200 layers. The superlattice 508 can include other materials and structures without departing from the scope of the present disclosure.

[0067] The stack includes a layer 510 located above the superlattice 508. In an example where the superlattice 508 is a transition structure including a plurality of layers gradually transitioning from aluminum nitride to gallium nitride, the layer 510 can include gallium nitride. The combination of the layer 510 and the layer 508 can contribute to forming a HEMT device capable of operating at very high voltages. For example, the combination of the layer 510 and the layer 508 can contribute to the HEMT device operating when the voltage between the terminals of the HEMT device exceeds 600V. Other materials, thicknesses, and operating voltages can be used without departing from the scope of the present disclosure.

[0068] The back barrier layer 512 is on the layer 510. In an example where the layer 510 includes carbon-doped gallium nitride, the back barrier layer 512 can include gallium nitride. The gallium nitride back barrier layer 512 can be doped with a selected dopant species. The thickness of the back barrier layer 512 can be between 50 nm and 300 nm.

[0069] The stack includes a channel layer 518 on the back barrier layer 512. In one embodiment, the channel layer 518 is gallium nitride and has a thickness between 50 nm and 150 nm. In one embodiment, the channel layer 518 is intrinsic gallium nitride and does not include any doping. The channel layer 518 can correspond to the layer that forms an electron gas during the operation of the transistor. As will be elaborated in more detail below, free electrons flow through the channel region based on the bias between the source electrode and the drain electrode and the control voltage applied to the gate electrode. The channel layer can have other materials and thicknesses without departing from the scope of the present disclosure.

[0070] In one embodiment, the stack includes a barrier layer 520 on the channel layer 518. The barrier layer 520 can include aluminum gallium nitride. The percentage of aluminum can be between 15% and 30%, but other combinations can be used without departing from the scope of the present disclosure. The barrier layer 520 can have a thickness between 30 nm and 70 nm. Other combinations and thicknesses can be used for the barrier layer 520 without departing from the scope of the present disclosure.

[0071] In one embodiment, a dielectric cap layer 522 is positioned on the barrier layer 520. The dielectric cap layer 522 can include silicon nitride and can have a thickness between 20 nm and 50 nm. Other materials and thicknesses can be used without departing from the scope of the present disclosure.

[0072] According to one embodiment, the transistor S1 includes a gate electrode 528. The gate electrode 528 can include a gate dielectric 530 and a gate metal 532. The gate dielectric 530 contacts the sidewalls of the back barrier layer 512, the layer 518, the layer 520, and the layer 522, and the top surface of the layer 522. The gate dielectric 530 can include alumina or other suitable materials, such as AlN, SiN, SiO2.

[0073] The gate metal 532 fills the remainder of the gate recess. Specifically, the gate metal 532 contacts the gate metal 532 and is located on top of the dielectric cap layer 522. The gate metal 532 can include tungsten and can be deposited by PVD, ALD, CVD, or other suitable deposition processes. The gate metal 532 can include other materials and configurations without departing from the scope of the present disclosure. For example, although the gate metal 532 is shown as a single gate metal, in fact, there can be multiple gate metals.

[0074] According to one embodiment, the transistor S1 includes a source electrode 534 and a drain electrode 536. The source electrode 534 and the drain electrode 536 may be formed after the gate electrode 528 is formed. Specifically, a lithography process may be performed to form trenches that partially extend into the channel layer 518. The source / drain metal may then be deposited and patterned to form the source electrode 534 and the drain electrode 536. The source / drain metal may include TiAl, TaAl, Au, or other suitable conductive materials. The source / drain metal may be deposited by PVD, ALD, CVD, or other suitable deposition processes. As can be seen, the source electrode 534 is closer to the gate electrode 528 than the drain electrode 536. This is beneficial for the electrical function of the HEMT S1.

[0075] The HEMT S1 may include various other layers, and the various other layers include a passivation layer and other dielectric layers to isolate and protect the source / drain metal in the gate electrode 528. The HEMT may be operated by applying a control voltage to the gate electrode 528 and biasing the source electrode 534 and the drain electrode 536. Depending on the control voltage and the bias voltage, the HEMT may be turned on or off. When the HEMT is turned on, the current of the electron gas may flow through the channel layer 518 and flow under the bottom of the gate electrode 528 between the drain electrode 536 and the source electrode 534.

[0076] Figure 6 is a flowchart of a method 600 according to one embodiment. The method 600 may utilize the components, processes, systems, and structures illustrated and described with respect to the above. At 602, the method 600 includes receiving a first driver signal corresponding to a square wave at a half-bridge adjustment circuit. At 604, the method 600 includes receiving a second driver signal corresponding to a square wave at the half-bridge adjustment circuit, wherein a first dead time is a period between the falling edge of the second driver signal and the rising edge of the first driver signal. At 606, the method 600 includes generating, using the half-bridge adjustment circuit, a first corrected driver signal corresponding to the first driver signal, the first corrected driver signal having a transition from a low voltage to an intermediate voltage during the first dead time and a transition from the intermediate voltage to a high voltage at the end of the first dead time. At 608, the method 600 includes driving a gate terminal of a first transistor of a half-bridge circuit using the first corrected driver signal.

[0077] Figure 7is a flowchart of a method 700 according to one embodiment. Method 700 may utilize the components, processes, systems, and structures illustrated and described with respect to the foregoing. At 702, method 700 includes providing a first square wave from a driver to a half-bridge adjustment circuit, the half-bridge adjustment circuit being coupled between the driver and a half-bridge resonant converter that includes a high-side GaN high electron mobility transistor (HEMT) and a low-side GaN HEMT, the first square wave having a high voltage value corresponding to the on-voltage of the HEMT and a low voltage value corresponding to the off-voltage of the HEMT and having a value less than 0V. At 704, method 700 includes providing a second square wave from the driver to the half-bridge adjustment circuit, the first square wave and the second square wave having opposite phases, the opposite phases providing a dead time, both the first square wave and the second square wave being low during the dead time. At 706, method 700 includes using the half-bridge adjustment circuit to generate a first corrected square wave in which the dead time is divided into a first portion and a second portion, the first corrected square wave being at the low voltage value during the first portion and at an intermediate voltage during the second portion. At 708, method 700 includes applying the first corrected square wave to the gate terminal of the high-side GaN HEMT.

[0078] In one embodiment, the method includes receiving, at a half-bridge adjustment circuit, a first driver signal corresponding to a square wave, and receiving, at the half-bridge adjustment circuit, a second driver signal corresponding to a square wave. A first dead time is a period between a falling edge of the second driver signal and a rising edge of the first driver signal. The method includes using the half-bridge adjustment circuit to generate a first corrected driver signal corresponding to the first driver signal, the first corrected driver signal having a transition from a low voltage to an intermediate voltage during the first dead time and a transition from the intermediate voltage to a high voltage at the end of the first dead time. The method includes using the first corrected driver signal to drive a gate terminal of a first transistor of a half-bridge circuit.

[0079] In one embodiment, the half-bridge adjustment circuit and the driver are implemented in the same integrated circuit die as the half-bridge circuit.

[0080] In one embodiment, the driver is implemented in an integrated circuit, and the half-bridge adjustment circuit is coupled between the integrated circuit and the half-bridge circuit.

[0081] In one embodiment, the second dead time is the period between the falling edge of the first driver signal and the rising edge of the second driver signal. The method includes using a half-bridge adjustment circuit to generate a second corrected driver signal corresponding to the second driver signal, the second corrected driver signal having a transition from a low voltage to an intermediate voltage during the second dead time, and a transition from the intermediate voltage to a high voltage at the end of the second dead time. The method includes using the second corrected driver signal to drive the gate terminal of the second transistor of the half-bridge circuit.

[0082] In one embodiment, the method includes using a half-bridge adjustment circuit to generate a dead time signal that has a high logic level during the first dead time and during the second dead time, and a low logic level outside the first dead time and the second dead time.

[0083] In one embodiment, the method includes using a half-bridge adjustment circuit to generate a first dead time control signal. The first dead time control signal includes a first transition during the first dead time and a second transition at the end of the first dead time.

[0084] In one embodiment, the first corrected driver signal transitions to the intermediate voltage in response to the first transition of the first dead time control signal. The first corrected driver signal transitions to the high voltage in response to the second transition of the first dead time control signal.

[0085] In one embodiment, the method includes using a half-bridge adjustment circuit to generate a second dead time control signal. The second dead time control signal includes a first transition during the second dead time and a second transition at the end of the second dead time.

[0086] In one embodiment, the second corrected driver signal transitions to the intermediate voltage in response to the first transition of the second dead time control signal. The second corrected driver signal transitions to the high voltage in response to the second transition of the second dead time control signal.

[0087] In one embodiment, the low voltage level is less than 0V and the intermediate voltage is 0V.

[0088] In one embodiment, the first transistor is a GaN transistor.

[0089] In one embodiment, the device includes a half-bridge circuit. The half-bridge circuit includes a high-side transistor and a low-side transistor, and the low-side transistor is coupled to the high-side transistor at an intermediate node. The device includes a driver configured to generate a high-side driver signal corresponding to a square wave and a low-side driver signal corresponding to the square wave. A first dead time is a period between a falling edge of the low-side driver signal and a rising edge of the high-side driver signal. The device includes a half-bridge adjustment circuit coupled between the driver and the half-bridge circuit. The half-bridge adjustment circuit is configured to generate a corrected high-side driver signal corresponding to the high-side driver signal, the corrected high-side driver signal having a transition from a low voltage to an intermediate voltage during the first dead time and a transition from the intermediate voltage to a high voltage at the end of the first dead time. The half-bridge adjustment circuit is configured to drive a gate terminal of the high-side transistor of the half-bridge circuit using the corrected high-side driver signal.

[0090] In one embodiment, the device includes an integrated circuit. The driver and the half-bridge adjustment circuit are implemented in the integrated circuit.

[0091] In one embodiment, the device includes a circuit board and an integrated circuit. The integrated circuit includes a driver. The integrated circuit, the half-bridge adjustment circuit, and the half-bridge circuit are mounted on the circuit board.

[0092] In one embodiment, a second dead time is a period between a falling edge of a first driver signal and a rising edge of a second driver signal. The half-bridge adjustment circuit is configured to generate a corrected low-side driver signal corresponding to the low-side driver signal, the corrected low-side driver signal having a transition from a low voltage to an intermediate voltage during the second dead time and a transition from the intermediate voltage to a high voltage at the end of the second dead time. The half-bridge adjustment circuit is configured to drive a gate terminal of the low-side transistor using the corrected low-side driver signal.

[0093] In one embodiment, the half-bridge adjustment circuit is configured to generate a dead time signal having a high logic level during the first dead time and during the second dead time and a low logic level outside the first dead time and the second dead time. The half-bridge adjustment circuit is configured to generate a first dead time control signal including a first transition during the first dead time and a second transition at the end of the first dead time.

[0094] In one embodiment, the half-bridge adjustment circuit is configured to generate a second dead time control signal including a first transition during the second dead time and a second transition at the end of the second dead time. The second corrected driver signal transitions to the intermediate voltage in response to the first transition of the second dead time control signal. The second corrected driver signal transitions to the high voltage in response to the second transition of the second dead time control signal.

[0095] In one embodiment, the method includes providing a first square wave from a driver to a half-bridge conditioning circuit coupled between the driver and a half-bridge resonant converter including a high-side GaN high electron mobility transistor (HEMT) and a low-side GaN HEMT. The first square wave has a high voltage value corresponding to the on-voltage of the HEMT and a low voltage value corresponding to the off-voltage of the HEMT and having a value less than 0V. The method includes providing a second square wave from the driver to the half-bridge conditioning circuit. The first square wave and the second square wave have opposite phases, the opposite phases providing a dead time during which both the first square wave and the second square wave are low. The method includes using the half-bridge conditioning circuit to generate a first corrected square wave in which the dead time is divided into a first portion and a second portion. The first corrected square wave is at the low voltage value during the first portion and at an intermediate voltage during the second portion. The method includes applying the first corrected square wave to the gate terminal of the high-side GaN HEMT.

[0096] In one embodiment, the method includes using the half-bridge conditioning circuit to generate a second corrected square wave in which the dead time is divided into a first portion and a second portion. The second corrected square wave is at the low voltage value during the first portion and at an intermediate voltage during the second portion. The method includes applying the second corrected square wave to the gate terminal of the low-side GaN HEMT.

[0097] In one embodiment, the half-bridge conditioning circuit includes a NOR gate configured to receive the first square wave, a comparator coupled to the output of the NOR gate, an AND gate coupled to the output of the NOR gate, and a switch coupled between the AND gate and the gate terminal of the high-side GaN HEMT.

[0098] The various embodiments described above can be combined to provide additional embodiments. These and other changes can be made to the embodiments in light of the above detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and claims, but should be construed to include all possible embodiments and the full scope of equivalents to such claims. Thus, the claims are not limited by the present disclosure.

Claims

1. A method comprising: receiving a first driver signal at a half-bridge regulation circuit, the first driver signal corresponding to a square wave; receiving a second driver signal at the half-bridge regulation circuit, the second driver signal corresponding to a square wave, wherein a first dead time is a period between a falling edge of the second driver signal and a rising edge of the first driver signal; generating, using the half-bridge regulation circuit, a first modified driver signal corresponding to the first driver signal, the first modified driver signal having a transition from a low voltage to an intermediate voltage during the first dead time and a transition from the intermediate voltage to a high voltage at the end of the first dead time; as well as A gate terminal of a first transistor of a half-bridge circuit is driven with the first modified driver signal. 2 . The method of claim 1 , wherein the half-bridge regulation circuit and the driver are implemented in the same integrated circuit die as the half-bridge circuit. 3 . The method of claim 1 , wherein the driver is implemented in an integrated circuit, wherein the half-bridge regulation circuit is coupled between the integrated circuit and the half-bridge circuit.

4. The method according to claim 1, wherein the second dead time is a period between a falling edge of the first driver signal and a rising edge of the second driver signal, the method comprising: generating, with the half-bridge regulation circuit, a second modified driver signal corresponding to the second driver signal, the second modified driver signal having a transition from the low voltage to the intermediate voltage during the second dead time and a transition from the intermediate voltage to the high voltage at the end of the second dead time; as well as A gate terminal of a second transistor of the half-bridge circuit is driven with the second modified driver signal.

5. The method according to claim 4, comprising: A dead time signal is generated using the half-bridge regulation circuit, the dead time signal having a high logic level during the first dead time and during the second dead time, and having a low logic level outside the first dead time and the second dead time.

6. The method according to claim 5, comprising: A first dead time control signal is generated using the half-bridge regulation circuit, wherein the first dead time control signal includes a first transition during the first dead time and a second transition at the end of the first dead time.

7. The method of claim 6, wherein the first correction driver signal transitions to the intermediate voltage in response to the first transition of the first dead time control signal, wherein the first correction driver signal transitions to the high voltage in response to the second transition of the first dead time control signal.

8. The method of claim 7, generating a second dead time control signal using the half-bridge regulation circuit, wherein the second dead time control signal comprises a first transition during the second dead time and a second transition at the end of the second dead time.

9. The method of claim 6, wherein the second modified driver signal transitions to the intermediate voltage in response to a first transition of the second dead time control signal, wherein the second modified driver signal transitions to the high voltage in response to a second transition of the second dead time control signal.

10. The method of claim 1, wherein the low voltage level is less than 0V, wherein the intermediate voltage is 0V. The method of claim 1 , wherein the first transistor is a GaN transistor.

12. A device comprising: A half-bridge circuit, the half-bridge circuit comprising: a high-side transistor; and a low-side transistor coupled to the high-side transistor at an intermediate node; a driver configured to generate a high-side driver signal and a low-side driver signal, the high-side driver signal corresponding to a square wave, the low-side driver signal corresponding to a square wave, wherein a first dead time is a period between a falling edge of the low-side driver signal and a rising edge of the high-side driver signal; a half-bridge regulation circuit, the half-bridge regulation circuit being coupled between the driver and the half-bridge circuit and being configured to: generating a modified high-side driver signal corresponding to the high-side driver signal, the modified high-side driver signal having a transition from a low voltage to an intermediate voltage during the first dead time and a transition from the intermediate voltage to a high voltage at the end of the first dead time; and A gate terminal of the high-side transistor of a half-bridge circuit is driven with the modified high-side driver signal.

13. The apparatus of claim 12, comprising an integrated circuit, wherein the driver and the half-bridge regulation circuit are implemented in the integrated circuit.

14. The apparatus according to claim 12, comprising: Circuit boards; as well as An integrated circuit includes the driver, wherein the integrated circuit, the half-bridge regulation circuit, and the half-bridge circuit are mounted to the circuit board.

15. The apparatus of claim 12, wherein: The second dead time is a period between a falling edge of the first driver signal and a rising edge of the second driver signal; the half-bridge regulation circuit being configured to generate a modified low-side driver signal corresponding to the low-side driver signal, the modified low-side driver signal having a transition from the low voltage to the intermediate voltage during the second dead time, and a transition from the intermediate voltage to the high voltage at the end of the second dead time; and The half-bridge regulation circuit is configured to drive a gate terminal of the low-side transistor with a modified low-side driver signal.

16. The apparatus of claim 15 , wherein the half-bridge regulation circuit is configured to generate a dead time signal having a high logic level during the first dead time and during the second dead time, and having a low logic level outside the first dead time and the second dead time, wherein the half-bridge regulation circuit is configured to generate a first dead time control signal including a first transition during the first dead time and a second transition at the end of the first dead time.

17. The apparatus of claim 16, wherein the half-bridge regulation circuit is configured to generate a second dead time control signal, the second dead time control signal comprising a first transition during the second dead time, and a second transition at an end of the second dead time, wherein the second modified driver signal transitions to the intermediate voltage in response to the first transition of the second dead time control signal, wherein the second modified driver signal transitions to the high voltage in response to the second transition of the second dead time control signal.

18. A method comprising: providing a first square wave to a half-bridge regulation circuit, the first square wave coming from a driver, the half-bridge regulation circuit being coupled between the driver and a half-bridge resonant converter, the half-bridge resonant converter including a high-side GaN high electron mobility transistor HEMT and a low-side GaN HEMT, the first square wave having a high voltage value and a low voltage value, the high voltage value corresponding to a turn-on voltage of the HEMT, the low voltage value corresponding to a turn-off voltage of the HEMT and having a value less than 0V; providing a second square wave to the half-bridge regulation circuit, the second square wave being from the driver, the first square wave and the second square wave having relative phases, the relative phases providing a dead time, the first square wave and the second square wave both being low during the dead time; and generating a first modified square wave using the half-bridge adjustment circuit, in which the dead time is divided into a first portion and a second portion, the first modified square wave being at the low voltage value during the first portion and at an intermediate voltage during the second portion; as well as The first modified square wave is applied to a gate terminal of the high-side GaN HEMT.

19. The method according to claim 18, comprising: generating a second modified square wave using the half-bridge adjustment circuit, in which the dead time is divided into a first portion and a second portion, the second modified square wave being at the low voltage value during the first portion and at an intermediate voltage during the second portion; as well as The second modified square wave is applied to a gate terminal of the low-side GaN HEMT.

20. The method of claim 19, wherein the half-bridge regulation circuit comprises a NOR gate, a comparator, an AND gate, and a switch, wherein the NOR gate is configured to receive the first square wave, the comparator is coupled to the output of the NOR gate, the AND gate is coupled to the output of the NOR gate, and the switch is coupled between the AND gate and the gate terminal of the high-side GaN HEMT.

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