Anti-winding and anti-pollution plating film carrier plate structure, plating method and battery piece

Abstract

The present application relates to a kind of anti-winding plating and anti-pollution's coating carrier plate structure, which is arranged in the process cavity of hot wire chemical vapor deposition, comprising: conveying carrier plate, silicon wafer is installed on it;Spacing plate is positioned between hot wire and conveying carrier plate, one side of spacing plate is towards hot wire, and the other side is towards the side of conveying carrier plate carrying silicon wafer;Wherein, first spacing is provided between spacing plate and conveying carrier plate, and second spacing is provided between spacing plate and hot wire.In addition, the present application also relates to a kind of coating method using the above-mentioned coating carrier plate structure and battery piece coated by the coating method.The present application can avoid winding plating and pollution problem when depositing thin film, and can directly prepare high-quality doped crystalline silicon layer without winding plating and pollution.

Description

Technical Field

[0001] This invention relates to the field of photovoltaic technology, and more specifically, to a coating carrier structure that prevents wrapping and contamination, a coating method using the coating carrier structure, and a solar cell coated using the coating method. Background Technology

[0002] With the increasing depletion of fossil fuels, solar cells have seen long-term development due to their clean and renewable advantages. Among various photovoltaic cells, such as TOPCon (Tunneling Oxide Passivated Contact), HJT (Heterojunction) and XBC (Interdigitated Back Contact) cells, vacuum coating technology is a key process in solar cell fabrication. The quality of the doped silicon thin film directly affects the cell's electrical performance, including efficiency. Currently, the main coating technologies in the industry are LPCVD (Low Pressure Chemical Vapor Deposition) and PECVD (Plasma Enhanced Chemical Vapor Deposition). However, both technologies result in varying degrees of coating around the front, back, and sides of the cell. The biggest impact of this coating on the cell is the accumulation of defects in the coated areas, which become recombination centers for carrier transport, ultimately causing leakage current, decreased cell resistance, and degraded module performance. Therefore, in the doped silicon coating process, producing cells without coating is extremely important for the cell's electrical performance.

[0003] Furthermore, the formation of swirling coating is mainly due to the average molecular free path and diffusion rate of the reactant gas in the vacuum chamber. The smaller the average molecular free path, the greater the probability of gas collisions; the higher the temperature, the faster the gas diffusion rate. The combination of these two factors results in swirling coating. For example, when preparing doped crystalline silicon thin films by LPCVD, the reaction temperature reaches above 600℃, and the gas pressure is 13-26 Pa. The average molecular free path of the reactant gas silane is only about 0.1 cm, and the diffusion rate at high temperatures is 25 m / s. This can cause swirling coating. Therefore, an acid-base etching process is usually added after coating to remove the swirling coating area. In TOPCon cells, the etching process accounts for about 7% (12 million) of the total line investment for 1GW. Moreover, the etching process is quite difficult. On the one hand, it cannot completely remove the swirling coating; on the other hand, it is affected by multiple etching factors, such as acid-base concentration, etching time, and etching liquid circulation, making it difficult to control precisely.

[0004] PECVD coating utilizes low-temperature plasma to generate glow discharge on the cathode of the process chamber, heating the sample to a predetermined temperature. Then, a suitable amount of process gas is introduced, and through a series of chemical and plasma reactions, a solid film is formed on the sample surface. The reactant gas enters the furnace chamber through the inlet and gradually diffuses to the sample surface. Under the influence of the electric field excited by the radio frequency source, the reactant gas decomposes into electrons, ions, and active groups. In PECVD, the silicon source flow rate reaches 1000 sccm (standard milliliters / min), and H2 can reach over 10000 sccm. The carrier plate filled with silicon wafers is made of graphite. Under the influence of the electric field, a large amount of diffused gas inevitably causes swirling deposition on the sides and back of the solar cells.

[0005] Therefore, there is an urgent need to design a structure and method that can prevent wrapping and contamination in the doped silicon coating process. Summary of the Invention

[0006] To address the shortcomings of existing technologies, the purpose of this invention is to provide a substrate structure and coating method for coating that prevents wrapping and contamination. This invention employs HWCVD (hot filament chemical vapor deposition) to prepare a doped silicon layer. The film layer is free from ionic damage, and the mean free path of the active groups is approximately 10 cm, almost equal to the distance from the hot filament to the silicon wafer / substrate. No collision reactions occur between gas groups, and the movement of groups in space is undisturbed. Furthermore, the chamber pressure is controlled to be as low as 1-10 Pa, and the total gas volume is reduced to within 3000 sccm. Combined with a unique substrate structure design, this allows for the direct fabrication of high-quality doped silicon layers that are free from wrapping and contamination.

[0007] To solve the above-mentioned technical problems or achieve the above-mentioned objectives, the present invention adopts the following technical solution:

[0008] According to one aspect of the present invention, a coating carrier structure that prevents wrapping and contamination is provided, the carrier structure being disposed within a hot-wire chemical vapor deposition process chamber, comprising:

[0009] A transport carrier plate on which silicon wafers are mounted;

[0010] A spacer plate is positioned between the hot wire and the transport carrier plate, with one side of the spacer plate facing the hot wire and the other side facing the side of the transport carrier plate that carries the silicon wafer.

[0011] A first gap is provided between the partition plate and the conveyor plate, and a second gap is provided between the partition plate and the hot wire.

[0012] In one embodiment of the invention, the silicon wafer is placed and mounted on a transport carrier by a mechanical gripper.

[0013] In one embodiment of the present invention, the silicon wafer comprises a plurality of silicon wafers uniformly distributed on a transport carrier.

[0014] In one embodiment of the present invention, 0cm < first spacing ≤ 20cm, and 5cm ≤ second spacing ≤ 20cm.

[0015] In one embodiment of the invention, the size of the spacer is larger than the size of the transport carrier plate.

[0016] In one embodiment of the present invention, the second spacing is greater than the first spacing.

[0017] According to another aspect of the present invention, a coating method for preventing wrapping and contamination is provided. This coating method employs the aforementioned carrier plate structure for preventing wrapping and contamination, and includes the following steps:

[0018] The spacer is fixed inside the process chamber of hot-wire chemical vapor deposition with one side of the spacer facing the hot wire.

[0019] The silicon wafers are placed and mounted on a conveyor plate using a mechanical gripper;

[0020] The transport carrier plate with the silicon wafer mounted is fed into the hot filament chemical vapor deposition process chamber with the side of the transport carrier plate carrying the silicon wafer facing the other side of the spacer plate.

[0021] Control the first gap between the partition plate and the conveyor plate and control the second gap between the partition plate and the hot wire;

[0022] The coating process begins when the carrier plate and the spacer plate are aligned.

[0023] In one embodiment of the present invention, during the coating process, the pressure in the process chamber of hot-wire chemical vapor deposition is controlled at 1-10 Pa.

[0024] In one embodiment of the present invention, the coating process employs either an I-IN-P coating process or an IN-IP coating process.

[0025] According to another aspect of the present invention, a battery cell is provided, which is coated using the anti-wrap and anti-pollution coating methods described above.

[0026] The technical solution provided by this invention has the following advantages compared with the prior art:

[0027] This invention can improve the coating area of ​​HWCVD vacuum deposition of doped crystalline silicon, which can be weakened to negligible level, thus avoiding battery leakage current. This invention solves the problem of carrier contamination during IN continuous deposition, and achieves stable IN continuous deposition process. This invention can extend the service life of the carrier. The carrier structure of this invention can be adapted to I-IN-P and IN-IP designs, reducing the number of silicon wafer flips and saving deposition time. Attached Figure Description

[0028] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0029] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, those skilled in the art can obtain other drawings based on these drawings without creative effort.

[0030] Figure 1 A schematic diagram of a coating carrier structure for preventing wrapping and contamination is shown in one embodiment of the present invention;

[0031] Figure 2 It shows Figure 1 A schematic diagram of the distribution of the conveyor plate, spacer plate, and hot wires in the middle section;

[0032] Figure 3 It shows the use of Figure 1 A schematic diagram of the coating method using a carrier plate structure for anti-winding and anti-pollution coating.

[0033] Among them, 1 is the transport carrier plate; 2 is the silicon wafer; 3 is the spacer plate; 4 is the hot wire; D is the first gap; d is the second gap. Detailed Implementation

[0034] To better understand the above-described objectives, features, and advantages of this disclosure, embodiments of this disclosure will be further described below. It should be noted that, unless otherwise specified, the embodiments and features described herein can be combined with each other.

[0035] Numerous specific details are set forth in the following description in order to provide a full understanding of this disclosure, but this disclosure may also be implemented in other ways than those described herein; obviously, the embodiments in the specification are only some, and not all, of the embodiments of this disclosure.

[0036] like Figure 1-2 As shown, an embodiment of the present invention provides a coating carrier structure that prevents wrapping and contamination. This carrier structure is disposed within the process chamber of hot-wire chemical vapor deposition (HWCVD) and includes a transport carrier 1, a silicon wafer 2, and a spacer 3. The silicon wafer 2 is mounted on the transport carrier 1. The spacer 3 is positioned between the hot wire 4 and the transport carrier 1, with one side of the spacer 3 facing the hot wire 4 and the other side facing the side of the transport carrier 1 that carries the silicon wafer 2. A first spacing D is provided between the spacer 3 and the transport carrier 1, and a second spacing d is provided between the spacer 3 and the hot wire 4.

[0037] In the above-described carrier plate structure for coating of the present invention, preferably, the silicon wafer 2 is placed and mounted on the transport carrier plate 1 by a mechanical gripper. Preferably, the silicon wafer 2 comprises a plurality of silicon wafers 2 uniformly distributed on the transport carrier plate 1, such as... Figure 1 As shown, nine silicon wafers 2 are mounted or carried on the transport carrier plate 1, which are evenly distributed.

[0038] In the above-described carrier plate structure for coating of the present invention, such as Figure 2 As shown, preferably, 0cm < D ≤ 20cm, 5cm ≤ d ≤ 20cm, and more preferably, the second spacing d is greater than the first spacing D. Of course, in other alternative embodiments, the second spacing d can be equal to the first spacing D, or the second spacing d can be less than the first spacing D.

[0039] In the above-described carrier plate structure for coating of the present invention, such as Figure 1-2 As shown, the size of the spacer 3 is larger than that of the transport carrier 1, that is, the length, width, and area of ​​the spacer 3 are all larger than those of the transport carrier 1. Of course, in an alternative embodiment, the size of the spacer 3 can be exactly the same as that of the transport carrier 1.

[0040] like Figure 3 As shown, an embodiment of the present invention also provides a method using the above-described... Figure 1-2 The coating method for the carrier plate structure used in the anti-wrapping and anti-contamination coating shown includes the following steps:

[0041] S1: Fix the spacer 3 in the process chamber of hot filament chemical vapor deposition (HWCVD) and make one side of the spacer 3 face the hot filament 4;

[0042] S2: Place and mount the silicon wafer 2 onto the transport carrier plate 1 using a mechanical gripper;

[0043] S3: The transport carrier 1 with silicon wafer 2 mounted is sent into the process chamber of hot filament chemical vapor deposition (HWCVD) and the side of the transport carrier 1 carrying silicon wafer 2 faces the other side of the spacer 3.

[0044] S4: Control the first distance D between the spacer plate 3 and the conveyor plate 1 and control the second distance d between the spacer plate 3 and the hot wire 4;

[0045] S5: The coating process begins when the position of the conveyor plate 1 coincides with that of the spacer plate 3.

[0046] In the above-described coating method of the present invention, preferably, during coating, the pressure of the HWCVD process chamber is controlled at 1-10 Pa, which can reduce the total amount of gas in the process chamber to within 3000 sccm.

[0047] In the above-described coating method of the present invention, the coating process can employ either an I-IN-P coating process or an IN-IP coating process. Specifically, the I-IN-P coating process involves depositing an intrinsic layer, i.e., layer I, followed by depositing a back-side layer I after wafer flipping, then depositing an N-type semiconductor layer, and finally depositing a P-type semiconductor layer after wafer flipping. The IN-IP coating process involves first depositing the intrinsic layer, i.e., layer I, followed by depositing an N-type semiconductor layer, and then depositing both layers after wafer flipping.

[0048] Furthermore, embodiments of the present invention also provide a battery cell, which is coated using the anti-wrap and anti-pollution coating methods described above.

[0049] In the above embodiments of the present invention, the main focus is on designing the carrier plate structure for film deposition within the HWCVD process cavity, referring again to... Figure 1-2 As shown, silicon wafer 2 is conveyed by a mechanical gripper and mounted onto the transport carrier 1, and then the entire wafer enters the HWCVD process chamber. Spacer 3 is fixed inside the HWCVD process chamber. The distribution of the transport carrier 1, spacer 3, and hot wire 4 is as follows: Figure 2 As shown, the first distance D between the spacer plate 3 and the conveyor plate 1 is controlled, and the second distance d between the spacer plate 3 and the hot wire 4 is controlled. When the conveyor plate 1 is conveyed to the position that coincides with the spacer plate 3, the coating process begins.

[0050] Refer again Figure 2 The range of the second distance d between the transport carrier 1 and the hot wire 4 is controlled to be 5cm ≤ d ≤ 20cm, for example, d can preferably be 10cm. The range of the first distance D between the spacer 3 and the transport carrier 1 is controlled to be 0cm < D ≤ 20cm, for example, D can preferably be 5cm. With this carrier structure design, film deposition is performed in the HWCVD process chamber. After the reactive gas in the process chamber is pyrolyzed at high temperature by the hot wire 4, it can be deposited uniformly and directionally in the region of the silicon wafer 2, reducing the non-directionality of gas deposition film formation and effectively improving the phenomenon of thin film being deposited around to the back side. Conversely, without the isolation provided by spacer 3, the doped gas, after being decomposed, would directly deposit on the uncovered areas of silicon wafer 2 and transport carrier 1. In I-IN-P or IN-IP coating processes, IN-connected plating (plating an I layer followed by an N-type semiconductor layer) would release the deposited phosphorus and oxygen atoms, which is detrimental to the preparation of intrinsic silicon films, resulting in IN mismatch and affecting cell efficiency. The designed spacer 3 can protect the transport carrier 1 from being coated with doped films over a large area, thereby further preventing plating around the substrate during coating and avoiding contamination during IN-connected plating.

[0051] Therefore, on the one hand, the structure and method of this invention can improve the plating area around doped crystalline silicon deposited by HWCVD vacuum deposition, reducing it to a negligible level and avoiding battery leakage current, i.e., preventing plating around during deposition. On the other hand, this invention can solve the problem of carrier contamination during IN-connected deposition, achieving stable IN-connected deposition process, i.e., preventing contamination during IN-connected deposition. Therefore, by adopting the above-mentioned structure and method of this invention, plating around and contamination problems can be avoided during thin film deposition. The resulting solar cells are free of plating around and contamination, and their electrical performance is unaffected, exhibiting excellent performance.

[0052] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to the process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0053] The above descriptions are merely embodiments of this application, which enable those skilled in the art to understand and implement this application. Various modifications to the embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments described herein, but is to be accorded the widest scope consistent with the principles and features disclosed herein.

Claims

1. A carrier plate structure for coating that prevents wrapping and contamination, characterized in that, The carrier plate structure is disposed within the process chamber of hot-wire chemical vapor deposition, and includes: A transport carrier plate on which silicon wafers are mounted; A spacer plate is fixed inside the hot-wire chemical vapor deposition process chamber. The spacer plate is positioned between the hot wire and the transport carrier plate. One side of the spacer plate faces the hot wire, and the other side faces the side of the transport carrier plate that carries the silicon wafer. The spacer plate and the conveying plate are provided with a first distance D and the spacer plate and the hot wire are provided with a second distance d, wherein 0cm < D ≤ 20cm, 5cm ≤ d ≤ 20cm, and the size of the spacer plate is larger than the size of the conveying plate to cover the projection area of ​​the conveying plate.

2. The carrier plate structure for anti-wrapping and anti-contamination coating according to claim 1, characterized in that, The silicon wafer is placed and mounted on the transport carrier by a mechanical gripper.

3. The anti-wrapping and anti-contamination carrier plate structure according to claim 1, characterized in that, The silicon wafers include a plurality of silicon wafers uniformly distributed on the transport carrier.

4. The carrier plate structure for anti-wrapping and anti-contamination coating according to claim 1, characterized in that, The second spacing is greater than the first spacing.

5. A coating method for preventing wrapping and contamination, characterized in that, The coating method employs a coating carrier plate structure with anti-winding and anti-contamination properties as described in any one of claims 1-4, and the coating method includes the following steps: The spacer is fixed inside the process chamber of hot-wire chemical vapor deposition with one side of the spacer facing the hot wire. The silicon wafers are placed and mounted on a conveyor plate using a mechanical gripper; The transport carrier plate with the silicon wafer mounted is fed into the hot filament chemical vapor deposition process chamber with the side of the transport carrier plate carrying the silicon wafer facing the other side of the spacer plate. Control the first gap between the partition plate and the conveyor plate and control the second gap between the partition plate and the hot wire; The coating process begins when the carrier plate and the spacer plate are aligned.

6. The coating method for preventing wrapping and contamination according to claim 5, characterized in that, During the coating process, the pressure in the hot filament chemical vapor deposition process chamber is controlled at 1-10 Pa.

7. The coating method for preventing wrapping and contamination according to claim 5, characterized in that, The coating process employs either the I-IN-P coating process or the IN-IP coating process.

8. A battery cell, characterized in that, The battery cells are coated using the anti-wrapping and anti-pollution coating method as described in any one of claims 5-7.

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