SiPM array coincidence reading system based on FPGA
By adopting a FPGA-based compliant readout system in the SiPM array detector, the problem of high SiPM dark counting rate and low signal-to-noise ratio are solved, efficient reading and long-term stability of SiPM array signals are achieved, and the miniaturization of nuclear radiation detectors is promoted.
Patent Information
- Application Number
- CN202411973889.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-30
- Publication Date
- 2025-05-23
AI Technical Summary
The SiPM dark counting rate is high, resulting in a low signal-to-noise ratio, limiting the miniaturization of nuclear radiation detectors.
The SiPM array based on FPGA is adopted to comply with the readout system. The SiPM array signal is converted into a digital signal through the SiPM analog signal processing module, and the signal addition and "An" gate judgment are performed in the FPGA logic processing module, and the summed SiPM array signal is output. At the same time, the working environment temperature of the SiPM array is monitored in real time and the power supply voltage is adjusted online based on the preset temperature-voltage relationship.
It significantly improves the signal-to-noise ratio of SiPM array signals, reduces the number of readout methods, helps to miniaturize large-area SiPM arrays, and improves the long-term stability of SiPM signals.
Smart Images
Figure CN120028825A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of nuclear detection, and in particular relates to a SiPM array coincidence readout system based on FPGA, which is used for scintillator detector readout and measurement and can be used for large-area SiPM array signal readout. Background Art
[0002] Scintillator detectors are a commonly used type of detector in the field of radiation measurement. Scintillator detectors need to be used in conjunction with photoelectric readout devices. Currently, most photomultiplier tubes (PMTs) are used to read out scintillation light signals. However, PMTs are large in size, are subject to electromagnetic interference, and require higher voltages, which limits the miniaturization of detectors.
[0003] Silicon photomultiplier (SiPM) is a relatively new type of semiconductor photodetector device with the characteristics of small size, low operating voltage, high photoelectric efficiency, and insensitivity to magnetic fields. It is gradually replacing the traditional PMT and is of great significance to the miniaturization of detectors. Therefore, it has great application prospects in the field of radiation detection. However, due to the high intrinsic dark count rate of SiPM detectors, in order to effectively read out the real signal and improve the signal-to-noise ratio, high requirements are placed on the SiPM readout technology. Summary of the invention
[0004] The present invention provides a SiPM array coincidence readout system based on FPGA, and the technical problem to be solved is: solving the difficult problem of high SiPM dark count rate, while improving the signal-to-noise ratio of the detector signal, which is conducive to realizing the miniaturization of nuclear radiation detectors.
[0005] In order to solve the above technical problems, the present invention provides a SiPM array compliance readout system based on FPGA, which is characterized by: comprising a SiPM analog signal processing module and an FPGA logic processing module; the SiPM analog signal processing module is used to merge and lead out the analog signals of the SiPM array and convert them into digital signals and then input them into the FPGA logic processing module; the FPGA logic processing module divides each group of digital signals into two paths, and performs signal addition and "AND" gate judgment respectively. When the "AND" gate is valid, the summed SiPM array signal is output.
[0006] It also includes a SiPM array power supply module, which reads the working environment temperature of the SiPM array in real time and adjusts the power supply voltage of the SiPM array online based on the temperature-voltage relationship preset in the FPGA logic processing module.
[0007] Furthermore, the SiPM analog signal processing module divides the SiPM array signals into multiple groups, and performs readout, operational amplification and analog-to-digital conversion on each group of SiPM signals.
[0008] Furthermore, the SiPM signal readout adopts an AC readout method to read out the signal of each SiPM unit.
[0009] Furthermore, the SiPM analog signal processing module includes an operational amplifier module, an operational amplifier gain control module and an analog-to-digital conversion module; the operational amplifier module adopts a charge-sensitive preamplifier; the operational amplifier gain control module adopts a multi-speed adjustable gain; and the analog-to-digital conversion module adopts a linear ADC.
[0010] Furthermore, the FPGA logic processing module includes a signal acquisition module, a signal processing module, a signal trigger module and a temperature feedback module;
[0011] The signal acquisition module performs peak search or integration on the converted SiPM digital signal, and adds and sums multiple groups of SiPM signals;
[0012] The signal processing module is used to compare the peak search or integration result of each group of SiPM signals with the set threshold parameter, and output the comparison result in binary format;
[0013] The signal trigger module is used to determine whether to output the added and summed SiPM signal according to the result of the signal processing module;
[0014] The temperature feedback module automatically generates a corresponding SiPM array voltage adjustment signal according to the received temperature monitoring result and the temperature-voltage relationship.
[0015] Furthermore, for the comparison result of the signal processing module, if it is greater than the threshold, "1" is output, and if it is less than the threshold, "0" is output.
[0016] Furthermore, the SiPM array power supply module includes a temperature monitoring module and a voltage module; the temperature monitoring module is used to measure the working environment temperature of the SiPM array in real time, and input it into the FPGA logic processing module in the form of a digital signal; the voltage module is used to provide voltage for the SiPM array grouping and can be independently adjusted by the FPGA logic processing module.
[0017] Furthermore, the SiPM array conformance readout system adopts a modular design and also includes a front-end board 1 and a back-end board 2, wherein the front-end board integrates a SiPM array and a SiPM analog signal processing module 5, and the back-end board integrates an FPGA logic processing module 7 and a SiPM array power supply module 6.
[0018] Furthermore, the space between the front end plate and the rear end plate is filled with heat insulating material.
[0019] Beneficial effects: The modular design of the present invention makes it easier to integrate and maintain the readout system, and isolates the influence of the heat generated by the back-end board on the performance of the SiPM array on the front-end board.
[0020] The present invention divides each group of digital signals into two paths through FPGA, and performs signal addition and "AND" gate judgment respectively. When the "AND" gate is valid, the system outputs the summed SiPM array signal, and when the "AND" gate is invalid, the system outputs the current electronic noise; the SiPM array power supply module reads the working environment temperature of the SiPM array in real time, and adjusts the supply voltage of the SiPM array online based on the temperature-voltage relationship preset in the FPGA. On the one hand, this technology solves the problem of excessively high output count rate of SiPM dark count noise signals through group matching readout, significantly improves the signal-to-noise ratio, and effectively reduces the number of readout paths of the SiPM array, which is useful for the development and application of miniaturization of large-area SiPM arrays; on the other hand, it eliminates the temperature dependence of the SiPM signal on the working environment, and improves the long-term stability of the SiPM signal. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] Figure 1 Schematic diagram of the readout system for the SiPM array based on FPGA;
[0022] Figure 2 Design schematic for FPGA-based SiPM array coincidence readout system;
[0023] Among them: 1 front-end board, 2 back-end board, 3 packaging structure, 4 SiPM array, 5 SiPM analog signal processing module, 6 SiPM array power supply module, 7 FPGA logic processing module, 8 input interface, 9 output interface. DETAILED DESCRIPTION
[0024] In order to make the purpose, content and advantages of the present invention more clear, the specific implementation methods of the present invention are further described in detail below.
[0025] The present invention proposes an FPGA-based SiPM array coincidence readout system, comprising a SiPM analog signal processing module, an FPGA logic processing module, and a SiPM array power supply module;
[0026] The SiPM analog signal processing module is used to merge and extract the analog signals of the SiPM array and convert them into digital signals and then input them into the FPGA logic processing module;
[0027] The FPGA logic processing module is used to implement the addition of multiple digital signals and output signals according to the logic;
[0028] The SiPM array power supply module is used to provide voltage to the SiPM array groups.
[0029] The FPGA logic processing module divides each group of digital signals into two paths, and performs signal addition and "AND" gate judgment respectively. When the "AND" gate is valid, the system outputs the summed SiPM array signal. When the "AND" gate is invalid, the system outputs the current electronic noise. The SiPM array power supply module reads the working environment temperature of the SiPM array in real time and adjusts the supply voltage of the SiPM array online based on the temperature-voltage relationship preset in the FPGA.
[0030] The SiPM analog signal processing module divides the SiPM array signals into multiple groups, and reads, operationally amplifies, and performs analog-to-digital conversion on the SiPM signals of each group of SiPMs. The SiPM signal readout adopts an AC readout method to read out the signal of each SiPM unit;
[0031] The operational amplifier is used to linearly amplify the SiPM signal;
[0032] The analog-to-digital conversion uses a high-speed analog-to-digital conversion device to convert the SiPM analog signal into a digital signal.
[0033] Specifically, the SiPM analog signal processing module includes an operational amplifier module, an operational amplifier gain control module and an analog-to-digital conversion module; the operational amplifier module adopts a charge-sensitive preamplifier; the operational amplifier gain control module adopts three adjustable gains of 1 / 2 / 4; and the analog-to-digital conversion module adopts a 12-bit linear ADC.
[0034] The FPGA logic processing module includes a signal acquisition module, a signal processing module, a signal trigger module and a temperature feedback module;
[0035] The signal acquisition module performs peak search or integration on the converted SiPM digital signal, and adds and sums multiple groups of SiPM signals.
[0036] The signal processing module is used to compare the peak search or integration result of each group of SiPM signals with the set threshold parameter, and output the comparison result in binary format, outputting "1" if it is greater than the threshold, and outputting "0" if it is less than the threshold;
[0037] The signal trigger module is used to determine whether to output the added and summed SiPM signal according to the result of the logic processing module;
[0038] The temperature feedback module automatically generates a corresponding SiPM array voltage adjustment signal based on the received temperature monitoring results and the temperature-voltage relationship written separately in the FPGA.
[0039] The SiPM array power supply module uses a DC-DC boost chip for voltage conversion. The SiPM array power supply module performs temperature negative feedback regulation and uses a thermistor to measure the working environment temperature near the SiPM array. The temperature coefficient can be measured according to the actual type of SiPM used.
[0040] The SiPM array power supply module includes a temperature monitoring module and a voltage module.
[0041] The temperature monitoring module is used to measure the working environment temperature of the SiPM array in real time and input it into the FPGA logic processing module in the form of digital signals;
[0042] The voltage module is used to provide voltage for the SiPM array group and can be independently adjusted by the FPGA.
[0043] In some optional implementations, the FPGA-based SiPM array coincidence readout system adopts a modular design, which is divided into a front-end board 1 and a back-end board 2:
[0044] The front and rear panels can be designed according to the shape of the detector to facilitate integration and assembly;
[0045] The front-end board is integrated with a SiPM array 4 and a SiPM analog signal processing module 5;
[0046] The backend board is integrated with an FPGA logic processing module 7 and a SiPM array power supply module 6;
[0047] The front-end board and the rear-end board are connected via a multi-pin connector to perform SiPM voltage supply and data transmission, and the space between the front-end board and the rear-end board is filled with heat-insulating material.
[0048] The readout system can be integrated with the detector and packaged in an integrated manner, with input and output interfaces 8 and 9 being provided outside the packaging structure.
[0049] The input interface is Type C, which is used for voltage supply and configuration parameter input;
[0050] The output interface is SMA type, used for SiPM array signal output.
[0051] The readout system is connected to the computer via the Type C interface. The computer can power the readout system. At the same time, the computer can use the host computer software to implement operations such as parameter configuration and status control of the readout system.
[0052] The present invention adopts an FPGA-based SiPM array coincidence readout system, and the nuclear radiation detector after final integration has the characteristics of small size, meets the demand for miniaturization of the detector, and has high flexibility and compatibility.
[0053] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.
Claims
1. A SiPM array coincidence readout system based on FPGA, characterized in that: It includes a SiPM analog signal processing module and an FPGA logic processing module; the SiPM analog signal processing module is used to merge and lead out the analog signals of the SiPM array and convert them into digital signals and then input them into the FPGA logic processing module; the FPGA logic processing module divides each group of digital signals into two paths, respectively performs signal addition and "AND" gate judgment, and when the "AND" gate is valid, outputs the summed SiPM array signal.
2. The FPGA-based SiPM array coincidence readout system according to claim 1, characterized in that: It also includes a SiPM array power supply module, which reads the working environment temperature of the SiPM array in real time and adjusts the power supply voltage of the SiPM array online based on the temperature-voltage relationship preset in the FPGA logic processing module.
3. The FPGA-based SiPM array coincidence readout system according to claim 1, characterized in that: The SiPM analog signal processing module divides the SiPM array signals into multiple groups, and performs readout, operational amplification and analog-to-digital conversion on each group of SiPM signals.
4. The FPGA-based SiPM array coincidence readout system according to claim 3, characterized in that: SiPM signal readout uses an AC readout method to read out the signal of each SiPM unit.
5. The FPGA-based SiPM array coincidence readout system according to claim 1, characterized in that: The SiPM analog signal processing module includes an operational amplifier module, an operational amplifier gain control module and an analog-to-digital conversion module; the operational amplifier module adopts a charge-sensitive preamplifier; the operational amplifier gain control module adopts a multi-gear adjustable gain; and the analog-to-digital conversion module adopts a linear ADC.
6. The FPGA-based SiPM array coincidence readout system according to claim 1, characterized in that: The FPGA logic processing module includes a signal acquisition module, a signal processing module, a signal trigger module and a temperature feedback module; The signal acquisition module performs peak search or integration on the converted SiPM digital signal, and adds and sums multiple groups of SiPM signals; The signal processing module is used to compare the peak search or integration result of each group of SiPM signals with the set threshold parameter, and output the comparison result in binary format; The signal trigger module is used to determine whether to output the added and summed SiPM signal according to the result of the signal processing module; The temperature feedback module automatically generates a corresponding SiPM array voltage adjustment signal according to the received temperature monitoring result and the temperature-voltage relationship.
7. The FPGA-based SiPM array coincidence readout system according to claim 6, characterized in that: For the comparison result of the signal processing module, if it is greater than the threshold, it outputs "1", and if it is less than the threshold, it outputs "0".
8. The FPGA-based SiPM array coincidence readout system according to claim 2, characterized in that: The SiPM array power supply module includes a temperature monitoring module and a voltage module; the temperature monitoring module is used to measure the working environment temperature of the SiPM array in real time and input it into the FPGA logic processing module in the form of a digital signal; the voltage module is used to provide voltage for the SiPM array grouping and can be independently adjusted by the FPGA logic processing module.
9. The FPGA-based SiPM array coincidence readout system according to any one of claims 1 to 9, characterized in that: The SiPM array conformance readout system adopts a modular design and also includes a front-end board 1 and a back-end board 2. The front-end board integrates a SiPM array and a SiPM analog signal processing module 5, and the back-end board integrates an FPGA logic processing module 7 and a SiPM array power supply module 6.
10. The FPGA-based SiPM array coincidence readout system according to claim 9, characterized in that: The space between the front end plate and the rear end plate is filled with heat insulation material.