LDO circuit and chip

Abstract

This application discloses an LDO circuit and chip, relating to the field of integrated circuit technology. The LDO circuit includes an LDO power output terminal, a reference voltage input terminal, a reference current input terminal, an LDO feedback control loop, and a current limiting protection circuit. The LDO feedback control loop includes an error amplifier and an LDO power transistor. The error amplifier can adjust the current flowing through the LDO power transistor based on the reference voltage and the output voltage to maintain a stable output voltage. The current limiting protection circuit includes a current mirror bias branch and a current mirror current limiting branch. The current mirror bias branch can provide a corresponding bias current based on the reference current. The current mirror current limiting branch limits the current flowing through the LDO power transistor based on the bias current, ensuring that the current flowing through the LDO power transistor does not exceed a first preset current limiting threshold. The current limiting protection setting of the LDO circuit in this application has the advantages of high current limiting accuracy, fast response speed, and low overall circuit power consumption.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to an LDO circuit and chip. Background Technology

[0002] Low dropout regulators (LDOs) are widely used in chips due to their simple structure, low output noise, and fast transient response. However, in real-world applications, when the load current changes rapidly or the input voltage is unstable, LDOs may experience overcurrent, meaning the output current exceeds the preset maximum current threshold. This can cause the chip temperature to rise, potentially leading to chip damage or system malfunction.

[0003] To protect LDOs and the chips used in their applications from damage, current limiting protection settings are typically applied to LDOs. However, existing current limiting protection settings for LDO circuits suffer from drawbacks such as low current limiting accuracy, slow response speed, and high overall circuit power consumption. Summary of the Invention

[0004] The main purpose of this application is to provide an LDO circuit that addresses the problems of low current limiting accuracy, slow response speed, and high overall power consumption in existing LDO circuits.

[0005] To achieve the above objectives, the LDO circuit proposed in this application includes:

[0006] LDO power output;

[0007] The reference voltage input terminal is used to input a reference voltage.

[0008] The reference current input terminal is used to input a reference current;

[0009] The LDO feedback control loop is connected to the LDO power output terminal and the reference voltage input terminal respectively. The LDO feedback control loop includes an error amplifier and an LDO power transistor. The error amplifier is used to adjust the current flowing through the LDO power transistor based on the reference voltage and the output voltage of the LDO power output terminal to keep the output voltage of the LDO power output terminal stable.

[0010] Current limiting protection circuit, the current limiting protection circuit includes:

[0011] A current mirror bias branch is connected to the reference current input terminal, and the current mirror bias branch is used to provide a corresponding bias current based on the reference current;

[0012] A current mirror current limiting branch is provided, which is connected to the current mirror bias branch and the LDO feedback control loop. The current mirror current limiting branch is used to limit the current flowing through the LDO power transistor based on the bias current, so that the current flowing through the LDO power transistor does not exceed a first preset current limiting threshold.

[0013] In one embodiment, the LDO circuit includes multiple current mirror current limiting branches; each of the multiple current mirror current limiting branches has an enable signal input terminal, which is used to input an enable signal to control the current mirror current limiting branch to be in an on / off state.

[0014] The multiple current mirror current limiting branches are used to limit the current flowing through the LDO power transistor based on the bias current, so that the output current value of the LDO power output terminal does not exceed a second preset current limiting threshold; wherein, the second preset current limiting threshold is the product of the number of current mirror current limiting branches in the on state and the first preset current limiting threshold.

[0015] In one embodiment, the LDO circuit includes a first power supply terminal; the LDO power transistor is a first MOSFET, and the LDO feedback control loop further includes a second MOSFET and a third MOSFET;

[0016] The source of the first MOSFET and the source of the second MOSFET are connected to the first power supply terminal, and the drain of the first MOSFET is connected to the power output terminal of the LDO; the gate of the first MOSFET, the gate of the second MOSFET, and the drain of the second MOSFET are connected to the source of the third MOSFET; the gate of the third MOSFET is connected to the output terminal of the error amplifier.

[0017] The error amplifier is used to adjust the current flowing through the third MOSFET based on the reference voltage and the output voltage of the LDO power supply output terminal, thereby adjusting the current of the first MOSFET.

[0018] In one embodiment, the LDO feedback control loop further includes a first resistor and a second resistor; one end of the first resistor and the drain of the first MOSFET are connected to the LDO power output terminal; the other end of the first resistor and one end of the second resistor are connected to the non-inverting input terminal of the error amplifier; the other end of the second resistor is grounded; and the inverting input terminal of the error amplifier is connected to the reference voltage input terminal.

[0019] The error amplifier is used to adjust the current flowing through the third MOS transistor based on the reference voltage and the voltage sampled at the other end of the first resistor.

[0020] In one embodiment, the current mirror bias branch includes a third resistor, a fourth MOSFET, and a fifth MOSFET; the current mirror current limiting branch includes a sixth MOSFET, a seventh MOSFET, and an eighth MOSFET.

[0021] One end of the third resistor, the reference current input terminal, the gate of the fourth MOS transistor, and the gate of the seventh MOS transistor are connected; the other end of the third resistor, the drain of the fourth MOS transistor, the gate of the fifth MOS transistor, and the gate of the eighth MOS transistor are connected; the source of the fourth MOS transistor is connected to the drain of the fifth MOS transistor; the gate of the sixth MOS transistor is connected to the first enable signal input terminal; the drain of the sixth MOS transistor is connected to the drain of the third MOS transistor; the source of the sixth MOS transistor is connected to the drain of the seventh MOS transistor; the source of the seventh MOS transistor is connected to the drain of the eighth MOS transistor; and the source of the eighth MOS transistor and the source of the fifth MOS transistor are grounded.

[0022] In one embodiment, the LDO circuit includes three current mirror current limiting branches; the first current mirror current limiting branch includes the sixth MOSFET, the seventh MOSFET, and the eighth MOSFET; the second current mirror current limiting branch includes the ninth MOSFET, the tenth MOSFET, and the eleventh MOSFET; and the third current mirror current limiting branch includes the twelfth MOSFET, the thirteenth MOSFET, and the fourteenth MOSFET.

[0023] The gate of the ninth MOS transistor is connected to the second enable signal input terminal; the source of the ninth MOS transistor is connected to the drain of the tenth MOS transistor; the source of the tenth MOS transistor is connected to the drain of the eleventh MOS transistor; the source of the eleventh MOS transistor is grounded; the drain of the ninth MOS transistor is connected to the drain of the third MOS transistor; the gate of the tenth MOS transistor is connected to the gate of the fourth MOS transistor; and the gate of the eleventh MOS transistor is connected to the gate of the fifth MOS transistor.

[0024] The gate of the twelfth MOS transistor is connected to the third enable signal input terminal; the source of the twelfth MOS transistor is connected to the drain of the thirteenth MOS transistor; the source of the thirteenth MOS transistor is connected to the drain of the fourteenth MOS transistor; the source of the fourteenth MOS transistor is grounded; the drain of the tenth MOS transistor is connected to the drain of the third MOS transistor; the gate of the thirteenth MOS transistor is connected to the gate of the fourth MOS transistor; and the gate of the thirteenth MOS transistor is connected to the gate of the fifth MOS transistor.

[0025] In one embodiment, the LDO circuit further includes:

[0026] A reference circuit, wherein a first output terminal of the reference circuit is connected to the reference voltage input terminal, and a second output terminal of the reference circuit is connected to the reference current input terminal; the reference circuit is used to provide the reference voltage and the reference current.

[0027] In one embodiment, the LDO circuit further includes a first power supply terminal, and the reference circuit includes a fifteenth MOS transistor, a sixteenth MOS transistor, a seventeenth MOS transistor, an eighteenth MOS transistor, an operational amplifier, a first transistor circuit, a second transistor circuit, a fourth resistor, a fifth resistor, a sixth resistor, and a seventh resistor.

[0028] The sources of the fifteenth, sixteenth, seventeenth, and eighteenth MOS transistors are connected to the first power supply terminal; the gates of the fifteenth, sixteenth, seventeenth, and eighteenth MOS transistors are connected to the output terminal of the operational amplifier; the drain of the fifteenth MOS transistor, the first terminal of the first transistor circuit, and one end of the fourth resistor are connected to the inverting input terminal of the operational amplifier; the drain of the sixteenth MOS transistor, the non-inverting input terminal of the operational amplifier, and one end of the fifth resistor are connected to one end of the sixth resistor; the drain of the seventeenth MOS transistor and the reference voltage input terminal are connected to one end of the seventh resistor; the drain of the eighteenth MOS transistor is connected to the reference current input terminal. The input terminal is connected; the other end of the fifth resistor is connected to the first end of the second transistor circuit; the second end of the first transistor circuit, the other end of the fourth resistor, the second end of the second transistor circuit, the other end of the sixth resistor, and the other end of the seventh resistor are grounded; wherein, the first transistor circuit includes a plurality of first transistors, the emitters of the plurality of first transistors are all connected to the first end of the first transistor circuit, and the collectors and bases of the plurality of first transistors are all connected to the second end of the first transistor circuit; the second transistor circuit includes a plurality of second transistors, the emitters of the plurality of second transistors are all connected to the first end of the second transistor circuit, and the collectors and bases of the plurality of second transistors are all connected to the second end of the second transistor circuit.

[0029] In one embodiment, the LDO circuit further includes a load resistor and a load capacitor, one end of the load resistor and one end of the load capacitor are connected to the LDO power output terminal, and the other end of the load resistor and the other end of the load capacitor are grounded.

[0030] This application also proposes a chip that includes the LDO circuit described above.

[0031] This application employs an LDO circuit, including an LDO power output terminal, a reference voltage input terminal, a reference current input terminal, an LDO feedback control loop, and a current limiting protection circuit. The error amplifier adjusts the current flowing through the LDO power transistor based on the reference voltage and the output voltage of the LDO power output terminal to maintain a stable output voltage at the LDO power output terminal. During the negative feedback regulation process of the LDO feedback control loop, a current limiting protection circuit is provided to limit the current flowing through the LDO power transistor. This current limiting protection circuit includes a current mirror bias branch and a current mirror current limiting branch. The current mirror bias branch provides a corresponding bias current based on the reference current. The current mirror current limiting branch limits the current flowing through the LDO power transistor based on the bias current, ensuring that the current flowing through the LDO power transistor does not exceed a first preset current limiting threshold. Consequently, the output current at the load terminal also does not exceed the first preset current limiting threshold, preventing damage to the LDO circuit and its application chips. Thus, this application achieves current-limiting protection for the LDO circuit. The output current is limited by the current mirror structure of the current-limiting protection circuit, reducing errors caused by the use of resistors and comparators in traditional structures, resulting in high current-limiting protection accuracy. If the output current at the load end exceeds the first preset current-limiting threshold, the current of the LDO power transistor drops rapidly, and the output voltage at the LDO power supply output terminal drops rapidly, resulting in a fast response speed for the current-limiting protection. Furthermore, the current-limiting protection circuit of this application only consumes the current of the current mirror bias branch and the current mirror current-limiting branch, resulting in very low overall power consumption of the LDO circuit. Therefore, compared with the prior art, the LDO circuit of this application has high current-limiting accuracy, fast response speed, and low overall circuit power consumption. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0033] Figure 1 An electronic circuit diagram of an embodiment of the LDO circuit provided in this application;

[0034] Figure 2 An electronic circuit diagram of a reference circuit for an embodiment of the LDO circuit provided in this application;

[0035] Figure 3 A schematic diagram of the simulation results of the output voltage and load current as a function of the output load resistance in an embodiment of the LDO circuit provided in this application.

[0036] Explanation of icon numbers:

[0037]

[0038]

[0039] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0040] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0041] It should be noted that all directional indicators (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicator will also change accordingly.

[0042] Furthermore, the use of terms such as "first" and "second" in this application is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. Additionally, the technical solutions of the various embodiments can be combined with each other, but only on the basis of being achievable by those skilled in the art. When the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed in this application.

[0043] Low dropout regulators (LDOs) are primarily used to convert input voltage into a stable output voltage. Due to their simple structure, low output noise, and fast transient response, they are widely used in various chips. To protect the LDO and the chips it's used in from damage, current limiting protection is typically implemented. However, existing current limiting protection mechanisms for LDO circuits suffer from drawbacks such as low current limiting accuracy, slow response speed, and high overall circuit power consumption.

[0044] This application proposes an LDO circuit.

[0045] Please see Figure 1 In one embodiment of this application, the LDO circuit includes:

[0046] LDO power output;

[0047] The reference voltage input terminal is used to input a reference voltage.

[0048] The reference current input terminal is used to input a reference current;

[0049] LDO feedback control loop 10 is connected to the LDO power output terminal and the reference voltage input terminal respectively. LDO feedback control loop 10 includes error amplifier EA and LDO power transistor. Error amplifier EA is used to adjust the current flowing through LDO power transistor based on the reference voltage and the output voltage of LDO power output terminal to keep the output voltage of LDO power output terminal stable.

[0050] Current limiting protection circuit 20, the current limiting protection circuit 20 includes:

[0051] The current mirror bias branch 21 is connected to the reference current input terminal and is used to provide a corresponding bias current based on the reference current.

[0052] The current mirror current limiting branch 22 is connected to the current mirror bias branch 21 and the LDO feedback control loop 10 respectively. The current mirror current limiting branch 22 is used to limit the current flowing through the LDO power transistor based on the bias current, so that the current flowing through the LDO power transistor does not exceed the first preset current limiting threshold.

[0053] In this embodiment, the LDO feedback control loop 10 can adjust the current flowing through the LDO power transistor based on the reference voltage and the output voltage of the LDO power supply output terminal to maintain a stable output voltage at the LDO power supply output terminal. For example, the LDO power transistor can be a PMOS transistor. When the output voltage of the LDO power supply output terminal suddenly increases, the error amplifier EA can detect this change based on the reference voltage, causing the output of the error amplifier EA to also increase. This adjusts the current of the LDO power transistor to decrease, thus decreasing the output voltage of the LDO power supply output terminal. Conversely, when the output voltage of the LDO power supply output terminal suddenly decreases, the error amplifier EA can detect this change based on the reference voltage, causing the output of the error amplifier EA to also decrease. This adjusts the current of the LDO power transistor to increase, thus decreasing the output voltage of the LDO power supply output terminal. Therefore, when the output voltage of the LDO power supply output terminal changes, the error amplifier EA can adjust the conduction level of the LDO power transistor, thereby adjusting the current flowing through the LDO power transistor to maintain a stable output voltage at the LDO power supply output terminal.

[0054] It should be noted that the LDO circuit may experience overcurrent when the load current changes rapidly or the input voltage is unstable. In this embodiment, a current-limiting protection circuit 20 is provided to protect the circuit from current fluctuations. This current-limiting protection circuit 20 includes a current mirror bias branch 21 and a current mirror current-limiting branch 22. The current mirror bias branch 21 provides a corresponding bias current based on a reference current, and the current mirror current-limiting branch 22 limits the current flowing through the LDO power transistor based on the bias current, ensuring that the current flowing through the LDO power transistor does not exceed a first preset current-limiting threshold. Thus, this embodiment can limit the current of the LDO power transistor. If the load current exceeds the first preset current-limiting threshold, the current of the LDO power transistor drops rapidly, and the output voltage at the LDO power output terminal drops rapidly, resulting in a fast response speed for the current-limiting protection.

[0055] In this embodiment, a first preset current limiting threshold can be set by configuring the width and length of the LDO power transistor in the LDO feedback control loop 10, as well as the parameter values ​​of other MOS transistors. Specifically, the current mirror structure of the current limiting protection circuit 20 limits the current of the LDO power transistor in the LDO feedback control loop 10, reducing errors caused by the use of resistors and comparators in traditional structures, resulting in high current limiting protection accuracy.

[0056] In this embodiment, when the output current at the load end exceeds the first preset current limiting threshold, the LDO power transistor in the LDO feedback control loop 10 cannot provide a current output exceeding the first preset current limiting threshold, the output voltage at the LDO power output end drops, and the current limiting protection response speed is fast.

[0057] In this embodiment, apart from the LDO feedback control loop 10, the current limiting protection circuit 20 only needs to consume the current of the current mirror bias branch 21 and the current mirror current limiting branch 22, so the overall LDO circuit power consumption is very low.

[0058] In this application, the error amplifier EA adjusts the current flowing through the LDO power transistor based on the reference voltage and the output voltage at the LDO power supply output terminal to maintain a stable output voltage at the LDO power supply output terminal. During the negative feedback regulation process of the LDO feedback control loop 10, a current limiting protection circuit 20 is provided to limit the current of the LDO power transistor. This current limiting protection circuit 20 includes a current mirror bias branch 21 and a current mirror current limiting branch 22. The current mirror bias branch 21 provides a corresponding bias current based on the reference current. The current mirror current limiting branch 22 is used to limit the current flowing through the LDO power transistor based on the bias current, ensuring that the current flowing through the LDO power transistor does not exceed a first preset current limiting threshold. Thus, this application achieves current limiting protection for the LDO circuit. By limiting the output current value at the LDO power supply output terminal through the current mirror structure of the current limiting protection circuit 20, the errors caused by the use of resistors and comparators in traditional structures are reduced, resulting in high current limiting protection accuracy. If the output current at the load end exceeds the first preset current limiting threshold, the current of the LDO power transistor drops rapidly, and the output voltage at the LDO power supply output terminal drops rapidly, resulting in a fast response speed for the current limiting protection. Furthermore, the current limiting protection circuit 20 of this application only consumes the current of two branches: the current mirror bias branch 21 and the current mirror current limiting branch 22, resulting in very low overall LDO circuit power consumption. Therefore, compared with the prior art, the LDO circuit of this application has high current limiting accuracy, fast response speed, and low overall circuit power consumption.

[0059] Please see Figure 1 In one embodiment of this application, the LDO circuit includes a multi-channel current mirror current limiting branch 22; each of the multi-channel current mirror current limiting branches 22 has an enable signal input terminal, which is used to input an enable signal to control the current mirror current limiting branch 22 to be in an on / off state.

[0060] The multi-channel current mirror current limiting branch 22 is used to limit the current flowing through the LDO power transistor based on the bias current, so that the output current value of the LDO power output terminal does not exceed the second preset current limiting threshold; wherein, the second preset current limiting threshold is the product of the number of current mirror current limiting branches 22 in the on state and the first preset current limiting threshold.

[0061] In this embodiment, a multi-channel current mirror current limiting branch 22 is added. The enable signal of the current mirror current limiting branch 22 can be set via communication with an external host computer, thereby enabling multi-level adjustment of different current limiting thresholds for current limiting protection. For example, when the enable signal is used to indicate that the three current mirror current limiting branches 22 are in the open state, the second preset current limiting threshold is equal to 3 multiplied by the first preset current limiting threshold. Thus, this embodiment can dynamically adjust the second preset current limiting threshold through the input enable signal. Different levels of the second preset current limiting threshold can be set according to actual needs and protection strategies, ensuring that the LDO circuit can provide flexible current protection under different load conditions, and has a multi-level fine overcurrent protection mechanism.

[0062] Please see Figure 1 In one embodiment of this application, the LDO circuit includes a first power supply terminal; the LDO power transistor is a first MOSFET MP1, and the LDO feedback control loop 10 also includes a second MOSFET MP2 and a third MOSFET MP3;

[0063] The source of the first MOSFET MP1 and the source of the second MOSFET MP2 are connected to the first power supply terminal; the drain of the first MOSFET MP1 is connected to the LDO power supply output terminal; the gate of the first MOSFET MP1, the gate of the second MOSFET MP2, and the drain of the second MOSFET MP2 are connected to the source of the third MOSFET MP3; the gate of the third MOSFET MP3 is connected to the output terminal of the error amplifier EA.

[0064] Error amplifier EA is used to adjust the current flowing through the third MOSFET MP3 based on the reference voltage and the output voltage of the LDO power supply, so as to adjust the current of the first MOSFET MP1.

[0065] The LDO feedback control loop 10 also includes a first resistor R1 and a second resistor R2; one end of the first resistor R1 and the drain of the first MOSFET MP1 are connected to the LDO power supply output terminal; the other end of the first resistor R1 and one end of the second resistor R2 are connected to the non-inverting input terminal of the error amplifier EA; the other end of the second resistor R2 is grounded; the inverting input terminal of the error amplifier EA is connected to the reference voltage input terminal.

[0066] Error amplifier EA is used to adjust the current flowing through the third MOS transistor MP3 based on the reference voltage and the voltage sampled at the other end of the first resistor R1.

[0067] Please see Figure 1 In one embodiment of this application, the LDO circuit further includes a load resistor RL and a load capacitor CL. One end of the load resistor RL and one end of the load capacitor CL are connected to the LDO power output terminal, and the other end of the load resistor RL and the other end of the load capacitor CL are grounded.

[0068] It should be noted that the first MOSFET MP1, the second MOSFET MP2, and the third MOSFET MP3 can all be PMOS transistors. The first MOSFET MP1 and the second MOSFET MP2 form a current mirror. In this embodiment, the ratio of the width-to-length ratio of the second MOSFET MP2 to the width-to-length ratio of the first MOSFET MP1 is set to K, i.e.

[0069] K*(W2 / L2)=W1 / L1

[0070] Where K is the scaling factor, W2 is the width of the second MOSFET MP2, L2 is the length of the second MOSFET MP2, W1 is the width of the first MOSFET MP1, and L1 is the length of the first MOSFET MP1.

[0071] Therefore, the current flowing through the first MOSFET MP1 is K times the current flowing through the second MOSFET MP2, that is...

[0072] K*I2=I1

[0073] Where I2 is the current flowing through the second MOSFET MP2, and I1 is the current flowing through the first MOSFET MP1.

[0074] It should be noted that the load circuit can be equivalent to a load resistor RL and a load capacitor CL connected in parallel. The load capacitor CL can filter out high-frequency noise to stabilize the output voltage Vout.

[0075] It should be noted that when the load resistance RL suddenly increases (resulting in a sudden decrease in the output current at the load end), causing a sudden increase in the output voltage, the feedback voltage VFB also increases. This leads to an increase in the output voltage of the error amplifier EA, a decrease in the gate-source voltage of the third MOSFET MP3, a decrease in the current flowing through the third MOSFET MP3, and a decrease in the current flowing through the first MOSFET MP1. Consequently, the output voltage Vout decreases, and the feedback voltage VFB also decreases until VFB = VBG (VBG is the reference voltage). Therefore, the output of the LDO feedback control loop 10 remains stable. Similarly, when the load resistance RL suddenly decreases (resulting in a sudden increase in the output current), causing a sudden decrease in the output voltage, the feedback voltage VFB also decreases. This leads to an increase in the output voltage of the error amplifier EA, an increase in the gate-source voltage of the third MOSFET MP3, an increase in the current flowing through the third MOSFET MP3, and a increase in the current flowing through the first MOSFET MP1. Consequently, the output voltage Vout increases, and the feedback voltage VFB also increases until VFB = VBG. The output of the LDO feedback control loop 10 remains stable. Therefore, when the output current at the load side changes, causing the output voltage Vout to fluctuate, the LDO feedback control loop 10 will adjust the current flowing through the third MOSFET MP3 in a timely manner to limit the current flowing through the first MOSFET MP1, thereby ensuring the stability of the output voltage Vout.

[0076] It should be noted that the relationship between the feedback voltage VFB and the output voltage Vout is as follows:

[0077] VFB = Vout * R2 / (R1 + R2)

[0078] The relationship between the output voltage Vout and the reference voltage VBG is as follows:

[0079] Vout=VFB*(R1+R2) / R2=VBG*(R1+R2) / R2

[0080] Thus, in this embodiment, the output voltage Vout can be stabilized near the voltage value of VBG*(R1+R2) / R2 through the LDO feedback control loop 10.

[0081] Please see Figure 1 In one embodiment of this application, the current mirror bias branch 21 includes a third resistor R3, a fourth MOSFET MN4 and a fifth MOSFET MN5; the current mirror current limiting branch 22 includes a sixth MOSFET MN6, a seventh MOSFET MN7 and an eighth MOSFET MN8.

[0082] One end of the third resistor R3, the reference current input terminal, the gate of the fourth MOSFET MN4, and the gate of the seventh MOSFET MN7 are connected; the other end of the third resistor R3, the drain of the fourth MOSFET MN4, the gate of the fifth MOSFET MN5, and the gate of the eighth MOSFET MN8 are connected; the source of the fourth MOSFET MN4 is connected to the drain of the fifth MOSFET MN5; the gate of the sixth MOSFET MN6 is connected to the first enable signal input terminal; the drain of the sixth MOSFET MN6 is connected to the drain of the third MOSFET MP3; the source of the sixth MOSFET MN6 is connected to the drain of the seventh MOSFET MN7; the source of the seventh MOSFET MN7 is connected to the drain of the eighth MOSFET MN8; the source of the eighth MOSFET MN8 and the source of the fifth MOSFET MN5 are grounded.

[0083] In this embodiment, the sixth MOSFET MN6 is set to the ON state, which can limit the current flowing through the second MOSFET MP2. The maximum current I2 flowing through the second MOSFET MP2 is the current in the current mirror current-limiting branch 22, which is the reference current IREF. Furthermore, since...

[0084] K*I2=I1

[0085] Therefore, the first preset current limiting threshold is K*IREF, which means the maximum current flowing through the first MOSFET MP1 is K*IREF, and the output current does not exceed K*IREF. In this way, precise current limiting of the output current at the LDO power supply output terminal is achieved.

[0086] Please see Figure 3 , Figure 3 This is a schematic diagram illustrating the simulation results of the output voltage at the LDO power supply output terminal varying with the output load resistance. M1 represents the curve of the output voltage varying with the load resistance RL, and M2 represents the curve of the load current passing through the load resistance RL varying with the load resistance RL.

[0087] When the load resistance RL is relatively large, for example, when the preset load resistance RL is 900Ω, the current at the load end reaches its maximum, which is a current value that does not exceed the first preset current limiting threshold. Therefore, when the load resistance RL is greater than 900Ω, as the load resistance RL increases, the output voltage at the LDO power supply output terminal remains stable, specifically stable around the voltage value of VBG*(R1+R2) / R2. According to Ohm's law, the load current decreases as the load resistance RL increases. When the load resistance RL is less than 900Ω, as the load resistance RL decreases, since the maximum current of the first MOSFET MP1 does not exceed the first preset current limiting threshold, the load current also does not exceed the first preset current limiting threshold. At this time, the load current is almost a maximum current constant. According to Ohm's law, the output voltage at the LDO power supply output terminal decreases as the load resistance RL decreases. Therefore, this embodiment can achieve precise current limiting protection for the LDO circuit.

[0088] Please see Figure 1 In one embodiment of this application, the LDO circuit includes three current mirror current limiting branches 22; the first current mirror current limiting branch 22 includes the sixth MOSFET MN6, the seventh MOSFET MN7 and the eighth MOSFET MN8, the second current mirror current limiting branch 22 includes the ninth MOSFET MN9, the tenth MOSFET MN10 and the eleventh MOSFET MN11, and the third current mirror current limiting branch 22 includes the twelfth MOSFET MN12, the thirteenth MOSFET MN13 and the fourteenth MOSFET MN14;

[0089] The gate of the ninth MOSFET MN9 is connected to the second enable signal input terminal; the source of the ninth MOSFET MN9 is connected to the drain of the tenth MOSFET MN10; the source of the tenth MOSFET MN10 is connected to the drain of the eleventh MOSFET MN11; the source of the eleventh MOSFET MN11 is grounded; the drain of the ninth MOSFET MN9 is connected to the drain of the third MOSFET MP3; the gate of the tenth MOSFET MN10 is connected to the gate of the fourth MOSFET MN4; and the gate of the eleventh MOSFET MN11 is connected to the gate of the fifth MOSFET MN5.

[0090] The gate of the twelfth MOSFET MN12 is connected to the third enable signal input terminal; the source of the twelfth MOSFET MN12 is connected to the drain of the thirteenth MOSFET MN13; the source of the thirteenth MOSFET MN13 is connected to the drain of the fourteenth MOSFET MN14; the source of the fourteenth MOSFET MN14 is grounded; the drain of the tenth MOSFET MN10 is connected to the drain of the third MOSFET MP3; the gate of the thirteenth MOSFET MN13 is connected to the gate of the fourth MOSFET MN4; and the gate of the thirteenth MOSFET is connected to the gate of the fifth MOSFET MN5.

[0091] In this embodiment, a common-source, common-gate current mirror is used to reduce the error of the current mirror. The third resistor R3, the fourth MOSFET MN4, and the fifth MOSFET MN5 form a self-biased structure for the current mirror. The current-limiting branch 22 of the current mirror is known to be the reference current IREF. According to the current formula in the saturation region of the MOSFET:

[0092]

[0093] Where, μ n For electron mobility, C ox V is the gate oxide capacitance per unit area, W is the width of the MOSFET, L is the length of the MOSFET, and V is the capacitance per unit area. GS V is the gate-source voltage of the MOSFET. TH This is the threshold voltage of the MOSFET.

[0094] The voltage at point P1 is:

[0095]

[0096] Therefore, the voltage at point P2 is:

[0097] VB2 = VB1 + IREF·R3

[0098] In this way, the operating voltage of the MOSFET in the saturation region can be calculated, and then a suitable reference current IREF can be selected according to the different parameters of the MOSFET, so that the reference current IREF is adapted to the operating state of the MOSFET in the saturation region.

[0099] In this embodiment, the fourth MOSFET MN4 to the fourteenth MOSFET MN14 can all be NMOS transistors. The width-to-length ratios of the fourth MOSFET MN4, the seventh MOSFET MN7, the tenth MOSFET MN10, and the thirteenth MOSFET MN13 are the same. The width-to-length ratios of the fifth MOSFET MN5, the eighth MOSFET MN8, the eleventh MOSFET MN11, and the fourteenth MOSFET MN14 are also the same. Therefore, the branch currents of the first current mirror current-limiting branch containing the eighth MOSFET MN8, the second current mirror current-limiting branch containing the eleventh MOSFET MN11, and the third current mirror current-limiting branch containing the fourteenth MOSFET MN14 are all equal to the reference current IREF. The sixth MOSFET MN6, the ninth MOSFET MN9, and the twelfth MOSFET MN12 are the switching transistors of the three current mirror current-limiting branches 22, controlled by the enable signal. By default, only the sixth MOSFET MN6 can be turned on. Therefore, the maximum current flowing through the second MOSFET MP2 and the third MOSFET MP3 is IREF. Furthermore, because the first MOSFET MP1 and the second MOSFET MP2 are current mirrors, their width-to-length ratios are:

[0100] K*(W2 / L2)=W1 / L1

[0101] Therefore, the maximum current flowing through the first MOSFET MP1 is K*IREF, which is the second preset current limiting threshold. When the output current at the load end exceeds K*IREF, the LDO power transistor cannot provide power, so the output voltage Vout will decrease, forcing the output current at the load end to decrease, thereby protecting the safety of the LDO circuit. Similarly, if the sixth MOSFET MN6, the ninth MOSFET MN9, and the twelfth MOSFET MN12 are all turned on, the maximum current flowing through the first MOSFET MP1 is 3K*IREF, which is the second current threshold. When the output current at the load end exceeds 3K*IREF, the LDO power transistor cannot provide power, so the output voltage Vout will decrease, forcing the output current to decrease, thereby protecting the safety of the LDO circuit. Thus, this embodiment can provide three levels of the second preset current limiting threshold: K*IREF, 2K*IREF, and 3K*IREF, improving the adaptability of the LDO circuit for various application scenarios. It is understandable that the current mirror current limiting branch 22 can also be N, where N is a positive integer of 2 or greater than 3. N can be specifically set according to the specific current limiting requirements, and there is no restriction here.

[0102] In this embodiment, for the accuracy of current limiting protection, a current mirror method is used, where the magnitude of the output current and the current value of the current limiting protection are mirrored, reducing the errors introduced by the resistor and comparator structures in traditional designs. Regarding the response speed of current limiting protection, the output of the error amplifier EA directly controls the current of the third MOSFET MP3. The current limiting protection circuit 20 limits the current of the third MOSFET MP3, and then replicates it through a current mirror formed by the first MOSFET MP1 and the second MOSFET MP2 to obtain the current of the first MOSFET MP1, i.e., the LDO power transistor. This limits the output current from the source, reducing the protection response time. The current limiting protection circuit 20 has a simple structure, and the current of a single current mirror current limiting branch 22 can be very low, thus achieving a low-power design.

[0103] Please see Figure 1 In one embodiment of this application, the LDO circuit further includes:

[0104] The reference circuit 30 has a first output terminal connected to the reference voltage input terminal and a second output terminal connected to the reference current input terminal; the reference circuit 30 is used to provide reference voltage and reference current.

[0105] It should be noted that the reference circuit 30 can be a low-voltage bandgap reference source circuit. The low-voltage bandgap reference source circuit can provide a stable reference voltage over a wide operating voltage range, and its output reference voltage and reference current are not easily affected by temperature changes, resulting in relatively stable outputs. This simplifies circuit design, reduces additional power consumption and complexity, and enhances the stability of the LDO circuit and improves current limiting accuracy.

[0106] Please see Figure 2 In one embodiment of this application, the LDO circuit further includes a first power supply terminal, and the reference circuit 30 includes a fifteenth MOS transistor MP15, a sixteenth MOS transistor MP16, a seventeenth MOS transistor MP17, an eighteenth MOS transistor MP18, an operational amplifier OP, a first transistor circuit Qm1, a second transistor circuit Qm2, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, and a seventh resistor R7.

[0107] The sources of the fifteenth MOSFET MP15, the sixteenth MOSFET MP16, the seventeenth MOSFET MP17, and the eighteenth MOSFET MP18 are connected to the first power supply terminal; the gates of the fifteenth MOSFET MP15, the sixteenth MOSFET MP16, the seventeenth MOSFET MP17, and the eighteenth MOSFET MP18 are connected to the output terminal of the operational amplifier OP; the drain of the fifteenth MOSFET MP15, the first terminal of the first transistor circuit Qm1, and one end of the fourth resistor R4 are connected to the inverting input terminal of the operational amplifier OP; the sixteenth MOSFET MP15... The drain of MOSFET MP16, the non-inverting input of operational amplifier OP, one end of the fifth resistor R5, and one end of the sixth resistor R6 are connected; the drain of the seventeenth MOSFET MP17, the reference voltage input, and one end of the seventh resistor R7 are connected; the drain of the eighteenth MOSFET MP18 is connected to the reference current input; the other end of the fifth resistor R5 is connected to the first end of the second transistor circuit Qm2; the second end of the first transistor circuit Qm1, the other end of the fourth resistor R4, the second end of the second transistor circuit Qm2, the other end of the sixth resistor R6, and the other end of the seventh resistor R7 are grounded.

[0108] It should be noted that the first transistor circuit Qm1 includes multiple first transistors connected in parallel, and the second transistor circuit Qm2 includes multiple second transistors connected in parallel. In this embodiment, the first and second transistors can be transistors with the same parameters, and the ratio of the number of first transistors to the number of second transistors is n. The emitters of all the first transistors are connected to the first terminal of the first transistor circuit Qm1, and the collectors and bases of all the first transistors are connected to the second terminal of the first transistor circuit Qm1. The second transistor circuit Qm2 includes multiple second transistors, the emitters of all the second transistors are connected to the first terminal of the second transistor circuit Qm2, and the collectors and bases of all the second transistors are connected to the second terminal of the second transistor circuit Qm2.

[0109] It should be noted that the fourth resistor R4, the fifth resistor R5, the sixth resistor R6 and the seventh resistor R7 in this embodiment are all zero temperature coefficient resistors, whose resistance values ​​do not change with temperature, so as to output a more stable reference voltage and reference current.

[0110] In this embodiment, the reference circuit 30 is specifically a low-voltage bandgap reference source circuit, connected to the first power supply terminal as input, and can output a reference voltage VBG and a reference current IREF with zero temperature coefficient. The fifteenth MOS transistor MP15 to the eighteenth MOS transistor MP18 can all be PMOS transistors, forming a PMOS current mirror, whose gate voltage is adjusted by the output of the operational amplifier OP. Utilizing the virtual short and virtual open characteristics of the operational amplifier OP, the voltages at points X and Y are kept at the same magnitude, equal to VBE1. By selecting appropriate values ​​to make R6 = R4, the current flowing through resistors R6 and R4 is the same, resulting in the following current formula:

[0111]

[0112] Among them, I R6 I is the current flowing through the sixth resistor R6. R4 VBE2 is the current flowing through the fourth resistor R4, VBE1 is the voltage difference between the first and second terminals of the second transistor circuit Qm2, and VBE2 is the voltage difference between the first and second terminals of the first transistor circuit Qm1.

[0113] but:

[0114]

[0115] Among them, I R5 Let n be the current flowing through the fifth resistor R5, and n be the ratio of the number of the first transistor to the number of the second transistor, which can generally be taken as 8. T This is the thermal voltage of the first transistor / second transistor.

[0116] Therefore, the current flowing through the seventeenth MOSFET MP17 is equal to the sum of the currents flowing through resistors R5 and R6, as shown in the following expression:

[0117]

[0118] The current flowing through resistor R7 generates the reference voltage VBG. Simultaneously, the eighteenth MOSFET MP18 replicates this current via a current mirror to obtain another reference current IREF. Therefore:

[0119]

[0120] In this embodiment, when R5 and R6 satisfy the relationship (R2 / R1)lnn≈17.2, the output reference voltage VBG and reference current IREF can have zero temperature coefficient.

[0121] Thus, this embodiment can provide a reference voltage VBG with zero temperature coefficient, whose voltage value does not change with temperature; it can also provide a reference current IREF with zero temperature coefficient, whose current value does not change with temperature. The provided reference voltage VBG and reference current IREF are both relatively stable, which improves the current limiting protection accuracy of the LDO circuit.

[0122] This application also proposes a chip that includes an LDO circuit. The specific structure of the LDO circuit is as described in the above embodiments. Since this chip adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be described in detail here.

[0123] The above description is merely an exemplary embodiment of this application and does not limit the patent scope of this application. Any equivalent structural transformations made based on the technical concept of this application and the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this application.

Claims

1. An LDO circuit, characterized in that, include: LDO power output; The reference voltage input terminal is used to input a reference voltage. The reference current input terminal is used to input a reference current; The LDO feedback control loop is connected to the LDO power output terminal and the reference voltage input terminal, respectively. The LDO feedback control loop includes an error amplifier and an LDO power transistor; the error amplifier is used to adjust the current flowing through the LDO power transistor based on the reference voltage and the output voltage of the LDO power output terminal, so as to keep the output voltage of the LDO power output terminal stable. Current limiting protection circuit, the current limiting protection circuit includes: A current mirror bias branch is connected to the reference current input terminal, and the current mirror bias branch is used to provide a corresponding bias current based on the reference current; A current mirror current limiting branch is provided, which is connected to the current mirror bias branch and the LDO feedback control loop. The current mirror current limiting branch is used to limit the current flowing through the LDO power transistor based on the bias current, so that the current flowing through the LDO power transistor does not exceed a first preset current limiting threshold.

2. The LDO circuit as described in claim 1, characterized in that, The LDO circuit includes multiple current mirror current limiting branches; each of the multiple current mirror current limiting branches has an enable signal input terminal, which is used to input an enable signal to control the current mirror current limiting branch to be in an on / off state. The multiple current mirror current limiting branches are used to limit the current flowing through the LDO power transistor based on the bias current, so that the output current value of the LDO power output terminal does not exceed a second preset current limiting threshold; wherein, the second preset current limiting threshold is the product of the number of current mirror current limiting branches in the on state and the first preset current limiting threshold.

3. The LDO circuit as described in claim 1, characterized in that, The LDO circuit includes a first power supply terminal; the LDO power transistor is a first MOSFET; and the LDO feedback control loop further includes a second MOSFET and a third MOSFET. The source of the first MOSFET and the source of the second MOSFET are connected to the first power supply terminal, and the drain of the first MOSFET is connected to the power output terminal of the LDO; the gate of the first MOSFET, the gate of the second MOSFET, and the drain of the second MOSFET are connected to the source of the third MOSFET. The gate of the third MOS transistor is connected to the output terminal of the error amplifier; The error amplifier is used to adjust the current flowing through the third MOSFET based on the reference voltage and the output voltage of the LDO power supply output terminal, thereby adjusting the current of the first MOSFET.

4. The LDO circuit as described in claim 3, characterized in that, The LDO feedback control loop further includes a first resistor and a second resistor; one end of the first resistor and the drain of the first MOSFET are connected to the LDO power output terminal; the other end of the first resistor and one end of the second resistor are connected to the non-inverting input terminal of the error amplifier; the other end of the second resistor is grounded; the inverting input terminal of the error amplifier is connected to the reference voltage input terminal. The error amplifier is used to adjust the current flowing through the third MOS transistor based on the reference voltage and the voltage sampled at the other end of the first resistor.

5. The LDO circuit as described in claim 3, characterized in that, The current mirror biasing branch includes a third resistor, a fourth MOSFET, and a fifth MOSFET; the current mirror current limiting branch includes a sixth MOSFET, a seventh MOSFET, and an eighth MOSFET. One end of the third resistor, the reference current input terminal, the gate of the fourth MOS transistor, and the gate of the seventh MOS transistor are connected; the other end of the third resistor, the drain of the fourth MOS transistor, the gate of the fifth MOS transistor, and the gate of the eighth MOS transistor are connected; the source of the fourth MOS transistor is connected to the drain of the fifth MOS transistor; the gate of the sixth MOS transistor is connected to the first enable signal input terminal; the drain of the sixth MOS transistor is connected to the drain of the third MOS transistor; the source of the sixth MOS transistor is connected to the drain of the seventh MOS transistor; the source of the seventh MOS transistor is connected to the drain of the eighth MOS transistor; and the source of the eighth MOS transistor and the source of the fifth MOS transistor are grounded.

6. The LDO circuit as described in claim 5, characterized in that, The LDO circuit includes three current mirror current limiting branches; the first current mirror current limiting branch includes the sixth MOSFET, the seventh MOSFET and the eighth MOSFET, the second current mirror current limiting branch includes the ninth MOSFET, the tenth MOSFET and the eleventh MOSFET, and the third current mirror current limiting branch includes the twelfth MOSFET, the thirteenth MOSFET and the fourteenth MOSFET; The gate of the ninth MOS transistor is connected to the second enable signal input terminal; the source of the ninth MOS transistor is connected to the drain of the tenth MOS transistor; the source of the tenth MOS transistor is connected to the drain of the eleventh MOS transistor; the source of the eleventh MOS transistor is grounded; the drain of the ninth MOS transistor is connected to the drain of the third MOS transistor; the gate of the tenth MOS transistor is connected to the gate of the fourth MOS transistor; and the gate of the eleventh MOS transistor is connected to the gate of the fifth MOS transistor. The gate of the twelfth MOS transistor is connected to the third enable signal input terminal; the source of the twelfth MOS transistor is connected to the drain of the thirteenth MOS transistor; the source of the thirteenth MOS transistor is connected to the drain of the fourteenth MOS transistor; the source of the fourteenth MOS transistor is grounded; the drain of the tenth MOS transistor is connected to the drain of the third MOS transistor; the gate of the thirteenth MOS transistor is connected to the gate of the fourth MOS transistor; and the gate of the thirteenth MOS transistor is connected to the gate of the fifth MOS transistor.

7. The LDO circuit as described in claim 1, characterized in that, The LDO circuit also includes: A reference circuit, wherein a first output terminal of the reference circuit is connected to the reference voltage input terminal, and a second output terminal of the reference circuit is connected to the reference current input terminal; the reference circuit is used to provide the reference voltage and the reference current.

8. The LDO circuit as described in claim 7, characterized in that, The LDO circuit also includes a first power supply terminal, and the reference circuit includes a fifteenth MOS transistor, a sixteenth MOS transistor, a seventeenth MOS transistor, an eighteenth MOS transistor, an operational amplifier, a first transistor circuit, a second transistor circuit, a fourth resistor, a fifth resistor, a sixth resistor, and a seventh resistor; The sources of the fifteenth, sixteenth, seventeenth, and eighteenth MOS transistors are connected to the first power supply terminal; the gates of the fifteenth, sixteenth, seventeenth, and eighteenth MOS transistors are connected to the output terminal of the operational amplifier; the drain of the fifteenth MOS transistor, the first terminal of the first transistor circuit, and one end of the fourth resistor are connected to the inverting input terminal of the operational amplifier; the drain of the sixteenth MOS transistor, the non-inverting input terminal of the operational amplifier, and one end of the fifth resistor are connected to one end of the sixth resistor; the drain of the seventeenth MOS transistor and the reference voltage input terminal are connected to one end of the seventh resistor; the drain of the eighteenth MOS transistor is connected to the reference current input terminal. The input terminal is connected; the other end of the fifth resistor is connected to the first end of the second transistor circuit; the second end of the first transistor circuit, the other end of the fourth resistor, the second end of the second transistor circuit, the other end of the sixth resistor, and the other end of the seventh resistor are grounded; wherein, the first transistor circuit includes a plurality of first transistors, the emitters of the plurality of first transistors are all connected to the first end of the first transistor circuit, and the collectors and bases of the plurality of first transistors are all connected to the second end of the first transistor circuit; the second transistor circuit includes a plurality of second transistors, the emitters of the plurality of second transistors are all connected to the first end of the second transistor circuit, and the collectors and bases of the plurality of second transistors are all connected to the second end of the second transistor circuit.

9. The LDO circuit as described in any one of claims 1 to 8, characterized in that, It also includes a load resistor and a load capacitor, one end of the load resistor and one end of the load capacitor are connected to the LDO power output terminal, and the other end of the load resistor and the other end of the load capacitor are grounded.

10. A chip, characterized in that, Includes the LDO circuit as described in any one of claims 1 to 9.

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