L-band signal acquisition and playback system based on FPGA and dual-ADC architecture

Abstract

The invention discloses an L-band signal acquisition and playback system based on an FPGA (Field Programmable Gate Array) and a double-ADC (Analog to Digital Converter) architecture. The system comprises an acquisition and playback daughter board, an FPGA carrier board and a mainboard which are electrically connected in sequence, the acquisition and playback daughter board comprises a radio frequency front-end module, a clock module, a data acquisition module and a data playback module; the FPGA carrier plate comprises an interconnection module, a cache module, a clock management module, a data stream processing module, a chip configuration module, an AXI DataMover and a configuration unit module of the AXI DataMover. Based on an FPGA + ADC / DAC architecture, aiming at an L frequency band and a sub-band signal thereof, a modular design concept is adopted, an L frequency band signal acquisition and playback system based on an FPGA and double-ADC architecture is provided, the system uses two ADCs to cover high-resolution analysis requirements of a panoramic spectrum and a sub-band spectrum, and the system has a wide application prospect. And meanwhile, rich logic resources in the FPGA are fully utilized to improve the data transmission efficiency, and the design also has the characteristics of portability and high flexibility, and is very suitable for being applied to multiple fields such as radar detection, electronic countermeasure and test.

Description

Technical Field

[0001] The present invention relates to the technical field of signal acquisition and playback, and in particular to an L-band signal acquisition and playback system based on FPGA and dual ADC architecture. Background Art

[0002] RF signals are widely used in many fields such as radar detection, electronic countermeasures, and complex system testing. Therefore, high-speed acquisition and playback testing of RF signals has important application value. This type of test can simulate complex electromagnetic environments and provide strong support for the research and field testing of communication algorithms. As the frequency range of signals gradually expands, high-frequency signals are widely used in many important fields such as wireless communications and satellite navigation. Existing systems face greater challenges in algorithm design and hardware performance.

[0003] Nowadays, the L-band panoramic spectrum is usually acquired through segmented down-conversion and splicing, but there are problems such as slow processing rate, complex splicing and spurious signals; high-frequency sampling has large spurious signals, low resolution, and it is difficult to accurately analyze sub-band signals.

[0004] An ultra-wideband multi-channel high-speed signal acquisition and recording system and a data acquisition and storage method disclosed in a Chinese patent document with publication number CN116049062A include a main control unit, a chassis unit, a storage unit, a time signal interface unit, and a signal transceiver processing unit. The chassis unit is provided with a transmission bus for realizing high-speed signal interconnection in the system; the signal transceiver processing unit includes: a signal conditioning module, which is configured as at least two and has a multi-channel input and output function, and is used to realize at least two intermediate frequency signal The invention discloses a method for obtaining a high-speed signal through a plurality of channels, comprising: receiving and transmitting signal conditioning; a signal acquisition and playback module, which is configured as at least two and respectively connected to the storage unit and the two signal conditioning modules for data transmission, so as to complete the acquisition, generation and storage of different types of intermediate frequency signals; wherein the main control unit is loaded with a system software module for controlling the working mode and data transmission status of each unit, and samples, stores and plays back the input intermediate frequency signals adaptively or under the control of the operation instructions, and has flexible configuration and strong applicability. However, the ultra-wideband multi-channel high-speed signal acquisition and recording system and the data acquisition and storage method have the problems of slow processing rate, complex splicing and spurious.

[0005] A high-speed digital signal integrated processing device for wireless communication disclosed in the Chinese patent document with announcement number CN102999465B, the hardware part of the high-speed digital signal integrated processing device for wireless communication includes 5 intermediate frequency analog signal access devices and corresponding 5 intermediate frequency signal high-speed data processing boards, a high-speed data conversion and radio frequency transmission device and corresponding radio frequency high-speed data processing boards, high-speed interconnection baseboard, power supply module, main board, clock management device, the radio frequency high-speed data processing board and the FPGA in the intermediate frequency signal high-speed data processing board are interconnected through rapid IO to form a 3×5+2 FPGA array, and the FPGAs between the boards can call each other to share resources, and communicate with the main board using CPCI-E through the high-speed interconnection baseboard, and complete the corresponding high-speed data acquisition and radio frequency signal transmission, and the software part configures, controls and manages the whole machine. The present invention can complete the integrated operation of wireless communication transmission and reception, overcome the technical bottleneck in the design, and has the characteristics of strong computing power, wide application range, good engineering applicability, etc., but the high-speed digital signal integrated processing device for wireless communication has large spurious, low resolution, and is difficult to accurately analyze sub-band signals.

[0006] In order to solve the above-mentioned deficiencies in the prior art, it is a problem worth studying to provide an L-band signal acquisition and playback system based on FPGA and dual ADC architecture. Summary of the invention

[0007] The purpose of the present invention is to overcome the shortcomings of slow processing rate, complex splicing and spuriousness in the L-band panoramic spectrum acquisition process, and to provide an L-band signal acquisition and playback system based on FPGA and dual ADC architecture, which achieves the technical effect of using two ADCs to cover the high-resolution analysis requirements of the panoramic spectrum and sub-band spectrum.

[0008] The purpose of the present invention is achieved through the following technical solutions:

[0009] An L-band signal acquisition and playback system based on FPGA and dual ADC architecture, comprising an acquisition and playback sub-board, an FPGA carrier board and a main board electrically connected in sequence;

[0010] The acquisition and playback sub-board includes a radio frequency front-end module, a clock module, a data acquisition module and a data playback module;

[0011] The FPGA carrier board includes an interconnection module, a cache module, a clock management module, a data stream processing module, a chip configuration module, and an AXIDataMover and its configuration unit module;

[0012] The main board includes a CPU and a storage unit.

[0013] The input end of the RF front-end module on the acquisition and playback sub-board is used to access the RF signal, and the output end of the RF front-end outputs the RF signal and the intermediate frequency analog signal. The RF front-end module can receive and process the RF signal, and cooperate with the dual ADC architecture to use two ADCs to sample one or more channels simultaneously, thereby improving the sampling rate, which is crucial for systems that require high-speed and high-precision signal acquisition.

[0014] The FPGA carrier board is connected to the acquisition and playback daughter board through a JESD204B interface, a LVDS interface and an SPI interface.

[0015] The interconnection modules on the FPGA carrier board include an AXI central interconnection module, an AXI stream interconnection module and an AXI I / O interconnection module;

[0016] The cache module includes an upstream FIFO and a downstream FIFO;

[0017] The chip configuration module on the FPGA carrier board includes a clock chip configuration unit, an acquisition chip configuration unit, a playback chip configuration unit and a reset configuration unit;

[0018] The data stream processing module on the FPGA carrier board includes a broadband acquisition data stream processing module, an intermediate frequency acquisition data stream processing module, and a playback data stream processing module;

[0019] The AXIDataMover and its configuration unit module include an AXIDataMover module and an AXIDataMover configuration unit. By subdividing the interconnect modules on the FPGA carrier board, appropriate interconnect modules are selected according to application requirements, the data transmission path is optimized, and the overall system performance is improved. Different interconnect modules support different data transmission modes and topological structures, and are flexibly configured according to system requirements, thereby improving the flexibility and scalability of the system. The subdivided interconnect modules have clear functions and interface definitions, which reduces the complexity of system design and improves development efficiency.

[0020] The AXIDataMover module configures the transmission data file size according to user requirements. The FPGA carrier board and the main board are connected using the PCI e3.0 bus. By combining the AXIDataMover module with the PCI e 3.0 bus, an optimized data transmission path is constructed to achieve efficient and reliable data transmission from the data source to the target.

[0021] The center frequency of the intermediate frequency analog signal output by the RF front end is 140MHz, and the bandwidth is 40MHz. The acquisition and playback sub-board acquires a panoramic spectrum frequency range of 950MHz to 2150MHz, and the processed intermediate frequency signal bandwidth is 40MHz.

[0022] The sampling rates of the two analog-to-digital converters of the data acquisition module in the acquisition and playback sub-board are 5 GSPS and 112 MHz respectively.

[0023] An L-band signal acquisition and playback method based on FPGA and dual ADC architecture includes the following steps:

[0024] Step 1: The user program on the main board first issues a broadband acquisition command, and the RF front end outputs a RF signal to complete broadband acquisition, and transmits the collected high-speed data to the FPGA carrier board via the JESD204B interface. After being processed by the acquisition playback data stream processing and integration module, it is sent to the FIFO to wait for data formation and conversion of clock domain;

[0025] Step 2: AXIDataMover writes the high-speed data stream into the cache at the specified address of the motherboard DDR through the AXI stream interconnection and XDMA via the PCIe3.0 interface according to the configured parameters. After writing, it is stored in the hard disk to complete the storage operation;

[0026] Step 3: The user adjusts the parameters of the RF front end after analyzing the panoramic spectrum;

[0027] Step 4: During playback, AXIDataMover takes data from the specified address and converts it to the FIFO clock domain through the PCIe3.0 interface. After being processed by the acquisition and playback data processing and integration module, it is sent to the digital-to-analog conversion chip for playback operation and sent to the target frequency by the up-converter.

[0028] In the step one, two analog-to-digital converters are used to perform analog-to-digital conversion on the RF signal and the intermediate frequency analog signal output by the RF front end, and a digital signal data stream is output. The two ADCs are used to process the RF signal and the intermediate frequency signal respectively, thereby increasing the flexibility of signal processing. Since the RF signal and the intermediate frequency signal have different frequency characteristics and processing requirements, performing analog-to-digital conversion separately can better meet these requirements.

[0029] The parameters configured in step 2 are determined by the user according to the size of the collected file, and the user sends instructions to the DataMover configuration unit. The configuration unit writes the instructions into the corresponding registers. AXIDataMover identifies the values ​​of each register and confirms the file size, transfer direction and target address before starting to execute the transfer task.

[0030] After adjusting the parameters of the RF front end in the step three, if no target signal is found, the broadband acquisition operation is continued. If the target signal is found, the corresponding center frequency is input to the RF front end, and the signal with a center frequency of 140MHz and a bandwidth of 40MHz is output. The intermediate frequency acquisition is completed by the acquisition and playback module, and transmitted to the FPGA carrier board through the LVDS interface for reception and integration, and then sent to the mainboard for storage through the PCIe3.0 interface.

[0031] Positive and beneficial effects: 1. This L-band signal acquisition and playback system based on FPGA and dual ADC architecture is based on FPGA+ADC / DAC architecture. It adopts modular design concept for L-band and its sub-band signals. It proposes an L-band signal acquisition and playback system based on FPGA and dual ADC architecture. The system uses two ADCs to cover the high-resolution analysis requirements of panoramic spectrum and sub-band spectrum, and makes full use of the rich logic resources inside FPGA to improve data transmission efficiency. In addition, the design is also portable and highly flexible, which is very suitable for radar detection, electronic countermeasures, testing and other fields.

[0032] 2. The L-band signal acquisition and playback system based on FPGA and dual ADC architecture, the AXIDataMover module can flexibly configure the size of the transmitted data file according to user needs, adapt to different data transmission requirements, improve the flexibility and adaptability of the system, support high-throughput data transmission, and can efficiently process large amounts of data, thereby improving the overall performance of the system.

[0033] 3. The L-band signal acquisition and playback system based on FPGA and dual ADC architecture uses two ADCs to process RF signals and IF signals respectively, which increases the flexibility of signal processing. Since RF signals and IF signals have different frequency characteristics and processing requirements, separate analog-to-digital conversion is performed to better meet these requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 It is a schematic diagram of the system structure of the present invention;

[0035] Figure 2 It is a top-level diagram of data transmission logic;

[0036] Figure 3 This is a schematic diagram of the AXIDataMover workflow;

[0037] Figure 4 The diagram is a schematic diagram of the system workflow. DETAILED DESCRIPTION

[0038] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and should not be construed as limiting the present invention.

[0039] Example 1

[0040] like Figures 1 to 4As shown, an L-band signal acquisition and playback system based on FPGA and dual ADC architecture includes an acquisition and playback sub-board, an FPGA carrier board and a main board electrically connected in sequence;

[0041] The acquisition and playback sub-board includes a radio frequency front-end module, a clock module, a data acquisition module, and a data playback module;

[0042] The FPGA carrier board includes an interconnect module, a cache module, a clock management module, a data stream processing module, a chip configuration module, and an AXIDataMover and its configuration unit module;

[0043] The motherboard includes the CPU and the memory unit.

[0044] like Figure 1 As shown, the input end of the RF front-end module on the acquisition and playback sub-board is used to access the RF signal, and the output end of the RF front-end outputs the RF signal and the intermediate frequency analog signal. The RF front-end module can receive and process the RF signal, and cooperate with the dual ADC architecture to use two ADCs to sample one or more channels at the same time, thereby improving the sampling rate, which is crucial for systems that require high-speed and high-precision signal acquisition. The RF front-end module can receive and process the RF signal, and cooperate with the dual ADC architecture to use two ADCs to sample one or more channels at the same time, thereby improving the sampling rate, which is crucial for systems that require high-speed and high-precision signal acquisition.

[0045] Furthermore, the RF front-end module is able to receive and process RF signals, and with the dual ADC architecture, use two ADCs to sample one or more channels simultaneously, thereby increasing the sampling rate, which is critical for systems that require high-speed, high-precision signal acquisition.

[0046] The FPGA carrier board is connected to the acquisition and playback daughter board through the JESD204B interface, LVDS interface and SPI interface. The JESD204B interface is used to transmit the broadband acquisition data stream from the acquisition and playback daughter board to the FPGA carrier board. The LVDS interface is used to transmit the intermediate frequency acquisition data stream from the acquisition and playback daughter board to the FPGA carrier board and to transmit the playback data stream from the FPGA carrier board to the acquisition and playback daughter board. The SPI interface is used to transmit the control instructions issued from the main board and distributed through the interconnection module.

[0047] like Figure 1 As shown, the interconnection modules on the FPGA carrier board include an AXI central interconnection module, an AXI stream interconnection module, and an AXII / O interconnection module;

[0048] The cache module includes an upstream FIFO and a downstream FIFO;

[0049] The chip configuration module on the FPGA carrier board includes a clock chip configuration unit, an acquisition chip configuration unit, a playback chip configuration unit, and a reset configuration unit;

[0050] The data stream processing module on the FPGA carrier board includes a broadband acquisition data stream processing module, an intermediate frequency acquisition data stream processing module, and a playback data stream processing module;

[0051] AXIDataMover and its configuration unit modules include AXIDataMover module and AXIDataMover configuration unit. By subdividing the interconnect modules on the FPGA carrier board, appropriate interconnect modules are selected according to application requirements, the data transmission path is optimized, and the overall system performance is improved. Different interconnect modules support different data transmission modes and topological structures, and can be flexibly configured according to system requirements, thereby improving the flexibility and scalability of the system. The subdivided interconnect modules have clear functions and interface definitions, which reduces the complexity of system design and improves development efficiency.

[0052] The uplink FIFO in the cache module acts as a data buffer to store data from the upper module or external devices. When the data input rate does not match the rate of the subsequent processing module, the FIFO smoothes the rate difference to prevent data loss. The downlink FIFO temporarily stores the data from the upper module and outputs it synchronously according to the processing rate of the lower module. This helps to achieve synchronous data transmission between different modules. The coordinated use of the uplink FIFO and the downlink FIFO significantly improves the data transmission efficiency of the system. By caching and synchronizing data, they reduce the waiting time in data transmission and improve the system response speed. The use of FIFO helps prevent data loss and disorder, thereby enhancing the reliability of the system. During the data transmission process, even if there is a short rate mismatch or interruption, the FIFO ensures the integrity and order of the data.

[0053] Based on FPGA+ADC / DAC architecture, a modular design concept is adopted for L-band and its sub-band signals. A L-band signal acquisition and playback system based on FPGA and dual ADC architecture is proposed. The system uses two ADCs to cover the high-resolution analysis requirements of the panoramic spectrum and sub-band spectrum, and makes full use of the rich logic resources inside the FPGA to improve data transmission efficiency. In addition, the design is also portable and highly flexible, which is very suitable for radar detection, electronic countermeasures, testing and other fields.

[0054] like Figures 2 to 4 As shown, a method for collecting and replaying L-band signals based on FPGA and dual ADC architecture includes the following steps:

[0055] Step 1: The user program on the main board first issues a broadband acquisition command, and the RF front end outputs a RF signal to complete broadband acquisition, and transmits the collected high-speed data to the FPGA carrier board via the JESD204B interface. After being processed by the acquisition playback data stream processing and integration module, it is sent to the FIFO to wait for data formation and conversion of clock domain;

[0056] Step 2: AXIDataMover writes the high-speed data stream into the cache at the specified address of the motherboard DDR through the AXI stream interconnection and XDMA via the PCIe3.0 interface according to the configured parameters. After writing, it is stored in the hard disk to complete the storage operation;

[0057] Step 3: The user adjusts the parameters of the RF front end after analyzing the panoramic spectrum;

[0058] Step 4: During playback, AXIDataMover takes data from the specified address and converts it to the FIFO clock domain through the PCIe3.0 interface. After being processed by the acquisition and playback data processing and integration module, it is sent to the digital-to-analog conversion chip for playback operation and sent to the target frequency by the up-converter.

[0059] Example 2

[0060] like Figure 1 to Figure 2 As shown, the AXIDataMover module configures the size of the data file to be transmitted according to user needs. The FPGA carrier board and the main board are connected using the PCIe3.0 bus. The AXIDataMover module can flexibly configure the size of the data file to be transmitted according to user needs, adapt to different data transmission requirements, improve the flexibility and adaptability of the system, support high-throughput data transmission, and efficiently process large amounts of data, thereby improving the overall performance of the system. The AXIDataMover module provides a byte-level data rearrangement function, and performs memory reading and writing of any byte offset position, which helps to handle complex data operation requirements.

[0061] By combining the AXIDataMover module with the PCIe 3.0 bus, an optimized data transmission path is constructed to achieve efficient and reliable data transmission from the data source to the target.

[0062] The center frequency of the intermediate frequency analog signal output by the RF front end is 140MHz, and the bandwidth is 40MHz. The acquisition and playback sub-board acquires a full spectrum frequency range of 950MHz to 2150MHz, and the processed intermediate frequency signal bandwidth is 40MHz.

[0063] The sampling rates of the two analog-to-digital converters in the data acquisition module in the acquisition and playback daughter board are 5GSPS and 112MHz respectively.

[0064] Example 3

[0065] like Figure 1 As shown, in step 1, two analog-to-digital converters are used to perform analog-to-digital conversion on the RF signal and the intermediate frequency analog signal output by the RF front end, and output digital signal data streams. Two ADCs are used to process the RF signal and the intermediate frequency signal respectively, which increases the flexibility of signal processing. Since the RF signal and the intermediate frequency signal have different frequency characteristics and processing requirements, the analog-to-digital conversion is performed separately to better meet these requirements. The two ADCs work independently, and each ADC optimizes the sampling rate and resolution according to the type of signal it processes. This helps to ensure that the details of the signal are captured during the acquisition process, thereby improving the fidelity and accuracy of the signal. The FPGA has a powerful parallel processing capability, and two ADCs are used to fully utilize this advantage to process the RF signal and the intermediate frequency signal in parallel, significantly reducing the processing time and improving the real-time performance of the system.

[0066] Furthermore, the RF signal and the IF signal may overlap or interfere in frequency. Using two ADCs to process them separately can reduce interference between the signals and improve signal purity and quality.

[0067] like Figure 3 As shown, the parameters configured in step 2 are determined by the user according to the size of the collected file, and the user sends instructions to the DataMover configuration unit. The configuration unit writes the instructions into the corresponding registers. AXIDataMover identifies the values ​​of each register and confirms the file size, transfer direction and target address before starting to execute the transfer task.

[0068] like Figure 4 As shown, after adjusting the parameters of the RF front end in step 3, if no target signal is found, the broadband acquisition operation continues. If the target signal is found, the corresponding center frequency is input to the RF front end, and the signal with a center frequency of 140MHz and a bandwidth of 40MHz is output. The intermediate frequency acquisition is completed by the acquisition and playback module, and transmitted to the FPGA carrier board through the LVDS interface for reception and integration, and then sent to the mainboard for storage through the PCIe3.0 interface.

Claims

1. An L-band signal acquisition and playback system based on FPGA and dual ADC architecture, characterized by: It includes a collection and playback sub-board, an FPGA carrier board and a main board which are electrically connected in sequence; The acquisition and playback sub-board includes a radio frequency front-end module, a clock module, a data acquisition module and a data playback module; The FPGA carrier board includes an interconnection module, a cache module, a clock management module, a data stream processing module, a chip configuration module, and an AXIDataMover and its configuration unit module; The main board includes a CPU and a storage unit.

2. The L-band signal acquisition and playback system based on FPGA and dual ADC architecture according to claim 1, characterized in that: The input end of the RF front-end module on the acquisition and playback sub-board is used to access the RF signal, and the output end of the RF front-end outputs the RF signal and the intermediate frequency analog signal.

3. The L-band signal acquisition and playback system based on FPGA and dual ADC architecture according to claim 1, characterized in that: The FPGA carrier board is connected to the acquisition and playback daughter board through a JESD204B interface, a LVDS interface and an SPI interface.

4. The L-band signal acquisition and playback system based on FPGA and dual ADC architecture according to claim 1, characterized in that: The interconnection modules on the FPGA carrier board include an AXI central interconnection module, an AXI stream interconnection module and an AXI I / O interconnection module; The cache module includes an upstream FIFO and a downstream FIFO; The chip configuration module on the FPGA carrier board includes a clock chip configuration unit, an acquisition chip configuration unit, a playback chip configuration unit and a reset configuration unit; The data stream processing module on the FPGA carrier board includes a broadband acquisition data stream processing module, an intermediate frequency acquisition data stream processing module, and a playback data stream processing module; The AXIDataMover and its configuration unit module include an AXIDataMover module and an AXIDataMover configuration unit.

5. The L-band signal acquisition and playback system based on FPGA and dual ADC architecture according to claim 1, characterized in that: The AXIDataMover module configures the size of the data file to be transmitted according to user requirements, the FPGA carrier board and the main board are connected using the PCIe3.0 bus, and the AXIDataMover module stores the data into the storage unit of the main board through the PCIe3.0 bus.

6. The L-band signal acquisition and playback system based on FPGA and dual ADC architecture according to claim 1, characterized in that: The center frequency of the intermediate frequency analog signal output by the RF front end is 140MHz, and the bandwidth is 40MHz. The acquisition and playback sub-board has an acquisition panoramic spectrum frequency range of 950MHz to 150MHz, and the processed intermediate frequency signal bandwidth is 40MHz. The sampling rates of the two analog-to-digital converters of the data acquisition module in the acquisition and playback sub-board are 5GSPS and 112MHz respectively.

7. A method for collecting and replaying L-band signals based on FPGA and dual ADC architecture according to claims 1-6, characterized in that: The following steps are involved: Step 1: The user program on the main board first issues a broadband acquisition instruction, and the RF front end outputs a RF signal to complete broadband acquisition, and transmits the collected high-speed data to the FPGA carrier board via the JESD204B interface. After being processed by the acquisition playback data stream processing and integration module, it is sent to the FIFO to wait for data formation and conversion of clock domain; Step 2: AXIDataMover writes the high-speed data stream into the cache at the specified address of the motherboard DDR through the AXI stream interconnection and XDMA via the PCIe3.0 interface according to the configured parameters. After writing, it is stored in the hard disk to complete the storage operation; Step 3: The user adjusts the parameters of the RF front end after analyzing the panoramic spectrum; Step 4: During playback, AXIDataMover takes data from the specified address and converts it to the FIFO clock domain through the PCIe3.0 interface. After being processed by the acquisition and playback data processing and integration module, it is sent to the digital-to-analog conversion chip for playback operation and sent to the target frequency by the up-converter.

8. The L-band signal acquisition and playback method based on FPGA and dual ADC architecture according to claim 7, characterized in that: In the step 1, two analog-to-digital converters are used to perform analog-to-digital conversion on the radio frequency signal and the intermediate frequency analog signal output by the radio frequency front end, respectively, and output a digital signal data stream.

9. The L-band signal acquisition and playback method based on FPGA and dual ADC architecture according to claim 7, characterized in that: The parameters configured in step 2 are determined by the user according to the size of the collected file, and the user sends instructions to the DataMover configuration unit. The configuration unit writes the instructions into the corresponding registers. AXIDataMover identifies the values ​​of each register and confirms the file size, transfer direction and target address before starting to execute the transfer task.

10. The L-band signal acquisition and playback system based on FPGA and dual ADC architecture according to claim 7, characterized in that: After adjusting the parameters of the RF front end in the step three, if no target signal is found, the broadband acquisition operation is continued. If the target signal is found, the corresponding center frequency is input to the RF front end, and the signal with a center frequency of 140MHz and a bandwidth of 40MHz is output. The intermediate frequency acquisition is completed by the acquisition and playback module, and transmitted to the FPGA carrier board through the LVDS interface for reception and integration, and then sent to the mainboard for storage through the PCIe3.0 interface.

Images