Multistage adjustable nonlinear random entropy source circuit system

Abstract

The invention relates to a multi-stage adjustable nonlinear random entropy source circuit system, which comprises K stages of circuits cascaded in sequence, the first-stage circuit comprises a plurality of basic units, the second-stage circuit to the Kth-stage circuit comprise a plurality of combination units, the number of the combination units in the second-stage circuit is half of the number of the basic units in the first-stage circuit, and in the third-stage circuit to the Kth-stage circuit, the number of the combination units in each stage circuit is half of the number of the combination units in the previous stage circuit. The number of the combination units in the Kth-stage circuit is 1; every two basic units in the first-stage circuit are connected to one combined unit in the second-stage circuit; the output ends of every two combination units of the second-stage circuit to the (K-1) th-stage circuit are connected with the two input ends of one combination unit in the next-stage circuit. The output end of the Kth-stage circuit serves as the output end of the circuit system; each basic unit is used for generating square waves with nonlinear clock jitter; and the combination unit is used for performing jitter amplification on the input signal and outputting a square wave with larger clock jitter.

Description

Technical Field

[0001] The present invention relates to the field of information security technology, and in particular to a multi-level adjustable nonlinear random entropy source circuit system. Background Art

[0002] A True Random Number Generator (TRNG) is a device or mechanism that can generate truly random numbers. True random numbers are unpredictable, non-periodic, and have the essential characteristics of randomness. The principles of their generation are generally as follows:

[0003] First, use thermal noise to generate truly random numbers. Thermal noise is generated by the thermal motion of electrons in electronic components and is random. This method is used in some chipsets to generate truly random numbers. Second, generate truly random numbers based on quantum properties. The quantum world is truly random in nature. Through the characteristics of quantum mechanics, find a random and unpredictable event to generate truly random numbers. Third, generate truly random numbers from other physical sources. Cosmic rays, particle decay, air noise, etc. can also be used as random sources to generate random numbers.

[0004] A device that can express a certain random characteristic is called an "entropy source". Entropy sources are generally used in cryptography, computer information security, scientific research and other fields.

[0005] In the field of cryptography, random numbers are the basis of cryptographic algorithms and one of the most important parts of modern encryption systems. In cryptography, true random numbers are used to generate keys and other key operations. For example, in symmetric encryption algorithms, the randomness of the key directly affects the security of encryption. If the key is not truly random, it may be cracked by attackers. True random number generators provide higher security for cryptographic applications because the random numbers they generate are unpredictable, greatly increasing the difficulty of password cracking.

[0006] In the field of computer security, websites and browsers use session keys to encrypt data sent between them, and the generation of this session key often requires a random number. True random number generators can provide a reliable source of random numbers for computer security-related operations to prevent security issues such as data theft or tampering. For example, in the SSL / TLS protocol, random numbers are used to generate session keys and other operations to ensure the security of network communications.

[0007] In the field of scientific research and academia, in some simulation experiments, truly random data is needed to simulate natural phenomena or random processes. There are also some studies involving probability statistics. If true random numbers are not used, it may lead to deviations in research results. In quantum physics research, many random phenomena at the quantum level are involved. The random numbers generated by true random number generators can be used to simulate or assist in the study of these quantum phenomena. At present, there are websites that provide true random number services specifically for academic and scientific research institutions, such as Quantum Random Bit Generator Service (QRBGS). Its randomness depends on the inherent randomness of the quantum physics process of semiconductor photon divergence. Photons are detected through the photoelectric effect. These randomly detected photons are independent of each other, providing a reliable source of random numbers for scientific research. Summary of the invention

[0008] In view of the above analysis, an embodiment of the present invention aims to provide a multi-stage adjustable nonlinear random entropy source circuit system to solve the problem that the existing entropy source is difficult to generate truly random numbers.

[0009] An embodiment of the present invention provides a multi-stage adjustable nonlinear random entropy source circuit system, the circuit system comprising: K stages of circuits cascaded in sequence; the first stage circuit comprises a plurality of basic units, the second to K-th stage circuits comprise a plurality of combination units, and the number of combination units in the second stage circuit is half of the number of basic units in the first stage circuit, and in the third to K-th stage circuits, the number of combination units in each stage circuit is half of the number of combination units in the previous stage circuit, and the number of combination units in the K-th stage circuit is 1; every two basic units in the first stage circuit are connected to a combination unit in the second stage circuit; the output ends of every two combination units in the second to K-1 stage circuits are connected to two input ends of a combination unit in the next stage circuit; the output end of the K-th stage circuit serves as the output end of the circuit system; each basic unit is used to generate a square wave with nonlinear clock jitter; the combination unit is used to perform jitter amplification on the input signal and output a square wave with greater clock jitter.

[0010] Furthermore, each combination unit includes two isolation units and one nonlinear unit, and the nonlinear unit has a dual-port input and single-port output structure; the input ends of the two isolation units serve as the two input ends of the combination unit, and the signal output ends of the two isolation units are respectively connected to a signal input end of the nonlinear unit; any one of the two input ends of the nonlinear unit serves as the output end of the combination unit.

[0011] Furthermore, the basic unit includes a first nonlinear adjustable ring oscillator module, a second nonlinear adjustable ring oscillator module, a first isolation enhancement module, a second isolation enhancement module, and a nonlinear unit. The first nonlinear adjustable ring oscillator module and the second nonlinear adjustable ring oscillator module are used to generate clocks of different frequencies under the action of a control signal; the clocks of different frequencies are respectively input to the nonlinear unit via the first isolation enhancement module and the second isolation enhancement module, and the nonlinear unit is used to add nonlinear jitter to the two input clocks of different frequencies to output a square wave of nonlinear clock jitter.

[0012] Furthermore, the first nonlinear adjustable ring oscillator module and the second nonlinear adjustable ring oscillator module have the same structure, and both include: N1 inverters and M1 nonlinear units, the N1 inverters are cascaded in sequence, and the output end of the last inverter is connected to the input end of the first inverter; the two input ends of each nonlinear unit are respectively provided with N1 groups of parallel switches, one end of each group of switches is connected to the two input ends of the nonlinear unit, and the other end of each group of switches is connected to the output end of an inverter; the output of the last inverter is used as the output end of the nonlinear adjustable ring oscillator module; wherein N1 is an odd number.

[0013] Furthermore, the first isolation enhancement module, the second isolation enhancement module, and the isolation unit have the same structure, and all include: a front-stage inverter and a rear-stage inverter; the output end of the front-stage inverter is connected to the input end of the rear-stage inverter; the size of the front-stage inverter is smaller than the first threshold; and the driving current of the rear-stage inverter is adapted to the driving current of the nonlinear unit.

[0014] Further, the front-stage inverter includes a third PMOS tube and a third NMOS tube connected in parallel; the gates of the third PMOS tube and the third NMOS tube are connected as the input end of the front-stage inverter; the drains of the third PMOS tube and the third NMOS tube are connected as the output end of the front-stage inverter; the source of the third PMOS tube is connected to the power supply VDD; the source of the third NMOS tube is grounded; the rear-stage inverter includes: a fourth PMOS tube, a fifth PMOS tube, a fourth NMOS tube and a fifth NMOS tube; the gates of the fourth PMOS tube, the fifth PMOS tube, the fourth NMOS tube and the fifth NMOS tube are connected as the input end of the rear-stage inverter; the source of the fourth PMOS tube is connected to the power supply VDD; the source of the fifth NMOS tube is grounded; the drain of the fourth PMOS tube is connected to the source of the fifth PMOS tube; the drain of the fifth PMOS tube is connected to the drain of the fourth NMOS tube and serves as the output end of the rear-stage inverter; the source of the fourth NMOS tube is connected to the drain of the fifth NMOS tube.

[0015] Further, the non-linear units in the basic unit and the non-linear units in the combination unit have the same structure, and both include a chaotic circuit with negative feedback; the chaotic circuit includes a first conduction module, a phase adjustment module, and a second conduction module connected in parallel; one parallel end of the first conduction module, the phase adjustment module, and the second conduction module serves as the first input end of the non-linear unit, and the other parallel end serves as the second input end of the non-linear unit; one of the first input end or the second input end serves as the output end of the non-linear unit.

[0016] Further, the phase adjustment module includes a sixth PMOS transistor, a sixth NMOS transistor, a pull-up load, and a pull-down load; the gate of the sixth PMOS transistor is connected to the drain of the sixth NMOS transistor and serves as the first input end of the phase adjustment module; the drain of the sixth PMOS transistor is connected to the gate of the sixth NMOS transistor and serves as the second input end of the phase adjustment module; the source of the sixth PMOS transistor is connected to the power supply VDD through the pull-up load; the source of the sixth NMOS transistor is grounded through the pull-down load.

[0017] Further, the pull-up load includes a resistor or a seventh PMOS transistor; when including the seventh PMOS transistor, the gate of the seventh PMOS transistor is connected to a control signal to make it in a conducting state, the source is connected to the power supply VDD, and the drain is connected to the source of the sixth PMOS transistor; alternatively, the gate and the drain of the seventh PMOS transistor are connected and then connected to the source of the sixth PMOS transistor, and at the same time the source of the seventh PMOS transistor is connected to the power supply VDD;

[0018] The pull-down load includes a resistor or a seventh NMOS transistor; when including the seventh NMOS transistor, the gate of the seventh NMOS transistor is connected to a control signal to make it in a conducting state, the source is grounded, and the drain is connected to the source of the sixth NMOS transistor; alternatively, the gate and the drain of the seventh NMOS transistor are connected and then connected to the source of the sixth NMOS transistor, and at the same time the source of the seventh NMOS transistor is grounded.

[0019] Further, each of the first conduction module and the second conduction module includes an identical transmission gate, one input end of each transmission gate is connected to the first input end of the phase adjustment module, and the other input end of each transmission gate is connected to the second input end of the phase adjustment module; the control end of the transmission gate is connected to the power supply VDD or an external control signal.

[0020] Compared with the prior art, the present invention can at least achieve one of the following beneficial effects:

[0021] 1. A multi-stage adjustable nonlinear random entropy source circuit system of the present invention comprises: K stages of circuits cascaded in sequence; the first stage circuit comprises a plurality of basic units, the second to K-th stage circuits comprise a plurality of combination units, and the number of combination units in the second stage circuit is half of the number of basic units in the first stage circuit, and in the third to K-th stage circuits, the number of combination units in each stage circuit is half of the number of combination units in the previous stage circuit, and the number of combination units in the K-th stage circuit is 1; every two basic units in the first stage circuit are connected to a combination unit in the second stage circuit; the output ends of every two combination units in the second to K-1 stage circuits are connected to two input ends of a combination unit in the next stage circuit; the output end of the K-th stage circuit serves as the output end of the circuit system; the present invention aims to provide a multi-stage adjustable nonlinear random entropy source architecture; the random entropy source architecture has the characteristics of multi-stage multiplexing, adjustability, and easy parameter adjustment, and has good feasibility and randomness.

[0022] 2. In each combination unit of a multi-stage adjustable nonlinear random entropy source circuit system of the present invention, the isolation unit includes a front-stage inverter and a rear-stage inverter; the output end of the front-stage inverter is connected to the input end of the rear-stage inverter; the size of the front-stage inverter is smaller than the first threshold; the driving current of the rear-stage inverter is adapted to the driving current of the nonlinear unit. The isolation unit has the function of isolating the basic unit from the nonlinear unit, has the characteristics of good stability, and also has the effect of adjusting the output signal driving capability of the basic unit and the front-stage combination unit.

[0023] 3. The first nonlinear adjustable ring oscillator module and the second nonlinear adjustable ring oscillator module of the basic unit in the multi-stage adjustable nonlinear random entropy source circuit system of the present invention both include: a plurality of inverters and a plurality of nonlinear units, wherein the plurality of inverters are sequentially cascaded, and the output end of the last inverter is connected to the input end of the first inverter; the two input ends of each nonlinear unit are respectively provided with a plurality of groups of parallel switches, one end of each group of switches is connected to the two input ends of the nonlinear unit, and the other end of each group of switches is respectively connected to the output end of an inverter; the output of the last inverter is used as the output end of the nonlinear adjustable ring oscillator module; wherein the number of inverters is an odd number. The basic unit generates a square wave with a certain nonlinear clock jitter, which increases the randomness of the entropy source.

[0024] 4. The nonlinear unit of a multi-stage adjustable nonlinear random entropy source circuit system of the present invention is a dual-port input and single-port output structure; the nonlinear unit structure includes a chaotic circuit with negative feedback; the chaotic circuit includes a first conduction module, a phase adjustment module, and a second conduction module connected in parallel; one parallel end of the first conduction module, the phase adjustment module, and the second conduction module serves as the first input end of the nonlinear unit, and the other parallel end serves as the second input end of the nonlinear unit; one of the first input end or the second input end serves as the output end of the nonlinear unit. This structure enables the random entropy source of the present invention to have the advantages of strong randomness, sensitivity to noise, and low power consumption. It can be used in information security fields such as equipment authentication, random number generation, and IP protection, effectively improving the security and practicality of the system.

[0025] In the present invention, the above-mentioned technical solutions can also be combined with each other to achieve more preferred combination solutions. Other features and advantages of the present invention will be described in the subsequent description, and some advantages can become obvious from the description, or can be understood by practicing the present invention. The purpose and other advantages of the present invention can be achieved and obtained through the contents particularly pointed out in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The drawings are only for the purpose of illustrating particular embodiments and are not to be considered limiting of the present invention. Like reference symbols denote like components throughout the drawings.

[0027] Figure 1 A block diagram of a random entropy source composed of two basic units in a multi-stage adjustable nonlinear random entropy source circuit system of the present invention;

[0028] Figure 2 A multi-stage adjustable nonlinear random entropy source circuit system of the present invention includes a random entropy source block diagram of a multi-stage combination unit;

[0029] Figure 3 This is a schematic diagram of the basic unit structure of a multi-stage adjustable nonlinear random entropy source circuit system of the present invention;

[0030] Figure 4 A circuit diagram of a nonlinear adjustable ring oscillator module of a multi-stage adjustable nonlinear random entropy source circuit system of the present invention;

[0031] Figure 5 It is a circuit diagram of an inverter at the control end of a multi-stage adjustable nonlinear random entropy source circuit system of the present invention;

[0032] Figure 6 This is a circuit diagram of an isolation enhancement module of a multi-stage adjustable nonlinear random entropy source circuit system of the present invention;

[0033] Figure 7A nonlinear unit circuit diagram of a multi-stage adjustable nonlinear random entropy source circuit system of the present invention;

[0034] Figure 8 The present invention is a circuit diagram of a nonlinear unit of a multi-stage adjustable nonlinear random entropy source circuit system according to a specific embodiment of the present invention.

[0035] Reference numerals:

[0036] 1- the first PMOS tube;

[0037] 2- the second PMOS tube;

[0038] 3- the second NMOS tube;

[0039] 4- the first NMOS tube;

[0040] 5- the third PMOS tube;

[0041] 6- the fourth PMOS tube;

[0042] 7- the third NMOS tube;

[0043] 8- fifth PMOS tube;

[0044] 9- the fourth NMOS tube;

[0045] 10- fifth NMOS tube;

[0046] 11-sixth NMOS tube;

[0047] 12-a first conduction module;

[0048] 13- second conduction module;

[0049] 14- the sixth PMOS tube. DETAILED DESCRIPTION

[0050] The preferred embodiments of the present invention are described in detail below in conjunction with the accompanying drawings, wherein the accompanying drawings constitute a part of this application and are used together with the embodiments of the present invention to illustrate the principles of the present invention, but are not used to limit the scope of the present invention.

[0051] A specific embodiment of the present invention discloses a multi-level adjustable nonlinear random entropy source circuit system, such as Figure 2As shown. The circuit system comprises: K levels of circuits cascaded in sequence; the first level circuit comprises a plurality of basic units, the second to K-th level circuits comprise a plurality of combination units, and the number of combination units in the second level circuit is half of the number of basic units in the first level circuit, and in the third to K-th level circuits, the number of combination units in each level circuit is half of the number of combination units in the previous level circuit, and the number of combination units in the K-th level circuit is 1; every two basic units in the first level circuit are connected to a combination unit in the second level circuit; the output ends of every two combination units in the second to K-1 level circuits are connected to two input ends of a combination unit in the next level circuit; the output end of the K-th level circuit serves as the output end of the circuit system; each basic unit is used to generate a square wave with nonlinear clock jitter; the combination unit is used to perform jitter amplification on the input signal and output a square wave with greater clock jitter.

[0052] The block diagram of the random entropy source composed of two basic units is as follows Figure 1 shown.

[0053] Specifically, the number of circuit stages can be selected according to actual application requirements. Generally speaking, the more stages there are, the greater the clock jitter, the better the stability of the random entropy source, and the stronger the randomness.

[0054] The basic unit includes a first nonlinear adjustable ring oscillator module, a second nonlinear adjustable ring oscillator module, a first isolation enhancement module, a second isolation enhancement module, and a nonlinear unit. The first nonlinear adjustable ring oscillator module and the second nonlinear adjustable ring oscillator module are used to generate clocks of different frequencies under the action of a control signal; the clocks of different frequencies are respectively input to the nonlinear unit through the first isolation enhancement module and the second isolation enhancement module. The first isolation enhancement module and the second isolation enhancement module are used to isolate the connected nonlinear adjustable ring oscillator module and the nonlinear unit. The nonlinear unit is used to add nonlinear jitter to the input two different frequency clocks to output a square wave of nonlinear clock jitter. Each basic unit generates a square wave with a certain nonlinear clock jitter to increase the randomness of the entropy source.

[0055] The basic unit structure diagram is as follows Figure 3 shown.

[0056] Specifically, the first isolation enhancement module and the second isolation enhancement module respectively have an input port and an output port. The input ports of the first isolation enhancement module and the second isolation enhancement module are respectively connected to the output ports of the first nonlinear adjustable ring oscillator module and the second nonlinear adjustable ring oscillator module, and the output ports of the first isolation enhancement module and the second isolation enhancement module are respectively connected to the input port of the nonlinear unit.

[0057] The block diagram of the random entropy source including multi-level combination units is as follows: Figure 2 shown.

[0058] The random entropy source has the advantages of good stability, strong randomness, sensitivity to noise, low power consumption, and multi-level adjustability.

[0059] The first nonlinear adjustable ring oscillator module and the second nonlinear adjustable ring oscillator module have the same structure, and both include: N1 inverters and M1 nonlinear units, wherein the N1 inverters are cascaded in sequence, and the output end of the last inverter is connected to the input end of the first inverter; the two input ends of each nonlinear unit are respectively provided with N1 groups of parallel switches, one end of each group of switches is connected to the two input ends of the nonlinear unit, and the other end of each group of switches is respectively connected to the output end of an inverter; the output of the last inverter is used as the output end of the nonlinear adjustable ring oscillator module; wherein N1 is an odd number.

[0060] Specifically, the first nonlinear adjustable ring oscillator module and the second nonlinear adjustable ring oscillator are used to generate clock signals of different frequencies, and the number of inverters and nonlinear units used by the first nonlinear adjustable ring oscillator module and the second nonlinear adjustable ring oscillator can be the same or different. The N1 group of switches receives a control signal from a controller, and the control signal controls one switch in each of the two groups of the N1 group of switches to be closed, and the rest to be opened. It represents the number of ways to select 2 different output ends from the output ends of N1 inverters.

[0061] The circuit diagram of the nonlinear adjustable ring oscillator module is as follows: Figure 4 shown.

[0062] The nonlinear adjustable ring oscillator module is an inverter ring formed by connecting multiple inverter circuits end to end. The output nodes of any two inverters can be connected to the port L and port F of the nonlinear unit, such as Figure 7 As shown, port L and port F are two input terminals of the nonlinear unit, and port L or port F also serves as an output terminal. Each nonlinear unit is controlled by a set of switches, and the on and off of the switches are controlled by an external input control signal. The number of nonlinear units connected to the inverter loop can be adjusted according to actual needs. The number of nonlinear units connected to the inverter loop can be selected by the input control signal, so that the nonlinear unit can realize an adjustable function.

[0063] The two nonlinear adjustable ring oscillator modules respectively have a group of control signal CTRL input ports, and each nonlinear adjustable ring oscillator module has an output port, which is connected to the input port of the first isolation enhancement module or the second isolation enhancement module.

[0064] The inverter comprises: a first PMOS tube 1, a second PMOS tube 2, a first NMOS tube 4, and a second NMOS tube 3; the source of the first PMOS tube 1 is connected to a power supply VDD, and the source of the first NMOS tube 4 is grounded; the gate of the first PMOS tube 1 is connected to a control signal ENP, and the gate of the first NMOS tube 4 is connected to a control signal ENN; the drain of the first PMOS tube 1 is connected to the source of the second PMOS tube 2, and the drain of the first NMOS tube 4 is connected to the source of the second NMOS tube 3; the gate of the second PMOS tube 2 is connected to the gate of the second NMOS tube 3 as an inverter input terminal; and the drain of the second PMOS tube 2 is connected to the drain of the second NMOS tube 3 as an inverter output terminal.

[0065] The inverter circuit diagram of a specific embodiment of the present invention is as follows Figure 5 shown.

[0066] Specifically, when ENP=0 and ENN=1, the first PMOS tube 1 ( Figure 5 The top PMOS transistor) and the first NMOS transistor 4 ( Figure 5 The lower NMOS transistor in the inverter) is turned on (can be regarded as a wire), and the inverter works normally; when ENP=1 and ENN=0, the first PMOS tube 1 and the first NMOS tube 4 of the inverter are both turned off, and the inverter does not work. The second PMOS tube 2 and the second NMOS tube 3 are controlled by the input signal IN to form an inverter circuit with complementary logic functions: that is, when the input signal IN is 1, the second PMOS tube 2 is turned off, the second NMOS tube 3 is turned on, and the output level is 0; conversely, when the input signal IN is 0, the second PMOS tube 2 is turned on, the second NMOS tube 3 is turned off, and the output level is 1.

[0067] Each combination unit includes two isolation units and a nonlinear unit. The nonlinear unit has a dual-port input and single-port output structure. The input ends of the two isolation units serve as the two input ends of the combination unit. The signal output ends of the two isolation units are respectively connected to a signal input end of the nonlinear unit. Any one of the two input ends of the nonlinear unit serves as the output end of the combination unit.

[0068] The first isolation enhancement module, the second isolation enhancement module and the isolation unit have the same structure, and all include: a front-stage inverter and a rear-stage inverter; the output end of the front-stage inverter is connected to the input end of the rear-stage inverter; the size of the front-stage inverter is smaller than the first threshold; and the driving current of the rear-stage inverter is adapted to the driving current of the nonlinear unit.

[0069] When the first isolation enhancement module, the second isolation enhancement module and the isolation unit are constructed, the driving capability including the output current can be adjusted according to the situation of the subsequent nonlinear unit. A buffer with adjustable driving capability can be used as the isolation enhancement module.

[0070] The first isolation enhancement module, the second isolation enhancement module, and the isolation unit also have an isolation function. The first isolation enhancement module and the second isolation enhancement module isolate the nonlinear unit from the first nonlinear adjustable ring oscillator module and the second nonlinear adjustable ring oscillator module. The isolation unit is used to isolate the previous stage combination unit or the basic unit from the nonlinear unit of this stage, so that when adjusting the circuit parameters, the performance of the nonlinear unit does not change due to the adjustment of the parameters of the first nonlinear adjustable ring oscillator module, the second nonlinear adjustable ring oscillator module, the previous stage combination unit or the basic unit. Since the parameters of the front and rear modules of the circuit often affect each other during circuit design, for example, in order to adjust the frequency of the first nonlinear adjustable ring oscillator module and the second nonlinear adjustable ring oscillator module, the size of the MOS transistor in the inverter used needs to be changed. If the first and second nonlinear adjustable ring oscillator modules are directly connected to the nonlinear unit without the first isolation enhancement module and the second isolation enhancement module, the size change of the inverter transistor at the end of the first and second nonlinear adjustable ring oscillator modules will cause the input current of the nonlinear unit to change, and the input current of the nonlinear unit often affects the performance of the nonlinear unit. Therefore, the design needs to take into account both the adjustable circuit parameters and the stable input current of the nonlinear unit, which will greatly increase the difficulty of design.

[0071] A specific embodiment of the present invention is Figure 6 It is a typical example of an isolation circuit. The circuit consists of two stages of inverters. The size of the front stage inverter is as small as possible to reduce the load of the first nonlinear adjustable ring oscillator module and the second nonlinear adjustable ring oscillator module. No matter how the first nonlinear adjustable ring oscillator module and the second nonlinear adjustable ring oscillator module are adjusted, the performance of the nonlinear unit will not be affected. The size of the transistor in the rear stage inverter can be adjusted in the design stage to control the output current according to the driving capability requirements. The larger the W / L, the larger the output current, and the smaller the W / L, the smaller the output current. Among them, W and L are the width and length of the transistor respectively.

[0072] It should be noted that the first isolation enhancement module, the second isolation enhancement module, and the isolation unit are not limited to Figure 6 The structure shown, all modules with similar functions are within the scope of protection of this patent.

[0073] The front-stage inverter includes a third PMOS tube 5 and a third NMOS tube 7 connected in parallel; the gates of the third PMOS tube 5 and the third NMOS tube 7 are connected as the input end of the front-stage inverter; the drains of the third PMOS tube 5 and the third NMOS tube 7 are connected as the output end of the front-stage inverter; the source of the third PMOS tube 5 is connected to the power supply VDD; the source of the third NMOS tube 7 is grounded; the rear-stage inverter includes: a fourth PMOS tube 6, a fifth PMOS tube 8, a fourth NMOS tube 9 and a fifth NMOS tube 10; the The gates of the fourth PMOS tube 6, the fifth PMOS tube 8, the fourth NMOS tube 9 and the fifth NMOS tube 10 are connected as the input end of the subsequent inverter; the source of the fourth PMOS tube 6 is connected to the power supply VDD; the source of the fifth NMOS tube 10 is grounded; the drain of the fourth PMOS tube 6 is connected to the source of the fifth PMOS tube 8; the drain of the fifth PMOS tube 8 is connected to the drain of the fourth NMOS tube 9 and serves as the output end of the subsequent inverter; the source of the fourth NMOS tube 9 is connected to the drain of the fifth NMOS tube 10.

[0074] The nonlinear unit in the basic unit and the nonlinear unit in the combination unit have the same structure, both of which include a chaotic circuit with negative feedback; the chaotic circuit includes a first conduction module 12, a phase adjustment module, and a second conduction module 13 connected in parallel with each other; one parallel end of the first conduction module 12, the phase adjustment module, and the second conduction module 13 serves as a first input end of the nonlinear unit, and the other parallel end serves as a second input end of the nonlinear unit; one of the first input end or the second input end serves as an output end of the nonlinear unit.

[0075] Specifically, the nonlinear unit acts to add chaotic characteristics to the two input clock signals, and the chaotic characteristics will affect the input signals L and F through the feedback structure.

[0076] The nonlinear unit takes two clock signals of different frequencies as input, otherwise it is difficult to generate nonlinearity. Its structure is a basic chaotic module with negative feedback, which feeds chaos back to the input signal through negative feedback. The signal after feedback is sensitive to initial values, noise, and has large clock jitter.

[0077] The phase adjustment module is used to adjust the phase of the signal that is in phase with the first conduction module 12 and the second conduction module 13 so that the phases thereof are staggered.

[0078] A nonlinear unit in a specific embodiment of the present invention is as follows Figure 8 shown.

[0079] The phase adjustment module includes a sixth PMOS tube 14, a sixth NMOS tube 11, a pull-up load and a pull-down load; the gate of the sixth PMOS tube 14 is connected to the drain of the sixth NMOS tube 11 and serves as the first input end of the phase adjustment module; the drain of the sixth PMOS tube 14 is connected to the gate of the sixth NMOS tube 11 and serves as the second input end of the phase adjustment module; the source of the sixth PMOS tube 14 is connected to the power supply VDD through the pull-up load; the source of the sixth NMOS tube 11 is grounded through the pull-down load.

[0080] The pull-up load includes a resistor or a seventh PMOS tube; when the seventh PMOS tube is included, the gate of the seventh PMOS tube is connected to a control signal to make it in a conducting state, the source is connected to the power supply VDD, and the drain is connected to the source of the sixth PMOS tube 14; or, the gate and drain of the seventh PMOS tube are connected and then connected to the source of the sixth PMOS tube 14, and the source of the seventh PMOS tube is connected to the power supply VDD;

[0081] The pull-down load includes a resistor or a seventh NMOS tube; when the seventh NMOS tube is included, the gate of the seventh NMOS tube is connected to a control signal to make it in an on state, the source is grounded, and the drain is connected to the source of the sixth NMOS tube 11; or, the gate and drain of the seventh NMOS tube are connected and then connected to the source of the sixth NMOS tube 11, and the source of the seventh NMOS tube is grounded.

[0082] Specifically, the first conduction module 12 and the second conduction module 13 each include an identical transmission gate, one input end of each transmission gate is connected to the first input end of the phase adjustment module, and the other input end of each transmission gate is connected to the second input end of the phase adjustment module; the control end of the transmission gate is connected to the power supply VDD or an external control signal.

[0083] Specifically, the first and second conduction modules 13 are composed of transmission gates, and the conduction of the first and second conduction modules 13 is controlled by the control signal CTRL. In order to reduce costs, the power supply VDD of the nonlinear unit can also be used as the CTRL control signal. The function of the pull-up and pull-down resistors in the phase adjustment module is to control the current size of the nonlinear unit, because the current size flowing through the system will affect the performance of the nonlinear unit. Figure 8The working mode of the phase adjustment module shown is as follows: when the F and L signals are both high level (that is, the phases are the same at this time), the sixth NMOS is turned on, and the F signal is pulled down to a low level by the sixth NMOS; similarly, when the F and L signals are both low level, the sixth PMOS tube 14 is turned on, and the L signal is pulled to a high level by the sixth PMOS tube 14. In this way, due to the turning on and off of the sixth PMOS tube 14 and the sixth NMOS tube 11, the F and L signals cannot maintain the same high level or the same low level state for a long time, and cannot have the same change trend, thereby realizing the performance of the nonlinear unit to increase the nonlinear jitter of the input clock.

[0084] Compared with the prior art, the present embodiment provides a multi-stage adjustable nonlinear random entropy source circuit system comprising: K stages of circuits cascaded in sequence; the first stage circuit comprises a plurality of basic units, the second to K-th stage circuits comprise a plurality of combination units, and the number of combination units in the second stage circuit is half of the number of basic units in the first stage circuit, and in the third to K-th stage circuits, the number of combination units in each stage circuit is half of the number of combination units in the previous stage circuit, and the number of combination units in the K-th stage circuit is 1; every two basic units in the first stage circuit are connected to a combination unit in the second stage circuit; the output ends of every two combination units in the second to K-1 stage circuits are connected to two input ends of a combination unit in the next stage circuit; the output end of the K-th stage circuit serves as the output end of the circuit system; the present invention aims to provide a multi-stage adjustable nonlinear random entropy source architecture; the random entropy source architecture has the characteristics of multi-stage multiplexing, adjustability, and easy parameter adjustment, and has good feasibility and randomness. In each combination unit of a multi-stage adjustable nonlinear random entropy source circuit system provided by this embodiment, the isolation unit includes a front-stage inverter and a rear-stage inverter; the output end of the front-stage inverter is connected to the input end of the rear-stage inverter; the size of the front-stage inverter is smaller than the first threshold; the driving current of the rear-stage inverter is adapted to the driving current of the nonlinear unit. The isolation unit has the function of isolating the basic unit from the nonlinear unit, has the characteristics of good stability, and also has the effect of adjusting the output signal driving capability of the basic unit and the front-stage combination unit. The first nonlinear adjustable ring oscillator module and the second nonlinear adjustable ring oscillator module of the basic unit in the multi-stage adjustable nonlinear random entropy source circuit system provided in this embodiment both include: a plurality of inverters and a plurality of nonlinear units, wherein the plurality of inverters are sequentially cascaded, and the output end of the last inverter is connected to the input end of the first inverter; the two input ends of each nonlinear unit are respectively provided with a plurality of groups of parallel switches, one end of each group of switches is connected to the two input ends of the nonlinear unit, and the other end of each group of switches is respectively connected to the output end of an inverter; the output of the last inverter is used as the output end of the nonlinear adjustable ring oscillator module; wherein the number of inverters is an odd number. The basic unit generates a square wave with a certain nonlinear clock jitter, which increases the randomness of the entropy source. The nonlinear unit of a multi-stage adjustable nonlinear random entropy source circuit system provided in this embodiment is a dual-port input and single-port output structure; the nonlinear unit structure includes a chaotic circuit with negative feedback; the chaotic circuit includes a first conduction module 12, a phase adjustment module, and a second conduction module 13 connected in parallel; one parallel end of the first conduction module 12, the phase adjustment module, and the second conduction module 13 is used as the first input end of the nonlinear unit, and the other parallel end is used as the second input end of the nonlinear unit; one of the first input end or the second input end is used as the output end of the nonlinear unit. This structure makes the random entropy source of the present invention have the advantages of strong randomness, sensitivity to noise, and low power consumption.It can be used in information security fields such as device authentication, random number generation, IP protection, etc., effectively improving the security and practicality of the system.

[0085] Those skilled in the art will appreciate that all or part of the processes of the above-mentioned embodiments can be implemented by instructing related hardware through a computer program, and the program can be stored in a computer-readable storage medium, wherein the computer-readable storage medium is a disk, an optical disk, a read-only storage memory, or a random access memory, etc.

[0086] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by any technician familiar with the technical field within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention.

Claims

1. A multi-stage adjustable nonlinear random entropy source circuit system, characterized in that: The circuit system includes: K levels of circuits cascaded in sequence; the first level circuit includes multiple basic units, the second to K-th level circuits include several combination units, and the number of combination units in the second level circuit is half of the number of basic units in the first level circuit, and in the third to K-th level circuits, the number of combination units in each level circuit is half of the number of combination units in the previous level circuit, and the number of combination units in the K-th level circuit is 1; every two basic units in the first level circuit are connected to a combination unit in the second level circuit; the output ends of every two combination units in the second to K-1 level circuits are connected to two input ends of a combination unit in the next level circuit; the output end of the K-th level circuit serves as the output end of the circuit system; each basic unit is used to generate a square wave with nonlinear clock jitter; the combination unit is used to jitter amplify the input signal and output a square wave with greater clock jitter.

2. The random entropy source circuit system according to claim 1, characterized in that: Each combination unit includes two isolation units and a nonlinear unit. The nonlinear unit has a dual-port input and single-port output structure. The input ends of the two isolation units serve as the two input ends of the combination unit. The signal output ends of the two isolation units are respectively connected to a signal input end of the nonlinear unit. Any one of the two input ends of the nonlinear unit serves as the output end of the combination unit.

3. The random entropy source circuit system according to claim 1, characterized in that: The basic unit includes a first nonlinear adjustable ring oscillator module, a second nonlinear adjustable ring oscillator module, a first isolation enhancement module, a second isolation enhancement module, and a nonlinear unit. The first nonlinear adjustable ring oscillator module and the second nonlinear adjustable ring oscillator module are used to generate clocks of different frequencies under the action of a control signal; the clocks of different frequencies are respectively input to the nonlinear unit via the first isolation enhancement module and the second isolation enhancement module, and the nonlinear unit is used to add nonlinear jitter to the two input clocks of different frequencies to output a square wave of nonlinear clock jitter.

4. The random entropy source circuit system according to claim 3, characterized in that: The first nonlinear adjustable ring oscillator module and the second nonlinear adjustable ring oscillator module have the same structure, and both include: N1 inverters and M1 nonlinear units, wherein the N1 inverters are cascaded in sequence, and the output end of the last inverter is connected to the input end of the first inverter; the two input ends of each nonlinear unit are respectively provided with N1 groups of parallel switches, one end of each group of switches is connected to the two input ends of the nonlinear unit, and the other end of each group of switches is respectively connected to the output end of an inverter; the output of the last inverter is used as the output end of the nonlinear adjustable ring oscillator module; wherein N1 is an odd number.

5. The random entropy source circuit system according to claim 2 or 3, characterized in that: The first isolation enhancement module, the second isolation enhancement module and the isolation unit have the same structure, and all include: a front-stage inverter and a rear-stage inverter; the output end of the front-stage inverter is connected to the input end of the rear-stage inverter; the size of the front-stage inverter is smaller than the first threshold; and the driving current of the rear-stage inverter is adapted to the driving current of the nonlinear unit.

6. The random entropy source circuit system according to claim 5, characterized in that: The front stage inverter comprises a third PMOS tube and a third NMOS tube connected in parallel; the gates of the third PMOS tube and the third NMOS tube are connected as the input end of the front stage inverter; the drains of the third PMOS tube and the third NMOS tube are connected as the output end of the front stage inverter; The source of the third PMOS tube is connected to the power supply VDD; The source of the third NMOS tube is grounded; the post-stage inverter includes: a fourth PMOS tube, a fifth PMOS tube, a fourth NMOS tube and a fifth NMOS tube; the gates of the fourth PMOS tube, the fifth PMOS tube, the fourth NMOS tube and the fifth NMOS tube are connected as the input end of the post-stage inverter; the source of the fourth PMOS tube is connected to the power supply VDD; the source of the fifth NMOS tube is grounded; the drain of the fourth PMOS tube is connected to the source of the fifth PMOS tube; The drain of the fifth PMOS tube is connected to the drain of the fourth NMOS tube and serves as the output end of the subsequent inverter; the source of the fourth NMOS tube is connected to the drain of the fifth NMOS tube.

7. The random entropy source circuit system according to claim 2, characterized in that: The nonlinear unit in the basic unit and the nonlinear unit in the combination unit have the same structure, both of which include a chaotic circuit with negative feedback; the chaotic circuit includes a first conduction module, a phase adjustment module, and a second conduction module connected in parallel with each other; one parallel end of the first conduction module, the phase adjustment module, and the second conduction module serves as a first input end of the nonlinear unit, and the other parallel end serves as a second input end of the nonlinear unit; one of the first input end or the second input end serves as an output end of the nonlinear unit.

8. The random entropy source circuit system according to claim 7, characterized in that: The phase adjustment module includes a sixth PMOS tube, a sixth NMOS tube, a pull-up load and a pull-down load; the gate of the sixth PMOS tube is connected to the drain of the sixth NMOS tube and serves as the first input end of the phase adjustment module; the drain of the sixth PMOS tube is connected to the gate of the sixth NMOS tube and serves as the second input end of the phase adjustment module; the source of the sixth PMOS tube is connected to the power supply VDD through the pull-up load; and the source of the sixth NMOS tube is grounded through the pull-down load.

9. The random entropy source circuit system according to claim 8, characterized in that: The pull-up load includes a resistor or a seventh PMOS tube; when the seventh PMOS tube is included, the gate of the seventh PMOS tube is connected to a control signal to make it in a conducting state, the source is connected to the power supply VDD, and the drain is connected to the source of the sixth PMOS tube; or, the gate and drain of the seventh PMOS tube are connected and then connected to the source of the sixth PMOS tube, and the source of the seventh PMOS tube is connected to the power supply VDD; The pull-down load includes a resistor or a seventh NMOS tube; when the seventh NMOS tube is included, the gate of the seventh NMOS tube is connected to a control signal to make it in an on state, the source is grounded, and the drain is connected to the source of the sixth NMOS tube; or, the gate and drain of the seventh NMOS tube are connected and then connected to the source of the sixth NMOS tube, and the source of the seventh NMOS tube is grounded.

10. The random entropy source circuit system according to claim 8, characterized in that: The first conduction module and the second conduction module each include an identical transmission gate, one input end of each transmission gate is connected to the first input end of the phase adjustment module, and the other input end of each transmission gate is connected to the second input end of the phase adjustment module; the control end of the transmission gate is connected to the power supply VDD or an external control signal.

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