Merging of interrupt loss events in multi-level interrupt system

Abstract

The invention relates to merging of interrupt loss events in a multi-level interrupt system. Systems, methods, and circuitry are provided for detecting a lost interrupt event in a reduced instruction set computer-V (RISC-V) architecture. An exemplary architecture includes an advanced platform level interrupt controller (APLIC) and an incoming message notification interrupt (MSI) controller (IMSIC) coupled to the APLIC. The APLIC includes a plurality of respective vectors connected to respective external interrupt inputs, wherein each vector is mapped to an interrupt priority and each vector includes vector interrupt loss (IL) bits. The IMSIC is configured to receive the MSI from the APLIC and maintain an interrupt file including a set of interrupt loss (IL) bits indexed by an interrupt priority.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority to U.S. Provisional Patent Application No. 63 / 601,994, filed on November 22, 2023, entitled “CONSOLIDATION OF INTERRUPTLOST EVENTS IN MULTI-LEVEL INTERRUPT SYSTEM,” the entire contents of which are incorporated herein. Technical Field

[0003] The present disclosure relates generally to the field of processors and central processing units (CPUs), and more particularly to interrupt architectures for processing systems. Background Art

[0004] Modern processors may include a multi-level interrupt system in which multiple sources may provide wired and / or messaged interrupts, and different interrupts may have different priorities and target different hardware threads. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Some examples of circuits, devices and / or methods will be described below only as examples. In this case, reference will be made to the accompanying drawings.

[0006] Figure 1 is a block diagram of an exemplary multi-level interrupt architecture in accordance with various described aspects.

[0007] Figure 2 According to the various aspects described Figure 1 A block diagram of a specific example of an exemplary architecture.

[0008] Figure 3 is a block diagram of an exemplary multi-level interrupt architecture that supports indication of lost interrupt events in accordance with various described aspects.

[0009] Figure 4 is a block diagram of an exemplary multi-level interrupt architecture that supports indication of lost interrupt events in accordance with various described aspects.

[0010] Figure 5 is a flow chart of an exemplary method for providing information about lost interrupt events to a compute core in accordance with various described aspects.

[0011] Figure 6 is a flow chart of an exemplary method for providing information about lost interrupt events to a compute core in accordance with various described aspects. DETAILED DESCRIPTION

[0012] The present disclosure is described with reference to the accompanying drawings. Similar parts in the various drawings may be represented by similar reference numerals. The accompanying drawings are not drawn to scale, and they are provided only to illustrate the present disclosure. For illustration, several aspects of the present disclosure are described below with reference to exemplary applications. Many specific details, relationships and methods are set forth to provide an understanding of the present disclosure. The present disclosure is not limited by the ordering of the illustrated actions or events, because some actions may occur in different orders and / or occur simultaneously with other actions or events. In addition, not all illustrated actions or events are required to implement the method of the present disclosure according to selection.

[0013] Figure 1 is a block diagram of the interrupt architecture of a Reduced Instruction Set – V (RISC-V) system. Figure 1 The architecture is configured to handle external interrupts from multiple hardware threads (harts) as well as other interrupt targets. Figure 1 The architecture includes several interrupt sources: an Advanced Platform Level Interrupt Controller (APLIC) 110 and two Peripheral Component Interconnect Express (PCIe) devices 105. The interrupt sources are coupled to two Incoming Message Notification Interrupt Controllers (IMSIC) 120 of two corresponding harts 150 (eg, processor cores or CPUs) via a bus network 108.

[0014] The APLIC 110 receives wired external interrupts. Each external interrupt received by the APLIC 110 has an associated interrupt target, which includes a specific HART (and in some examples, a specific privilege level of the HART) and an associated interrupt priority. The APLIC 110 converts the wired external interrupt into a message notification interrupt (MSI) 130, which transmits interrupt information about the received interrupt (e.g., interrupt priority and interrupt target).

[0015] The PCIe device 105 also generates an MSI 130 that conveys information about the interrupt generated by the PCIe device.

[0016] The bus network 108 routes each MSI to the appropriate IMSIC 120 for the hart of the interrupt target indicated by the MSI. The IMSIC 120 maintains interrupt information for each interrupt target. In the illustrated example, the interrupt information is stored as a bit array in one or more interrupt files 125. An interrupt file 125 is maintained for each privilege level of the hart. Figure 1In the example, for machine level privileges, a machine level interrupt file is maintained, and for supervisor level privileges, a supervisor level interrupt file is maintained. In other examples, interrupt files may also be maintained for different virtual machines / customer IDs. In each interrupt file, the interrupt pending (IP) and interrupt enabled (IE) bit arrays include bits for each interrupt priority level, and these bits are addressed by the interrupt priority level. Therefore, an "interrupt target" can be viewed as a specific IP bit in a specific bit array of a specific interrupt file maintained by the IMSIC 120 for its specific hart 150.

[0017] Now refer to Figure 2 , Figure 1 Aspects of the interrupt architecture of the APLIC 110 are shown in more detail. The APLIC 110 defines the interrupt identification of the core external interrupt (wired or software interrupt). The APLIC 110 interrupt identification is associated with the physical interrupt line or software interrupt structure. The APLIC 110 includes a per-interrupt control register 112 (1-1023) storing a bit vector, each vector corresponding to a unique interrupt identification. Each control register maps the interrupt received on a specific line to a hart-ID and a privilege level within the hart, which can be M-Mode (machine mode), S- / HS-Mode (supervisor or hypervisor supervisor mode) or VSx (customer ID-virtual machine x supervisor mode). Each control register 112 configures the received interrupt with a priority (external interrupt identification number-EIID), and provides means for setting, storing and clearing the interrupt pending information (e.g., IP bit) and interrupt enable information (e.g., IE bit) of the interrupt, as well as means for defining the event scenario of each incoming interrupt line.

[0018] The APLIC 110 arbitrates pending interrupts according to the hart privilege level granularity and notifies the local IMSIC 120 of the target hart of the information of the winning interrupt as MSI 130. The MSI 130 indicates the interrupt target, which includes the configured HARTID, privilege level and interrupt priority (EIID). When notifying the MSI 130 of the arbitrated pending interrupt, the APLIC clears the interrupt pending (IP) information in the control register of the corresponding APLIC interrupt identification. It is noted that there can be more than one APLIC in the system that notifies the MSI to the IMSIC module.

[0019] Each hart 150 is coupled to a dedicated IMSIC 120. The IMISC 120 provides (e.g., maintains and stores) interrupt files 127, one file for each supported privilege level (M, S / HS) and one file for each supported customer ID (virtual machine). Each interrupt file 127 has a configurable number of priorities associated with the hart's interrupt vector table 157. For each privilege level, and possibly also for each virtual machine (customer), the IMSIC 120 provides an interrupt file 127 that includes an interrupt pending (IP) bit for each priority level and an interrupt enable (IE) bit for each priority level.

[0020] While an interrupt of a given privilege / priority is pending in the APLIC 110, it can happen that the APLIC receives one or more new interrupts through its corresponding interrupt input signals and / or through software writes, which are intended to set the already set interrupt pending bits of the vectors stored in the control registers. In other words, the APLIC 110 may receive an interrupt for a given target before the APLIC has a chance to signal the previous interrupt for the same target. In addition, while a particular interrupt priority is pending in the IMSIC 120, the IMSIC may again receive additional MSIs addressing the same interrupt priority. These subsequent interrupts may not be captured in existing systems and are referred to as lost interrupts or lost interrupt events. In some safety-related situations (such as automotive applications), it can be important to detect scenarios when one or more interrupts are lost at the APLIC or IMSIC level.

[0021] Systems, methods and architectures are provided herein that support detection and merging of lost interrupt events to notify processing cores thereof. In one example, APLIC and IMSIC interrupt identifiers are extended using a lost interrupt detection mechanism and a lost interrupt information structure. Lost interrupt information is notified from APLIC to IMSIC along with the corresponding MSI (MSI includes: information about priority, target core, target privilege level, extended by lost information). IMSIC merges lost interrupt information notified by MSI, but is also able to detect interrupt loss events at the priority level. IMSIC can then make the lost interrupt information available to the corresponding core.

[0022] Figure 3 1 is a block diagram of a general interrupt architecture that supports the transmission of lost interrupt occurrences to hardware threads. In one example, the interrupt architecture is a modified RISC-V advanced interrupt architecture. However, the disclosed solution can be applied in any processing environment.

[0023] The architecture includes hardware components arranged in a HART 350, an interrupt source 310, and a message controller 320 of the HART. The HART 350 includes an interrupt vector table 357 mapped to multiple interrupt targets. Each interrupt target is associated with a given priority of the HART. In some examples, the HART includes an interrupt target for each privilege or and / or each virtual machine. The setting of the interrupt target or its associated value in the interrupt vector table 357 enables the HART to take certain actions (possibly different actions for different interrupt targets) in response to the interrupt. In some cases, if multiple interrupts occur relatively quickly in succession for the same interrupt target (for example, to close together for individual notifications via interrupt messages, thereby losing the interrupt), the response to the interrupt may be prioritized as higher than a single occurrence of the interrupt. Alternatively, when a lost interrupt is detected, a different response may be taken by the HART.

[0024] Interrupt source 310 (e.g., Figure 1 The APLIC is configured to receive a corresponding external interrupt signal indicating a corresponding interrupt event. Each interrupt event is associated with a corresponding interrupt target. The interrupt source transmits an interrupt message (e.g., MSI) based on the received interrupt signal. For the interrupt event, each MSI includes information about the interrupt target of the interrupt event.

[0025] The interrupt source may include: a source level lost interrupt detection circuit system 315, which performs a lost interrupt detection function. In one example, in order to detect a lost interrupt event, the source level lost interrupt detection circuit system 315 detects that an interrupt signal of a second interrupt event of a given interrupt target is received before the interrupt source 310 transmits an interrupt message of a first interrupt event of a given interrupt target. For example, when the source level lost interrupt detection circuit system 315 receives an interrupt of an interrupt target whose interrupt pending (IP) bit in the vector of the interrupt target has been set, the source level lost interrupt detection circuit system 315 may detect an interrupt lost event. In response, the source level lost interrupt detection circuit system 315 stores an indication of the interrupt loss of the given interrupt target (e.g., by setting a vector interrupt lost (IL) bit in the vector of the interrupt identifier). The interrupt source 310 encodes the interrupt lost event information in a pending (e.g., in an arbitration queue) interrupt message that transmits information about the first received interrupt. The interrupt source may also be configured to clear the indication of the interrupt loss (e.g., the vector IL bit) in response to transmitting an interrupt message indicating a lost interrupt.

[0026] The message controller 320 (eg, Figure 1The IMSIC is configured to receive interrupt messages from an interrupt source 310 and store interrupt information of an interrupt target based on the received message. The message controller 320 includes a controller level lost interrupt circuit system 323 that determines (e.g., based on one or more of the received interrupt messages) that an interrupt event of an interrupt target has been lost. In response, the message controller 320 provides an indication of one or more lost interrupt events to a target hart 350 of the affected interrupt target.

[0027] The controller level lost interrupt circuit system 323 detects lost interrupts and stores information reflecting the lost interrupts as interrupt information. The controller level lost interrupt circuit system 323 may be configured to detect that an interrupt has been lost in response to receiving an interrupt message indicating a lost interrupt for a given target or receiving an interrupt message for a given target when the interrupt information 327 indicates that an interrupt for the given target is already pending. The message controller 320 may be configured to reset the lost interrupt information 327 for an interrupt target in response to a different interrupt target having the same or greater privileges than the given interrupt target receiving an indication of the one or more lost interrupt events. Alternatively or in addition, the lost interrupt information for an interrupt target may be set or reset by software.

[0028] The message controller 320 may be configured to notify one or more indications of lost interrupt events on a per interrupt priority basis or on a per interrupt target basis. Thus, the MSI controller combines information about lost interrupt events from multiple sources and provides the information to the HART so that the HART can take responsive actions.

[0029] Figure 4 is a block diagram of an exemplary RISC-V interrupt architecture, which is Figure 1 and 2 The architecture of the MCU is modified to provide detection, merging and indication of lost interrupt events. Figure 4 The architecture is Figure 3 A specific example of an architecture of FIG. 1 , and aspects of the illustrated architecture may be implemented by Figure 3 The general architecture implementation of .

[0030] In the illustrated architecture, the APLIC control register 412 has been modified to store a vectored interrupt lost (IL) bit for each interrupt flag. The APLIC 410 has been modified to set and (optionally) reset the vectored IL bit. The MSI message 430 includes one or more bits encoding the status of the vectored IL bit 418. The IMSIC has been modified to add an array 428 that includes one interrupt lost (IL) bit for each interrupt priority level or group of interrupt priorities.

[0031] An exemplary vector format for the interrupt flags stored by the control register 412 is illustrated in Figure 4 The bits encoding the source information, destination identification, and interrupt priority (EIID) are set by the configuration of the architecture. The IE bit and IP bit are set by the received external interrupt. When a new interrupt event is detected for an interrupt identifier while the IP bit of the interrupt identifier is already set, APLIC 410 (e.g., Figure 3 The vector IL bit is set by the source level lost interrupt detection circuitry of the APLIC 410. When the interrupt flag is arbitrated, its current vector IL bit status is notified as part of the modified MSI message 430. When an interrupt lost scenario is detected in parallel with the MSI notification / interrupt pending clear, the vector IL information may be set and notified with the next interrupt via the MSI. When the vector IL information is notified via the MSI message 430, the vector IL information may be cleared by software or via the APLIC 410. The APLIC 410 may detect lost interrupt events with different granularities (e.g., per interrupt or per group of interrupts).

[0032] For interrupts, the enhanced MSI 430 indicates the target hart ID, privilege level, priority (IIED), and an indication of the vector IL bit status of the notified interrupt identity.

[0033] The IMSIC interrupt file 427 is modified to add one interrupt lost bit (IL) per interrupt privilege level or per group of interrupt privilege levels. For example, an additional bit array 428 may be included in the interrupt file to store n IL bits indexed by n interrupt priority levels. The IE bit and IP bit are set by the MSIS 430, and the IMSIC 420 (e.g., Figure 3 The IL bit may be set by the controller level lost interrupt detection circuit system (of the controller level lost interrupt detection circuit system). For example, when an MSI for an interrupt identifier is received by the IMSIC 420 while the associated priority IP bit of the interrupt identifier has been set, the IMSIC will set the IL bit of the priority. In response to receiving an MSI indicating to set the vector IL bit for an interrupt identifier with a given priority, the IMSIC 420 may set the IL bit associated with the given priority. The IL information may be cleared by software and / or the IMSIC 420.

[0034] IL information can be provided to the interrupt target through the standard IMSIC register interface and can be cleared along with the IP bit. IL information can be provided directly to the corresponding privilege level / priority interrupt vector table 457 of the target hart 450.

[0035] The granularity of detecting, consolidating, and reporting lost interruption information may be based on per priority / privilege level, per priority / virtual machine level, per privilege level, per hart, etc. With different granularities, lost interruption information may be detected, consolidating, and reporting.

[0036] Figure 5 is a flowchart outlining an exemplary method 500 for notifying a computing core (eg, hart) of lost interrupt information. The method 500 may be, for example, respectively Figure 3 The interrupt source 310 or Figure 1 and 2 and Figure 4 The method includes: at 510, receiving an external interrupt signal, each external interrupt signal being associated with an interrupt priority. Each external interrupt signal may be associated with a preconfigured interrupt identifier, the interrupt identifier including an interrupt source identifier, a target hart / privilege level identifier, and a priority (EIID) for the notified interrupt. At 520, based on the received interrupt signal, determining that an interrupt signal of a given interrupt priority has been lost. In some examples, a lost interrupt signal is detected when an interrupt signal of a given interrupt identifier is received before a computing core has been notified of a previous interrupt signal of the given interrupt identifier.

[0037] In some examples, the method includes providing a plurality of corresponding vectors connected to corresponding external interrupt inputs for receiving external interrupt signals. Each vector is associated with a target computing core and includes an indication of an interrupt priority, a vector interrupt pending (IP) bit, and a vector interrupt lost (IL) bit. In these examples, the method includes setting a vector IL bit when an interrupt is received by a corresponding external interrupt input while a vector IP bit is set.

[0038] The method 500 includes providing, at 530, an indication to a computing core that an interrupt signal of the given interrupt priority has been lost. In some examples, this operation is performed by selecting a vector based on an arbitration rule and transmitting a message notification interrupt (MSI) to an incoming MSI controller (IMSIC) of a target computing core connected to the selected vector. The MSI includes an indication of the interrupt priority of the selected vector and a status of a vector IL bit of the selected vector.

[0039] Figure 6 is a flowchart outlining an exemplary method 600 for notifying a computing core (eg, hart) of lost interrupt information. The method 600 may be, for example, respectively Figure 3 The message controller 320 or Figure 1 and 2 and Figure 4 The method comprises: at 610, receiving an interrupt message, the interrupt message comprising an indication of an interrupt priority level among a plurality of interrupt priority levels. The interrupt message may be Figure 1 and 2 and Figure 4The MSI 130 or 430. The MSI may include an interrupt lost (IL) bit that is set to indicate that an interrupt signal of the same priority level is lost.

[0040] The method includes: at 620, determining that an interrupt of a given interrupt priority is lost based on an interrupt message. In some examples, the method includes: receiving an MSI, the MSI including an indication of the interrupt priority and an indication that an interrupt signal of the interrupt priority has been lost; and in response to the MSI message, setting an IL bit of the interrupt priority mapped in the interrupt file. The method may also include: in response to receiving an MSI including an indication of the interrupt priority while the IP bit of the interrupt priority in the interrupt file has been set, setting the IL bit of the interrupt priority mapped in the interrupt file. The method may include: in response to resetting the IP bit mapped to the given interrupt priority in the interrupt file, resetting the IL bit mapped to the given interrupt priority in the interrupt file.

[0041] Method 600 includes: at 630, providing corresponding lost interrupt information of corresponding interrupt priority indicating whether the interrupt is lost to the computing core. In some examples, the method includes: providing IL information via maintaining one or more interrupt files mapped to the corresponding interrupt target. In some examples, the status of one or more IL bits can be combined or summarized on a per priority or privilege level basis to generate lost interrupt information provided to the computing core. Interrupt loss information can be provided to the computing core through a standard IMSIC register interface, which includes an IL bit in each interrupt file. In some examples, instead of each interrupt file including an IL bit, IMSIC can maintain an IL bit set, each IL bit being associated with a set of priority and / or privileges. In some examples, lost interrupt information can be provided directly to the privilege level of the affected computing core.

[0042] In this description and the appended claims, the use of the term "determine" in reference to an entity (e.g., a parameter, a variable, etc.) when describing a method step or function should be interpreted broadly. For example, "determine" should be interpreted to cover, for example, receiving and parsing a communication that encodes an entity or a value of an entity. "Determine" should be interpreted to cover accessing and reading a memory (e.g., a lookup table, a register, a device memory, a remote memory, etc.) that stores an entity or a value of an entity. "Determine" should be interpreted to cover calculating or obtaining an entity or a value of an entity based on other quantities or entities. "Determine" should be interpreted to cover any way of deriving or identifying an entity or a value of an entity.

[0043] As used herein, the term "identify" when used with reference to an entity or a value of an entity should be broadly interpreted to encompass any manner of determining an entity or a value of an entity. For example, the term "identify" should be interpreted to encompass, for example, receiving and parsing communications encoding an entity or a value of an entity. The term "identify" should be interpreted to encompass accessing and reading a memory (e.g., a device queue, a lookup table, a register, a device memory, a remote memory, etc.) that stores an entity or a value of an entity.

[0044] As used herein, the term "indication," when used with reference to an entity (e.g., a parameter or setting) or a value of an entity, should be broadly interpreted to encompass any manner of conveying an entity or a value of an entity, either explicitly or implicitly. For example, bits within a transmitted message may be used to explicitly encode the value of an indication, or may encode an index or other indicator that is mapped to the value of an indication through prior configuration. The absence of a field within a message may implicitly indicate the value of an entity based on prior configuration.

[0045] As can be seen from the foregoing description, the disclosed interrupt architecture provides a mechanism for detecting interrupt loss events at a functional interrupt level (e.g., APLIC), merging them at a privilege level / priority level (e.g., IMSIC), extending them with additional (interrupt loss) event detection at a priority level, and then making this information available to the corresponding processor core or hart and there to the corresponding privileged mode.

[0046] Although the present invention has been illustrated and described with reference to one or more implementations, changes and / or modifications may be made to the illustrated examples without departing from the spirit and scope of the appended claims. In particular, with respect to the various functions performed by the above-described components or structures (assemblies, devices, circuits, circuit systems, systems, etc.), unless otherwise indicated, terms used to describe such components (including references to "members") are also intended to correspond to any component or structure that performs the specified function of the described component (e.g., which is functionally equivalent), even if not structurally equivalent to the disclosed structure that performs that function in the exemplary implementations of the invention illustrated herein.

[0047] Examples can include subject matter according to the embodiments and examples described herein, such as methods, components for performing actions or blocks of the methods, and at least one machine-readable medium including instructions that, when executed by a machine, cause the machine to detect a lost interrupt event and respond to the lost interrupt event.

[0048] Example 1 is a Reduced Instruction Set Computer-V (RISC-V) architecture, the architecture comprising: an advanced platform level interrupt controller (APLIC) comprising a plurality of respective vectors connected to respective external interrupt inputs, wherein each vector is mapped to an interrupt priority level and each vector comprises a vector interrupt lost (IL) bit; and an incoming message notification interrupt (MSI) controller (IMSIC) coupled to the APLIC, the IMSIC being configured to receive MSIs from the APLIC and to maintain an interrupt file comprising a set of interrupt lost (IL) bits indexed by interrupt priority levels.

[0049] Example 2 includes the subject matter of Example 1, including or omitting optional elements, wherein the IMSIC is configured to set the IL bit of a given interrupt priority mapped to the interrupt file in response to: receiving a message notification interrupt (MSI), the message notification interrupt (MSI) including an indication of the given interrupt priority and an indication that the vector IL bit of the corresponding vector is set; or receiving an MSI including an indication of the given interrupt priority while an interrupt pending (IP) bit of the given interrupt priority in the interrupt file is set.

[0050] Example 3 includes the subject matter of Example 1, including or omitting optional elements, wherein the IMSIC is configured to reset an IL bit mapped to a given interrupt priority level in the interrupt file in response to resetting an IP bit mapped to the given interrupt priority level in the interrupt file.

[0051] Example 4 includes the subject matter of Example 1, including or omitting optional elements, wherein the APLIC is configured to: set the vector IL bit of the vector when an interrupt is received by a corresponding external interrupt input while the IP bit of the vector is set; and in response, transmit an MSI to the IMSIC, the MSI including an indication of the interrupt priority level of the vector and a status of the vector IL bit of the vector.

[0052] Example 5 includes the subject matter of Example 1, including or omitting optional elements, wherein respective vectors are each mapped to respective interrupt targets and respective interrupt priorities of the respective interrupt targets; and the IMSIC maintains an interrupt file for each interrupt target.

[0053] Example 6 includes the subject matter of Example 5, including or omitting optional elements, wherein the interrupt target comprises: a target hardware thread (hart); a target hart and a privilege level of the target hart; or a target hart and a virtual machine ID of the target hart.

[0054] Example 7 includes the subject matter of Example 1, including or omitting optional elements, wherein the APLIC is configured to set an IL bit mapped to a given interrupt vector in response to receiving a new interrupt for a given interrupt vector while an interrupt pending (IP) bit of the interrupt vector is set.

[0055] Example 8 includes the subject matter of Example 1, including or omitting optional elements, wherein the APLIC is configured to reset an IL bit mapped to a given interrupt vector in response to resetting an interrupt pending (IP) bit mapped to the given interrupt vector when a corresponding interrupt is signaled as an MSI.

[0056] Example 9 is an interrupt architecture, which includes: hardware components arranged in one or more hardware threads (harts); an interrupt source configured to: receive a corresponding external interrupt signal indicating a corresponding interrupt event, each interrupt event having a corresponding interrupt target, wherein each interrupt target corresponds to the interrupt priority of a target hart in the one or more harts; based on the received interrupt signal, transmit a message notification interrupt (MSI), wherein for an interrupt event, the MSI includes information about the interrupt target of the interrupt event; an MSI controller configured to: receive the MSI from the one or more interrupt sources; based on the received MSI, store the interrupt information of the interrupt target; determine that the interrupt event of the interrupt target has been lost; and in response, provide lost interrupt information to the target hart of the interrupt target, wherein the lost interrupt information includes an indication of one or more lost interrupt events.

[0057] Example 10 includes the subject matter of Example 9, including or omitting optional elements, wherein the interrupt target includes an interrupt priority level at a privilege level at the target hart or a virtual machine at the target hart.

[0058] Example 11 includes the subject matter of Example 9, including or omitting optional elements, wherein an MSI in the MSI indicating an interrupt event for a given interrupt target includes an indication that an interrupt signal for a subsequent interrupt event for the given interrupt target was received prior to transmission of the MSI.

[0059] Example 12 includes the subject matter of Example 11, including or omitting optional elements, wherein the MSI controller is further configured to: based on the received MSI, save interrupt information for each interrupt target, the interrupt information indicating whether the interrupt has been lost; and provide the lost interrupt information to a target hart associated with the interrupt target where the interrupt has been lost.

[0060] Example 13 includes the subject matter of Example 9, including or omitting optional elements, wherein the MSI controller is configured to, in response to receiving an MSI indicating an interrupt event for a given interrupt target when the interrupt information for the given interrupt target indicates that an interrupt is pending or receiving an MSI indicating that the interrupt event for the given interrupt target is lost, set the interrupt information for the given interrupt target to indicate that an interrupt has been lost.

[0061] Example 14 includes the subject matter of Example 9, including or omitting optional elements, wherein the interrupt source is further configured to: convert a corresponding wired interrupt into a corresponding MSI; detect that an interrupt signal of a second interrupt event of a given interrupt target is received before the MSI of a first interrupt event of the given interrupt target is transmitted; and in response, store an indication that the interrupt of the given interrupt target is lost; and encode the lost interrupt information in the first MSI of the first interrupt event.

[0062] Example 15 includes the subject matter of Example 14, including or omitting the optional elements, wherein the interrupt source is further configured to clear the indication that the interrupt was lost in response to transmitting the first MSI.

[0063] Example 16 includes the subject matter of Example 9, including or omitting the optional elements, wherein the MSI controller is configured to signal an indication of one or more lost interrupt events on a per interrupt priority basis.

[0064] Example 17 includes the subject matter of Example 9, including or omitting the optional elements, wherein the MSI controller is configured to signal an indication of one or more missed interrupt events on a per interrupt target basis.

[0065] Example 18 includes the subject matter of Example 9, including or omitting optional elements, wherein the MSI controller is configured to reset the lost interrupt information of the interrupt target in response to an interrupt target having the same or greater privileges than the interrupt target receiving an indication of the one or more lost interrupt events.

[0066] Example 19 is a method comprising: receiving an interrupt message, the interrupt message comprising an indication of an interrupt priority among multiple interrupt priority levels; and based on the interrupt message, determining that an interrupt of a given interrupt priority level is lost; and providing corresponding lost interrupt information of the corresponding interrupt priority level to a computing core, the lost interrupt information indicating whether the interrupt is lost.

[0067] Example 20 includes the subject matter of Example 19, including or omitting optional elements, and further includes: in response to receiving an MSI including an indication of the interrupt priority and an indication that the vector IL bit in the interrupt source vector of the interrupt priority is set, setting the IL bit of the interrupt priority mapped in the interrupt file.

[0068] Example 21 includes the subject matter of Example 19, including or omitting optional elements, and further includes: setting an IL bit mapped to the interrupt priority in the interrupt file in response to receiving an MSI including an indication of the interrupt priority while the IP bit for the interrupt priority in the interrupt file is set.

[0069] Example 22 includes the subject matter of Example 21, including or omitting optional elements, and further includes: resetting an IL bit mapped to a given interrupt priority in the interrupt file in response to resetting the IP bit mapped to the given interrupt priority in the interrupt file.

[0070] Example 23 is a method that includes: receiving an external interrupt signal, each external interrupt signal being associated with an interrupt priority; determining, based on the received interrupt signals, that an interrupt signal of a given interrupt priority has been lost; and providing an indication that the interrupt signal of the given interrupt priority has been lost to a computing core.

[0071] Example 24 includes the subject matter of Example 23, including or omitting optional elements, and further includes: providing a plurality of respective vectors connected to respective external interrupt inputs that receive the external interrupt signals, where each vector is associated with a target computing core, and where each vector includes an indication of the interrupt priority, a vector interrupt pending (IP) bit, and a vector interrupt lost (IL) bit; and setting the vector IL bit of the vector when an interrupt is received by a corresponding external interrupt input while the vector IP bit of the vector is set.

[0072] Example 25 includes the subject matter of Example 24, including or omitting optional elements, and further includes: selecting a vector based on arbitration rules; and transmitting a message signaled interrupt (MSI) to an incoming MSI controller (IMSIC) of a target computing core connected to the selected vector, the MSI including an indication of the interrupt priority of the selected vector and the status of the vector IL bit of the selected vector.

[0073] The various illustrative logics, logic blocks, modules, circuitry, and circuits described in connection with the aspects disclosed herein can be implemented or performed using a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. The general purpose processor can be a microprocessor, but in the alternative, the processor can be any conventional processor, controller, microcontroller, or state machine.

[0074] In the present disclosure, similar reference numerals are always used to refer to similar elements, and the structures and devices illustrated therein may not be drawn to scale. As used herein, the terms "module", "component", "system", "circuit", "circuitry", "element", "slice", etc. are intended to refer to computer-related entities, hardware, software (e.g., in execution) and / or firmware. For example, circuitry or similar terms can be a processor, a process running on a processor, a controller, an object, an executable program, a storage device, and / or a computer with a processing device. As an illustration, an application and a server running on a server can also be a circuitry. One or more circuitry can reside in a process, and the circuitry can be localized on a computer and / or distributed between two or more computers. A set of components or other circuitry sets can be described herein, where the term "set" can be interpreted as "one or more".

[0075] As another example, a circuit system or similar terms can be a device having a specific function provided by mechanical parts operated by an electrical circuit system or an electronic circuit system, wherein the electrical circuit system or the electronic circuit system can be operated by a software application or a firmware application executed by one or more processors. The one or more processors can be located internal or external to the device and can execute at least a portion of the software or firmware application. As another example, a circuit system can be a device that provides a specific function by electronic components without mechanical parts; the electronic components can include field gates, logic components, hard-coded logic, register transfer logic, one or more processors to execute software and / or firmware that at least partially imparts the functions of the electronic components.

[0076] The use of exemplary words is intended to present concepts in a specific manner. The terms used in this article are only used for the purpose of describing specific examples, and are not intended to limit examples. As used herein, unless the context clearly indicates otherwise, the singular forms "one", "an" and "the" are intended to also include plural forms. It will also be understood that when used in this article, the terms "include" and / or "comprise" specify the features, integers, steps, operations, elements and / or parts of the existence statement, but do not exclude the existence or addition of one or more other features, integers, steps, operations, elements, parts and / or their groups. As used herein, the term "or" includes the options of all elements related to the word "or". For example, "A or B" should be interpreted as including only A, only B and both A and B. In addition, the phrase "one or more of ... " followed by "A, B or C" should be interpreted as including A, B, C, AB, AC, BC and ABC.

Claims

1. A Reduced Instruction Set Computer-V (RISC-V) architecture, comprising: an advanced platform level interrupt controller (APLIC) comprising a plurality of respective vectors connected to respective external interrupt inputs, wherein each vector is mapped to an interrupt priority level and each vector includes a vector interrupt lost (IL) bit; and An incoming message notification interrupt (MSI) controller (IMSIC), coupled to the APLIC, is configured to receive MSIs from the APLIC and maintain an interrupt file including a set of interrupt lost (IL) bits indexed by interrupt priority level.

2. The RISC-V architecture of claim 1 , wherein the IMSIC is configured to set an IL bit of a given interrupt priority level mapped to the interrupt file in response to: receiving a message notification interrupt (MSI), the message notification interrupt (MSI) comprising an indication of the given interrupt priority level and an indication that a vector IL bit of a corresponding vector is set; or An MSI including an indication of the given interrupt priority level is received while an interrupt pending (IP) bit for the given interrupt priority level in the interrupt file is set.

3. The RISC-V architecture of claim 1 , wherein the IMSIC is configured to reset an IL bit mapped to a given interrupt priority level in the interrupt file in response to resetting an IP bit mapped to the given interrupt priority level in the interrupt file.

4. The RISC-V architecture of claim 1, wherein the APLIC is configured to: When an interrupt is received by a corresponding external interrupt input while the IP bit of a vector is set, setting the vector IL bit of the vector; and In response, an MSI is transmitted to the IMSIC, the MSI including an indication of the interrupt priority level of the vector and a status of the vector IL bit of the vector.

5. The RISC-V architecture of claim 1, wherein The respective vectors are mapped to respective interrupt targets and respective interrupt priorities of the respective interrupt targets; and The IMSIC maintains an interrupt file for each interrupt target.

6. The RISC-V architecture of claim 5, wherein the interrupt target comprises: target hardware thread (hart); a target hart and the privilege level of said target hart; or A target hart and a virtual machine ID of the target hart.

7. The RISC-V architecture of claim 1 , wherein the APLIC is configured to set an IL bit mapped to a given interrupt vector in response to receiving a new interrupt to the given interrupt vector while an interrupt pending (IP) bit of the given interrupt vector is set.

8. The RISC-V architecture of claim 1, wherein the APLIC is configured to reset an IL bit mapped to a given interrupt vector in response to resetting an interrupt pending (IP) bit mapped to the given interrupt vector when a corresponding interrupt is notified as an MSI.

9. An interrupt architecture comprising: Hardware components, arranged in one or more hardware threads (harts); Interrupt sources, configured as: receiving a corresponding external interrupt signal indicating a corresponding interrupt event, each interrupt event having a corresponding interrupt target, wherein each interrupt target corresponds to an interrupt priority level of a target hart in the one or more harts; Based on the received interrupt signal, transmitting a message notification interrupt (MSI), wherein for an interrupt event, the MSI includes information about the interrupt target of the interrupt event; The MSI controller is configured as: receiving an MSI from the interrupt source; Based on the received MSI, storing interrupt information of the interrupt target; The interrupt event that determines the interrupt target has been lost; and In response, lost interruption information is provided to a target hart of the interruption target, the lost interruption information including an indication of one or more lost interruption events.

10. The interrupt architecture of claim 9, wherein the interrupt target includes an interrupt priority level at the target hart or a virtual machine at the target hart.

11. The interrupt architecture of claim 9, wherein an MSI of the MSIs that indicates an interrupt event for a given interrupt target includes an indication that an interrupt signal for a subsequent interrupt event for the given interrupt target was received prior to transmission of the MSI.

12. The interrupt architecture of claim 11, wherein the MSI controller is further configured to: Based on the received MSI, saving interrupt information for each interrupt target, the interrupt information indicating whether the interrupt has been lost; and The lost interruption information is provided to a target hart associated with the interruption target for which the interruption was lost.

13. The interrupt architecture of claim 9 , wherein the MSI controller is configured to, in response to receiving an MSI indicating an interrupt event for a given interrupt target when the interrupt information for the given interrupt target indicates that an interrupt is pending or receiving an MSI indicating that the interrupt event for the given interrupt target is lost, set the interrupt information for the given interrupt target to indicate that an interrupt has been lost.

14. The interrupt architecture of claim 9, wherein the interrupt source is further configured to: Convert the corresponding wired interrupt into the corresponding MSI; detecting that an interrupt signal of a second interrupt event of a given interrupt target is received before an MSI of a first interrupt event of the given interrupt target is transmitted; And in response, storing an indication that an interrupt to the given interrupt target was lost; and The lost interruption information is encoded in a first MSI of the first interruption event.

15. The interrupt architecture of claim 14, wherein the interrupt source is further configured to clear the indication that the interrupt was lost in response to transmitting the first MSI.

16. The interrupt architecture of claim 9, wherein the MSI controller is configured to signal an indication of one or more missed interrupt events on a per interrupt priority basis.

17. The interrupt architecture of claim 9, wherein the MSI controller is configured to signal an indication of one or more missed interrupt events on a per interrupt target basis.

18. The interrupt architecture of claim 9, wherein the MSI controller is configured to reset the lost interrupt information of the interrupt target in response to an interrupt target having equal or greater privileges than the interrupt target receiving an indication of the one or more lost interrupt events.

19. A method comprising: receiving an interrupt message, the interrupt message comprising an indication of an interrupt priority level among a plurality of interrupt priority levels; and Based on the interrupt message, determining that an interrupt of a given interrupt priority level is lost; and Corresponding lost interrupt information of corresponding interrupt priority is provided to the computing core, the lost interrupt information indicating whether the interrupt is lost.

20. The method of claim 19, further comprising: In response to receiving an MSI including an indication of the interrupt priority level and an indication that a vector IL bit in an interrupt source vector for the interrupt priority level is set, setting the IL bit of the interrupt priority level mapped in an interrupt file.

21. The method of claim 19, further comprising: In response to receiving an MSI including an indication of the interrupt priority level while an IP bit of the interrupt priority level in the interrupt file is set, an IL bit mapped to the interrupt priority level in the interrupt file is set.

22. The method of claim 21, further comprising: In response to resetting the IP bit mapped to the given interrupt priority level in the interrupt file, resetting the IL bit mapped to the given interrupt priority level in the interrupt file.

23. A method comprising: Receive external interrupt signals, each external interrupt signal is associated with an interrupt priority level; Based on the received interrupt signal, determining that an interrupt signal for a given interrupt priority level has been lost; and An indication is provided to a computing core that the interrupt signal for the given interrupt priority level has been lost.

24. The method of claim 23, further comprising: providing a plurality of respective vectors connected to respective external interrupt inputs for receiving the external interrupt signal, wherein each vector is associated with a target computing core, and further wherein each vector includes an indication of an interrupt priority level, a vectored interrupt pending (IP) bit, and a vectored interrupt lost (IL) bit; and When an interrupt is received by a corresponding external interrupt input while the vector IP bit of a vector is set, the vector IL bit of the vector is set.

25. The method of claim 24, further comprising: Selecting a vector based on an arbitration rule; and A message notification interrupt (MSI) is transmitted to an incoming MSI controller (IMSIC) of a target compute core connected to a selected vector, the MSI including an indication of the interrupt priority level of the selected vector and a status of the vector IL bit of the selected vector.

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