DDR interface and DDR read-write control method based on same
By designing the DDR interface, the efficient data reading and writing of FPGA on a single DDR memory stick is solved, and the problems of increased resource requirements and limited system efficiency in the prior art are solved, and the system flexibility and data processing efficiency are improved.
Patent Information
- Application Number
- CN202510053064.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-14
- Publication Date
- 2025-05-23
AI Technical Summary
In ultrasonic diagnostic systems, FPGAs need to perform real-time read and write operations of multiple data simultaneously. The prior art requires allocating these operations to different DDR memory sticks, resulting in increased resource requirements, expanded hardware area, and limited system flexibility and efficiency.
Design a DDR interface, including a control part and an interface part, and realizes efficient data read and write operations between the FPGA and the DDR IP core through control registers, interface settings modules, data write FIFO modules and data read FIFO modules. This interface allows read and write operations on a single DDR memory stick to manage the read and write process of DDR through instruction buffers and control registers.
It realizes efficient data reading and writing of FPGA on a single DDR memory stick, avoids the need for multiple memory sticks, saves costs and space, and improves system flexibility and data processing efficiency.
Smart Images
Figure CN120029939A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of DDR storage technology, and in particular to a DDR interface and a DDR read-write control method based on the interface. Background Art
[0002] In ultrasound diagnosis systems, FPGA is usually used for data processing, and external DDR memory is used for data storage. In order to simplify the control logic of FPGA, it is usually necessary to assign the reading and writing tasks of different data used simultaneously in real-time scanning to different DDRs, that is, it is necessary to separate memory reading and writing to different DDRs. This not only increases the resource requirements of FPGA and the area of hardware, resulting in limited flexibility and efficiency of ultrasound diagnosis system design, but also is not conducive to the efficient use of DDR memory.
[0003] Therefore, the present invention urgently needs to provide a technical solution that can enable FPGA to efficiently read and write on a single DDR memory stick. Summary of the invention
[0004] In view of the above-mentioned deficiencies in the prior art, the present invention provides a DDR interface and a DDR read and write control method based on the interface, so as to realize efficient data reading and writing of FPGA on a single DDR memory stick and improve data processing efficiency.
[0005] In order to achieve the above object, the present invention adopts the following technical solutions:
[0006] In a first aspect, the present invention provides a DDR interface, the DDR interface comprising a control part and an interface part sequentially connected between an internal logic module of an FPGA and a DDR IP core, the control part comprising a control register, an interface setting module, a write data FIFO module and a read data FIFO module, the interface part comprising a configuration port, a data write port, a data read port, an instruction configuration register, an instruction cache area, an address cache area and an interface logic module;
[0007] The interface setting module is used to set the instructions in the instruction cache area through the configuration port to establish an instruction linked list, and is also used to set the instruction configuration register through the configuration port so that the instruction configuration register performs instruction configuration, wherein the instructions include write instructions and read instructions, and the address cache area is used to store the DDR address corresponding to each instruction;
[0008] The control register is used to start DDR read and write operations to trigger the interface logic module to execute instructions in the instruction chain list, wherein, if the currently executed instruction is a write instruction, the data cached in the write data FIFO module is written to the DDR address corresponding to the instruction through the data write port; if the currently executed instruction is a read data instruction, the data in the DDR address corresponding to the instruction is read out to the read data FIFO module for caching through the data read port.
[0009] Furthermore, the interface setting module includes:
[0010] An internal interface setting unit, wherein an input end of the internal interface setting unit is connected to an internal control module of the FPGA;
[0011] An external interface setting unit, wherein an input end of the external interface setting unit is connected to an external controller;
[0012] A first selector, wherein an input end of the first selector is connected to output ends of the internal interface setting unit and the external interface setting unit, an output end of the first selector is connected to the configuration port, and a control end of the first selector is connected to the control register.
[0013] Furthermore, the write data FIFO module includes:
[0014] An internal write data FIFO, an input end of which is connected to an internal write module of the FPGA;
[0015] An external write data FIFO, wherein an input end of the external write data FIFO is connected to an external controller;
[0016] A second selector, wherein the input end of the second selector is connected to the output ends of the internal write data FIFO and the external write data FIFO, the output end of the second selector is connected to the data write port, and the control end of the second selector is connected to the control register.
[0017] Furthermore, the read data FIFO module includes:
[0018] An internal read data FIFO, the input end of which is connected to an internal processing module of the FPGA;
[0019] An external read data FIFO, wherein an input end of the external read data FIFO is connected to an external controller;
[0020] A third selector, wherein the output end of the third selector is connected to the input ends of the internal read data FIFO and the external read data FIFO, the input end of the third selector is connected to the data read port, and the control end of the third selector is connected to the control register.
[0021] Further, the FPGA includes a main board and a sub-board;
[0022] The internal logic module of the FPGA includes a main board write module, a sub-board write module, a main board read module, a sub-board read module, a fourth selector and a fifth selector;
[0023] The input ends of the main board writing module and the auxiliary board writing module are connected to the external controller, the output ends of the main board writing module and the auxiliary board writing module are connected to the input end of the fourth selector, and the output end of the fourth selector is connected to the external interface setting unit and the external write data FIFO;
[0024] The output ends of the main board readout module and the sub-board readout module are connected to the external controller, the input ends of the main board readout module and the sub-board readout module are connected to the output end of the fifth selector, and the input end of the fifth selector is connected to the external read data FIFO.
[0025] Furthermore, the FPGA is applied to an ultrasonic diagnostic system, the internal control module is an ultrasonic scanning control module, the internal writing module is a scanning data receiving module, and the internal processing module is a scanning beam synthesis module.
[0026] On the other hand, the present invention provides a DDR read / write control method based on the DDR interface as described above, comprising:
[0027] Setting the instructions in the instruction cache area through the interface setting module to establish an instruction linked list;
[0028] Setting the instruction configuration register through the interface setting module so that the instruction configuration register performs instruction configuration;
[0029] The DDR read and write operations are started through the control register to trigger the interface logic module to execute the instructions in the instruction chain list.
[0030] Further, the instruction configuration includes setting a starting instruction to be executed, setting a number of chain repetitions of the instruction chain list, and setting a DDR address corresponding to the first instruction and the last instruction in the instruction chain list;
[0031] The interface logic module executes the instructions in the instruction chain list, including: repeatedly executing the instructions in the instruction chain list until the number of repetitions of the chain list is reached.
[0032] Furthermore, the process of the interface logic module repeatedly executing the instructions in the instruction chain list is as follows:
[0033] Performing interface initialization to initialize the address buffer area according to the DDR addresses corresponding to the first instruction and the last instruction in the instruction chain list;
[0034] Execute the current instruction in the instruction chain list, the initial current instruction being the start instruction;
[0035] The DDR address in the address cache is updated according to the execution result of the current instruction, and the DDR address corresponding to the next instruction after the update is determined;
[0036] Determine whether the next instruction is the starting instruction. If not, use the next instruction as the new current instruction and return to the step of executing the current instruction in the instruction list. If so, decrement the number of repetitions of the linked list and determine whether the number of repetitions of the linked list is 0. If it is 0, the process ends. If not, use the next instruction as the new current instruction and return to the step of executing the current instruction in the instruction list.
[0037] Furthermore, each of the instructions cached in the instruction cache area carries a corresponding execution rule, and the execution rule includes the number of repetitions and the address step length of the corresponding instruction execution;
[0038] The executing the current instruction in the instruction chain list includes: executing the current instruction according to the execution rule carried by the current instruction.
[0039] By adopting the above technical solution, the present invention has the following beneficial effects:
[0040] The present invention realizes efficient data read and write operations on a single DDR memory stick by designing a DDR interface connected between the internal logic module of FPGA and the DDR IP core, avoiding the operations that need to be allocated to different memory sticks in the prior art, saving costs and space, and greatly improving the flexibility of the system and data processing efficiency. In addition, the present invention manages the read and write process of DDR by using the instruction cache and control register, and ensures smooth connection and data exchange between the DDR IP core and the internal logic module of FPGA by using the write data FIFO module when writing data; when reading data, the read data FIFO module is used to continuously pass the data obtained in DDR to the receiving end, ensuring efficient use of data and stability of transmission. The whole process is initialized by the instruction configuration register, and the current DDR operation address is updated in real time through the address cache, so that continuous reading and writing of data can be realized. BRIEF DESCRIPTION OF THE DRAWINGS
[0041] Figure 1 This is a structural block diagram of a DDR interface according to Embodiment 1 of the present invention;
[0042] Figure 2A This is a schematic diagram of a generation interface of a DDR IP core in Example 1 of the present invention;
[0043] Figure 2B This is a schematic diagram of another interface generation interface of the DDR IP core in Example 1 of the present invention;
[0044] Figure 3A This is a timing diagram of the DDR IP core read channel in Example 1 of the present invention;
[0045] Figure 3B This is a timing diagram of the DDR IP core write channel in Example 1 of the present invention;
[0046] Figure 4 Flow chart of the DDR read and write control method according to embodiment 2 of the present invention. DETAILED DESCRIPTION
[0047] In order to make the purpose, technical scheme and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.
[0048] The terms used in the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure. The singular forms "a", "the" and "the" used in the present disclosure and the appended claims are also intended to include plural forms unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.
[0049] In order to realize efficient data reading and writing of FPGA on a single DDR memory stick, the present invention provides a DDR interface and a DDR reading and writing control method based on the interface.
[0050] Example 1
[0051] This embodiment provides a DDR interface, such as Figure 1 As shown, the DDR interface is designed to connect the internal logic module of the FPGA with the DDR IP CORE (core) and implement the reading and writing process of the DDR.
[0052] As an example but not a limitation, the FPGA development tool used in this embodiment is AMD Vivado2022.1 or later, the IP core generator is DDR4 SDRAM v2.2, and the operating system is Windows 10.
[0053] like Figure 2A-2B As shown, the generation interface of 8GB DDR4 IP CORE based on AMD Vivado is shown. After the DDR4 IP CORE is generated, one end is connected to DDR4, and the other end is connected to the DDR interface of this embodiment to perform corresponding DDR operations according to the interface signal.
[0054] In this embodiment, the main interface signals that need to be processed between the DDR interface and the DDR4 IP CORE are divided into two groups: read and write. Figure 3A-3B As shown, the timing diagram of the DDR IP core read channel and the timing diagram of the write channel are shown, which characterizes the timing and signal flow of DDR4 data reading and writing. The specific definition of each signal in the timing diagram can be referred to the document [UtraScaleArchitecture-Based FPGAs Memory IP V1.4, PG150 December 5, 2018].
[0055] In the read channel, since the data app_rd_data and data valid signal app_rd_data_valid obtained from the DDR4 IP CORE will appear randomly, the receiving end (that is, the DDR interface) should be designed to ensure that valid output data will not be lost. For example, when using FIFO to cache data read from the DDR4 IP CORE, there must be enough FIFO depth to avoid data write overflow. In the write channel, with 64-bit as the minimum operation unit, the app_wdf_mask signal can be ignored.
[0056] See again Figure 1 As shown, the DDR interface of this embodiment includes a control part and an interface part which are sequentially connected between the internal logic module of the FPGA and the DDR IP core. Among them, the control part mainly includes a control register, an interface setting module, a write data FIFO module and a read data FIFO module; the interface part mainly includes a configuration port, a data write port, a data read port, an instruction configuration register, an instruction cache, an address cache and an interface logic module, so as to realize the read and write process of DDR through the instruction cache, the configuration register, the control register and the interface logic module.
[0057] In this embodiment, the interface setting module is mainly used to set the instructions (including write instructions and read instructions) in the instruction cache area through the configuration port to establish an instruction list, and is also used to set the instruction configuration register through the configuration port so that the instruction configuration register performs instruction configuration. The address cache area is mainly used to store the DDR address corresponding to each instruction. The control register is mainly used to start the DDR read and write operation to trigger the interface logic module to execute the instructions in the instruction list. Among them, if the currently executed instruction is a write instruction, the data cached in the write data FIFO module is written to the DDR address corresponding to the instruction through the data write port; if the currently executed instruction is a read data instruction, the data in the DDR address corresponding to the instruction is read out to the read data FIFO module through the data read port for caching.
[0058] By way of example and not limitation, Figure 1 As shown, the interface setting module in this embodiment includes: an internal interface setting unit, the input end of the internal interface setting unit is connected to the internal control module of the FPGA; an external interface setting unit, the input end of the external interface setting unit is connected to an external controller (such as an external PC); a first selector M1, the input end of the first selector is connected to the output ends of the internal interface setting unit and the external interface setting unit, the output end of the first selector is connected to the configuration port, and the control end of the first selector is connected to the control register. It can be seen that the DDR interface of this embodiment has two paths to perform DDR operation settings. By controlling the first selector through the control register, the setting side of the instruction configuration register and the instruction cache area can be selected as the internal interface setting unit or the external interface setting unit.
[0059] When the FPGA in this embodiment is applied to an ultrasonic diagnostic system, the internal control module can be an ultrasonic scanning control module, and the internal interface setting unit sets the instruction configuration register and the instruction cache area according to the ultrasonic scanning control logic; the external interface setting unit sets the instruction configuration register and the instruction cache area according to the command of the external controller.
[0060] As an example but not a limitation, the write data FIFO module in this embodiment includes: an internal write data FIFO, the input end of the internal write data FIFO is connected to the internal write module of the FPGA; an external write data FIFO, the input end of the external write data FIFO is connected to the external controller; a second selector M2, the input end of the second selector is connected to the output ends of the internal write data FIFO and the external write data FIFO, the output end of the second selector is connected to the data write port, and the control end of the second selector is connected to the control register. That is, this embodiment controls the first selector through the control register, and can select the internal write module or the external controller as the sender of the write data.
[0061] When the FPGA in this embodiment is applied to an ultrasonic diagnostic system, the internal writing module may be a scanning data receiving module for receiving ultrasonic scanning data.
[0062] It should be understood that this embodiment does not impose any restriction on the number of external write data FIFOs and internal write data FIFOs.
[0063] As an example but not a limitation, the read data FIFO module in this embodiment includes: an internal read data FIFO, an external read data FIFO and a third selector M3. Among them, the input end of the internal read data FIFO is connected to the internal processing module of the FPGA; the input end of the external read data FIFO is connected to the external controller; the output end of the third selector M3 is connected to the input ends of the internal read data FIFO and the external read data FIFO, the input end of the third selector is connected to the data read port, and the control end of the third selector is connected to the control register. That is, this embodiment controls the third selector through the control register, and can select the internal processing module or the external controller as the sender of the write data.
[0064] When FPGA is applied to an ultrasonic diagnostic system, the internal processing module may be a scanning beam synthesis module.
[0065] It should be understood that this embodiment does not impose any restrictions on the number of external read data FIFOs and internal read data FIFOs. Figure 1 In the example shown, the read data FIFO module includes two internal read data FIFOs, one of which is an internal parameter read FIFO and the other is an internal data read FIFO, which are respectively used to store the read ultrasound scanning parameters and ultrasound scanning data.
[0066] In one practicable manner, the instruction cache is a RAM with 128-bit data lines and 5-bit address lines. Each instruction in the instruction cache is 128 bits, and the number of instructions depends on the specific application. The specific definition of the instructions is shown in Table 1 below:
[0067] Table 1
[0068] bit 106…104 100…96 93…64 63…32 15…0 domain instr_cmd instr_nxt_instr instr_start_addr instr_burst_num instr_addr_step
[0069] The specific meanings of the fields carried by the instruction are shown in Table 2 below:
[0070] Table 2
[0071]
[0072] By defining the instr_nxt_instr field in each instruction, an instruction list can be formed to facilitate subsequent execution of complex read and write operations.
[0073] In an practicable manner, the instruction configuration register is used to perform instruction configuration, and its definition is shown in the following Table 3:
[0074] Table 3
[0075] bit 100…96 79…64 36...32 4…0 domain Start Instruction Iteration Number First Instruction Last Instruction
[0076] The specific meanings of the fields in the instruction configuration register are shown in Table 4 below:
[0077] Table 4
[0078]
[0079] In this embodiment, the address buffer is a buffer maintained inside the DDR interface, which is used to store the current DDR operation address of each instruction, and its number is the same as the instruction buffer. After the DDR operation is started, the address buffer defined by the First Instruction and Last Instruction in the instruction configuration register is initialized first. From the First Instruction to the Last Instruction, the DDR start address carried in the instruction is taken out and stored in the corresponding address buffer.
[0080] At the beginning of the current instruction execution, the DDR start address corresponding to the instruction is read from the corresponding address of the address buffer. During the instruction execution process, the DDR address is updated immediately. After the instruction is completed, the updated DDR address is stored in the address buffer corresponding to the instruction, and the current DDR address corresponding to the next instruction is read at the same time.
[0081] In this embodiment, the control register is used to select the FIFO of the data writing and reading port, and the setting module of the configuration port, and the DDR reset (RESET) and DDR startup are also controlled by it. The specific definition of the control register is shown in Table 5 below:
[0082] Table 5
[0083]
[0084] In this embodiment, for the external interface setting unit, the 64-bit data on PCIe x1 is combined into 128-bit data, and the six address lines A9-A4 on the address bus are mapped to the configuration port of the DDR interface, with BYTE as the addressing unit. For the write operation on the DDR control space (0x2xxx_xxxx / 0xAxxx_xxxx), when A9=1, it indicates the write instruction configuration register (0x2000_0200 / 0xA000_0200), and when A9=0, it indicates the write instruction buffer (0x2000_000x–0x2000_01Fx / 0xA000_000x-0xA000_01Fx).
[0085] For the external interface setting unit, the data bus is 128-bit, the address bus is 6-bit, and the addressing unit is 128-bit. When A5=1, it means writing the instruction configuration register (0x20). When A5=0, it means writing the instruction cache (0x00-0x1F).
[0086] In an operative manner, the FPGA is connected to an external PC. For example, the XDMA of PCIe x1 has a data bus width of 64, and the data bus width of DDR4 IP CORE is 512. A 64-bit input and 512-bit output write FIFO (i.e., external write FIFO) is used to cross the clock domain and buffer. The read-end logic of the external write FIFO is as follows:
[0087] assign wr_fifo_rd_en=app_wdf_wren
[0088] assign app_wdf_data=wr_fifo_dout
[0089] That is, the data write enable signal of DDR4 IP CORE is used as the data read enable of write FIFO, and the output data of write FIFO is used as the data input of DDR4 IP CORE. wr_fifo_empty&app_rdy&app_wdf_rdy are used as the write operation enable signal app_en and the data write enable signal app_wdf_wren.
[0090] The control logic of the internal write FIFO is similar, the difference is the write data width, the specific width depends on the specific application.
[0091] In one practicable manner, a 512-bit input and 64-bit output external read FIFO is used on the read channel as a buffer for reading data from the DDR on the external command interface path. The write logic of the read FIFO is as follows:
[0092] assign rd_fifo_wr_en=app_rd_data_validassignrd_fifo_din=app_rd_data
[0093] That is, the data and data valid signal obtained from the DDR4 IP CORE are used as the data input and data write signal of the read FIFO.
[0094] rd_fifo_full&app_rdy are used as the enable signal app_en for DDR4 read operation.
[0095] The control logic inside the internal read FIFO is similar, but has different read data widths.
[0096] In addition, this embodiment supports inter-board expansion of FPGA, that is, FPGA can include a main board and a sub-board. Figure 1 As shown, the internal logic module of the FPGA may include a main board write module, a sub-board write module, a main board read module, a sub-board read module, a fourth selector M4 and a fifth selector M5. The input ends of the main board write module and the sub-board write module are connected to an external controller, the output ends of the main board write module and the sub-board write module are connected to the input end of the fourth selector, and the output end of the fourth selector is connected to an external interface setting unit and an external write data FIFO. The output ends of the main board read module and the sub-board read module are connected to an external controller, the input ends of the main board read module and the sub-board read module are connected to the output end of the fifth selector, and the input end of the fifth selector is connected to an external read data FIFO. The selection of the fifth selector is controlled by the main and sub-board settings.
[0097] It should be understood that the FPGA in this embodiment may not be expanded, that is, the FPGA only includes a mainboard.
[0098] As an example but not a limitation, in this embodiment, when the FPGA is expanded, the address space allocation table of the FPGA is shown in Table 6 below:
[0099] Table 6
[0100] Space category Starting address Space size Motherboard control 0x0000_0000 8 CONFIG 0x2000_0000 0x1000_0000 data 0x6000_0000 0x2000_0000 Vice board control 0x8000_0000 8 CONFIG 0xA000_0000 0x1000_0000 data 0xE000_0000 0x2000_0000
[0101] Among them, the CONFIG space contains the instruction cache and instruction configuration register. The starting address of the data space motherboard is 0x6000_0000, and the space size is 0x2000_0000 (520MB). The read and write operations to this space are mapped to the read FIFO and write FIFO. This space size means that the read and write of DDR4 is up to 520MB at a time (starting from 0x6000_0000), and the read and write address of DDR4 is set by instructions. The highest bit of the address space (32 bits) is reserved for inter-board expansion.
[0102] It should be noted that, this embodiment is described by taking DDR4 as an example, but the present invention is not limited to the type of DDR, and is also applicable to DD2, DD3, etc.
[0103] Example 2
[0104] like Figure 4 As shown, this embodiment provides a DDR read and write control method based on the above-mentioned DDR interface, and the method mainly includes the following steps:
[0105] S1, setting the instructions in the instruction cache through the interface setting module to establish an instruction linked list.
[0106] Specifically, the interface setting module may set the following information corresponding to the instruction in the instruction: address step (step), instruction repetition number (Burst Num), DDR start address, next instruction address, DDR command, etc.
[0107] S2, setting the instruction configuration register through the interface setting module so that the instruction configuration register performs instruction configuration.
[0108] Specifically, the instruction configuration may include setting a starting instruction to be executed, setting an Iteration Number of chained list repetitions of the instruction chained list, and setting a DDR address corresponding to the first instruction and the last instruction in the instruction chained list.
[0109] S3, start DDR read and write operations through the control register.
[0110] S4, executing the instructions in the instruction chain list through the interface logic module of the DDR interface. When the chain list repetition number is configured, this step includes repeatedly executing the instructions in the instruction chain list until the chain list repetition number is reached.
[0111] In an practicable manner, a DDR reset operation is performed in advance before executing step S1.
[0112] In an practicable manner, the specific process of step S4 repeatedly executing the instructions in the instruction chain list is as follows:
[0113] First, the interface is initialized, specifically including initializing the address buffer according to the DDR addresses corresponding to the first instruction and the last instruction in the instruction chain list.
[0114] Then, the current instruction in the instruction list is executed, wherein the initial current instruction is the aforementioned start instruction.
[0115] Then, the DDR address in the address cache is updated according to the execution result of the current instruction, and the current DDR address corresponding to the next instruction after the update is determined.
[0116] Determine whether the next instruction is the starting instruction. If not, use the next instruction as the new current instruction and return to the step of executing the current instruction in the instruction list. If so, decrement the Iteration Number of the linked list by 1 (i.e., COUNT-DOWN), and then determine whether the number of linked list repetitions is 0. If it is 0, the process ends. If not, use the next instruction as the new current instruction and return to the step of executing the current instruction in the instruction list.
[0117] As described above, each instruction in the instruction cache carries execution rules such as the number of repetitions (BurstNum) and address step (step) of the corresponding instruction. Therefore, when executing the current instruction, this embodiment executes the current instruction according to the execution rules carried by the current instruction. Figure 1 As shown, before executing the current instruction, the number of repetitions Burst Num corresponding to the current instruction is decremented by 1, and then the read / write operation is performed according to the DDR starting address and address step step corresponding to the current instruction, and it is determined whether Burst Num is 0. If it is not 0, the step of decrementing the number of repetitions Burst Num corresponding to the current instruction by 1 is returned. If it is 0, the control variable is updated to execute the next instruction.
[0118] In summary, the present invention has the following beneficial effects compared with the prior art:
[0119] Efficient reading and writing of a single memory: The DDR interface proposed in the present invention can complete data reading and writing operations on the same memory stick, avoiding the need to allocate operations to different memory sticks in traditional methods, saving costs and space, and greatly improving system flexibility and data processing efficiency.
[0120] Stable data transmission: The coordinated work of the instruction cache, control register, and address cache, combined with the design of write and read FIFOs, achieves stable data transmission and ensures that valid data is not lost during data interaction between FPGA and DDR memory.
[0121] Optimize memory usage: By reasonably dividing the address space and configuring the use of registers, the capacity of DDR memory is maximized, the utilization rate of memory resources is improved, and a larger data storage and processing space is provided for the ultrasonic medical diagnostic system.
[0122] Reduce system costs: Efficient reading and writing on a single DDR memory stick is achieved, reducing the need for multiple memory sticks, thereby reducing hardware costs and improving the economy of the system.
[0123] The above beneficial effects make the DDR interface of the present invention have important practical application value in ultrasonic diagnostic systems, can improve system performance, and meet the demand for efficient data processing.
[0124] Although the specific embodiments of the present invention are described above, it should be understood by those skilled in the art that this is only for illustration and the protection scope of the present invention is defined by the appended claims. Those skilled in the art may make various changes or modifications to these embodiments without departing from the principles and essence of the present invention, but these changes and modifications all fall within the protection scope of the present invention.
Claims
1. A DDR interface, characterized in that: The DDR interface includes a control part and an interface part which are sequentially connected between the internal logic module of the FPGA and the DDRIP core, the control part includes a control register, an interface setting module, a write data FIFO module and a read data FIFO module, and the interface part includes a configuration port, a data write port, a data read port, an instruction configuration register, an instruction cache area, an address cache area and an interface logic module; The interface setting module is used to set the instructions in the instruction cache area through the configuration port to establish an instruction linked list, and is also used to set the instruction configuration register through the configuration port so that the instruction configuration register performs instruction configuration, wherein the instructions include write instructions and read instructions, and the address cache area is used to store the DDR address corresponding to each instruction; The control register is used to start DDR read and write operations to trigger the interface logic module to execute instructions in the instruction chain list, wherein, if the currently executed instruction is a write instruction, the data cached in the write data FIFO module is written to the DDR address corresponding to the instruction through the data write port; if the currently executed instruction is a read data instruction, the data in the DDR address corresponding to the instruction is read out to the read data FIFO module for caching through the data read port.
2. The DDR interface according to claim 1, characterized in that: The interface setting module includes: An internal interface setting unit, wherein an input end of the internal interface setting unit is connected to an internal control module of the FPGA; An external interface setting unit, wherein an input end of the external interface setting unit is connected to an external controller; A first selector, wherein an input end of the first selector is connected to output ends of the internal interface setting unit and the external interface setting unit, an output end of the first selector is connected to the configuration port, and a control end of the first selector is connected to the control register.
3. The DDR interface according to claim 2, characterized in that: The write data FIFO module comprises: An internal write data FIFO, an input end of which is connected to an internal write module of the FPGA; An external write data FIFO, wherein an input end of the external write data FIFO is connected to an external controller; A second selector, wherein the input end of the second selector is connected to the output ends of the internal write data FIFO and the external write data FIFO, the output end of the second selector is connected to the data write port, and the control end of the second selector is connected to the control register.
4. The DDR interface according to claim 3, characterized in that: The read data FIFO module comprises: An internal read data FIFO, the input end of which is connected to an internal processing module of the FPGA; An external read data FIFO, wherein an input end of the external read data FIFO is connected to an external controller; A third selector, wherein the output end of the third selector is connected to the input ends of the internal read data FIFO and the external read data FIFO, the input end of the third selector is connected to the data read port, and the control end of the third selector is connected to the control register.
5. The DDR interface according to claim 4, characterized in that: The FPGA includes a main board and a sub-board; The internal logic module of the FPGA includes a main board write module, a sub-board write module, a main board read module, a sub-board read module, a fourth selector and a fifth selector; The input ends of the main board writing module and the auxiliary board writing module are connected to the external controller, the output ends of the main board writing module and the auxiliary board writing module are connected to the input end of the fourth selector, and the output end of the fourth selector is connected to the external interface setting unit and the external write data FIFO; The output ends of the main board readout module and the sub-board readout module are connected to the external controller, the input ends of the main board readout module and the sub-board readout module are connected to the output end of the fifth selector, and the input end of the fifth selector is connected to the external read data FIFO.
6. The DDR interface according to claim 4, characterized in that: The FPGA is applied to an ultrasonic diagnostic system, the internal control module is an ultrasonic scanning control module, the internal writing module is a scanning data receiving module, and the internal processing module is a scanning beam synthesis module.
7. A DDR read / write control method based on the DDR interface as described above, characterized in that: include: Setting the instructions in the instruction cache area through the interface setting module to establish an instruction linked list; Setting the instruction configuration register through the interface setting module so that the instruction configuration register performs instruction configuration; The DDR read and write operations are started through the control register to trigger the interface logic module to execute the instructions in the instruction chain list.
8. The DDR read / write control method according to claim 7, characterized in that: The instruction configuration includes setting the starting instruction to be executed, setting the number of chain repetitions of the instruction chain list, and setting the DDR addresses corresponding to the first instruction and the last instruction in the instruction chain list; The interface logic module executes the instructions in the instruction chain list, including: repeatedly executing the instructions in the instruction chain list until the number of repetitions of the chain list is reached.
9. The DDR read / write control method according to claim 8, characterized in that: The process of the interface logic module repeatedly executing the instructions in the instruction chain list is as follows: Performing interface initialization, the interface initialization comprising initializing the address buffer area according to the DDR addresses corresponding to the first instruction and the last instruction in the instruction chain list; Execute the current instruction in the instruction chain list, the initial current instruction being the start instruction; The DDR address in the address cache is updated according to the execution result of the current instruction, and the DDR address corresponding to the next instruction after the update is determined; Determine whether the next instruction is the starting instruction. If not, use the next instruction as the new current instruction and return to the step of executing the current instruction in the instruction list. If so, decrement the number of repetitions of the linked list and determine whether the number of repetitions of the linked list is 0. If it is 0, the process ends. If not, use the next instruction as the new current instruction and return to the step of executing the current instruction in the instruction list.
10. The DDR read / write control method according to claim 9, characterized in that: Each of the instructions cached in the instruction cache area carries a corresponding execution rule, wherein the execution rule includes the number of repetitions and the address step length of the corresponding instruction execution; The executing the current instruction in the instruction chain list includes: executing the current instruction according to the execution rule carried by the current instruction.