MIPI channel control circuit and method thereof

Abstract

The invention discloses an MIP1 channel control circuit, which comprises a high-speed channel, a low-speed channel, a common port, an NVM memory and a controller, and is characterized in that the high-speed channel comprises a plurality of high-speed sub-channels, the low-speed channel comprises a plurality of low-speed sub-channels, and the common port is connected with the NVM memory; the plurality of high-speed sub-channels and the plurality of low-speed sub-channels receive data sent by a terminal through the common port; the controller is used for loading high-speed channel sequence configuration data from an NVM (Non-Volatile Memory) after being electrified, determining the sequence of the plurality of high-speed sub-channels according to the high-speed channel sequence configuration data, and combining data received from the high-speed channels according to the sequence, the high-speed channel sequence configuration data is pre-stored in the NVM memory. According to the invention, the NVM is combined with the channel sequence processing module, and the configuration data used for judging the sequence of the high-speed channels is pre-stored in the NVM, so that the sequence judgment of the high-speed channels is realized.

Description

Technical Field

[0001] The invention relates to a MIPI channel control circuit and a method thereof. Background Art

[0002] Traditional MIPI (Mobile Industry Processor Interface) channel sequence control is controlled by external port BS signal, such as Figure 1 and Figure 2 This control method using the external port BS requires the BS pin and the corresponding circuit to be reserved, and the BS routing and BS high and low control circuit need to be added to the FPC cable, which makes the cable design unfriendly. Summary of the invention

[0003] In view of the above problems, the present invention provides a MIPI channel control circuit and method thereof which can realize effective channel sequence without requiring a BS pin.

[0004] In a first aspect, the present invention provides a MIPI channel control circuit, comprising: a high-speed channel, a low-speed channel, a common port, an NVM memory and a controller, wherein the high-speed channel comprises a plurality of high-speed sub-channels, the low-speed channel comprises a plurality of low-speed sub-channels, the plurality of high-speed sub-channels and the plurality of low-speed sub-channels receive and / or send data through the common port; the controller is used to load high-speed channel sequence configuration data from the NVM memory after power-on, determine the sequence of the plurality of high-speed sub-channels according to the high-speed channel sequence configuration data, and combine the data received from the high-speed channel according to the sequence, wherein the high-speed channel sequence configuration data is pre-stored in the NVM memory.

[0005] In some embodiments, the controller includes a channel sequence loading module and a data processing module, the channel sequence recording module is used to load high-speed channel sequence configuration data from the NVM memory and send the high-speed channel sequence configuration data to the data processing module, and the data processing module is used to combine the received data according to the high-speed channel sequence configuration data.

[0006] In some embodiments, the controller is further configured to traverse data changes of the plurality of low-speed sub-channels in the low-speed channel, determine a low-speed sub-channel exhibiting data changes, and use the determined low-speed sub-channel to transmit low-speed data.

[0007] In some embodiments, the data change includes a change between 0 and 1 in the data.

[0008] In a second aspect, a MIPI channel control method is provided, comprising: after power-on, loading high-speed channel sequence configuration data from an NVM memory; determining the order of the multiple high-speed sub-channels according to the high-speed channel sequence configuration data; and combining data received from the high-speed channels according to the order, wherein the high-speed channel sequence configuration data is pre-stored in the NVM memory.

[0009] In some embodiments, the method further includes: traversing data changes of the plurality of low-speed sub-channels in the low-speed channel; determining a low-speed sub-channel showing data changes; and transmitting low-speed data using the determined low-speed sub-channel.

[0010] In a third aspect, a MIPI channel control method is provided, comprising: traversing data changes of multiple low-speed sub-channels in a MIPI channel; determining a low-speed sub-channel showing data changes, and setting the determined low-speed sub-channel as a target low-speed channel; and transmitting low-speed data through the target low-speed channel.

[0011] In some embodiments, it also includes: using the target low-speed sub-channel to transmit high-speed channel sequence configuration data; determining the order of multiple high-speed sub-channels through the channel sequence configuration data, and combining the data obtained from the multiple high-speed sub-channels according to the order to obtain data.

[0012] The MIPI channel sequence control implementation method of the present invention is no longer controlled by the BS signal outside the channel, but is combined with the NVM memory and the channel sequence processing module, and the configuration data for high-speed channel sequence judgment is pre-stored in the NVM memory to realize the sequence judgment of the high-speed channel.

[0013] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented according to the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present invention. Moreover, the same reference numerals are used throughout the drawings to represent the same components. In the drawings:

[0015] Figure 1 It is a traditional MIPI channel sequence control circuit;

[0016] Figure 2 It is the traditional MIPI channel control order;

[0017] Figure 3 It is a schematic diagram of the structure of the MIPI channel control circuit in some embodiments of the present invention;

[0018] Figure 4 The figure is a flowchart of a MIPI channel control method in some embodiments of the present invention. DETAILED DESCRIPTION

[0019] The following embodiments of the technical solution of the present invention are described in detail in conjunction with the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present invention, and are therefore only used as examples, and cannot be used to limit the protection scope of the present invention.

[0020] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by technicians in the technical field to which the present invention belongs; the terms used herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention; the terms "including" and "having" in the specification and claims of the present invention and the above-mentioned drawings and any variations thereof are intended to cover non-exclusive inclusions.

[0021] In the description of the embodiments of the present invention, the technical terms "first", "second", etc. are only used to distinguish different objects, and cannot be understood as indicating or implying relative importance or implicitly indicating the number, specific order or primary and secondary relationship of the indicated technical features. In the description of the embodiments of the present invention, the meaning of "multiple" is more than two, unless otherwise clearly and specifically defined.

[0022] Reference to "embodiment" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiment may be included in at least one embodiment of the present invention. The appearance of the phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments. In the description of embodiments of the present invention, the term "multiple" refers to more than two (including two).

[0023] MIPI interface is a screen interface standard widely used in mobile devices, defined by the MIPI Alliance, which aims to standardize the interfaces inside mobile devices, such as cameras, displays, basebands, radio frequency interfaces, etc. The main features of MIPI interface include high-speed transmission, low power consumption, noise suppression and fewer pins, making PCB layout more convenient.

[0024] The MIPI interface supports two working modes: high-speed and low-speed. The high-speed mode is generally used to transmit large-capacity data information, and its rate can support a resolution of up to 2048×1536@60FPS. The low-speed mode is generally used to transmit control and command information. The design of the MIPI interface needs to strictly comply with the differential design rules to ensure differential impedance matching, and the differential impedance value of the transmission line is 80-125 ohms.

[0025] based on Figure 1 and Figure 2 It can be seen that the existing MIPI data transmission interface requires an external port BS signal for control during data transmission. This transmission control method has the advantages of being simple and easy to implement, but it also has the following problems: the chip design requires the BS pin and the corresponding circuit to be reserved. In projects with tight pin resources, the BS pin is not easy to handle, and the BS pin routing and BS high and low control circuit need to be added to the FPC cable, making the cable design less friendly; in addition, although the BS pin designs of different chip manufacturers are relatively unified, as shown in Table 1, incompatibility often occurs, and even design errors may lead to application incompatibility.

[0026] This application provides a method for solving the above problems. Figure 3 As shown, the present invention provides a MIPI channel control circuit, comprising: a high-speed channel, a low-speed channel, a common port, an NVM memory and a controller, wherein the high-speed channel comprises a plurality of high-speed sub-channels, the low-speed channel comprises a plurality of low-speed sub-channels, and the plurality of high-speed sub-channels and the plurality of low-speed sub-channels receive data sent by a terminal through the common port; the controller is used to load high-speed channel sequence configuration data from the NVM memory after power-on, determine the sequence of the plurality of high-speed sub-channels according to the high-speed channel sequence configuration data, and combine the data received from the high-speed channel according to the sequence, wherein the high-speed channel sequence configuration data is pre-stored in the NVM memory.

[0027] Specifically, NVM (Non-Volatile Memory) memory is a memory that does not lose data when power is off. Figure 3 Medium DP <n>: The data positive port of the Nth channel, N is usually 0-3, DN <n>: Data negative port of the Nth channel.

[0028] The MIPI channel sequence control implementation method of the present invention is no longer controlled by the BS signal outside the channel, but is combined with the NVM memory and the channel sequence processing module, and the configuration data for high-speed channel sequence judgment is pre-stored in the NVM memory to realize the sequence judgment of the high-speed channel.

[0029] In some embodiments, the controller includes a channel sequence loading module and a data processing module, the channel sequence recording module is used to load high-speed channel sequence configuration data from the NVM memory and send the high-speed channel sequence configuration data to the data processing module, and the data processing module is used to combine the received data according to the high-speed channel sequence configuration data.

[0030] Specifically, high-speed channel sequence configuration data is pre-stored in the NVM memory. After the circuit is powered on, the channel sequence loading module is used to load the high-speed channel sequence configuration data from the NVM memory and send the loaded high-speed channel sequence configuration data to the data processing module. The data processing module parses the configuration data and combines the data received by the channel according to the configuration data based on the high-speed channel sequence configuration data.

[0031] In some embodiments, the order of the multiple high-speed sub-channels is determined according to the high-speed channel sequence configuration data, and the data received from the high-speed channels are combined according to the order to obtain correct data. For example, the high-speed channel includes a first high-speed sub-channel, a second high-speed sub-channel, a third high-speed sub-channel, and a fourth high-speed sub-channel. The order determined based on the high-speed channel sequence configuration data is the second high-speed sub-channel, the first high-speed sub-channel, the third high-speed sub-channel, and the fourth high-speed sub-channel. After receiving data through these high-speed sub-channels, the output processing module sequentially combines the data received from the second high-speed sub-channel, the first high-speed sub-channel, the third high-speed sub-channel, and the fourth high-speed sub-channel to obtain correct data.

[0032] In some embodiments, the controller is further used to traverse the data changes of the multiple low-speed sub-channels in the low-speed channel, determine the low-speed sub-channel showing data changes, and use the determined low-speed sub-channel to transmit low-speed data. Specifically, the channel with data will have changes between 0 and 1, and the channel without data will be always 1 or always 0. By determining whether there is a low-speed sub-channel with changes between 0 and 1 among the multiple low-speed sub-channels, the low-speed sub-channel used to send and receive low-speed information is determined.

[0033] In this embodiment, a low-speed channel determination method that is different from the high-speed channel determination order is provided, so that even in the debugging stage without NVM memory, the low-speed channel can be determined, and the low-speed channel can receive the control command sent by the host to achieve normal debugging.

[0034] In some embodiments, Figure 4 As shown, a MIPI channel control method is provided, including:

[0035] Step 101: After power-on, load high-speed channel sequence configuration data from the NVM memory.

[0036] Step 102: Determine the order of the plurality of high-speed sub-channels according to the high-speed channel order configuration data;

[0037] Step 103: Combine the data received from the high-speed channel according to the sequence, wherein the high-speed channel sequence configuration data is pre-stored in the NVM memory.

[0038] In some embodiments, the method further includes: traversing data changes of the plurality of low-speed sub-channels in the low-speed channel; determining a low-speed sub-channel showing data changes; and transmitting low-speed data using the determined low-speed sub-channel.

[0039] In some embodiments, a method for testing the MIPI data transmission interface is provided that does not require an external BS pin and does not use NVM memory, specifically: traversing data changes in multiple low-speed sub-channels in the MIPI channel; determining a low-speed sub-channel that exhibits data changes, and setting the determined low-speed sub-channel as a target low-speed channel; and transmitting low-speed data through the target low-speed channel.

[0040] In some embodiments, the target low-speed sub-channel is used to transmit the high-speed channel sequence configuration data; the sequence of the multiple high-speed sub-channels is determined by the channel sequence configuration data, and the data obtained from the multiple high-speed sub-channels are combined according to the sequence to obtain data. In this embodiment, by first determining the low-speed sub-channel that can be used for data transmission, the high-speed channel sequence configuration data is transmitted using the low-speed sub-channel, and the data obtained from the multiple high-speed sub-channels are combined according to the high-speed channel sequence configuration data to obtain data. If the data meets the requirements, the test is successful, otherwise, the test fails.

[0041] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention, and they should all be included in the scope of the claims and specification of the present invention. In particular, as long as there is no structural conflict, the various technical features mentioned in each embodiment can be combined in any way. The present invention is not limited to the specific embodiments disclosed herein, but includes all technical solutions that fall within the scope of the claims.< / n> < / n>

Claims

1. A MIPI channel control circuit, characterized in that: include: A high-speed channel, a low-speed channel, a common port, a NVM memory and a controller, wherein the high-speed channel includes a plurality of high-speed sub-channels, the low-speed channel includes a plurality of low-speed sub-channels, and the plurality of high-speed sub-channels and the plurality of low-speed sub-channels receive and / or send data through the common port; the controller is used to load high-speed channel sequence configuration data from the NVM memory after power-on, determine the sequence of the plurality of high-speed sub-channels according to the high-speed channel sequence configuration data, and combine the data received from the high-speed channel according to the sequence, wherein the high-speed channel sequence configuration data is pre-stored in the NVM memory.

2. The MIPI channel control circuit according to claim 1, characterized in that: The controller includes a channel sequence loading module and a data processing module. The channel sequence recording module is used to load high-speed channel sequence configuration data from the NVM memory and send the high-speed channel sequence configuration data to the data processing module. The data processing module is used to combine the received data according to the high-speed channel sequence configuration data.

3. The MIPI channel control circuit according to claim 1 or 2, characterized in that: The controller is further configured to traverse data changes of the plurality of low-speed sub-channels in the low-speed channel, determine a low-speed sub-channel showing alternating data changes, and use the determined low-speed sub-channel to transmit low-speed data.

4. The MIPI channel control circuit according to claim 3, characterized in that: The data alternation includes the data changing between 0 and 1.

5. A MIPI channel control method, characterized in that: include: After power-on, the high-speed channel sequential configuration data is loaded from the NVM memory; Determining the order of the plurality of high-speed sub-channels according to the high-speed channel order configuration data; The data received from the highway channel is combined according to the sequence, wherein the highway channel sequence configuration data is pre-stored in the NVM memory.

6. The MIPI channel control method according to claim 4, characterized in that: Also includes: Traversing data changes of the plurality of low-speed sub-channels in the low-speed channel; Determine the low-speed subchannel presenting the data change; Use the specified low-speed subchannel to transmit low-speed data.

7. A MIPI channel control method, characterized in that: include: Traverse the data changes of multiple low-speed sub-channels in the MIPI channel; Determine a low-speed sub-channel showing alternating data changes, and set the determined low-speed sub-channel as a target low-speed channel; The low-speed data is transmitted through the target low-speed channel.

8. The MIPI channel control method according to claim 7, characterized in that: Also includes: Using the target low-speed sub-channel to transmit high-speed channel sequential configuration data; The sequence of the plurality of high-speed sub-channels is determined by the channel sequence configuration data, and the data acquired from the plurality of high-speed sub-channels are combined according to the sequence to obtain data.

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